1Gbit SLC NAND Flash
FSNU8A001G
Datasheet
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FORESEE
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SLC NAND Flash
FSNU8A001G
Datasheet
LM-00003
Rev 1.3
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LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONSser
2
u
B01 WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein
受控is provided on an
“AS IS” basis, without warranties of any kind. All brand names, trademarks and registered trademarks belong to their respective
owners.
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1
This document and all information discussed herein remain the sole and exclusive property of Longsys Electronics. No license
of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party
25
7
For updates or additional information about-Longsys
2 0 products, contact your nearest Longsys office.
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© 2020 Shenzhen B
Longsys
5 Electronics Co., Ltd. All rights reserved.
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under this document, by implication, estoppel or other-wise.
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FSNU8A001G
Datasheet
Revision History
24
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Rev.
Date
Changes
1.0
2020/01/28
Initial release
1.1
2021/10/12
Revise descriptions in 10.1, 10.4, 10.6.2, 10.6.3, 12.5
1.2
2021/11/22
Revise descriptions in 4, 14.1, 14.2
1.3
2021/12/3
Add Chap 15
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1Gbit SLC NAND Flash
FSNU8A001G
Datasheet
Content
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Content....................................................................................................................................................
1BB 3
C
2
8D1
1 General Description ........................................................................................................................
5
A
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2 Features ...........................................................................................................................................
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3 Product List .....................................................................................................................................6
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Revision History .....................................................................................................................................2
4
Package Types and Pin Configurations .........................................................................................7
5
Pin Descriptions .............................................................................................................................. 8
6
Block Diagram .................................................................................................................................9
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Array Organization and Mapping .................................................................................................10
2802Mode Selection .............................................................................................................................. 11
9
Command Set ................................................................................................................................ 12
4
12
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10 Device Operation ........................................................................................................................... 13
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10.1 Reset (FFh) ........................................................................................................................................ 13
10.2 Read Operation ................................................................................................................................. 13
10.2.1
Page Read (00h-30h).................................................................................................................................... 13
10.2.2
Random Data Output (05h-E0h) ................................................................................................................... 14
10.2.3
Read Status (70h) ........................................................................................................................................ 15
10.2.4
Read ID (90h)............................................................................................................................................... 16
10.2.5
Read Parameter Page (ECh) .......................................................................................................................... 17
10.2.6
Read Unique ID (EDH) .................................................................................................................................. 20
10.3 Program Operation ........................................................................................................................... 21
10.3.1
Page Program (80h-10h) .............................................................................................................................. 21
10.3.2
Random Data Input (85h)............................................................................................................................. 21
10.4 Copy Back Operation ....................................................................................................................... 22
10.4.1
Copy Back Read (00h-35h) ........................................................................................................................... 22
10.4.2
Copy Back Program (85h-10h) ...................................................................................................................... 22
10.5 Block Erase (60h-D0h) ...................................................................................................................... 23
10.6 Feature Operation ............................................................................................................................. 24
10.6.1
Feature Register .......................................................................................................................................... 24
10.6.2
Get Feature (EEh) ........................................................................................................................................ 24
10.6.3
Set Feature (EFh) ......................................................................................................................................... 25
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10.7 OTP Operation ................................................................................................................................... 26
10.7.1
OTP Read / Program Operation .................................................................................................................... 26
10.7.2
OTP Lock Operation ..................................................................................................................................... 26
10.8 Block Protection................................................................................................................................ 27
10.9 Write Protect ...................................................................................................................................... 28
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FSNU8A001G
Datasheet
11 Software Algorithm .......................................................................................................................31
11.1
11.2
11.3
11.4
11.5
Initial Invalid Block(s) ....................................................................................................................... 31
Identifying Initial Invalid Block(s) .................................................................................................... 31
Error in Operation ............................................................................................................................. 32
Addressing for Program Operation ................................................................................................ 32
System Interface Using CE# Don’t-Care ........................................................................................ 33
12.4
12.5
12.6
12.7
12.8
Pin Capacitance ................................................................................................................................ 36
DC Electrical Characteristics ........................................................................................................... 36
AC Measurement Conditions........................................................................................................... 37
AC Electrical Characteristics ........................................................................................................... 37
Read / Program / Erase Characteristics ......................................................................................... 38
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12 Electrical Characteristics ..............................................................................................................
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12.1 Absolute Maximum Ratings .............................................................................................................
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12.2 Operating Ranges ............................................................................................................................. 35
12.3 Power-up Timing ...............................................................................................................................
35
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21302Timing Diagram .............................................................................................................................39
14 Part Marking Scheme ....................................................................................................................48
14.1
14.2
4
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48-TSOP (20x12mm) ......................................................................................................................... 48
63-TFBGA (11x9mm) ......................................................................................................................... 48
C1
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15 Packaging Information ..................................................................................................................
49
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15.1 48-TSOP (20x12mm) .........................................................................................................................
49
15.2 63-TFBGA (11x9mm) ......................................................................................................................... 51
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1Gbit SLC NAND Flash
FSNU8A001G
Datasheet
1
General Description
24
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The FSNU8A001G is a 1G-bit (128Mx8bit) NAND Flash Memory with spare 32M-bit. The device
on a single 1.8V VCC. A program operation can be performed in typical 350µs on the (2K+64) Byte page
and an erase operation can be performed in typical 2ms on a (128K+4K) Byte block. Data in the page
buffer can be read out at 25ns cycle time per Byte. The FSNU8A001G is an optimum solution for large
nonvolatile storage applications such as solid state file storage and other portable applications requiring
non-volatility.
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The FSNU8A001G supports the standard NAND flash memory interface using the multiplexed 8-bit bus
to transfer data, addresses, and command instructions. The five control signals, CLE, ALE, CE#, RE#
and WE# handle the bus interface protocol. Also, the device has two other signal pins, the WP# and the
R/B# for monitoring the device status.
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Features
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Voltage Supply
- VCC: 1.7V ~ 1.95V
Advanced Features
- Hardware WP# write protect
- Software block protect
- Unique ID
- One 2kB parameter page
- Sixty-two 2kB OTP Pages
- Promised golden block0
Organization
- Memory Cell Array: (128M + 4M) Byte
- Page Size: (2k + 64) Byte
- Block Size: 64 pages, (128k + 4k) Byte
- Plane Size: 1,024 Blocks
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High Performance 22
- Random Read:
2025µs
- Sequential
Read: 25ns
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24- Page Program Time: 350µs (Typ.)
B01
High Reliability
- Endurance: typical 100k cycles (1)
- Data Retention: 10 years (1)
.
Package
- 48-TSOP
- 63-TFBGA (11x9mm)
- Block Erase Time: 2ms (Typ.)
Low Power
- Standby: 10µA (Typ.)
- Read: 10mA (Typ.)
- Program/Erase: 15mA (Typ.)
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Note:
2
0:0 1bit / 528Byte ECC
(1) Endurance and Data Retention specification is based on
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FSNU8A001G
Datasheet
3
Product List
Table 1 Product List
Part Number
Density
I/O Type
Voltage Range
FSNU8A001G-TWT
1Gb
x8
1.7V ~ 1.95V
FSNU8A001G-TAT
1Gb
x8
1.7V ~ 1.95V
FSNU8A001G-BWT
1Gb
x8
1.7V ~ 1.95V
FSNU8A001G-BAT
1Gb
x8
1.7V ~ 1.95V
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48-TSOP
-40°C ~ 85°C
Tray
1BTrayB
C
48-TSOP
-40°C ~ 105°
C
2
8D1 Tray
A
63-TFBGA
-40°
C
~ 85°C
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63-TFBGA use -40°C ~ 105°C
Tray
Package
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F SN U 8 A 001G - T W T
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Temp. Range
Packing
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Figure 1 Marketing Part Numbering Chart
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Packing
T = Tray
Temp. Range
W = -40°C~85°C
A = -40°C~105°C
3 = AECQ100 G3
2 = AECQ100 G2
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Package
T = 48-TSOP
B = 63-TFBGA
Density
001G = 1Gbit
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A = Version A
I/O Type
8 = x8 & ECC Required
Voltage Range
U = 1.7V~1.95V
Product Type
SN = SLC NAND
Brand
F = FORESEE
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FSNU8A001G
Datasheet
4
Package Types and Pin Configurations
Figure 2 Pin Configuration 48-TSOP
202
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VC C
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
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2-0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
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A
2
NC
NC
3
6
7
8
NC
WP#
ALE
VSS
CE#
WE#
R/B#
D
NC
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
NC
NC
NC
H
NC
IO0
NC
NC
NC
VCC
J
NC
IO1
NC
VCC
IO5
IO7
K
VSS
IO2
IO6
VSS
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NC
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L
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B
B0
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NC
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IO3
IO4
9
10
NC
NC
NC
NC
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NC
NC
NC
NC
NC
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NC
NC
NC
NC
IO7
IO6
IO5
IO4
NC
NC
NC
VCC
Vss
NC
NC
NC
IO3
IO2
IO1
IO0
NC
NC
NC
NC
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Figure 3 Pin Configuration 63-TFBGA
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10
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13
14
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FSNU8A001G
Datasheet
5
Pin Descriptions
24
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B
C1B
2
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Chip Enable
.
s
er CE# high is ignored, and the
The CE# input is the device selection control. When the device is in the Busy
usstate,
device does not return to standby mode in program or erase operation.
Read Enable
受控
Table 2 Pin Description
Pin Name
CE#
RE#
FB
Pin Functions
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t REA
after the falling edge of RE# which also increments the internal column address counter by one.
02
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1
Write Enable
WE#
The WE# input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
2the5WE# pulse.
7
2-0 Command Latch Enable
202CLE
The CLE input controls the activating path for commands sent to the command register.
Commands are
latched on the rising edge of WE# with CLE high.
4
12
0
B
B
The ALE input controls the activating path for address sent to the address registers. Addresses are latched1
C on
2
1
the rising edge of WE# with ALE high.
A8D
.
s
Write Protect
er
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The WP# input can be used to prevent the inadvertent program / erase to the device. All program / erase
operations are disabled when WP# is active low.
受控
Ready / Busy Output
Address Latch Enable
ALE
WP#
R/B#
IO7 - IO0
FB5
4
2
VSS
B01
2
0:0
1
does not float to high-z
-25condition when the chip is deselected or when outputs are disabled.
7
0
Data Inputs
2- / Outputs
2
0
2The IO pins are used to input command, address and data and to output data during read operations. The IO
The R/B# output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
Ground
VCC
Power Supply
NC
No Connection
受控
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pins float to high-z when the chip is deselected or when the outputs are disabled.
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FSNU8A001G
Datasheet
6
Block Diagram
Figure 4 Block Diagram
High Voltage
Circuit
CLE
ALE
Control
Logic
IO Port
WE#
WP#
RE#
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Address
Counter
R/B#
IO[7:0]
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X-DEC
CE#
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Memory Array
Page Buffer
Y-DEC
Data Buffer
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FSNU8A001G
Datasheet
7
Array Organization and Mapping
Figure 5 Array Organization
24
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64K Pages
(=1,024 Blocks)
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1 Page = (2K + 64) Bytes
1 Block = 64 Pages
受控 = (128K + 4K) Bytes
1 Block = 64 Pages
(128K + 4K) Bytes
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52K1Bytes
2
7
2-0
1 Device = 1,024 Blocks
= 1,024 x (128K + 4K) Bytes
= 1,056 Mbits
64 Bytes
8 Bits
IO 0 ~ IO 7
Page Buffer
2K Bytes
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64 Bytes
Table 3 Addressing
Column Address
IO7
IO6
IO5
1st cycle
A7
A6
A5
2nd cycle
L
L
3rd cycle
A19
A18
C1
2
1
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.
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usIO2
IO4
IO3
A4
控
L 受 L
A3
A2
A1
A0
A11
A10
A9
A8
A15
A14
A13
A12
A22
A21
A20
A17
A16
2
4th cycle
0A27:0 A26 A25 A24 A23
1
Note
25
7
0
(1) L: A low condition, which
2- must be held during the address cycle to insure correct processing.
2
0
(2) A17~A12 are2
page addresses, A27~A18 are block addresses.
FB5
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B01
Row Address
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FSNU8A001G
Datasheet
8
Mode Selection
Table 4 Mode Selection
Mode
ALE
CE#
Command Input
H
L
L
Address Input (4 cycles)
L
H
L
Command Input
H
L
L
Address Input (4 cycles)
L
H
Data Input
L
L
Data Output
L
L
受控 L
H
During Read (Busy)
X
X
X
X
H
X
During Program (Busy)
X
X
X
X
X
H
X
X
H
X
X
L
X
X
0V / VCC
Read
Write
WE#
RE#
24
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B
CLE
WP#
H
X
L
C1XB
H
2
1
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H
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H
H
us
L
H
H
X
X
X
2
0
:
Write Protect
X
X
X
10
5
2
X
X
H
7-Stand-by
0
2
02
2Note
(1) “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” can be V
During Erase (Busy)
IL
FB
X
or VIH.
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0
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2
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B0
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1
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FSNU8A001G
Datasheet
9
Command Set
Table 5 Command Table
1st Cycle
2nd Cycle
Reset
FFh
-
Page Read
00h
30h
Random Data Output
05h
E0h
Read Status
70h
-
Read ID
90h
-
Read Parameter Page
ECh
Read Unique ID
EDh
-
Page Program
80h
10h
85h
-
00h
35h
85h
10h
60h
D0h
Get Feature
EEh
-
Set Feature
EFh
-
Command
Random Data Input
25
Copy Back 7
Program
-0
2Erase
Block
2
0
2
Copy Back Read
02
:
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1
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Yes
-
4
12
BB0
Note
C1
2
1
Any commands not in the above table are considered as undefined and are prohibited as inputs.
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(1) Random Data Input and Random Data Output command is only to be used within a page.
(2)
24
1
0
B
Acceptable While Busy
FB5
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2
B01
2
0:0
1
-25
7
0
22
0
2
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FSNU8A001G
Datasheet
10
Device Operation
10.1 Reset (FFh)
24
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The device offers a reset operation, executed by writing FFh to the command register. When the device
is in busy state during random read, program or erase mode, the reset operation will abort these
operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status
Register is cleared to value C0h when WP# is high. If the device is already in Ready state, a new reset
command will be accepted by the command register, and the device is reset instantly, but the R/B# pin
will not change to low.
受控
25
7
R/B#
2-0
2
0
2
02
:
0
1
Figure 6 Reset Sequence
tRST
IOx
4
FFh
12
BB0
C1
2
1
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10.2 Read Operation
受控
10.2.1 Page Read (00h-30h)
2
0:0
1
-25
7
0
22
0
2
The FSNU8A001G array is accessed in page of 2,112 bytes. When the device powers on, 00h command
is latched to command register. Therefore, system only issues four address cycles and 30h command for
initial read from the device. This operation can also be entered by writing 00h command to the command
register, and then write four address cycles, followed by writing 30h command. After writing 30h
command, the data is transferred from NAND array to page buffer during tR.
FB5
4
2
B01
.
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e
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u
Data transfer progress can be done by monitoring the status of the R/B# signal output. R/B# signal will
be LOW during data transfer. Also, there is an alternate method by using the Read Status command. If
the Read Status command is issued during read operation, the Page Read command must be re-issued
to read out the data from page buffer.
受控
02
:
0
1
Once the data in a page is loaded into the page buffer, R/B# signal goes high, and the data can be read
from Page buffer by toggling RE#. Read is sequential from initial column address to the end of the page.
25
7
2-0
202
If the host side uses a sequential access time (t RC) of less than 30ns, the data can be latched on the next
falling edge of RE# as the waveform of EDO mode.
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
13 / 52
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The device may output random data in a page instead of the consecutive sequential data by writing
Random Data Output command. The column address of next data, which is going to be out, may be
changed to the address which follows random data output command. Random data output can be
operated multiple times regardless of how many times it is done in a page.
Figure 7 Page Read Sequence
CLE
24
1
0
B
FB
C1B
2
1
A8D
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受控
CE#
WE#
ALE
202
25
7
2-0
02
:
0
1
tRD
R/B#
RE#
IOx
00h
Address(4Cycle)
30h
Data Output(Serial Access)
4
12
BB0
C1
2
1
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Col.Add.1,2 & Row Add.1,2
受控
FB5
4
2
B01
2
0:0
1
-25
7
0
22
0
2
Data Field
Spare Field
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10.2.2 Random Data Output (05h-E0h)
受控
The Random Data Output command allows the selection of random column addresses to read out data
from a single or multiple of addresses. The use of the Random Data Output command is available after
the Page Read (00h-30h) sequence by writing the 05h command following by the two cycle column
address and then the E0h command. Toggling RE# will output data sequentially. The Random Data
Output command can be issued multiple times, but limited to the current loaded page.
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
02
:
0
1
202
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Figure 8 Page Read with Random Data Output Sequence
tRD
R/B#
RE#
IOx
Address
4Cycle
00h
30h
Data Output
24
1
0
B
FB
C1B
2
1
A8D
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Address
2CycleS
05h
E0h
Data Output
Col.Add.1,2
Col.Add.1,2 & Row Add.1,2
Data Field
Data Field
Spare Field
Spare Field
受控
25
7
2-0
02
:
0
1
10.2.3 Read Status (70h)
02device contains a Status Register which may be read to find out whether program or erase operation
2The
is completed, and whether the program or erase operation is completed successfully. After writing 70h
command to the command register, a read cycle outputs the content of the Status Register to the I/O
pins on the falling edge of CE# or RE#, whichever occurs last. This two line control allows the system to
poll the progress of each device in multiple memory connections even when R/B pins are common-wired.
RE# or CE# does not need to be toggled for updated status. Refer to Table 6 for specific Status Register
definitions.
4
12
BB0
C1
2
1
A8D
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受控
The command register remains in Read Status mode until another command is issued. Therefore, if the
status register is read during a random read cycle, the Page Read command should be given before
starting read cycles.
FB5
4
2
CLE
B01
2
0:0
1
-25 Figure 9 Read Status Sequence
7
0
22
0
2
tCLS
tCLH
tCS
tCH
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tCLR
tCEA
tCHZ
受控
CE#
tCOH
tWP
WE#
02
:
0
1
RE#
IOx
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
tRHZ
tRHOH
2tDS5
7
70h
2-0
tDH
202
tIR
tREA
Status Output
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Datasheet
Table 6 Status Register Definition
SR Bits
Page Program
Block Erase
Read
Definition
IO 0
Pass / Fail
Pass / Fail
Not use
0 = Pass, 1 = Fail
IO 1
Not use
Not use
Not use
Don’t -care
IO 2
Not use
Not use
Not use
Don’t -care
IO 3
Not use
Not use
Not use
Don’t -care
IO 4
Not use
Not use
Not use
Don’t -care
IO 5
Not Use
Not Use
Not Use
IO 6
Ready / Busy
Ready / Busy
Ready/Busy
C1B
2
1
A8D
Don’t -care
.
s
er
0 = Busy, 1u=s
Ready
IO 7
Write Protect
Write Protect
Write Protect
0 = Protected, 1 = Unprotected
受控
Note
24
1
0
B
FB
(1) IOs defined ’Not use’ are recommended to be masked out when Read Status is being executed.
02
:
0
1
10.2.4 Read ID (90h)
25
7
2-0
Read ID command is comprised of two modes determined by the input address, device (00h) or ONFI
(20h) identification information. To enter the Read ID mode, write 90h command following by a 00h
address cycle, then toggle RE# for 5 single byte cycles. The pre-programmed code includes the
Manufacturer ID, Device ID, and Product-Specific Information (See Table 8). If the Read ID command is
followed by 20h address, the output code includes 4 single byte cycles of ONFI identifying information.
The device remains in the Read ID mode until the next valid command is issued.
202
4
12
BB0
C1
2
1
A8D
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Figure 10 Read ID Sequence
tCLR
CLE
受控
tCEA
CE#
WE#
FB5
4
2
B01
ALE
2
0:0
1
-25
7
0
22
0
2
tAR
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tWHR
RE#
tREA
IOx
00h
90h
MID
25
7
2-0 A1h
DID
3rd
Cyc.
4th
Cyc.
受5th控
Cyc.
02
:
0
1
Table 7 Device and ONFI identification information
Address
1st Byte/Cycle
00h
02
2
Manufacturer ID
20h
4Fh
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
CDh
2nd Byte/Cycle
3rd Byte/Cycle
4th Byte/Cycle
5th Byte/Cycle
00h
95h
40h
46h
49h
-
Device ID
4Eh
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Datasheet
Table 8 Product-Specific Information
Terms
Description
IO7
IO6
IO5
IO4
3rd Byte
0 = Not supported
Multiple die operation
0 = Not supported
page number
00 = SLC
Die number per CE
00 = 1
0
Sequential access min
10 = 25ns
Organization
0 = x8
Block size (without spare)
01 = 128kB
25
7
2-0
202
IO0
24
1
0
B
0
4th Byte
Page size
IO1
0
00 = 1
Cell type
Spare size per 512B
IO2
00h
Cache Program
Simultaneously Programmed
IO3
1
0
FB
C1B
2
1
8D
0 s.A
0
r
0
0
use
95h
受控
0
0
0
1
2 1 = 16
0
:
01 = 2kB
10
1
5th Byte
0
1
0
0
40h
Internal ECC
0 = Not supported
Plane size
100 = 1Gb
Plane number per CE
00 = 1
ECC requirement
00 = 1bit / 528B
0
1
0
0
0
4
12
BB0
0
C1
2
1
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10.2.5 Read Parameter Page (ECh)
Read Parameter Page can read out the device’s parameter data structure, such as, manufacturer
information, device organization, timing parameters, key features, and other pertinent device parameters.
The data structure is stored with at least three copies in the device’s parameter page. The Random Data
Output command is supported during data output.
受控
IOx
5
B
F
4
2
B01
2
0:0
1
-25Figure 11 Read Parameter Page Sequence
7
0
22
0
2
ECh
00h
P0
P1
…
P1023
tR
R/B#
.
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受控
02
:
0
Byte Number
Descriptions
5 1
2
0~3
Parameter Page Signature,
07 "ONFI" ASCII characters
2
2
4~5
Revision Number
20
B5
F
4
012
B
B
2 C1
1
D
8
Table 9 Parameter Definition
Everything for Memory
17 / 52
Values
4Fh 4Eh 46h 49h
02h 00h
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Byte Number
Descriptions
Values
Feature Supported
b6-b15 reserved (0)
6~7
b5
1 = supports source synchronous
b4
1 = supports odd to even page Copyback
b3
1 = supports interleaved operations
b2
1 = supports non-sequential page programming
b1
1 = supports multiple LUN operations
b0
1 = supports 16-bit data bus width
Optional Command Supported
8~9
1 = supports Read Unique ID
b4
1 = supports Copy-back
2
:
10= supports Get Features and Set Features
0
1
b3
FB
C1B
2
1
A8D
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受控
b6-b15 reserved (0)
b5
24
1
0
B
10h 00h
1 = supports Read Status Enhanced
34h 00h
b2
202
10~31
1 = supports Read Cache commands
1 = supports Page Cache Program command
Reserved (0)
all 00h
46h 4Fh 52h 45h
32~43
Device manufacturer , 12 ASCII characters
4
12
BB0
53h 45h 45h 20h
C1
2
1
46h 53h 4Eh 55h
8D
A
.
s
38h 41h 30h e
30h
r
s
u
31h 47h 20h 20h
20h 20h 20h 20h
44-63
Device Model, 20 ASCII characters
受控
64
65-66
67-79
80-83
84-85
24
B01
2C
8D1
25 b1
7
b0
2-0
FB586-89
2
Date Code
0:0
1
Reserved (0) 25
07of -Data Bytes per Page
Number
2
202Number of Spare Bytes per Page
JEDEC MID
20h 20h 20h 20h
20h 20h 20h 20h
CDh
00h 00h
all 00h
00h 08h 00h 00h
40h 00h
Number of Data Bytes per Partial Page
00h 02h 00h 00h
90-91
Number of Spare Bytes per Partial Page
10h 00h
92-95
Number of Pages per Block
40h 00h 00h 00h
96-99
Number of Block per Logic Unit
00h 04h 00h 00h
Number of Logic Units
01h
100
Number of Address Bytes
101
b4-b7 column address cycles
25
7
2-0
b0-b3 row address cycles
102
受控
02
:
0
1
Number of Bits per Cell
103-104
Bad Blocks Maximum
202 per Logic Unit
105-106
Block Endurance
5
B
F
10724
Guaranteed Valid Blocks at Beginning of Target
1
0
B
Block Endurance for Guaranteed Valid Blocks
1B 108-109
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22h
01h
14h 00h
01h 05h
01h
01h 03h
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Byte Number
110
Values
Number of Programs per Page
04h
Partial Programming Attributes
b5-b7 reserved (0)
111
b4
1 = partial page layout is partial page data
followed by partial page spare
b1-b3 reserved (0)
b0
112
1 = partial page programming has constraints
Number of ECC Bits Correctability
Number of Interleaved Address Bits
113
受控
b4-b7 reserved (0)
24
1
0
B
00h
FB
C1B
2
1
A8D
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01huse
00h
b0-b3 number of interleaved address bits
Interleaved Operation Attributes
02 restrictions for program cache
:
address
0
1
b4-b7 reserved (0)
202
b3
25 b2
7
b1
2-0
114
b0
115-127
128
00h
1 = program cache supported
1 = no block address restrictions
overlapped / concurrent interleaving support
Reserved (0)
all 00h
I/O Pin Capacitance, Maximum
08h
Asynchronous Timing Mode Support
b6-b15 reserved (0)
129-130
FB5131-132
4
2
B01
8D
Descriptions
b5
1 = supports timing mode 5
b4
1 = supports timing mode 4
b3
1 = supports timing mode 3
b2
1 = supports timing mode 2
1 = supports timing mode 1
b0
1 = supports timing mode 0, shall be 1
b4
1 = supports timing mode 4
b3
1 = supports timing mode 3
b2
1 = supports timing mode 2
b1
1 = supports timing mode 1
b0
1 = supports timing mode 0, shall be 1
tPROG Maximum Page Program Time (us)
135-136
tBER Maximum Block Erase Time (us)
02
:
0
1
5 Time (ns)
2Setup
139~140
t
Minimum Change Column
7
-0
141-163
Reserved (0)022
2
164-165
Vendor Specific Revision Number
5
166-2534FB Vendor Specific
012
254-255
Integrity CRC
B
B
1
tR Maximum Page read Time (us)
CCS
12C
C1
2
1
A8D
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1Fh 00h
2
0:0
1
5 Cache Timing Mode Support
Asynchronous
-2Program
7
0
b6-b15
2- reserved (0)
2
0
2 b5
1 = supports timing mode 5
b1
133-134
137-138
受控
4
12
BB0
Everything for Memory
19 / 52
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00h 00h
受控
BCh 02h
10h 27h
19h 00h
3Ch 00h
all 00h
00h 00h
all 00h
20h 47h
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Datasheet
Byte Number
Descriptions
256-511
Value of Bytes 0-255
512-767
Value of Bytes 0-255
768+
Values
Additional Redundant Parameter Pages
24
1
0
(1) The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were
1BBthe
C
2
transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated
using
8D1
A
following 16-bit generator polynomial: G(X) = X16 + X15 +X2 + 1
.
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10.2.6 Read Unique ID (EDH)
受控
Note:
FB
The unique ID is 32-byte and with 16 copies for back-up purpose. After writing the Unique ID read
command and following the one address byte (00h), the host may read out the unique ID data. The host
need to XOR the 1st 16-byte unique data and the 2nd 16-byte complement data to get the result, if the
result is FFh, the unique ID data is correct; otherwise, host need to repeat the XOR with the next copy of
Unique ID data.
02
:
0
1
25
7
2-0
02 sending the EDh command, the NAND device will remain in the Unique ID read mode until next
2Once
valid command is sent. The Random Data Output command is supported during data output.
4
12
0
B
B
The Read Status command can be used to check the completion. To continue the read operation,
C1a
2
1
following read command (00h) to re-enable the data out is necessary.
A8D
.
s
er
s
u
Figure 12 Read Unique ID Sequence
受控
IOx
EDh
R/B#
00h
2
0:0
1
-25
7
0
22
0
2
UID 0
Do 0
UID 0
Do 1
UID 0
Do 31
UID 1
Do 0
Busy
FB5
4
2
B01
IOx
Figure 13 Read Unique ID Sequence with Random Data Output
EDh
UID 0
Do 0
00h
UID 0
Do 1
R/B#
Busy
25
7
2-0
B0
B
1
2C
8D1
.
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B5
F
4
12
Everything for Memory
05h
02
:
0
1
1st Add
Cyc.
2nd Add
Cyc.
E0h
受控
UID m
Do n
UID m
Do n+1
Repeat if needed
202
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Datasheet
10.3 Program Operation
10.3.1 Page Program (80h-10h)
24
1
0
B
The device is programmed basically on a page basis, but it does allow multiple partial page programming
of a word or consecutive bytes up to 2,112 in a single page program cycle. The number of consecutive
partial page programming operation within the same page without an intervening erase operation must
NOT exceed 4 times for a single page. The addressing should be done in sequential order in a block.
FB
C1B
2
1
A8D
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A page program cycle consist of a serial data loading period in which up to 2,112-bytes of data may be
loaded into the page buffer, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell.
受控
02
:
0
1
The serial data loading period begins by inputting the 80h command, followed by the four cycle address
inputs and then serial data loading. The words other than those to be programmed do not need to be
loaded. The 10h command initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process.
202
25
7
2-0
The internal write state controller automatically exe-cutes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process
starts, the Read Status command may be entered to read the status register. The system controller can
detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (IO6) of the
Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status bit (IO 0) may be checked (See Figure
14). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to
the command register.
4
12
BB0
C1
2
1
A8D
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受控
R/B#
FB5
4
2
IOx
B01
:02
0
1
5 Figure 14 Page Program Sequence
2
-07
2
2
t
20
PROG
“0”
80h
Address &
Data input
10h
70h
I/O0
.
ers
Passus
受Fail控
Col.Add.1,2 & Row Add.1,2
Data
“1”
02
:
0
1
25
7
After the Page Program 80h command
2-0 execution of the initial data has been loaded into the page buffer,
2
0
2 of data is required, using the Random Data Input command can perform
if the need for additional writing
this function toBa5new column address prior to the 10h command. The Random Data Input may be
4F times regardless of how many times it is done in a page.
2multiple
operated
1
0
BB
1
C
2
8D1
10.3.2 Random Data Input (85h)
Everything for Memory
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Datasheet
Figure 15 Page Program with Random Data Input Sequence
tPROG
R/B#
24
1
0
B
“0”
IOx
80h
Address &
Data input
85h
Col.Add.1,2 & Row Add.1,2
Data
Address &
Data input
10h
Col.Add.1,2
Data
70h
I/O0
Pass
FB
C1B
2
1
A8D
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“1”
Fail
受控
10.4 Copy Back Operation
02
:
0
1
Copy Back operations can quickly and efficiently rewrite data stored in one page. The benefit is
especially obvious when a portion of a block is updated and the rest of the block also needs to be copied
to the newly assigned free block. The operations require two sequential command sets. Issue a Copy
Back Read command first, then the Copy Back Program command.
202
25
7
2-0
Since Copy Back operations do not use external memory and the data of source page might include a bit
errors, a competent ECC scheme should be developed to check the data before programming data to a
new destination page.
4
12
BB0
C1
2
1
D
A8odd
.
s
Note: Copy Back Operation can only be used to copy even page to even page or to
copy
page to
r
e
s
u
odd page.
受控
10.4.1 Copy Back Read (00h-35h)
2
0:0
1
-25
7
0
22
0
2
The Copy Back Read command is used together with the Copy Back Program command. To start
execution, 00h command is written to the command register, followed by the four cycles of the source
page address. To start the transfer of the selected page data from the memory array to the page buffer,
write the 35h command to the command register.
FB5execution of the Copy Back Read command sequence and R/B# returns to HIGH marking thesers.
4
After
2
B01 completion of the operation, the transferred data from the source page into the page buffer may be readu
out by toggling RE#. Data is output sequentially from the column address that was originally
受控 specified
with the Copy Back Read command (See Figure 16).
The Random Data Output commands can be issued multiple times without any limitation after Copy Back
Read command has been executed.
25
7
2-0
02
:
0
1
202
10.4.2 Copy Back Program (85h-10h)
B5
F
4
12
After the Copy Back Read command operation has been completed and R/B# goes HIGH, the Copy
Back Program command can be written to the Command Register.
B0
B
1
2C
8D1
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Datasheet
The operation is initiated by issuing 85h command with destination page address. Actual programming
operation begins after 10h command is issued. Once the program process starts, the Read Status
command may be entered to read the status register. The system controller can detect the completion of
a program cycle by monitoring the R/B# output, or the Status bit (IO6) of the Status Register. When the
copy back program is complete, the Write Status Bit (IO0) may be checked (See Figure 16). The
command register remains in Read Status command mode until another valid command is written to the
command register.
24
1
0
B
FB
C1B
2
1
A8D
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During copy-back program, data modification is possible using Random Data Input command with
multiple times (see Figure 17).
受控
Figure 16 Copy Back Read and Copy Back Program Sequence
R/B#
25
7
IOx -0
2
2
0
2
00h
02
:
0
1
tPROG
tR
0
Add.(4Cycles)
Data Output
35h
85h
Add.(4Cycles)
I/O0
70h
10h
Col.Add.1,2 & Row Add.1,2
Destination Address
Col.Add.1,2 & Row Add.1,2
Source Address
Pass
1
Fail
4
12
BB0
C1
2
1
A8D
.
s
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Figure 17 Copy Back Program with Random Data Input Sequence
IOx
tPROG
tR
R/B#
00h
Add.(4Cycles)
Data Output
35h
2
0:0
1
-25
7
0
22
0
2
Col.Add.1,2 & Row Add.1,2
Source Address
85h
受控
Add.(4Cycles) Data
Col.Add.1,2 & Row Add.1,2
Destination Address
85h
Add.(2Cycles) Data
10h
70h
Col.Add.1,2
There is no limitation for the number of repetition
10.5
FB5 Block Erase (60h-D0h)
4
2
B01
.
rs
e
s
u
The erase operation is done on a block basis. Block address loading is accomplished in two cycles
initiated by 60h command. Only address A18 to A27 is valid while A12 to A17 is ignored. The D0h
command following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by execution command ensures that memory contents are not accidentally
erased due to external noise conditions.
受控
25
7
2-0
02
:
0
1
At the rising edge of WE# after the erase confirm command input, the internal write controller handles
erase and erase-verify. The system controller can detect the completion of an erase cycle by monitoring
the R/B# output, or the Status bit (IO6) of the Status Register. When the block erase operation is
complete, the Write Status Bit (IO0) may be checked.
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
202
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Figure 18 Block Erase Sequence
tBERS
R/B#
“0”
IOx
D0h
I/O0
70h
24
1
0
B
Pass
FB
C1B
2
1
Fail
A8D
.
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Row Add 1,2
“1”
受控
10.6 Feature Operation
The Feature Set operation is to change the default power-on feature sets by using the Set Feature and
Get Feature command and writing the specific parameter data (P1-P4) on the specific feature addresses.
The NAND device may remain the current feature set until next power cycle since the feature set data is
volatile. However, the Reset command cannot reset the current feature set.
25
7
2-0
02
210.6.1
02
:
0
1
Feature Register
4
12
BB0
Table 10 Feature Register
Feature
Register
Address
Parameter
P1
Operation
Mode
FB5
4
2
B01
2
8D1
Address
Input(2cycle)
60h
Block
Protection
90h
C1
2
1
D
A8default
.
s
Normal
Mode,
value
r
e
0
s
u after power cycle.
IO7
IO6
IO5
IO4
IO3
IO2
IO1
0
0
0
0
0
0
0
0
0
0
0
0
0
受控
0
1
0
0
0
1
1
2
0:0
1
P2 25
70
P3
2
202 P4
0
0
0
IO0
Description
OTP Operation Mode. See
10.7.1 for detail information
OTP Lock Mode. See 10.7.2
for detail information
Reserved (0)
Reserved (0)
Reserved (0)
Default value after power
P1
R
BP3
BP2
BP1
BP0
TB
0
SP
cycle is 00000000 (00h).
.
rs
e
s
u
See 10.8 for detail
受控
information
A0h
P2
Reserved (0)
P3
Reserved (0)
P4
10.6.2 Get Feature (EEh)
02
:
0
1
Reserved (0)
25
7
2-0
02
2
The Get Feature command is to read feature parameter. After sending the Get Feature command and
B5address, the host may read out the P1-P4 sub- feature parameter data. Once sending
following register
F
4
2
01command,
the B
EEh
the NAND device will remain in the Get Feature mode until next valid command is
B
C1
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sent.
Figure 19 Get Feature Sequence
24
1
0
B
CLE
C1B
2
1
A8D
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WE#
ALE
受控
RE#
IOx
202
FB
02
:
0
5R/B#1
2
7
2-0
EEh
FA
P1
P2
P3
P4
tFEAT
4
10.6.3 Set Feature (EFh)
012
B
B
The Set Feature command is to change the power-on default feature set. After sending the Set Feature
C1
2
1
command and following register address and then input the P1-P4 parameter data to change
the
feature
A8Duntil next
.
s
set. Once sending the EFh command, the NAND device will remain in the Set Feature
mode
ser
valid command is sent. The Set Feature command is completed instantly, u
and the R/B# pin will not
change to low.
受控
Figure 20 Set Feature Sequence
FB5
4
2
B01
2
0:0
1
CLE
-25
7
0
22
0
2 WE#
.
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e
s
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ALE
受控
RE#
IOx
EFh
B0
B
1
2C
8D1
Everything for Memory
P1
25
7
2-0
R/B#
B5
F
4
12
FA
P2
P3
02
:
0
1
P4
202
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1Gbit SLC NAND Flash
FSNU8A001G
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10.7 OTP Operation
The OTP area has 62 pages (62 x 2,112-byte). It is a non-erasable and one-time programmable area,
which is default to “1” and allows whole page or partial page program to be “0”. Once the OTP protection
mode is set, the OTP area becomes read-only and cannot be programmed again.
24
1
0
B
FB
1B
C
2
1
The OTP operation is operated by the Set Feature / Get Feature operation to access the8OTP
D Operation
A
.
s
Mode and OTP Lock Mode.
r
use
To check the NAND device is ready or busy in the OTP operation mode, either checking the R/B# or
控
using the Read Status command to check the status. 受
To exit the OTP operation or protect mode, it can be done by writing 00h to P1 at feature address 90h.
02
:
0
1
25
7
2-0
10.7.1 OTP Read / Program Operation
2To02enter the OTP Operation Mode, it is by using the Set Feature command and followed by the feature
address 90h and then input the 01h to P1 and 00h to P2-P4 of sub-Feature Parameter data (see Table
10 Feature Register).
4
12
BB0
C1
2
1
A8D
.
s
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After enter the OTP Operation Mode, the OTP area can be read or programmed like non-OTP area. The
address of OTP is located on the 02h-3Fh of page address.
10.7.2 OTP Lock Operation
控
受
To prevent the further OTP data to be changed, the OTP lock operation is necessary. To enter the OTP
Lock Mode, it can be done by using the Set2Feature command and followed by the feature address 90h
0to:0P2-P4 of sub-Feature Parameter data (see Table 10 Feature
and then input the 03h to P1 and 00h
1
Register). And then the normal
-25Page Program command with the address 00h before the 10h command
7
0
2is required.
2
0
2
The
FB5OTP lock operation is operated on the whole OTP area instead of individual OTP page. Once thesers.
4
2
1
u
OTP protection mode is set, the OTP area can NOT be programmed or unprotected again.
受控
Figure 21 OTP Lock Operation Sequence
IOx
80h
R/B#
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
4 Add.cyc.
00h
25
7
2-0
00h
Dummy
02inputdata
:
0
1
10h
70h
Status
Output
tPROG
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10.8 Block Protection
The block protect operation can protect the whole chip or selected blocks from erasing or programming.
When program or erase attempt at a protected block is happened, the R/B# keeps low for the time of
tPBSY, and the Status Read command may get the 41h result.
24
1
0
B
FB
1B
C
2
1
At power-on, all the blocks are default to be un-protected. The Set Feature command
8D with feature
A
.
s
address A0h followed by the destined protection bits with data “1” is necessaryeto
r protect those selected
s
u
blocks. After the selected blocks are protected, those protected blocks can be un-protected again by
reset Block Protection Bit to “0” if required.
受控
The “solid-protection” feature can be set by writing the Set Feature command with feature address A0h
and the “SP” solid protection bit as “1” (see Table 10 Feature Register), after that, the selected block is
solid-protected and cannot be up-protected until next power cycle.
20TB2
02
:
0
1
25
7
2-0
Table 11 Block Protection Bits
Protected
Protected Page
Protected
Protected
Block(s)
Address PA[15:0]
Density
Portion
0
NONE
NONE
NONE
NONE
0
1
1022 & 1023
FF80h - FFFFh
256KB
Upper 1/512
0
1
0
1020 thru 1023
FF00h - FFFFh
512KB
Upper 1/256
0
0
1
1
1016 thru 1023
FE00h - FFFFh
0
0
1
0
0
1008 thru 1023
FC00h - FFFFh
C1
2
1
8D 1/128
AUpper
1MB
.
s
r Upper 1/64
2MB
use
0
0
1
0
1
992 thru 1023
F800h - FFFFh
4MB
Upper 1/32
0
0
1
1
0
960 thru 1023
F000h - FFFFh
受控
8MB
Upper 1/16
0
0
1
1
1
896 thru 1023
16MB
Upper 1/8
0
1
0
0
0
768 thru 1023
C000h - FFFFh
32MB
Upper 1/4
0
1
8000h - FFFFh
64MB
Upper 1/2
1
0
0000h – 007Fh
256KB
Lower 1/512
1
0
02
:
0
1
0
0
1
5512 thru 1023
2
0
0
0&1
-017
2
2
0
0 thru 3
20 1 0
E000h - FFFFh
0000h - 00FFh
512KB
Lower 1/256
0
0
1
1
0 thru 7
0000h - 01FFh
1MB
Lower 1/128
0
1
0
0
0 thru 15
0000h - 03FFh
2MB
Lower 1/64
1
0
1
0
1
0 thru 31
0000h - 07FFh
4MB
Lower 1/32
1
0
1
1
0
0 thru 63
0000h - 0FFFh
8MB
1
0
1
1
1
0 thru 127
0000h - 1FFFh
16MB
1/16
受控 Lower
Lower 1/8
1
1
0
0
0
0 thru 255
0000h - 3FFFh
32MB
Lower 1/4
1
1
0
0
1
0 thru 511
64MB
Lower 1/2
X
1
0
1
X
02 - FFFFh
0:0000h
128MB
ALL
X
1
1
X
X
0000h - FFFFh
128MB
ALL
BP3
BP2
BP1
BP0
X
0
0
0
0
0
0
0
0
0
1 5
F
4 1B
2
1
B0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
5 1
0 thru 1023
2
7
2-0
0 thru 1023
0000h - 7FFFh
4
12
BB0
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10.9 Write Protect
WP# pin can enable or disable program and erase commands preventing or allowing program and erase
operations. Figure 22 to Figure 27 shows the enabling or disabling timing with WP# setup time (tWW ) that
is from rising or falling edge of WP# to latch the first commands. After first command is latched, WP# pin
must not toggle until the command operation is complete and the device is in the ready state. (Status
Register Bit6 (IO6) equal 1).
24
1
0
B
FB
C1B
2
1
A8D
.
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Figure 22 Erase Enable
受控
WE#
tww
IOx
202
25
7
2-0
02
:
0
1
60h
D0h
WP#
4
12
BB0
R/B#
C1
2
1
A8D
.
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Figure 23 Erase Disable
受控
WE#
tww
:02
0
1
IOx
-25
7
0
22
0
2
WP#
60h
FB5
4
2
B01
.
rs
e
s
u
R/B#
受控
25
7
2-0
B0
B
1
2C
8D1
D0h
B5
F
4
12
Everything for Memory
02
:
0
1
202
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Figure 24 Program Enable
WE#
tww
80h
IOx
10h
WP#
202
02
:
0
1
C1B
2
1
A8D
.
s
r
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Figure 25 Program Disable
WE#
tww
80h
IOx
10h
WP#
02
2
WE#
4
12
BB0
C1
2
1
A8D
.
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受控
R/B#
FB5
4
2
B01
FB
受控
R/B#
25
7
2-0
24
1
0
B
:02
0
1
5 Figure 26 Program for Copy-Back Enable
2
7
2- 0
.
rs
e
s
u
tww
85h
IOx
10h
受控
WP#
25
7
2-0
R/B#
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
02
:
0
1
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Figure 27 Program for Copy-Back Disable
WE#
tww
85h
IOx
10h
WP#
202
FB
C1B
2
1
A8D
.
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受控
R/B#
25
7
2-0
24
1
0
B
02
:
0
1
4
12
BB0
C1
2
1
A8D
.
s
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受控
FB5
4
2
B01
2
0:0
1
-25
7
0
22
0
2
.
rs
e
s
u
受控
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
02
:
0
1
202
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11
Software Algorithm
11.1 Initial Invalid Block(s)
24
1
0
B
FB
C1B
2
1
A8D
.
s
r
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Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is
not guaranteed. Devices with initial invalid block(s) have the same quality level as devices with all valid
blocks and have the same electrical characteristics. An initial invalid block(s) does not affect the
performance of valid block(s). The system design must be able to mask out the initial invalid block(s) via
address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
at the time of shipment.
受控
Table 12 Valid Block Number
Parameter
Valid block number
25
7
2-0
02
211.2
Symbol
02 N
:
0
1
VB
Min
Max
Unit
1004
1024
Blocks
Identifying Initial Invalid Block(s)
4
12
BB0
All device locations are erased (FFh) except locations where the initial invalid block(s) information is
written prior to shipping. All initial invalid blocks are marked with non-FFh at the first byte of spare area
on the 1st or 2nd page. Since the initial invalid block information is also erasable in most cases, it is
impossible to recover the information once it has been erased. Therefore, the system must be able to
recognize the initial invalid block(s) based on the original initial invalid block information and create the
initial invalid block table via the suggested flow (Figure 28). Any intentional erasure of the original initial
invalid block information is prohibited.
C1
2
1
A8D
.
s
r
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FB5
4
2
B01
202
控
受
Figure 28 Flow to Create Initial Invalid Block Table
2
0:0
1
-25
7
0
2-
.
rs
e
s
u
受控
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
02
:
0
1
202
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11.3 Error in Operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. The following
possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail
during a page program does not affect the data of the other pages in the same block, block replacement
can be executed with a page-sized buffer by finding an erased empty block and reprogramming the
current target data and copying the rest of the replaced block. In case of Read, ECC must be employed.
To improve the efficiency of memory space, it is recommended that the read or verification failure due to
single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate
does not include those reclaimed blocks.
24
1
0
B
FB
C1B
2
1
A8D
.
s
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受控
Table 13 Failure Modes
Operation
25 Status read after program → Block Replacement
7
2-0
Erase
202
Detection and recommended procedure
02
:
0
1 read after erase → Block Replacement
Status
Program
Read
Verify ECC → ECC correction
4
12
BB0
Figure 29 Bad Block Replacement
C1
2
1
A8D
.
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受控
FB5
4
2
B01
2
0:0
1
-25
7
0
22
0
2
.
rs
e
s
u
受控
25
02
:
0
1
11.4 Addressing for Program
-07 Operation
B5
F
4
12
2
202
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of
the block to the MSB(most significant bit) pages of the block. The LSB page is defined as the start page
among the pages to be programmed, does not need to be page 0 in the block. Random page address
B0
B
1
2C
8D1
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programming is prohibited.
Figure 30 Addressing for Program Operation
24
1
0
B
FB
C1B
2
1
A8D
.
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受控
202
25
7
2-0
02
:
0
1
11.5 System Interface Using CE# Don’t-Care
4
012
B
B
For an easier system interface, CE# may be inactive during the data-loading or serial access as shown
1
Cthe
2
1
below. The internal 2,112 byte data registers are utilized as separate buffers for this operation
and
A8Dcycle time
.slow
s
system design gets more flexible. In addition, for voice or audio applications which r
use
useaccess would provide
on the order of μ-seconds, de-activating CE# during the data-loading and serial
significant savings in power consumption.
Figure 31 Program Operation with
受CE#控don’t-care
2
0:0
1
25
7
0
CE#
22
0
2
CLE
FB5
4
2
B01
CE# don,t-care
.
rs
e
s
u
WE#
ALE
IOx
受控
80h
Address(4Cycles)
tCS
CE#
Data Input
tCH
25
7
t 2-0
2
0
2
Data Input
80h
02
:
0
1
WP
WE#
B0
B
1
2C
8D1
B5
F
4
12
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Figure 32 Read Operation with CE# don’t-care
CLE
24
1
0
B
CE# don,t-care
RE#
ALE
受控
RB
WE#
202
IOx
25
7
2-0
FB
C1B
2
1
A8D
.
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CE#
02
:
0
1
00h
Address(4Cycles)
Data Output(serial access)
30h
tCEA
CE#
4
12
BB0
tREA
RE
out
I/O0~7
C1
2
1
A8D
.
s
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受控
FB5
4
2
B01
2
0:0
1
-25
7
0
22
0
2
.
rs
e
s
u
受控
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
02
:
0
1
202
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Datasheet
12
Electrical Characteristics
12.1 Absolute Maximum Ratings
Table 14 Absolute Maximum Rating
Parameters
Symbol
Supply Voltage
VCC
Voltage Applied to Any Pin
VIO
受控T
Temperature under Bias
Storage Temperature
Short circuit output current, I/Os
24
1
0
B
C1B
2
1
Range 8D
Unit
A
.
s
V
e–0.6r to +2.5
us–0.6
to V +0.4
V
CC
TBIAS
–40 to +125
°C
STG
–65 to +150
°C
5
mA
IOS
FB
Note:
02
:
0
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