2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
S
FORESEE
®
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2Gbit SLC NAND Flash
FSNS8A002G
G
Datasheet
LM-00008
LO
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Rev 1.2
LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS
WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an
“AS IS” basis, without warranties of any kind. All brand names, trademarks and registered trademarks belong to their respective
owners.
This document and all information discussed herein remain the sole and exclusive property of Longsys Electronics. No license of
any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party
under this document, by implication, estoppel or other-wise.
For updates or additional information about Longsys products, contact your nearest Longsys office.
© 2020 Shenzhen Longsys Electronics Co., Ltd. All rights reserved.
Everything for Memory
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Revision History
Date
Changes
Editor
1.0
2021/01/15
1. Initial release.
Alex
1.1
2021/11/08
1. Revise descriptions in 4, 10.1, 10.4, 12.5, 14.
Alex
1.2
2021/12/01
1. Add chapter 15.
Alex
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Rev.
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Content
Revision History .....................................................................................................................................2
Content....................................................................................................................................................3
General Description ........................................................................................................................ 5
2
Features ...........................................................................................................................................5
3
Product List .....................................................................................................................................6
4
Package Types and Pin Configurations ......................................................................................... 7
5
Pin Descriptions .............................................................................................................................. 8
6
Block Diagram .................................................................................................................................9
7
Array Organization and Mapping .................................................................................................10
8
Mode Selection .............................................................................................................................. 11
9
Command Set ................................................................................................................................ 12
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S
1
10 Device Operation ........................................................................................................................... 13
N
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10.1 Reset (FFh) ........................................................................................................................................ 13
10.2 Read Operation ................................................................................................................................. 13
10.2.1
Page Read (00h-30h).................................................................................................................................... 13
10.2.2
Random Data Output (05h-E0h) ................................................................................................................... 14
10.2.3
Read Status (70h) ........................................................................................................................................ 15
10.2.4
Read ID (90h)............................................................................................................................................... 16
10.2.5
Read Parameter Page (ECh) .......................................................................................................................... 17
10.2.6
Read Unique ID (EDH) .................................................................................................................................. 20
LO
10.3 Program Operation ........................................................................................................................... 21
10.3.1
Page Program (80h-10h) .............................................................................................................................. 21
10.3.2
Random Data Input (85h)............................................................................................................................. 21
10.4 Copy Back Operation ....................................................................................................................... 22
10.4.1
Copy Back Read (00h-35h) ........................................................................................................................... 22
10.4.2
Copy Back Program (85h-10h) ...................................................................................................................... 22
10.5 Block Erase (60h-D0h) ...................................................................................................................... 23
10.6 Feature Operation ............................................................................................................................. 24
10.6.1
Feature Register .......................................................................................................................................... 24
10.6.2
Get Feature (EEh) ........................................................................................................................................ 25
10.6.3
Set Feature (EFh) ......................................................................................................................................... 25
10.7 OTP Operation ................................................................................................................................... 26
10.7.1
OTP Read / Program Operation .................................................................................................................... 26
10.7.2
OTP Lock Operation ..................................................................................................................................... 26
10.8
10.9
Block Protection................................................................................................................................ 27
Write Protect ...................................................................................................................................... 28
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
11 Software Algorithm ....................................................................................................................... 31
11.1
11.2
11.3
11.4
11.5
Initial Invalid Block(s) ....................................................................................................................... 31
Identifying Initial Invalid Block(s).................................................................................................... 31
Error in Operation ............................................................................................................................. 32
Addressing for Program Operation ................................................................................................ 32
System Interface Using CE# Don’t-Care ........................................................................................ 33
12 Electrical Characteristics ..............................................................................................................35
S
Absolute Maximum Ratings ............................................................................................................. 35
Operating Ranges ............................................................................................................................. 35
Power-up Timing ............................................................................................................................... 35
Pin Capacitance ................................................................................................................................ 36
DC Electrical Characteristics ........................................................................................................... 36
AC Measurement Conditions ........................................................................................................... 37
AC Electrical Characteristics ........................................................................................................... 37
Read / Program / Erase Characteristics ......................................................................................... 38
SY
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
13 Timing Diagram ............................................................................................................................. 39
14 Packaging Information ..................................................................................................................48
48-TSOP (20x12mm) ......................................................................................................................... 48
63-TFBGA (11x9mm) ......................................................................................................................... 50
G
14.1
14.2
15 Part Marking Scheme .................................................................................................................... 52
48-TSOP (20x12mm) ......................................................................................................................... 52
63-TFBGA (11x9mm) ......................................................................................................................... 53
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15.1
15.2
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
1
General Description
The FSNS8A002G is a 2G-bit (256Mx8bit) NAND Flash Memory with spare 64M-bit. The device operates
on a single 3.3V VCC. A program operation can be performed in typical 350µs on the (2K+64) Byte page
and an erase operation can be performed in typical 2ms on a (128K+4K) Byte block. Data in the page
buffer can be read out at 25ns cycle time per Byte. The FSNS8A002G is an optimum solution for large
nonvolatile storage applications such as solid-state file storage and other portable applications requiring
non-volatility.
Features
Voltage Supply
- VCC: 2.7V ~ 3.6V
N
Organization
- Memory Cell Array: (256M + 8M) Byte
- Page Size: (2k + 64) Byte
- Block Size: 64 pages, (128k + 4k) Byte
- Plane Size: 1,024 Blocks
LO
High Performance
- Random Read: 25µs
- Sequential Read: 25ns
- Page Program Time: 350µs (Typ.)
- Block Erase Time: 2ms (Typ.)
Low Power
- Standby: 10µA (Typ.)
- Read: 10mA (Typ.)
- Program/Erase: 15mA (Typ.)
Everything for Memory
Advanced Features
- Hardware WP# write protect
- Software block protect
- Unique ID
- One 2kB parameter page
- Sixty-two 2kB OTP Pages
- Promised golden block0
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2
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S
The FSNS8A002G supports the standard NAND flash memory interface using the multiplexed 8-bit bus to
transfer data, addresses, and command instructions. The five control signals, CLE, ALE, CE#, RE# and
WE# handle the bus interface protocol. Also, the device has two other signal pins, the WP# and the R/B#
for monitoring the device status.
High Reliability
- Endurance: typical 100k cycles (1)
- Data Retention: 10 years (1)
Package
- 48-TSOP (20x12mm)
- 63-TFBGA (11x9mm)
Note:
(1) Endurance and Data Retention specification is based on
1bit / 528Byte ECC
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
3
Product List
Table 1 Product List
Part Number
Density
I/O Type
Voltage Range
Package
Temp. Range
Packing
FSNS8A002G-TWT
2Gb
x8
2.7V ~ 3.6V
48-TSOP
-40°C ~ 85°C
Tray
FSNS8A002G-TAT
2Gb
x8
2.7V ~ 3.6V
48-TSOP
-40°C ~ 105°C
Tray
FSNS8A002G-BWT
2Gb
x8
2.7V ~ 3.6V
63-TFBGA
-40°C ~ 85°C
Tray
FSNS8A002G-BAT
2Gb
x8
2.7V ~ 3.6V
63-TFBGA
-40°C ~ 105°C
Tray
F SN S 8 A 002G - T W T
S
Figure 1 Marketing Part Numbering Chart
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Packing
T = Tray
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G
Temp. Range
W = -40°C~85°C
A = -40°C~105°C
3 = AECQ100 G3
2 = AECQ100 G2
Density
002G = 2Gbit
Version
A = Version A
I/O Type
8 = x8 & ECC Required
LO
Everything for Memory
Package
T = 48-TSOP
B = 63-TFBGA
Voltage Range
S = 2.7V~3.6V
Product Type
SN = SLC NAND
Brand
F = FORESEE
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
4
Package Types and Pin Configurations
Figure 2 Pin Configuration 48-TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
IO7
IO6
IO5
IO4
NC
NC
NC
VCC
Vss
NC
NC
NC
IO3
IO2
IO1
IO0
NC
NC
NC
NC
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S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
Figure 3 Pin Configuration 63-TFBGA
2
NC
NC
3
4
N
A
1
B
6
7
8
NC
C
WP#
ALE
VSS
CE#
WE#
R/B#
D
NC
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
NC
NC
NC
H
NC
IO0
NC
NC
NC
VCC
J
NC
IO1
NC
VCC
IO5
IO7
K
VSS
IO2
IO3
IO4
IO6
VSS
LO
Everything for Memory
5
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
5
Pin Descriptions
Table 2 Pin Description
Pin Name
Pin Functions
Chip Enable
CE#
The CE# input is the device selection control. When the device is in the Busy state, CE# high is ignored, and the
device does not return to standby mode in program or erase operation.
Read Enable
RE#
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t REA
after the falling edge of RE# which also increments the internal column address counter by one.
WE#
S
Write Enable
The WE# input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
Command Latch Enable
CLE
SY
the WE# pulse.
The CLE input controls the activating path for commands sent to the command register.
Commands are
latched on the rising edge of WE# with CLE high.
Address Latch Enable
ALE
The ALE input controls the activating path for address sent to the address registers. Addresses are latched on
the rising edge of WE# with ALE high.
WP#
G
Write Protect
The WP# input can be used to prevent the inadvertent program / erase to the device. All program / erase
operations are disabled when WP# is active low.
Ready / Busy Output
The R/B# output indicates the status of the device operation. When low, it indicates that a program, erase or
N
R/B#
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
Data Inputs / Outputs
The IO pins are used to input command, address and data and to output data during read operations. The IO
LO
IO7 - IO0
pins float to high-z when the chip is deselected or when the outputs are disabled.
VSS
Ground
VCC
Power Supply
NC
No Connection
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
6
Block Diagram
CE#
High Voltage
Circuit
CLE
WP#
RE#
Control
Logic
Memory Array
Page Buffer
Address
Counter
R/B#
IO[7:0]
LO
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Data Buffer
Y-DEC
S
WE#
IO Port
ALE
X-DEC
Figure 4 Block Diagram
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
7
Array Organization and Mapping
Figure 5 Array Organization
128K Pages
(=2,048 Blocks)
1 Block = 64 Pages
(128K + 4K) Bytes
S
1 Page = (2K + 64) Bytes
1 Block = 64 Pages
= (128K + 4K) Bytes
1 Device = 2,048 Blocks
= 2,048 x (128K + 4K) Bytes
= 2,112 Mbits
8 Bits
64 Bytes
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2K Bytes
Page Register
IO 0 ~ IO 7
Page Register
64 Bytes
G
2K Bytes
Table 3 Addressing
IO5
IO4
IO3
IO2
IO1
IO0
A7
A6
A5
A4
A3
A2
A1
A0
2nd cycle
L
L
L
A12
A11
A10
A9
A8
3rd cycle
A19
A18
A17
A16
A15
A14
A13
A12
4th cycle
A27
A26
A25
A24
A23
A22
A21
A20
5th cycle
L
L
L
L
L
L
L
A28
LO
Row Address
1st cycle
IO6
N
Column Address
IO7
Note
(1) L: A low condition, which must be held during the address cycle to insure correct processing.
(2) A17~A12 are page addresses, A28~A18 are block addresses.
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
8
Mode Selection
Table 4 Mode Selection
RE#
WP#
L
H
X
H
L
H
X
H
L
L
H
H
Address Input (5 cycles)
L
H
L
H
H
Data Input
L
L
L
H
H
Data Output
L
L
L
H
During Read (Busy)
X
X
X
X
H
X
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X
X
X
X
H
Write Protect
X
X
X
X
X
L
Stand-by
X
H
X
X
0V / VCC
Write
ALE
CE#
Command Input
H
L
Address Input (5 cycles)
L
Command Input
Note
WE#
X
X
S
Read
CLE
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Mode
LO
N
G
(1) “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” can be VIL or VIH.
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
9
Command Set
Table 5 Command Table
1st Cycle
2nd Cycle
Acceptable While Busy
Reset
FFh
-
Yes
Page Read
00h
30h
Random Data Output
05h
E0h
Read Status
70h
-
Read ID
90h
-
Read Parameter Page
ECh
-
Read Unique ID
EDh
-
Page Program
80h
Random Data Input
85h
Copy Back Read
00h
S
Yes
10h
-
35h
SY
Command
Copy Back Program
Block Erase
Get Feature
Set Feature
Note
85h
10h
60h
D0h
EEh
-
EFh
-
G
(1) Random Data Input and Random Data Output command is only to be used within a page.
LO
N
(2) Any commands not in the above table are considered as undefined and are prohibited as inputs.
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
10
Device Operation
10.1 Reset (FFh)
S
The device offers a reset operation, executed by writing FFh to the command register. When the device
is in busy state during random read, program or erase mode, the reset operation will abort these
operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status
Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset
command will be accepted by the command register, and the device is reset instantly, but the R/B# pin
will not change to low.
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Figure 6 Reset Sequence
tRST
R/B#
IOx
N
10.2 Read Operation
G
FFh
10.2.1 Page Read (00h-30h)
LO
The FSNS8A002G array is accessed in page of 2,112 bytes. When the device powers on, 00h command
is latched to command register. Therefore, system only issues five address cycles and 30h command for
initial read from the device. This operation can also be entered by writing 00h command to the command
register, and then write five address cycles, followed by writing 30h command. After writing 30h
command, the data is transferred from NAND array to page buffer during tR.
Data transfer progress can be done by monitoring the status of the R/B# signal output. R/B# signal will
be LOW during data transfer. Also, there is an alternate method by using the Read Status command. If
the Read Status command is issued during read operation, the Page Read command must be re-issued
to read out the data from page buffer.
Once the data in a page is loaded into the page buffer, R/B# signal goes high, and the data can be read
from Page buffer by toggling RE#. Read is sequential from initial column address to the end of the page.
If the host side uses a sequential access time (t RC) of less than 30ns, the data can be latched on the next
falling edge of RE# as the waveform of EDO mode.
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
The device may output random data in a page instead of the consecutive sequential data by writing
Random Data Output command. The column address of next data, which is going to be out, may be
changed to the address which follows random data output command. Random data output can be
operated multiple times regardless of how many times it is done in a page.
Figure 7 Page Read Sequence
CLE
S
CE#
WE#
SY
ALE
R/B#
tR
RE#
IOx
Address(5Cycle)
30h
Data Output(Serial Access)
G
00h
LO
N
Col.Add.1,2 & Row Add.1,2,3
Data Field
Spare Field
10.2.2 Random Data Output (05h-E0h)
The Random Data Output command allows the selection of random column addresses to read out data
from a single or multiple of addresses. The use of the Random Data Output command is available after
the Page Read (00h-30h) sequence by writing the 05h command following by the two cycles column
address and then the E0h command. Toggling RE# will output data sequentially. The Random Data
Output command can be issued multiple times, but limited to the current loaded page.
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Figure 8 Page Read with Random Data Output Sequence
tR
R/B#
RE#
IOx
00h
Address
5Cycle
30h
Data Output
Address
2CycleS
05h
E0h
Data Output
Col.Add.1,2
Col.Add.1,2 & Row Add.1,2,3
Data Field
Spare Field
Spare Field
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S
Data Field
10.2.3 Read Status (70h)
N
G
The device contains a Status Register which may be read to find out whether program or erase operation
is completed, and whether the program or erase operation is completed successfully. After writing 70h
command to the command register, a read cycle outputs the content of the Status Register to the I/O
pins on the falling edge of CE# or RE#, whichever occurs last. This two-line control allows the system to
poll the progress of each device in multiple memory connections even when R/B pins are common-wired.
RE# or CE# does not need to be toggled for updated status. Refer to Table 6 for specific Status Register
definitions.
LO
The command register remains in Read Status mode until another command is issued. Therefore, if the
status register is read during a random read cycle, the Page Read command should be given before
starting read cycles.
Figure 9 Read Status Sequence
tCLS
tCLH
tCS
tCH
tCLR
CLE
tCEA
tCHZ
CE#
tCOH
tWP
WE#
tRHZ
tRHOH
RE#
tDS
IOx
Everything for Memory
tDH
70h
tIR
tREA
Status Output
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Table 6 Status Register Definition
SR Bits
Page Program
Block Erase
Read
Definition
IO 0
Pass / Fail
Pass / Fail
Not use
0 = Pass, 1 = Fail
IO 1
Not use
Not use
Not use
Don’t -care
IO 2
Not use
Not use
Not use
Don’t -care
IO 3
Not use
Not use
Not use
Don’t -care
IO 4
Not use
Not use
Not use
Don’t -care
IO 5
Not Use
Not Use
Not Use
Don’t -care
IO 6
Ready / Busy
Ready / Busy
Ready/Busy
0 = Busy, 1 = Ready
IO 7
Write Protect
Write Protect
Write Protect
0 = Protected, 1 = Unprotected
Note
S
(1) IOs defined ’Not use’ are recommended to be masked out when Read Status is being executed.
SY
10.2.4 Read ID (90h)
G
Read ID command is comprised of two modes determined by the input address, device (00h) or ONFI
(20h) identification information. To enter the Read ID mode, write 90h command following by a 00h
address cycle, then toggle RE# for 5 single byte cycles. The pre-programmed code includes the
Manufacturer ID, Device ID, and Product-Specific Information (See Table 8). If the Read ID command is
followed by 20h address, the output code includes 4 single byte cycles of ONFI identifying information.
The device remains in the Read ID mode until the next valid command is issued.
Figure 10 Read ID Sequence
CE#
LO
WE#
tCLR
N
CLE
tCEA
tAR
ALE
tWHR
RE#
90h
IOx
tREA
00h
MID
DID
3rd
Cyc.
4th
Cyc.
5th
Cyc.
Table 7 Device and ONFI identification information
Address
00h
20h
Everything for Memory
st
1 Byte/Cycle
2nd Byte/Cycle
CDh
DAh
Manufacturer ID
Device ID
4Fh
4Eh
3rd Byte/Cycle
4th Byte/Cycle
5th Byte/Cycle
00h
95h
44h
46h
49h
-
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Table 8 Product-Specific Information
Terms
Description
IO7
IO6
IO5
IO4
3rd Byte
0 = Not supported
Multiple die operation
0 = Not supported
page number
0
0
IO1
IO0
0
0
0
1
0
0
0
0
00 = 1
Cell type
00 = SLC
Die number per CE
00 = 1
0
0
4th Byte
95h
10 = 25ns
1
Organization
0 = x8
Block size (without spare)
01 = 128kB
Spare size per 512B
1 = 16
0
0
S
Sequential access min
0
1
1
01 = 2kB
SY
Page size
IO2
00h
Cache Program
Simultaneously Programmed
IO3
th
5 Byte
44h
Internal ECC
0 = Not supported
Plane size
100 = 1Gb
Plane number per CE
01 = 2
ECC requirement
00 = 1bit / 528B
0
1
0
0
1
G
0
10.2.5 Read Parameter Page (ECh)
LO
N
Read Parameter Page can read out the device’s parameter data structure, such as, manufacturer
information, device organization, timing parameters, key features, and other pertinent device parameters.
The data structure is stored with at least three copies in the device’s parameter page. The Random Data
Output command is supported during data output.
IOx
ECh
Figure 11 Read Parameter Page Sequence
00h
P0
P1
…
P1023
tR
R/B#
Table 9 Parameter Definition
Byte Number
Descriptions
Values
0~3
Parameter Page Signature, "ONFI" ASCII characters
4Fh 4Eh 46h 49h
4~5
Revision Number
02h 00h
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Longsys Copyright
2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Byte Number
Descriptions
Values
Feature Supported
b6-b15 reserved (0)
6~7
b5
1 = supports source synchronous
b4
1 = supports odd to even page Copy-back
b3
1 = supports interleaved operations
b2
1 = supports non-sequential page programming
b1
1 = supports multiple LUN operations
b0
1 = supports 16-bit data bus width
10h 00h
Optional Command Supported
10~31
1 = supports Read Unique ID
b4
1 = supports Copyback
b3
1 = supports Read Status Enhanced
b2
1 = supports Get Features and Set Features
b1
1 = supports Read Cache commands
b0
1 = supports Page Cache Program command
34h 00h
SY
8~9
b5
S
b6-b15 reserved (0)
Reserved (0)
all 00h
46h 4Fh 52h 45h
32~43
Device manufacturer, 12 ASCII characters
53h 45h 45h 20h
64
65-66
46h 53h 4Eh 53h
38h 41h 30h 30h
32h 47h 20h 20h
20h 20h 20h 20h
20h 20h 20h 20h
JEDEC MID
CDh
Date Code
00h 00h
Reserved (0)
all 00h
LO
67-79
Device Model, 20 ASCII characters
N
44-63
G
20h 20h 20h 20h
80-83
Number of Data Bytes per Page
00h 08h 00h 00h
84-85
Number of Spare Bytes per Page
40h 00h
86-89
Number of Data Bytes per Partial Page
00h 02h 00h 00h
90-91
Number of Spare Bytes per Partial Page
10h 00h
92-95
Number of Pages per Block
40h 00h 00h 00h
96-99
Number of Block per Logic Unit
00h 08h 00h 00h
Number of Logic Units
01h
100
Number of Address Bytes
101
b4-b7 column address cycles
23h
b0-b3 row address cycles
102
Number of Bits per Cell
01h
103-104
Bad Blocks Maximum per Logic Unit
28h 00h
105-106
Block Endurance
01h 05h
Guaranteed Valid Blocks at Beginning of Target
01h
Block Endurance for Guaranteed Valid Blocks
01h 03h
107
108-109
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Byte Number
110
Descriptions
Values
Number of Programs per Page
04h
Partial Programming Attributes
b5-b7 reserved (0)
111
b4
1 = partial page layout is partial page data
followed by partial page spare
00h
b1-b3 reserved (0)
b0
112
1 = partial page programming has constraints
Number of ECC Bits Correctability
01h
Number of Interleaved Address Bits
b4-b7 reserved (0)
00h
b0-b3 number of interleaved address bits
Interleaved Operation Attributes
b4-b7 reserved (0)
115-127
128
b3
address restrictions for program cache
b2
1 = program cache supported
b1
1 = no block address restrictions
b0
overlapped / concurrent interleaving support
SY
114
S
113
Reserved (0)
00h
all 00h
I/O Pin Capacitance, Maximum
08h
G
Asynchronous Timing Mode Support
b6-b15 reserved (0)
1 = supports timing mode 5
b4
1 = supports timing mode 4
b3
1 = supports timing mode 3
b2
1 = supports timing mode 2
b1
1 = supports timing mode 1
b0
1 = supports timing mode 0, shall be 1
1Fh 00h
N
129-130
b5
LO
Asynchronous Program Cache Timing Mode Support
b6-b15 reserved (0)
131-132
b5
1 = supports timing mode 5
b4
1 = supports timing mode 4
b3
1 = supports timing mode 3
b2
1 = supports timing mode 2
b1
1 = supports timing mode 1
b0
1 = supports timing mode 0, shall be 1
00h 00h
133-134
tPROG Maximum Page Program Time (us)
BCh 02h
135-136
tBERS Maximum Block Erase Time (us)
10h 27h
137-138
tR Maximum Page read Time (us)
19h 00h
139~140
tCCS Minimum Change Column Setup Time (ns)
3Ch 00h
141-163
Reserved (0)
all 00h
164-165
Vendor Specific Revision Number
00h 00h
166-253
Vendor Specific
all 00h
254-255
Integrity CRC
85h B3h
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Byte Number
Descriptions
256-511
Value of Bytes 0-255
512-767
Value of Bytes 0-255
768+
Values
Additional Redundant Parameter Pages
Note:
(1)
The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were
transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the
following 16-bit generator polynomial: G(X) = X16 + X15 +X2 + 1
10.2.6 Read Unique ID (EDH)
SY
S
The unique ID is 32-byte and with 16 copies for back-up purpose. After writing the Unique ID read
command and following the one address byte (00h), the host may read out the unique ID data. The host
need to XOR the 1st 16-byte unique data and the 2nd 16-byte complement data to get the result, if the
result is FFh, the unique ID data is correct; otherwise, host need to repeat the XOR with the next copy of
Unique ID data.
Once sending the EDh command, the NAND device will remain in the Unique ID read mode until next
valid command is sent. The Random Data Output command is supported during data output.
G
The Read Status command can be used to check the completion. To continue the read operation, a
following read command (00h) to re-enable the data out is necessary.
IOx
EDh
UID 0
Do 0
00h
LO
R/B#
N
Figure 12 Read Unique ID Sequence
UID 0
Do 1
UID 0
Do 31
UID 1
Do 0
Busy
Figure 13 Read Unique ID Sequence with Random Data Output
IOx
EDh
00h
UID 0
Do 0
UID 0
Do 1
05h
1st Add
Cyc.
2nd Add
Cyc.
E0h
UID m
Do n
UID m
Do n+1
R/B#
Repeat if needed
Busy
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
10.3 Program Operation
10.3.1 Page Program (80h-10h)
The device is programmed basically on a page basis, but it does allow multiple partial page programming
of a byte or consecutive bytes up to 2,112 in a single page program cycle. The number of consecutive
partial page programming operation within the same page without an intervening erase operation must
NOT exceed 4 times for a single page. The addressing should be done in sequential order in a block.
S
A page program cycle consists of a serial data loading period in which up to 2,112-bytes of data may be
loaded into the page buffer, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell.
SY
The serial data loading period begins by inputting the 80h command, followed by the five cycle address
inputs and then serial data loading. The bytes other than those to be programmed do not need to be
loaded. The 10h command initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process.
N
G
The internal write state controller automatically exe-cutes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process
starts, the Read Status command may be entered to read the status register. The system controller can
detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (IO6) of the
Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status bit (IO 0) may be checked (See Figure
14). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to
the command register.
LO
Figure 14 Page Program Sequence
tPROG
R/B#
IOx
80h
Address &
Data input
0
10h
70h
I/O0
Col.Add.1,2 & Row Add.1,2,3
Data
Pass
1
Fail
10.3.2 Random Data Input (85h)
After the Page Program 80h command execution of the initial data has been loaded into the page buffer,
if the need for additional writing of data is required, using the Random Data Input command can perform
this function to a new column address prior to the 10h command. The Random Data Input may be
operated multiple times regardless of how many times it is done in a page.
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FSNS8A002G
Datasheet
Figure 15 Page Program with Random Data Input Sequence
tPROG
R/B#
0
IOx
80h
Address &
Data input
Address &
Data input
85h
Col.Add.1,2 & Row Add.1,2,3
Data
10h
70h
I/O0
Col.Add.1,2
Data
Pass
1
Fail
S
10.4 Copy Back Operation
SY
Copy Back operations can quickly and efficiently rewrite data stored in one page. The benefit is
especially obvious when a portion of a block is updated and the rest of the block also needs to be copied
to the newly assigned free block. The operations require two sequential command sets. Issue a Copy
Back Read command first, then the Copy Back Program command.
G
Since Copy Back operations do not use external memory and the data of source page might include a bit
errors, a competent ECC scheme should be developed to check the data before programming data to a
new destination page.
N
Note: Copy Back Operation can only be used to copy even page to even page or to copy odd page to
odd page.
10.4.1 Copy Back Read (00h-35h)
LO
The Copy Back Read command is used together with the Copy Back Program command. To start
execution, 00h command is written to the command register, followed by the five cycles of the source
page address. To start the transfer of the selected page data from the memory array to the page buffer,
write the 35h command to the command register.
After execution of the Copy Back Read command sequence and R/B# returns to HIGH marking the
completion of the operation, the transferred data from the source page into the page buffer may be read
out by toggling RE#. Data is output sequentially from the column address that was originally specified
with the Copy Back Read command (See Figure 16).
The Random Data Output commands can be issued multiple times without any limitation after Copy Back
Read command has been executed.
10.4.2 Copy Back Program (85h-10h)
After the Copy Back Read command operation has been completed and R/B# goes HIGH, the Copy
Back Program command can be written to the Command Register.
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Datasheet
The operation is initiated by issuing 85h command with destination page address. Actual programming
operation begins after 10h command is issued. Once the program process starts, the Read Status
command may be entered to read the status register. The system controller can detect the completion of
a program cycle by monitoring the R/B# output, or the Status bit (IO6) of the Status Register. When the
copy back program is complete, the Write Status Bit (IO0) may be checked (See Figure 16). The
command register remains in Read Status command mode until another valid command is written to the
command register.
S
During copy-back program, data modification is possible using Random Data Input command with
multiple times (see Figure 17).
SY
Note: Copy back program operation is allowed only within the same memory plane, which means the
address A28 of destination page must be the same as that of source page.
Figure 16 Copy Back Read and Copy Back Program Sequence
tR
R/B#
IOx
00h
Add.(5Cycles)
tPROG
Data Output
35h
Col.Add.1,2 & Row Add.1,2,3
Source Address
85h
Add.(5Cycles)
70h
10h
0
I/O0
G
Col.Add.1,2 & Row Add.1,2,3
Destination Address
Pass
1
Fail
R/B#
tPROG
tR
00h
Add.(5Cycles)
35h
LO
IOx
N
Figure 17 Copy Back Program with Random Data Input Sequence
Col.Add.1,2 & Row Add.1,2,3
Source Address
Data Output
85h
Add.(5Cycles) Data
Col.Add.1,2 & Row Add.1,2,3
Destination Address
85h
Add.(2Cycles) Data
10h
70h
Col.Add.1,2
There is no limitation for the number of repetition
10.5 Block Erase (60h-D0h)
The erase operation is done on a block basis. Block address loading is accomplished in two cycles
initiated by 60h command. Only address A18 to A28 is valid while A12 to A17 is ignored. The D0h
command following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by execution command ensures that memory contents are not accidentally
erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles
erase and erase-verify. The system controller can detect the completion of an erase cycle by monitoring
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Datasheet
the R/B# output, or the Status bit (IO6) of the Status Register. When the block erase operation is
complete, the Write Status Bit (IO0) may be checked.
Figure 18 Block Erase Sequence
tBERS
R/B#
0
IOx
Address
Input(3cycle)
60h
D0h
I/O0
70h
Row Add 1,2,3
Pass
1
S
Fail
SY
10.6 Feature Operation
10.6.1 Feature Register
G
The Feature Set operation is to change the default power-on feature sets by using the Set Feature and
Get Feature command and writing the specific parameter data (P1-P4) on the specific feature addresses.
The NAND device may remain the current feature set until next power cycle since the feature set data is
volatile. However, the reset command cannot reset the current feature set.
Table 10 Feature Register
Register
Address
Parameter
LO
P1
Operation
Mode
90h
Protection
IO6
IO5
IO4
IO3
IO2
IO1
IO0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
P2
Reserved (0)
P3
Reserved (0)
P4
Reserved (0)
P1
Block
IO7
N
Feature
Description
Normal Mode, default value
after power cycle.
OTP Operation Mode. See
10.7.1 for detail information
OTP Lock Mode. See 10.7.2
for detail information
Default value after power
R
BP3
BP2
BP1
BP0
TB
0
SP
cycle is 00000000 (00h).
See 10.8 for detail
information
A0h
P2
Reserved (0)
P3
Reserved (0)
P4
Reserved (0)
Note:
(1) R: Reserved Bit and has no function. They may be read out as a “0” or “1”. It is recommended to ignore the values of those
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Datasheet
bits. During a Set Feature command, the Reserved Bits can be written as “0”, but there will not be any effects.
10.6.2 Get Feature (EEh)
The Get Feature command is to read feature parameter. After sending the Get Feature command and
following register address, the host may read out the P1-P4 sub-feature parameter data. Once sending
the EEh command, the NAND device will remain in the Get Feature mode until next valid command is
sent.
S
The Status Read command can be used to check the completion. To continue the read operation, a
following 00h command to re-enable the data out is necessary.
Figure 19 Get Feature Sequence
SY
CLE
WE#
RE#
IOx
EEh
FA
P1
P2
P3
P4
tFEAT
N
R/B#
G
ALE
LO
10.6.3 Set Feature (EFh)
The Set Feature command is to change the power-on default feature set. After sending the Set Feature
command and following register address and then input the P1-P4 parameter data to change the feature
set. Once sending the EFh command, the NAND device will remain in the Set Feature mode until next
valid command is sent. The Status Read command may check the completion of the Set Feature.
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Figure 20 Set Feature Sequence
CLE
WE#
ALE
RE#
EFh
FA
P1
P2
P3
P4
S
IOx
tFEAT
SY
R/B#
10.7 OTP Operation
G
The OTP area has 62 pages (62 x 2,112-byte). It is a non-erasable and one-time programmable area,
which is default to “1” and allows whole page or partial page program to be “0”. Once the OTP protection
mode is set, the OTP area becomes read-only and cannot be programmed again.
N
The OTP operation is operated by the Set Feature / Get Feature operation to access the OTP Operation
Mode and OTP Lock Mode.
To check the NAND device is ready or busy in the OTP operation mode, either checking the R/B# or
using the Read Status command to check the status.
LO
To exit the OTP operation or protect mode, it can be done by writing 00h to P1 at feature address 90h.
10.7.1 OTP Read / Program Operation
To enter the OTP Operation Mode, it is by using the Set Feature command and followed by the feature
address 90h and then input the 01h to P1 and 00h to P2-P4 of sub-Feature Parameter data (see Table
10 Feature Register).
After enter the OTP Operation Mode, the OTP area can be read or programmed like non-OTP area. The
address of OTP is located on the 000002h-00003Fh of page address.
10.7.2 OTP Lock Operation
To prevent the further OTP data to be changed, the OTP lock operation is necessary. To enter the OTP
Lock Mode, it can be done by using the Set Feature command and followed by the feature address 90h
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Datasheet
and then input the 03h to P1 and 00h to P2-P4 of sub-Feature Parameter data (see Table 10 Feature
Register). And then the normal Page Program command with the address 00h before the 10h command
is required.
The OTP lock operation is operated on the whole OTP area instead of individual OTP page. Once the
OTP protection mode is set, the OTP area can NOT be programmed or unprotected again.
Figure 21 OTP Lock Operation Sequence
IOx
80h
00h
5 Add. cyc.
00h
10h
Status
Output
70h
Dummy data input
S
tPROG
SY
R/B#
10.8 Block Protection
G
The block protect operation can protect the whole chip or selected blocks from erasing or programming.
When program or erase attempt at a protected block is happened, the R/B# keeps low for the time of
tPBSY, and the Status Read command may get the 41h result.
N
At power-on, all the blocks are default to be un-protected. The Set Feature command with feature
address A0h followed by the destined protection bits with data “1” is necessary to protect those selected
blocks. After the selected blocks are protected, those protected blocks can be un-protected again by
reset Block Protection Bit to “0” if required.
LO
The “solid-protection” feature can be set by writing the Set Feature command with feature address A0h
and the “SP” solid protection bit as “1” (see Table 10 Feature Register), after that, the selected block is
solid-protected and cannot be up-protected until next power cycle.
Table 11 Block Protection Bits
Protected
Protected Page
Protected
Protected
Block(s)
Address PA[16:0]
Density
Portion
0
NONE
NONE
NONE
NONE
0
1
2047
1FFC0h – 1FFFFh
128KB
Upper 1/2048
0
1
0
2046 & 2047
1FF80h – 1FFFFh
256KB
Upper 1/1024
0
0
1
1
2044 thru 2047
1FF00h – 1FFFFh
512KB
Upper 1/512
0
0
1
0
0
2040 thru 2047
1FE00h – 1FFFFh
1MB
Upper 1/256
0
0
1
0
1
2032 thru 2047
1FC00h – 1FFFFh
2MB
Upper 1/128
0
0
1
1
0
2016 thru 2047
1F800h – 1FFFFh
4MB
Upper 1/64
0
0
1
1
1
1984 thru 2047
1F000h – 1FFFFh
8MB
Upper 1/32
0
1
0
0
0
1920 thru 2047
1E000h – 1FFFFh
16MB
Upper 1/16
TB
BP3
BP2
BP1
BP0
X
0
0
0
0
0
0
0
0
0
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
1
0
0
1
1792 thru 2047
1C000h – 1FFFFh
32MB
Upper 1/8
0
1
0
1
0
1536 thru 2047
18000h – 1FFFFh
64MB
Upper 1/4
0
1
0
1
1
1024 thru 2047
10000h – 1FFFFh
128MB
Upper 1/2
1
0
0
0
1
0
00000h – 0003Fh
128KB
Lower 1/2048
1
0
0
1
0
0&1
00000h – 0007Fh
256KB
Lower 1/1024
1
0
0
1
1
0 thru 3
00000h – 000FFh
512KB
Lower 1/512
1
0
1
0
0
0 thru 7
00000h – 001FFh
1MB
Lower 1/256
1
0
1
0
1
0 thru 15
00000h – 003FFh
2MB
Lower 1/128
1
0
1
1
0
0 thru 31
00000h – 007FFh
4MB
Lower 1/64
1
0
1
1
1
0 thru 63
00000h – 00FFFh
8MB
Lower 1/32
1
1
0
0
0
0 thru 127
00000h – 01FFFh
16MB
Lower 1/16
1
1
0
0
1
0 thru 255
00000h – 03FFFh
32MB
Lower 1/8
1
1
0
1
0
0 thru 511
00000h – 07FFFh
64MB
Lower 1/4
1
1
0
1
1
0 thru 1023
00000h – 0FFFFh
128MB
Lower 1/2
X
1
1
X
X
0 thru 2047
00000h – 1FFFFh
256MB
ALL
SY
10.9 Write Protect
S
0
N
G
WP# pin can enable or disable program and erase commands preventing or allowing program and erase
operations. Figure 22 to Figure 27 shows the enabling or disabling timing with WP# setup time (t WW) that
is from rising or falling edge of WP# to latch the first commands. After first command is latched, WP# pin
must not toggle until the command operation is complete and the device is in the ready state. (Status
Register Bit6 (IO6) equal 1).
Figure 22 Erase Enable
LO
WE#
tww
IOx
60h
D0h
WP#
R/B#
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
Figure 23 Erase Disable
WE#
tww
60h
IOx
D0h
WP#
S
R/B#
WE#
tww
80h
WP#
N
R/B#
10h
G
IOx
SY
Figure 24 Program Enable
LO
Figure 25 Program Disable
WE#
tww
IOx
80h
10h
WP#
R/B#
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Datasheet
Figure 26 Program for Copy-Back Enable
WE#
tww
85h
IOx
10h
WP#
S
R/B#
WE#
tww
WP#
10h
LO
N
R/B#
85h
G
IOx
SY
Figure 27 Program for Copy-Back Disable
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2Gbit SLC NAND Flash
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Datasheet
11
Software Algorithm
11.1 Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is
not guaranteed. Devices with initial invalid block(s) have the same quality level as devices with all valid
blocks and have the same electrical characteristics. An initial invalid block(s) does not affect the
performance of valid block(s). The system design must be able to mask out the initial invalid block(s) via
address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
at the time of shipment.
Symbol
Min
Valid block number
NVB
2008
Max
Unit
2048
Blocks
SY
Parameter
S
Table 12 Valid Block Number
11.2 Identifying Initial Invalid Block(s)
N
G
All device locations are erased (FFh) except locations where the initial invalid block(s) information is
written prior to shipping. All initial invalid blocks are marked with non-FFh at the first byte of spare area
on the 1st or 2nd page. Since the initial invalid block information is also erasable in most cases, it is
impossible to recover the information once it has been erased. Therefore, the system must be able to
recognize the initial invalid block(s) based on the original initial invalid block information and create the
initial invalid block table via the suggested flow (Figure 28). Any intentional erasure of the original initial
invalid block information is prohibited.
LO
Figure 28 Flow to Create Initial Invalid Block Table
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Datasheet
11.3 Error in Operation
Table 13 Failure Modes
Operation
Program
Read
Detection and recommended procedure
Status read after erase → Block Replacement
SY
Erase
S
Within its life time, additional invalid blocks may develop with NAND Flash memory. The following
possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail
during a page program does not affect the data of the other pages in the same block, block replacement
can be executed with a page-sized buffer by finding an erased empty block and reprogramming the
current target data and copying the rest of the replaced block. In case of Read, ECC must be employed.
To improve the efficiency of memory space, it is recommended that the read or verification failure due to
single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate
does not include those reclaimed blocks.
Status read after program → Block Replacement
Verify ECC → ECC correction
LO
N
G
Figure 29 Bad Block Replacement
11.4 Addressing for Program Operation
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of
the block to the MSB(most significant bit) pages of the block. The LSB page is defined as the start page
among the pages to be programmed, does not need to be page 0 in the block. Random page address
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Datasheet
programming is prohibited.
SY
S
Figure 30 Addressing for Program Operation
11.5 System Interface Using CE# Don’t-Care
N
G
For an easier system interface, CE# may be inactive during the data-loading or serial access as shown
below. The internal 2,112 bytes data registers are utilized as separate buffers for this operation and the
system design gets more flexible. In addition, for voice or audio applications which use slow cycle time
on the order of μ-seconds, de-activating CE# during the data-loading and serial access would provide
significant savings in power consumption.
Figure 31 Program Operation with CE# don’t-care
LO
CLE
CE# don ,t-care
CE#
WE#
ALE
IOx
80h
Address(5Cycles)
tCS
Data Input
Data Input
80h
tCH
CE#
tWP
WE#
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Figure 32 Read Operation with CE# don’t-care
CLE
CE# don ,t-care
CE#
RE#
ALE
S
RB
IOx
00h
Address(5Cycles)
SY
WE#
Data Output(serial access)
30h
tCEA
CE#
tREA
G
RE
out
LO
N
I/O0~7
Everything for Memory
34 / 53
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2Gbit SLC NAND Flash
FSNS8A002G
Datasheet
12
Electrical Characteristics
12.1 Absolute Maximum Ratings
Table 14 Absolute Maximum Rating
Symbol
Range
Unit
Supply Voltage
VCC
–0.6 to +4.6
V
Voltage Applied to Any Pin
VIO
–0.6 to VCC+0.4
V
Temperature under Bias
TBIAS
–40 to +125
°C
Storage Temperature
TSTG
–65 to +150
°C
S
Parameters
Short circuit output current, I/Os
IOS
Note:
mA
Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
SY
(1)
5
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