1Gbit SPI NAND Flash
F35UQA001G
Datasheet
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SPI NAND Flash
F35UQA001G
Datasheet
LM-00001
Rev 1.3
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LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONSser
2
u
B01 WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein
受控is provided on an
“AS IS” basis, without warranties of any kind. All brand names, trademarks and registered trademarks belong to their respective
owners.
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This document and all information discussed herein remain the sole and exclusive property of Longsys Electronics. No license
of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party
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For updates or additional information about-Longsys
2 0 products, contact your nearest Longsys office.
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© 2022 Shenzhen B
Longsys
5 Electronics Co., Ltd. All rights reserved.
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under this document, by implication, estoppel or other-wise.
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Revision History
Rev.
Date
1.0
2020/01/28
Initial release
1.1
2021/11/22
Revise descriptions in 4, 12.5, 12.7, 12.8, 14.1.
1.2
2021/12/3
Add Chap 14
1.3
2022/1/13
Chap 3 Add Tape & Reel
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Content
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Content....................................................................................................................................................
1BB 3
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2
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1 General Description ........................................................................................................................
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2 Features ...........................................................................................................................................
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3 Product List .....................................................................................................................................6
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Revision History .....................................................................................................................................2
4
Package Types and Pin Configurations .........................................................................................7
5
Pin Descriptions .............................................................................................................................. 8
6
Block Diagram .................................................................................................................................9
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Array Organization and Mapping .................................................................................................10
2802Device Operation ........................................................................................................................... 11
8.1
8.2
8.3
8.4
General ................................................................................................................................................11
SPI Modes ...........................................................................................................................................11
Hold Function .................................................................................................................................... 12
Write Protection ................................................................................................................................ 12
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9 Status Registers ............................................................................................................................
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9.1
Protection Register (SR-1) ............................................................................................................... 15
9.1.1 Block Protect Bits (BP3-0, TB) ...........................................................................................................................
15
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9.1.2
Status Register Protect Bits (BPRWD, SP) .......................................................................................................... 15
9.1.3
Status Register Memory Protection .................................................................................................................. 16
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9.2
Configuration Register (SR-2) ......................................................................................................... 16
9.2.1 One Time Program Lock Bit (OTP-L) .................................................................................................................. 16
9.2.2 Enter OTP Access Mode Bit (OTP-E) .................................................................................................................. 17
9.2.3 ECC Enable Bit (ECC-E) ..................................................................................................................................... 17
9.2.4 Output Driver Strength (DRV1-0) ...................................................................................................................... 17
9.2.5 Quad Enable Bit (QE) ....................................................................................................................................... 17
9.3
Status Register (SR-3) ...................................................................................................................... 17
9.3.1 ECC Status Bit (ECCS1-0)................................................................................................................................... 17
9.3.2 Program/Erase Failure (P-FAIL, E-FAIL) .............................................................................................................. 18
9.3.3 Write Enable Latch (WEL) ................................................................................................................................. 18
9.3.4 Operation in Progress (OIP) .............................................................................................................................. 18
9.4
Sector ECC Status Register (Sector0-3 ECC Status) .................................................................... 18
9.4.1 Sector Information........................................................................................................................................... 19
9.4.2 Sector ECC Status ............................................................................................................................................. 19
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10 Commands .....................................................................................................................................20
10.1
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1
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Command Set .................................................................................................................................... 20
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F35UQA001G
Datasheet
10.2 Soft Reset (FFh) ................................................................................................................................ 21
10.3 Read JEDEC ID (9Fh) ........................................................................................................................ 22
10.4 Feature Operations ........................................................................................................................... 22
10.4.1
Get Feature (0Fh) and Set Feature (1Fh) ....................................................................................................... 22
10.4.2
Write Enable (WREN, 06h) ........................................................................................................................... 23
10.4.3
Write Disable (WRDI, 04h) ........................................................................................................................... 24
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10.5 Read Operations ............................................................................................................................... 24
10.5.1
Page Read (13h)........................................................................................................................................... 24
10.5.2
Read From Cache (03h or 0Bh) ..................................................................................................................... 25
10.5.3
Read From Cache x 2 (3Bh) .......................................................................................................................... 25
10.5.4
Read From Cache x 4 (6Bh) .......................................................................................................................... 26
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10.6 Program Operations ......................................................................................................................... 26
10.6.1
Page Program .............................................................................................................................................. 26
10.6.2
Program Data Load (02h) / Random Program Data Load (84h) ...................................................................... 27
10.6.3
Program Data Load x 4 (32h) / Random Program Data Load x 4 (34h) ........................................................... 27
10.6.4
Program Execute (10h)................................................................................................................................. 28
10.6.5
Internal Data Move ...................................................................................................................................... 29
10.7 Block Erase Operations ................................................................................................................... 29
10.8 UID / Parameter / OTP Pages ........................................................................................................... 30
10.8.1
Read UID / Parameter / OTP Pages ............................................................................................................... 30
10.8.2
Program OTP Pages and OTP Lock Operation ................................................................................................ 31
10.8.3
Parameter Page Data Definition ................................................................................................................... 31
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11 Software Algorithm .......................................................................................................................
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11.1 Initial Invalid Block(s) ....................................................................................................................... 33
11.2 Identifying Initial Invalid Block(s) ....................................................................................................
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11.3
11.4
11.5
Error in Operation ............................................................................................................................. 34
Internal ECC ....................................................................................................................................... 34
Addressing for Program Operation ................................................................................................ 35
12.6
12.7
12.8
AC Measurement Conditions........................................................................................................... 38
AC Electrical Characteristics ........................................................................................................... 38
Read / Program / Erase Characteristics ......................................................................................... 39
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12.1 Absolute Maximum Ratings ............................................................................................................. 36
B5 Operating Ranges ............................................................................................................................. 36 ers.
F12.2
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B01 12.3 Power-up and Power-down Timing Requirements........................................................................u36s
12.4 Pin Capacitance ................................................................................................................................ 37
12.5 DC Electrical Characteristics ...........................................................................................................
38
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15 Packaging Information
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13 Timing Diagram ............................................................................................................................. 40
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B0
1Gbit SPI NAND Flash
F35UQA001G
Datasheet
1
General Description
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The F35UQA001G is a 1G-bit (128Mx8bit) Serial NAND Flash Memory, operates on a single 1.8V VCC.
The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad SPI: Serial Clock, Chip
Select, Serial Data SIO0 (DI), SIO1 (DO), SIO2 (WP#) and SIO3 (HOLD#). SPI clock frequencies of up
to 66 MHz are supported.
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The F35UQA001G supports JEDEC standard manufacturer and device ID, Unique ID, one parameter
page and 62 OTP pages. An internal 1-bit ECC logic is available in the chip, which is enabled by default.
The internal ECC can be disabled or enabled by command.
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Features
5 0
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2
2
0 Supply
2Voltage
Advanced Features
- On chip 1-Bit ECC for memory array
- Software and Hardware write protect
- Unique ID
- One 2kB parameter page
- Sixty-two 2kB OTP Pages
- Promised golden block0
- VCC: 1.7V ~ 1.95V
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Organization
- Memory Cell Array: (128M + 4M) Byte
- Page Size: (2k + 64) Byte
- Block Size: 64 pages, (128k + 4k) Byte
Serial Interface
- Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#
- Dual SPI: CLK, CS#, SIO0-SIO1, WP#, HOLD#
- Quad SPI: CLK, CS#, SIO0-SIO3
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High Performance
2
- 66 5
MHz Standard/Dual/Quad SPI clocks
FB
124- Page Program Time: 350µs (Typ.)
- Block Erase Time: 2ms (Typ.)
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High Reliability
- Endurance: typical 100k cycles (1)
- Data Retention: 10 years (1)
Package
- 8-WSON (8x6mm)
.
(1) Endurance and Data Retention specification is based on
Low Power
- Standby: 10µA (Typ.)
- Page Read: 10mA (Typ.)
- Program/Erase: 15mA (Typ.)
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Note:
1bit / 528Byte ECC
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
3
Product List
Table 1 Product List
24
F35UQA001G-WWT
1Gb
x1, x2, x4
1.7V~1.95V
8-WSON (8x6mm)
-40°C ~ 85°C
TrayB01
C1B& Reel
F35UQA001G-WWR
1Gb
x1, x2, x4
1.7V~1.95V
8-WSON (8x6mm)
-40°C ~ 85°C 12Tape
8D
F35UQA001G-WAT
1Gb
x1, x2, x4
1.7V~1.95V
8-WSON (8x6mm)
-40°C.
~A
105°C
Tray
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Figure 1 Marketing Part Numbering Chart
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F 35 U Q A 001G - W W T Packing
Part Number
Density
I/O Type
Voltage Range
Temp. Range
Packing
FB
T = Tray
R = Tape & Reel
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2202
Package
5 0
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Temp. Range
W = -40°C~85°C
A = -40°C~105°C
3 = AECQ100 G3
2 = AECQ100 G2
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001G = 1Gbit use
Version
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受 A = Version A
Package
W = 8-WSON
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Voltage Range
U = 1.7V~1.95V
Product Type
35 = Serial SLC NAND
Brand
F = FORESEE
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I/O Type
Q = x1, x2, x4 & ECC Free
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F35UQA001G
Datasheet
4
Package Types and Pin Configurations
Figure 2 Pin Configuration 8-WSON (8x6mm)
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CS# 1
8
DO/SIO1 2
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WP#/SIO2 3
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GND 4
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HOLD#/SIO3
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
5
Pin Descriptions
Table 2 Pin Description
Pin Name
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Pin Functions
FB
C1B
2
1
D devices power
A8the
the Serial Data Output (DO or SIO0-3) pins are at high impedance. When deselected,
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consumption will be at standby levels unless an internal erase, program
usorewrite status register cycle is in
progress. When CS# is brought low the device will be selected, power consumption will increase to active levels
and instructions can be written to and data read from the
受控device. After power-up, CS# must transition from high
Chip Select
The SPI Chip Select pin enables and disables device operation. When CS# is high the device is deselected and
CS#
to low before a new instruction will be accepted.
Serial Data Input, Output and IOs
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The device supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the
unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of
2the5Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status
7
2-0 from the device on the falling edge of CLK. Dual and Quad SPI instructions use the bidirectional IO pins to
DI, DO and
SIO0-SIO3
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serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status
from the device on the falling edge of CLK.
4
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B
B
The WP# pin can be used to prevent the Status Register from being written. Used in conjunction with the Status
C1
2
1
Register’s Block Protect bits (BP[3:0], TB) and Status Register Protect bits (BPRWD, SP), a portion
8D as small as
A
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256k-Byte (2x128kB blocks) or up to the entire memory array can be hardware protected.
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Hold
During Standard and Dual SPI operations, the HOLD# pin allows the device to be paused while it is actively
受the控DO pin will be at high impedance and signals on
selected. When HOLD# is brought low, while CS# is low,
Write Protect
WP#
HOLD#
5
FBCLK
4
2
B01
GND
VCC
NC
the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device operation can resume.
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active low.
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When a Quad
2- SPI Read/Program Data Load command is issued, HOLD# pin will become a data I/O pin for the
2
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2Quad operations and no HOLD function is available until the current Quad operation finishes.
The HOLD function can be useful when multiple devices are sharing the same SPI signals. The HOLD# pin is
Serial Clock
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.
Ground
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VCC
Power Supply
No Connection
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
6
Block Diagram
Figure 3 Block Diagram
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Serial NAND controller
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CLK
CS#
SIO0-SIO3
VCC
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Page
Buffer
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GND
0
ECC and Status
Register
NAND
Memory
Core
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B01
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F35UQA001G
Datasheet
7
Array Organization and Mapping
Figure 4 Array Organization
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64K Pages
(=1,024 Blocks)
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1 Page = (2K + 64) Bytes
1 Block = 64 Pages
受控 = (128K + 4K) Bytes
1 Block = 64 Pages
(128K + 4K) Bytes
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52K0Bytes
2
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2-0
1 Device = 1,024 Blocks
= 1,024 x (128K + 4K) Bytes
= 1,056 Mbits
8 Bits
64 Bytes
Page Buffer
2K Bytes
4
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BB0
64 Bytes
Figure 5 Address Mapping
Block# 1023
FB5
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2
B01
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Byte# 2111
Page# 0
Block address
PA[15:6]
Page address
PA[5:0]
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Page# 63
Block# 0
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Byte#
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Byte address
CA[11:0]
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
8
Device Operation
8.1
General
1.
2.
3.
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Before a command is issued, status register should be checked via get features operations to
ensure device is ready for the intended operation.
When incorrect command is inputted to this device, this device becomes standby mode and keeps
the standby mode until next CS# falling edge. In standby mode, SIO pin of this device should be
High-Z.
When correct command is inputted to this device, this device becomes active mode and keeps the
active mode until next CS# rising edge.
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8.2 SPI Modes
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2
2
0 NAND supports two SPI modes:
2SPI
•
•
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
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Input data is latched on the rising edge of CLK and data shifts out on the falling edge of CLK for both
modes. All timing diagrams shown in this data sheet are mode 0. The difference of Mode 0 and Mode 3 is
shown as Figure 6.
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Figure 6 SPI Mode Supported
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CLK
0
(SPI Mode 0) 0
0
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0
(SPI Mode 3) 1
2-0 CLK
2
0
2
SI
FB5
4
2
1
0
B
CPOL
CPHA
shift in
shift out
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MSB
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SO
MSB
Standard SPI
SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO).
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Dual SPI
SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These
commands allow data to be transferred to or from the device at two times the rate of the standard SPI.
When using the Dual SPI command the DI and DO pins become bidirectional I/O pins: SIO0 and SIO1.
B0
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1
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Quad SPI
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These
commands allow data to be transferred to or from the device at four times the rate of the standard SPI.
When using the Quad SPI command the DI and DO pins become bidirectional I/O pins: SIO0 and SIO1,
and WP# and HOLD# pins become SIO2 and SIO3.
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C1B
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Hold Function
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For Standard SPI and Dual SPI operations, the HOLD# signal allows the device operation to be paused
while it is actively selected (when CS# is low). The Hold function may be useful in cases where the SPI
data and clock signals are shared with other devices. For example, consider if the page buffer was only
partially written when a priority interrupt requires use of the SPI bus. In this case the Hold function can
save the state of the instruction and the data in the buffer so programming can resume where it left off
once the bus is available again. The Hold function is only available for standard SPI and Dual SPI
operation, not during Quad SPI. When a Quad SPI command is issued, HOLD# pin will act as a
dedicated IO pin (SIO3).
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BB0
To initiate a HOLD condition, the device must be selected with CS# low. A HOLD condition will activate
on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the
HOLD condition will activate after the next falling edge of CLK. The HOLD condition will terminate on the
rising edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD
condition will terminate after the next falling edge of CLK. During a HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and serial Clock (CLK) are ignored. The Chip
Select (CS#) signal should be kept active (low) for the full duration of the HOLD operation to avoid
resetting the internal logic state of the device. See Figure 7 for more details.
C1
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CS#
FB5CLK
4
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B01
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HOLD#
(SIO3)
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Active
Hold
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Write Protection
Active
Hold
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Active
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The device provides several means to protect the data from inadvertent writes.
• Device resets when VCC is below threshold
• Write enable/disable instructions and automatic write disable after erase or program
B0
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1
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
•
•
•
Software and Hardware (WP# pin) write protection using Protection Register (SR-1)
Lock Down write protection for Protection Register (SR-1) until the next power-up
One Time Program (OTP) write protection for memory array using Protection Register (SR-1)
24
1
0
B
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Program Execute or
Block Erase instruction will be accepted. After completing a program or erase instruction the Write
Enable Latch (WEL) is automatically cleared to a write-disabled state of 0.
FB
C1B
2
1
A8D
.
s
r
use
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (BPRWD, SP) and Block Protect (TB, BP[3:0]) bits. These settings allow a
portion or the entire memory array to be configured as read only. Used in conjunction with the WP# pin,
changes to the Status Register can be enabled or disabled under hardware control. See
受控
50
:
9
0
Protection Register (SR-1) for further information.
202
25
7
2-0
4
12
BB0
C1
2
1
A8D
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r
use
受控
FB5
4
2
B01
0
9:5
0
-25
7
0
22
0
2
.
rs
e
s
u
受控
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
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0
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
9
Status Registers
Three Status Registers are: Protection Register (SR-1), Configuration Register (SR-2) and Status
Register (SR-3). Each register is accessed by Get Feature (0Fh) and Set Feature (1Fh) commands
combined with 1-Byte Register Address respectively.
24
1
0
B
C1B
2
1
D
A8combined
Four Sector ECC Status Registers can be accessed by Get Feature (0Fh) command
with
.
s
r
e
1-Byte Register Address respectively.
us
Table 3 Status Registers
Data Bits
受控
Register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BPRWD
BP3
BP2
BP1
BP0
TB
R
SP
OTP-E
R
ECC-E
R
DRV1
DRV0
QE
R
ECCS1
ECCS0
P-FAIL
E-FAIL
WEL
OIP
R
R
0
0
S0ES3
S0ES2
S0ES1
S0ES0
84h
R
R
0
1
S1ES3
S1ES2
S1ES1
S1ES0
88h
R
R
1
0
S2ES3
S2ES2
8Ch
R
R
1
1
S3ES3
Protection
A0h
Configuration
B0h
0
9:5R
OTP-L
0
Sector0 ECC -25
-07 80h
Status
2
2
0 ECC
2Sector1
Status
C0h
Status
4
Sector2 ECC
Status
Sector3 ECC
Status
Note:
12
BB0
C1
2
1
A8D S3ES0
S3ES2 s.
S3ES1
r
use
S2ES1
S2ES0
受控
(1) R: Reserved Bit and has no function. They may be read out as a “0” or “1”. It is recommended to ignore the values of those
bits. During a Set Feature command, the Reserved Bits can be written as “0”, but there will not be any effects.
0
9:5
0
-25
7
0
22
0
2
The Reset command (FFh) will not clear the previous feature setting, the feature setting data bits remain
until the power is being cycled or modified by the settings in the table below. After a Reset command is
issued, the OIP bit will go high. This bit can be polled to determine when the Reset operation is complete,
as it will return to the default value (0) after the reset operation is finished. Issuing the Reset command
has no effect on the Block Protection and Configuration registers.
FB5
4
2
B01
8D
FB
.
rs
e
s
u
受控
Table 4 Default Values of the Status Registers after power up and Device Reset
Register
Protection
Address
A0h
Bits
Shipment Default
Power Up
After Reset Command
BP3-0,TB
11111
11111
No Change
0
No Change
0
No Change
0
Locked:1, else 0
No Change
0
0
0
ECC-E
1
1
No Change
QE
0
0
0
DRV1-0
00
00
No Change
BPRWD
5
OTP-L 7-2
2-0
OTP-E
2
0
2
SP
B5
F
4
2
B01
Configuration
1B
C
2
1
Everything for Memory
B0h
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0
0
0
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Register
Address
Status
Bits
Shipment Default
Power Up
After Reset Command
ECCS1-0
00
Status of Page0 of Block0
00
P-FAIL
0
0
0
E-FAIL
0
0
0
WEL
0
0
0
OIP
0
C0h
Sector0 ECC Status
80h
S0ES3-0
0000
Sector1 ECC Status
84h
S1ES3-0
0000
Sector2 ECC Status
88h
S2ES3-0
0000
Sector3 ECC Status
8Ch
S3ES3-0
0000
9.1
24
1
0
B
FB
C1B
0 020 0
1
8D 0 0 0 0
Status of Page0 of Block0 s.A
er
Status of Page0 u
of s
Block0
0000
Status of Page0 of Block0
0000
控
受
0
0
Status of Page0 of Block0
Protection Register (SR-1)
0
5
:
9
9.1.1 Block Protect
5 0 Bits (BP3-0, TB)
2
The 2
Block
-07Protect bits (BP3-0, TB) are volatile read/write bits that provide Write Protection control and
2
0 Block Protect bits can be set using the Set Feature Instruction. All, none or a portion of the
2status.
memory array can be protected from Program and Erase instructions (See Table 6). The default values
for the Block Protection bits are 1 after power up to protect the entire array.
4
12
BB0
C1
2
1
9.1.2 Status Register Protect Bits (BPRWD, SP)
A8D
.
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r
usecontrol the method of
The Status Register Protect bits (BPRWD, SP) are volatile read/write bits which
write protection: software protection, hardware protection, power supply lock-down.
受控
Table 5 Status Register Protection
BPRWD
X
X
50
B
F
24 1
B01
1
:50
9WP#
0
0
X
-125
7
0
2
X
X
2012
SP
QE
Descriptions
SR-1 can be changed
No WP# functionality, WP# pin will always function as SIO2
SR-1 cannot be changed during the current power cycle
0
0
X
SR-1 can be changed
0
0
0
SR-1 can NOT be changed
0
0
1
SR-1 can be changed
Note:
(1) When SP =1, a power-down, power-up cycle will change (BPRWD, SP) to (0, 0) state.
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
.
rs
e
s
u
受控
50
:
9
0
202
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
9.1.3
Status Register Memory Protection
Table 6 Block Protection Bits
TB
BP3
BP2
BP1
PROTECTED
BP0
BLOCK(S)
PROTECTED
PAGE ADDRESS
PA[15:0]
X
0
0
0
0
NONE
NONE
0
0
0
0
1
1022 & 1023
FF80h - FFFFh
0
0
0
1
0
1020 thru 1023
FF00h - FFFFh
0
0
0
1
1
1016 thru 1023
FE00h - FFFFh
0
0
1
0
0
1008 thru 1023
FC00h - FFFFh
0
0
1
0
1
992 thru 1023
控
受- FFFFh
F800h
0
0
1
1
0
960 thru 1023
0
0
1
1
1
50 0
0
1
0
0
:
9
0
1
0
5 00 1
2
1
-007 0 0 1
2
2
201 0 0 1 0
PROTECTED
PROTECTED
DENSITY
PORTION
FB
NONE
C1B
2
1
256kB
8DUpper 1/512
A
.
s
512kB
Upper 1/256
ser
u1MB
Upper 1/128
NONE
2MB
Upper 1/64
4MB
Upper 1/32
F000h - FFFFh
8MB
Upper 1/16
896 thru 1023
E000h - FFFFh
16MB
Upper 1/8
768 thru 1023
C000h - FFFFh
32MB
Upper 1/4
512 thru 1023
8000h - FFFFh
64MB
Upper 1/2
0&1
0000h – 007Fh
256kB
Lower 1/512
0 thru 3
0000h - 00FFh
512kB
Lower 1/256
1
0
0
1
1
0 thru 7
0000h - 01FFh
1MB
Lower 1/128
1
0
1
0
0
0 thru 15
0000h - 03FFh
2MB
Lower 1/64
1
0
1
0
1
0 thru 31
0000h - 07FFh
1
0
1
1
0
0 thru 63
0000h - 0FFFh
1
0
1
1
1
0 thru 127
0000h - 1FFFh
1
1
0
0
0
0 thru 255
0000h - 3FFFh
1
1
0
0
1
0 thru 511
X
1
0
1
X
0 thru 1023
受控
0000h - FFFFh
0000h - 7FFFh
24
1
0
B
4
12
BB0
C1
2
1
D
A8Lower
.
s
16MB
1/8
r
e
s
u
32MB
Lower 1/4
4MB
Lower 1/32
8MB
Lower 1/16
64MB
Lower 1/2
128MB
ALL
0000h - FFFFh
128MB
ALL
0
Note:
9:5
0
(1) X = don’t care
25
7
0
(2) If any Erase or Program
2- command specifies a memory region that contains protected data portion, this command will be
2
0
2
ignored.
s.
FB5
r
4
e
2
us
B01 9.2 Configuration Register (SR-2)
9.2.1 One Time Program Lock Bit (OTP-L)
受控
X
1
1
X
X
0 thru 1023
OTP-L is non-volatile.
50
:
9
0
The device provides an OTP area for the system to store critical data that cannot be changed once it’s
locked. The OTP area consists of 62 pages of 2,112-Byte each. The default data in the OTP area are
FFh. Only Program command can be issued to the OTP area to change the data from “1” to “0”, and the
OTP area cannot be erased.
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
202
Once the correct data is programmed in and verified, the system developer can set OTP-L bit to 1, so
that the entire OTP area will be locked to prevent further alteration to the data.
Everything for Memory
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
9.2.2
Enter OTP Access Mode Bit (OTP-E)
The OTP-E bit must be set to 1 in order to use the standard Program/Read commands to access the
OTP area as well as to read the Unique ID / Parameter Page information. The default value after power
up or a RESET command is 0.
24
1
0
B
9.2.3
FB
C1B
2
1
A8D
.
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r
use
ECC Enable Bit (ECC-E)
The device has a built-in ECC algorithm that can be used to preserve the data integrity. Internal ECC
calculation is done during page programming, and the result is stored in the extra 64-Byte area for each
page. During the data read operation, ECC engine will verify the data values according to the previously
stored ECC information and to make necessary corrections if needed. The verification and correction
status is indicated by the ECC Status Bits. ECC function is enabled by default when power on
(ECC-E=1), and it will not be changed by the Device Reset command.
受控
25
7
2-0
02
29.2.4
50
:
9
0
Output Driver Strength (DRV1-0)
Table 7 Output Driver Strength
9.2.5
DRV1
DRV0
Output Driver Strength
0
0
100% (default)
0
1
1
0
1
1
4
12
BB0
C1
2
1
8D
A
.
s
r50%
use 25%
75%
受控
Quad Enable Bit (QE)
0
9:5
0
-25
7
0
22
0
2
The Quad Enable (QE) bit is a volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,
HOLD# are enabled. While QE is "1", it performs Quad I/O mode and WP#, HOLD# are disabled. In
another word, if the system goes into four I/O mode (QE=1), the WP# and HOLD# function will be
disabled. Upon power cycle, the QE bit will go into the factory default setting "0".
FB5
4
2
B01
9.3
.
rs
e
s
u
Status Register (SR-3)
9.3.1
受控
ECC Status Bit (ECCS1-0)
ECC function is used in NAND flash memory to correct limited memory errors during read operations.
The ECC Status Bits (ECCS1, ECCS0) should be checked after the completion of a Read operation to
verify the data integrity. The ECC Status bits values are don’t care if ECC-E=0. These bits will be cleared
to 0 after a RESET command.
25
7
2-0
B5
F
4
12
50
:
9
0
202
The ECCS1-0 value reflects the ECC status of the content of the page 0 of block 0 after a power-on
reset.
B0
B
1
2C
8D1
Everything for Memory
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Table 8 ECC Bits Status
ECCS1
ECCS0
Description
0
0
No bit errors were detected during the previous read operation
0
1
1-bit error was detected in one or more sector and was corrected
1
X
More than 1-bit error was detected in one or more sector and cannot be corrected
24
1
0
B
FB
C1B
2
1
D
A8Program/Erase
The Program/Erase Failure Bits are used to indicate whether the internally-controlled
.
s
r
operation was executed successfully or not. P-FAIL bit will also be set when
usethe Program command is
issued to a protected block or locked OTP area, and E-FAIL bit will also be set when the Erase command
控beginning of the Program Execute or Block
is issued to a protected block. Both bits will be cleared 受
at the
9.3.2
Program/Erase Failure (P-FAIL, E-FAIL)
Erase instructions as well as the device Reset command.
9.3.3
50
:
9
0
Write Enable Latch (WEL)
25
7
2-0
Write Enable Latch (WEL) is a read only bit. The WEL bit is set to 1 after executing a Write Enable
Instruction. The WEL bit is cleared to 0 when the device is write disabled. A write disable state occurs
upon power-up or after any of the following instructions: Write Disable, Program Execute, Block Erase,
Page Data Read, and Program Execute for OTP pages.
202
4
12
BB0
C1
2
1
8D
A
.
s
OIP is a read only bit that is set to a 1 state when the device is powering up or executing
er a Page Read,
s
u
Program Execute, Block Erase and OTP Locking. During this time the device will ignore further
instructions except for the Get Feature or Soft Reset instructions. When the program, erase or page read
控
instruction has completed, the OIP bit will be cleared to a 0受
state indicating the device is ready for further
9.3.4
Operation in Progress (OIP)
instructions.
0
9:5
0
9.4 Sector ECC Status
-25Register (Sector0-3 ECC Status)
7
0
22
0
2
A sector is composed
by a 512 Byte main areas and a 16 Byte spare area, so a page has four sectors.
The
B5Sector ECC Status Register indicates the number of errors in each sector as identified from an ECC ers.
F
4
2
us
B01 check during a read operation.
Table 9 2Kbyte Page Assignment
1 Main
2 Main
3 Main
4 Main
1 Spare
2 Spare
3 Spare
受控 4 Spare
8D
st
nd
512B
512B
rd
th
st
512B
512B
nd
16B
16B
rd
th
16B
16B
0 Address (Byte)
5Column
:
9
0
Table 10 Definition of 528Btye Sector
5 Field
2Main
7
2-0 0 ~ 511
2,048 ~ 2,063
Sector
st
1 Sector
nd
B5
3 4Sector
F
2
B01 4 Sector
2
1B
C
2
1
Sector
202
Spare Field
512 ~ 1,023
2,064 ~ 2,079
rd
1,024 ~ 1,535
2,080 ~ 2,095
th
1,536 ~ 2,047
2,096 ~ 2,111
Everything for Memory
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Table 11 ECC Status Register0-3
Bit7
Bit6
Bit5
Reserved
9.4.1
Bit4
Bit3
Sector Information
Sector Information
Bit 5 ~ Bit 4
Bit1
24
1
0
B
FB
C1B
2
1
A8D
Table 12 Sector Information
.
s
r
Sector Informationuse
Sector (Main and Spare area)
Sector (Main and Spare area) 控
受
1st
01
2nd
10
3rd
Sector (Main and Spare area)
11
th
Sector (Main and Spare area)
50
:
9
0 Status
9.4.2 Sector
5ECC
2
-07
2
2
20
Bit 3 ~ Bit 0
Table 13 Sector ECC Status
Sector ECC Status
4
0000
No bit error was detected during the previous read operation
0001
1 bit error was detected in the sector and was corrected
001x
More than 1 bit errors were detected in the sector and cannot be corrected
Others
Bit0
Sector ECC Status
00
4
Bit2
Reserved
12
BB0
C1
2
1
A8D
.
s
r
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受控
FB5
4
2
B01
0
9:5
0
-25
7
0
22
0
2
.
rs
e
s
u
受控
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
50
:
9
0
202
19 / 43
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
10
Commands
10.1 Command Set
24
1
0
B
Table 14 Command Set
Commands
Byte1
Byte2
Byte3
MID
1B
C
2
1
Byte4
Byte5
A8D ByteN
.
s
r
uDIDse DID
Soft RESET
FFh
Read JEDEC ID
9Fh
Dummy
Get Feature
0Fh
SR Addr
Set Feature
1Fh
SR Addr
S7-0
Write Enable
06h
D8h
Dummy
PA15-8
PA7-0
02h
CA15-8
CA7-0
84h
CA15-8
Quad Program Data Load
32h
Random Quad Program Data Load
受控S7-0
S7-0
S7-0
D7-D0
Next Byte
…
CA7-0
D7-D0
Next Byte
…
CA15-8
CA7-0
D7-D0 / 4
Next Byte
…
34h
CA15-8
CA7-0
D7-D0 / 4
Next Byte
…
Program Execute
10h
Dummy
PA15-8
PA7-0
Page Read (to cache)
13h
Dummy
PA15-8
03h or 0Bh
CA15-8
CA7-0
Read From Cache x 2
3Bh
CA15-8
Dummy
D7-D0 / 2
Next Byte
Read From Cache x 4
6Bh
CA15-8
控
受CA7-0
Dummy
D7-D0 / 4
Next Byte
Write Disable
50
:
9
0
S7-0
04h
25
7
Program
2-0Data Load
2
0
2 Random Program Data Load
Block Erase
FB
Read From Cache
CA7-0
4
12
BB0
C1
2
1
A8D
.
PA7-0
s
r
use D7-D0 Next Byte
Dummy
0
9:5
0
(2) Column Address (CA) only requires
-25CA [11:0], CA [15:12] are considered as dummy bits.
7
0
2- 16 bits. PA [15:6] is the address for 128kB blocks (total 1,024 blocks), PA[5:0] is the address for
(3) Page Address (PA)
requires
2
0
2
2kB pages (total 64 pages for each block).
5 SPI Data Output (D7-0 / 2) format:
(4)
s.
FBDual
r
4
e
2
us
SIO0 = D6, D4, D2, D0…
B01
SIO1 = D7, D5, D3, D1…
(5) Quad SPI Data Input / Output (D7-0 / 4) format:
受控
Note:
(1) Output designates data output from the device.
SIO0 = D4, D0 ……
SIO1 = D5, D1 ……
SIO2 = D6, D2 ……
25
7
2-0
SIO3 = D7, D3 ……
50
:
9
0
(6) All Quad Program/Read commands are disabled when QE bit is set to 0 in the Configuration Register
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
202
20 / 43
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
10.2 Soft Reset (FFh)
Once the Reset command is accepted by the device, the device will take approximately tRST to reset,
depending on the current operation the device is performing, tRST can be 5us~200us. During this period,
no command will be accepted.
24
1
0
B
FB
1B
C
2
1
Data corruption may happen if there is an on-going internal Erase or Program operation
8D when Reset
A
.
s
command is accepted by the device. It is recommended to check the OIP bite
inrStatus Register before
s
u
issuing the Reset command.
控
受
Figure 8 Soft Reset
Sequence
CS#
5 0
2
-07
2
2
DI
20
(SIO0)
CLK
tcs
0
9:5
0
Mode 3
7
Mode 3
Mode 0
Mode 0
Instruction
FFh
DO
(SIO1)
4
12
BB0
High Impedance
C1
2
1
A8D
.
s
r
use
CS#
0
Mode 3
CLK
受控
8
7
Mode 0
0
90Fh:5
DI
0
(SIO0)
-25
7
0
22
DO
0
2(SIO1)
Get feature
FB5
4
2
B01
15
Status register address
7
6
1
0
High Impedance
7
.
rs
e
s
u
CS#
16
23
22
24
30
31
32
0
7
CLK
Status register
data out
DI
(SIO0)
DO
(SIO1)
B0
B
1
2C
8D1
16
B5
F
4
12
Everything for Memory
7
202
25
7
2-0
6
受控
Status register
data out
50
:
9
0
1
0
7
21 / 43
6
1
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
10.3 Read JEDEC ID (9Fh)
The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial
memories that was adopted in 2003.
24
1
0
B
1B
C
2
1
8D
AValue
.
s
r CDh
use
61h
Table 15 JEDEC ID Table
ID
Manufacture ID
Byte 1
Device ID
FB
受控
Byte 2
61h
Figure 9 Read JEDEC ID
CS#
25
7
-0
2CLK
Mode 3
202
50
:
9
0
7
0
8
15
16
23
24
31
32
38
Mode 0
Mode 0
8 Dummy
Clocks
Instruction
DI
(SIO0)
4
12
BB0
9Fh
Mfr. ID
DO
(SIO1)
Mode 3
High Impedance
Device ID
DID Byte1
MID
=MSB
C1
2
1
A8D
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DID Byte2
受控
0
9:5
0
5 Set Feature (1Fh)
-2and
10.4.1 Get Feature (0Fh)
7
0
22
0
2 (0Fh) and Set Feature (1Fh) commands are used to monitor the device status and alter
The Get Feature
theBdevice
5 behavior. These commands use a 1-byte feature address to determine which feature is to be rs.
F
4
2
or modified. Features such as OTP and block locking can be enabled or disabled by setting specific
use
B01 read
feature bits. The status register is mostly read, except WEL, which is a writable bit with the Write Enable
(06h) and Write Disable (04h) command. When a feature is set, it remains active until the
device is power
受控
10.4 Feature Operations
cycled or the feature is written to. Unless otherwise specified, once the device is set, it remains set, even
if a RESET (FFH) command is issued. Refer to Status Registers for detail information.
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
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Figure 10 Get Feature
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 3
24
1
0
B
Mode 0
Mode 0
Command
DI
(SIO0)
C1B
2
1
A8D
.
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1 byte address
7
0Fh
6
5
4
3
2
1
FB
0
Data byte
DO
(SIO1)
High Impedance
7
=MSB
6
5
4
3
2
1
0
受控
Figure 11 Set Feature
50
:
9
0
CS#
25
7
2-0
Mode 3
202
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Mode 3
Mode 0
Command
DI
(SIO0)
1 byte address
7
1Fh
6
5
4
3
Data byte
2
1
7
0
6
5
4
3
2
1
0
4
12
BB0
DO
(SIO1)
C1
2
1
A8D
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High Impedance
=MSB
受控
10.4.2 Write Enable (WREN, 06h)
The Write Enable (WREN, 06h) command is for setting Write Enable Latch (WEL) bit. The WEL bit must
be set prior to every Page Program, Block Erase and OTP.
FB5
4
2
B01
0
9:5
0
-25 Figure 12 Write Enable Sequence
7
0
22
0
2
Mode 3
CLK
0
1
2
3
4
5
Mode 0
DI
(SIO0)
Everything for Memory
7
Mode 3
受控
06h
DO
(SIO1)
B5
F
4
12
6
Mode 0
Command
B0
B
1
2C
8D1
.
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CS#
25
7
2-0
0
5Impedance
:
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0
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10.4.3 Write Disable (WRDI, 04h)
The Write Disable (WRDI, 04h) instruction is to reset Write Enable Latch (WEL) bit. Note that the WEL bit
is automatically reset after Power-up and upon completion of the Page Program, Block Erase, and Reset
commands.
24
1
0
B
C1B
2
1
A8D
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Figure 13 Write Disable Sequence
CS#
Mode 3
CLK
0
Mode 0
1
2
3
4
受控
5
6
FB
7
Mode 3
Mode 0
Command
DI
(SIO0)
0
9:5
2202
04h
5 0 DO
2
(SIO1)
07
High Impedance
4
12
BB0
10.5 Read Operations
C1
2
1
8D the data
The device supports Power-on Read function, after power up, the device will automatically
Aload
.
s
of the 1st page of 1st block from array to cache. The host micro-controller mayudirectly
ser read the 1st page
of 1st block data from the cache buffer.
受控
10.5.1 Page Read (13h)
0
9:5
0
-25
7
0
22
0
2
The device will have a period of time (tRD or tRD_ECC) being busy after the CS# goes high. The Get
s.
Feature
FB5 command may be used to poll the operation status.
r
4
e
2
us
B01
After read operation is completed, the Read from Cache (03h or 0Bh), Read from cache (x2) (3Bh), Read
from cache (x4) (6Bh) may be issued to fetch the data.
受控
The page read operation transfers data from array to cache by issuing the Page Read (13h) command
followed by the 24-bit address (including the dummy/block/page address).
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
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Figure 14 Page Read Sequence
CS#
7
0
Mode 3
CLK
8
9
29
30
31
8
7
0
15
14
16
23
22
Mode 3
24
1
0
B
Mode 0
Mode 0
24-bit Address
Instruction
DI
(SIO0)
13h
23
22
21
2
1
0Fh
0
7
6
DO
(SIO1)
High Impedance
FB
C1B
2
1
A8D
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1 byte Address
Get Feature
tCS
1
0
Data byte
7
6
1
0
=MSB
受控
10.5.2 Read From Cache (03h or 0Bh)
50
:
9
0
The Read From Cache command allows one or more data bytes to be sequentially read from the Data
Buffer after executing the Read Page command.
202
25
7
2-0
Figure 15 Read From Cache (03h) Sequence
4
12
BB0
CS#
Mode 3
CLK
7
0
8
9
21
22
23
31
32
38
Mode 0
DI
(SIO0)
8 Dummy
Clocks
Column Address[15:0]
Instruction
03h
15
14
DO
(SIO1)
13
2
1
0
受控
High Impedance
C1
2
1
A8D
.
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39
40
6
1
47
Data Out 2
Data Out 1
7
46
0
7
6
1
0
0
9:5
0
-25Figure 16 Read From Cache (0Bh) Sequence
7
0
22
0
2
7
=MSB
FB5
4
2
B01
CS#
CLK
Mode 3
7
0
8
9
21
22
23
31
32
.
38
39
40
46
rs
e
s
u
47
Mode 0
DI
(SIO0)
0Bh
15
14
13
2
受控
8 Dummy
Clocks
Column Address[15:0]
Instruction
1
0
Data Out 2
Data Out 1
DO
(SIO1)
High Impedance
0
9:5
5 0
2
7
2-0
7
6
1
0
7
6
1
0
7
=MSB
02
2
10.5.3 Read From Cache x 2 (3Bh)
B5
F
4
The Read
012From Cache x 2 (3Bh) command is similar to the Read From Cache (03h or 0Bh) command
B
B
1
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except that data is output on two pins: SIO0 and SIO1. This allows data to be transferred at twice the rate
of standard SPI devices.
Figure 17 Read From Cache x2 (3Bh) Sequence
24
1
0
B
CS#
CLK
8
7
0
Mode 3
9
22
21
23
31
32
C1B
2
1
A8D
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33
34
Mode 0
DI
(SIO0)
8 Dummy
Clocks
Column Address[15:0]
Instruction
3Bh
15
14
DO
(SIO1)
13
2
1
0
High Impedance
6
受控
4
35
2
36
0
5
37
6
38
4
39
2
40
6
0
Data Out 2
Data Out 1
7
FB
3
7
1
5
3
7
1
=MSB
50
:
9
0
25
7
2-0
10.5.4 Read From Cache x 4 (6Bh)
02 Read From Cache x 4 (6Bh) command is similar to the Read From Cache x 2 (3Bh) command
2The
except that data is output on four pins: SIO0, SIO1, SIO2 and SIO3. This allows data to be transferred at
four times the rate of standard SPI devices.
4
12
BB0
C1
2
1
A8D
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When QE bit in the Status Register is set to a 0, this command is disabled.
Figure 18 Read From Cache x4 (6Bh) Sequence
受控
CS#
Mode 3
0
8
7
9
21
0
9:5
0
-25
7
0
22
0
2
CLK
22
31
23
32
33
34
35
36
37
38
39
40
Mode 0
Instruction
DI
(SIO0)
8 Dummy
Clocks
6Bh
Column Address[15:0]
15
14
13
2
1
0
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
DO
(SIO1)
High Impedance
FB5
4
2
B01
WP#
(SIO2)
High Impedance
HOLD#
(SIO3)
High Impedance
=MSB
25
7
2-0
10.6 Program Operations
10.6.1 Page Program
B5
F
4
12
Data
Out 1
Data
Out 2
受控
7
3
Data
Out 3
7
3
Data
Out 4
.
rs
e
s
u
7
Data
Out 5
50
:
9
0
202
The Page Program operation sequence programs 1 byte to 2112 bytes of data within a page. The page
program sequence is as follows:
B0
B
1
2C
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F35UQA001G
Datasheet
1.
2.
3.
4.
Issue Program Data Load (02h) / Program Data Load x4 (32h)
Issue Write Enable command (06h)
Issue Program Execute command (10h)
Issue Get Feature command (0Fh) to read the status
24
1
0
B
FB
C1B
2
1
8D data into
Aprogram
The Program Data Load or Random Program Data Load command is used to load the
.
s
er the command code
the data buffer. The command is initiated by driving the CS# pin low then
usshifting
“02h” or “84h” followed by a 16-bit column address (only CA[11:0] is effective) and at least one byte of
data into the DI pin. The CS# pin must be held low for the控
受 entire length of the instruction while data is
10.6.2 Program Data Load (02h) / Random Program Data Load (84h)
being sent to the device. If the number of data bytes sent to the device exceeds the number of data bytes
in the Data Buffer, the extra data will be ignored by the device.
50
:
9
0
The Program Load Data command has to be issued prior to Random Program Load Data command for
random page program. The difference is that Program Load Data command will reset the unused the
data bytes in the Data Buffer to FFh value, while Random Program Load Data command will only update
the data bytes that are specified by the command input sequence, the rest of the Data Buffer will
remain unchanged.
202
25
7
2-0
Figure 19 (Random) Program Data Load Sequence
CS#
0
Mode 3
CLK
8
7
9
DO
(SIO1)
FB5
4
2
B01
CS#
22
Column Address[15:0]
0
9:5
0
-25
7
0
22
0
2
02h/84h
15
14
13
2
23
24
C1
2
1
A8D
.
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r
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受控
Mode 0
Instruction
DI
(SIO0)
21
1
0
7
High Impedance
24
31
30
32
38
39
.
40
Mode 3
CLK
Mode 0
Data-0
DI
(SIO0)
4
12
BB0
7
6
Data-1
0
1
7
6
DO
(SIO1)
受控
rs
e
s
u
Data-2111
1
0
7
0
7
6
1
0
High Impedance
25
7
2-0
50
:
9
0
202
10.6.3 Program Data Load x 4 (32h) / Random Program Data Load x 4 (34h)
B5
F
4
12
The Program Data Load x 4 and Random Program Data Load x 4 commands are similar to the Program
Load Data and Random Program Load Data, the only difference is that “x4” commands will input the data
B0
B
1
2C
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bytes from all four IO pins instead of the single DI pin. This method will significantly shorten the data
input time when a large amount of data needs to be loaded into the Data Buffer.
The Program Data Load x 4 command has to be issued prior to Random Program Data Load x 4
command for random page program. The difference is that Program Data Load x 4 command will reset
the unused the data bytes in the Data Buffer to FFh value, while Random Program Data Load x 4
instruction will only update the data bytes that are specified by the command input sequence, the rest of
the Data Buffer will remain unchanged.
24
1
0
B
FB
C1B
2
1
A8D
.
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When QE bit in the Status Register is set to 0, all Quad SPI instructions are disabled.
受控
Figure 20 (Random) Program Data Load x4 Sequence
CS#
Mode 3
25
7
2-0
CLK
202
Mode 0
DI
(SIO0)
50
:
9
0
0
8
7
9
21
22
23
24
25
26
27
Mode 3
Mode 0
Instruction
Column Address[15:0]
32h/34h
15
14
13
2
1
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
7
3
7
3
7
DO
(SIO1)
High Impedance
WP#
(SIO2)
High Impedance
HOLD#
(SIO3)
High Impedance
=MSB
Data
1
受控
Data
2
4
12
BB0
C1
2
1
A8D
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2
3
6
2
7
3
Data
N
0
9:5
0
25
7
0
The Program Executewill program the Data Buffer content into the physical memory page that
2 command
02command.
is specified in 2
the
Prior to performing the Program Execute operation, a Write Enable (06h)
command
5 must be issued to set the WEL bit.
B
s.
F
r
4
e
2
B01 The Program Execute command is initiated by driving the CS# pin low then shifting the instruction codeus
“10h” followed by 8-bit dummy clocks and the 16-bit Page Address into the DI pin.
受控
10.6.4 Program Execute (10h)
After CS# is driven high to complete the instruction cycle, the self-timed Program Execute instruction will
commence for time duration of tPROG (See AC Characteristics). While the Program Execute cycle is in
progress, the Get Feature command (0Fh) may be used for checking the status of the OIP bit. The OIP
bit is a 1 during the Program Execute cycle and becomes a 0 when the cycle is finished and the device is
ready to accept other instructions again. After the Program Execute cycle has finished, the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Program Execute command will not be
executed if the addressed page is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bits.
Only 4 partial page program times are allowed on every single page.
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
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The pages within the block have to be programmed sequentially from the lower order page address to
the higher order page address within the block. Programming pages out of sequence is prohibited.
24
1
0
B
Figure 21 Program Execute Sequence
C1B
2
1
A8D
.
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r
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CS#
Mode 3
CLK
0
7
8
9
15
16
29
17
30
31
Mode 3
Mode 0
Mode 0
8 Dummy
Clocks
Instruction
DI
(SIO0)
FB
10h
受控
15
14
Page Address[15:0]
13
2
1
0
High Impedance
DO
(SIO1)
25
7
2-0
50
:
9
0
10.6.5 Internal Data Move
02Internal Data Move command sequence programs or replaces data in a page with existing data. The
2The
sequence is as follows:
1. Issue Page Read command (13h)
2. Program Load Random Data (Optional)
3. Issue Write Enable command (06h)
4. Issue Program Execute command (10h)
5. Issue Get Feature command (0Fh) to read the status
4
12
BB0
C1
2
1
A8D
.
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r
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受控
Prior to performing an internal data move operation, the target page content must be read out into the
cache register by issuing a Page Read (13h) command. One or more Program Load Random Data
(84h/34h) command can be issued, if user wants to update bytes of data in the page. After the data is
loaded, the Write Enable command (06h) and the Program Execute (10h) command can be issued to
start the program operation.
0
9:5
0
-25
7
0
22
0
2
FB5 Block Erase Operations
4
2
10.7
B01
.
rs
e
s
u
受控
The Block Erase instruction sets all memory within a specified block to the erased state of all 1s (FFh). A
Write Enable command must be executed before the device will accept the Block Erase Instruction
(Status Register bit WEL must equal 1). The command is initiated by driving the CS# pin low and shifting
the command code “D8h” followed by 8-bit dummy clocks and the 16-bit page address.
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
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B0
1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Figure 22 Block Erase Sequence
CS#
Mode 3
CLK
0
7
8
9
15
16
29
17
30
31
8 Dummy
Clocks
Instruction
DI
(SIO0)
Mode 3
Mode 0
Mode 0
Page Address[15:0]
D8h
15
14
13
24
1
0
B
FB
C1B
2
1
A8D
.
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2
1
0
受控
10.8 UID / Parameter / OTP Pages
In addition to the main memory array, the device has one Unique ID Page, one Parameter Page, and
sixty-two OTP Pages.
202
25
Page Address
7
0
2-PA[15:0]
50
:
9
0
Table 16 UID / Parameter / OTP Pages
Page Name
Descriptions
Data Length
00_00h
Unique ID Page
Factory programmed, Read Only
32-Byte x 16
00_01h
Parameter Page
Factory programmed, Read Only
256-Byte x 3
00_02h
OTP Page [0]
Program Only, OTP lockable
…
OTP Pages [1:60]
Program Only, OTP lockable
00_3Fh
OTP Page [61]
Program Only, OTP lockable
4
12
BB0
C1
2
1
8D
A
.
s
r 2,112-Byte
use
2,112-Byte
2,112-Byte
受控
Unique ID Page: To accommodate robust retrieval of the UID in the case of bit errors, sixteen copies
(each copy has 32 bytes) of the UID and the corresponding complement are stored. On each 32-byte,
the first 16-byte and following 16-byte are complementary. If the XOR of the UID and its bit-wise
complement is all ones, then the UID is valid.
0
9:5
0
-25
7
0
Parameter Page: Contains
2- at least three identical copies of the 256-Byte Parameter Data.
2
0
2
5 these additional data pages, the OTP-E bit in Configuration Register (SR-2) must be set to “1” rs.
To
FBaccess
4
2
1 first. Then, Read operations can be performed on Unique ID and Parameter Pages, Read and Programuse
operations can be performed on the OTP pages if it’s not already locked. To return to the main memory
array operation, OTP-E bit needs to be to set to 0.
受控
10.8.1 Read UID / Parameter / OTP Pages
50
:
9
0
The Read UID / Parameter / OTP pages sequence is as follows:
1. Issue Set Feature command (1Fh) to set OTP-E=1.
2. Issue Page Read command (13h) with address shown in the table above.
3. Issue Get Feature command (0Fh) to read the status.
4. Issue Read from cache command (03h/0Bh/3Bh/6Bh) to read data.
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
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202
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Datasheet
Note:
(1)
For OTP pages, Internal ECC can be enabled for the OTP page read operations to ensure the data integrity.
(2)
When reading UID / Parameter page, Internal ECC is disabled by the chip.
10.8.2 Program OTP Pages and OTP Lock Operation
24
1
0
B
FB
C1B
2
1
A8D
.
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OTP pages provide the additional space (2K-Byte x 62) to store important data or security information
that can be locked to prevent further modification in the field. These OTP pages are in an erased state
set in the factory, and can only be programmed (change data from “1” to “0”) until being locked by OTP-L
bit in the Configuration Register (SR-2).
受控
The Program OTP Pages sequence is as follows:
1. Issue Set Feature command (1Fh) to set OTP-E=1
2. Issue WREN command (06h) to set WEL bit
3. Issue Program Data Load and Program Execute command
4. Issue Get Feature command (0Fh) to read the status.
50
:
9
0
25
7
2-0
02 ECC is enabled, ECC calculation will be performed during Program Execute.
2When
4
12
BB0
Once the OTP pages are correctly programmed, OTP-L bit can be used to permanently lock these pages
so that no further modification is possible.
C1
2
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The OTP Lock sequence is as follows:
1. Issue Set Feature command (1Fh) to set OTP-E=1 and OTP-L=1
2. Issue WREN command (06h) to set WEL bit
3. Issue Program Execute command (10h), page address is “don’t care”
4. Issue Get Feature command (0Fh) to read the status.
5. Issue Set Feature command (1Fh) to set OTP-E=0, return to the main memory array operation.
受控
10.8.3
0
9:5
0
-25
7
0
- Data Definition
2Page
Parameter
2
0
2
5
FBByte
4
Number
2
B01
.
Table 17 Parameter Definition
Descriptions
Values
0~3
Parameter Page Signature, "ONFI" ASCII characters
4Fh 4Eh 46h 49h
4~5
Revision Number
00h 00h
6~31
Reserved (0)
all 00h
rs
e
s
u
受控
46h 4Fh 52h 45h
32~43
0
9:5
Device manufacturer , 12 ASCII characters
5 0
2
7
2-0
44-63
1B
C
2
8D1
24
B01
20h 20h 20h 20h
46h 33h 35h 55h
20220 ASCII characters
Device Model,
FB5
Everything for Memory
53h 45h 45h 20h
51h 41h 30h 30h
31h 47h 20h 20h
20h 20h 20h 20h
20h 20h 20h 20h
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1Gbit SPI NAND Flash
F35UQA001G
Datasheet
Byte Number
64
Descriptions
Values
JEDEC MID
CDh
65-66
Date Code
00h 00h
67-79
Reserved (0)
All 00h
80-83
Number of Data Bytes per Page
00h 08h 00h 00h
84-85
Number of Spare Bytes per Page
40h 00h
86-89
Number of Data Bytes per Partial Page
00h 02h 00h 00h
90-91
Number of Spare Bytes per Partial Page
92-95
Number of Pages per Block
96-99
Number of Block per Logic Unit
受控
00h 04h 00h 00h
Number of Logic Units
101
Reserved (0)
00h
102
Number of Bits per Cell
01h
Bad Blocks Maximum per Logic Unit
14h 00h
50
:
9
0 Endurance
Block
25 Guaranteed Valid Blocks at Beginning of Target
107
7
-0
2108-109
2
Block Endurance for Guaranteed Valid Blocks
0
2
105-106
110
01h
01h 05h
01h
01h 03h
Number of Programs per Page
04h
4
12
BB0
Partial Programming Attributes
b5-b7 reserved (0)
111
b4
1 = partial page layout is partial page data
followed by partial page spare
00h
b1-b3 reserved (0)
b0
112
113-127
128
129-132
133-134
135-136
137-138
5
B
24F 139-163
1
0
B
164-165
C1
2
1
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1 = partial page programming has constraints
受控
Number of ECC Bits Correctability
Reserved (0)
0
9:5
0
Reserved (0)
-25 Page Program Time (us)
tPROG0Maximum
7
22
tBER Maximum Block Erase Time (us)
0
2
I/O Pin Capacitance, Maximum
00h
all 00h
08h
all 00h
BCh 02h
10h 27h
tR Maximum Page read Time (us)
3Ch 00h
Reserved (0)
all 00h
Vendor Specific Revision Number
00h 00h
166-253
Vendor Specific
all 00h
254-255
Integrity CRC
8Dh 98h
256-511
Value of Bytes 0-255
512-767
Value of Bytes 0-255
768+
FB
C1B
2
1
A8D
.
10h 00h
s
se00hr 00h
40hu
00h
100
103-104
24
1
0
B
.
rs
e
s
u
受控
50
:
9
0
Additional Redundant Parameter Pages
25
7
(1) The Integrity CRC (Cycling Redundancy
2-0 Check) field is used to verify that the contents of the parameters page were
2
0
2 Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the
transferred correctly to the host.
following 16-bit
B5generator polynomial: G(X) = X16 + X15 +X2 + 1
F
4
012
B
B
1
Note:
2C
8D1 Everything for Memory
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Datasheet
11
Software Algorithm
11.1 Initial Invalid Block(s)
24
1
0
B
FB
C1B
2
1
A8D
.
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r
use
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is
not guaranteed. Devices with initial invalid block(s) have the same quality level as devices with all valid
blocks and have the same electrical characteristics. An initial invalid block(s) does not affect the
performance of valid block(s). The system design must be able to mask out the initial invalid block(s) via
address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
at the time of shipment.
受控
Table 18 Valid Block Number
Parameter
Valid block number
25
7
2-0
02
211.2
Symbol
50 N
:
9
0
VB
Min
Max
Unit
1004
1024
Blocks
Identifying Initial Invalid Block(s)
4
12
BB0
All device locations are erased (FFh) except locations where the initial invalid block(s) information is
written prior to shipping. All initial invalid blocks are marked with non-FFh at the first byte of spare area
on the 1st or 2nd page. Since the initial invalid block information is also erasable in most cases, it is
impossible to recover the information once it has been erased. Therefore, the system must be able to
recognize the initial invalid block(s) based on the original initial invalid block information and create the
initial invalid block table via the suggested flow ( Figure 23). Any intentional erasure of the original initial
invalid block information is prohibited.
C1
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1
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FB5
4
2
B01
202
控
受
Figure 23 Flow to Create Initial Invalid Block Table
0
9:5
0
-25
7
0
2-
.
rs
e
s
u
受控
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
50
:
9
0
202
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11.3 Error in Operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. The following
possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail
during a page program does not affect the data of the other pages in the same block, block replacement
can be executed with a page-sized buffer by finding an erased empty block and reprogramming the
current target data and copying the rest of the replaced block. In case of Read, ECC must be employed.
To improve the efficiency of memory space, it is recommended that the read or verification failure due to
single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate
does not include those reclaimed blocks.
24
1
0
B
FB
C1B
2
1
A8D
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受控
Table 19 Failure Modes
Operation
25 Status read after program → Block Replacement
7
2-0
Erase
202
Detection and recommended procedure
50
:
9
0 read after erase → Block Replacement
Status
Program
Read
Verify ECC → ECC correction
4
12
BB0
Figure 24 Bad Block Replacement
C1
2
1
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受控
FB5
4
2
B01
0
9:5
0
-25
7
0
22
0
2
.
rs
e
s
u
受控
11.4 Internal ECC
B5
F
4
12
25
7
2-0
50
:
9
0
202
The internal ECC logic may detect 2-bit error and correct 1-bit error in an ECC segment. An ECC
segment is composed by a main area (512 Byte) and a spare area (16 Byte). The default state of the
B0
B
1
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8D1
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Datasheet
internal ECC is enabled. To enable/disable the internal ECC, it is operated by the Set Feature operation
to enable internal ECC or disable the internal ECC, and then check the internal ECC state by Get
Feature operation.
24
1
0
B
The internal ECC is enabled by using Set Feature command (1Fh) to set ECC-E. To disable the internal
ECC can be done by using the Set Feature command (1Fh) to clear ECC-E.
FB
C1B
2
1
A8aDStatus Read
When the internal ECC is enabled, after the data transfer time (tRD_ECC) is completed,
.
s
r
operation is required to check any uncorrectable read error happened. Please
userefer to Status Register
(SR-3)
受控
The number of partial-page program is not 4 in an ECC segment, the user need to program the main
area (512B)+spare area (16B) at one program time, so the ECC parity code can be calculated properly
and stored in the additional hidden spare area.
50
:
9
0
25
7
0
11.5
for Program Operation
2-Addressing
2
0
2
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of
the block to the MSB(most significant bit) pages of the block. The LSB page is defined as the start page
among the pages to be programmed, does not need to be page 0 in the block. Random page address
programming is prohibited.
4
12
BB0
Figure 25 Addressing for Program Operation
C1
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受控
FB5
4
2
B01
0
9:5
0
-25
7
0
22
0
2
.
rs
e
s
u
受控
25
7
2-0
B0
B
1
2C
8D1
B5
F
4
12
Everything for Memory
50
:
9
0
202
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Datasheet
12
Electrical Characteristics
12.1 Absolute Maximum Ratings
Table 20 Absolute Maximum Rating
Parameters
Symbol
Supply Voltage
VCC
Voltage Applied to Any Pin
VIO
24
1
0
B
C1B
2
1
Range 8D
Unit
A
.
s
V
e–0.6r to +2.5
us–0.6
to V +0.4
V
CC
受控T
Temperature under Bias
Storage Temperature
TBIAS
–40 to +125
°C
STG
–65 to +150
°C
5
mA
Short circuit output current, I/Os
FB
IOS
Note:
50
:
9
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