ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
1.
•
3.
AEC-Q100 (
•
ADX111Q)
ADX111(Q)
(ADC)
3mm × 3mm MSOP
•
QFN
2.0V
•
145µA (
(PGA)
5.5V
•
)
8SPS
I 2C
QFN-10
ADX111(Q)
2mm × 1.5mm × 0.4mm
•
16
MSOP-10
ADX111(Q)
8SPS
860SPS PGA
±256mV
860SPS
±6.144V
ADX111(Q)
(MUX)
ADX111(Q)
•
•
•
•
ADX111(Q)
2
IC
•
ADX111(Q)
ADX111(Q)
•
•
–40°C
Table 1
125°C
2.
•
•
•
•
•
VDD
Comparator
Voltage
Reference
AIN0
AIN1
AIN2
MUX
PGA
16-Bit
ΔΣ
ADC
ALERT/RDY
ADDR
I2C
Interface
SCL
SDA
AIN3
Oscillator
ADX111(Q)
GND
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
Table 1 lists the order information.
Table 1. Order Information
BODY
SIZE
(mm)
MARK
ODR
(SPS)
INTERFACE
COMPARATOR
MSOP-10
3× 3
ADX111
860
I2C
Yes
No
No
–40-125 T/R-3000
16
MSOP-10
3× 3
ADX111Q
860
I2C
Yes
No
No
–40-125 T/R-3000
16
QFN-10
2 × 1.5
111
860
I2C
Yes
No
No
–40-125 T/R-4000
MARK
ODR
(SPS)
INTERFACE
COMPARATOR
ORDER NUMBER(1)
CH
(#)
ADX111AMSOP10
2(4)
16
2(4)
2(4)
ADX111QAMSOP10
(1)
ADX111AQFN10
BITS PACKAGE
TEMP
50/60
SENSOR REJECTION
OP.
TEMP
(°C)
PKG.
OPTION
Table 2. Family Selection Guide
ORDER NUMBER(1)
CH
(#)
BITS PACKAGE
BODY
SIZE
(mm)
TEMP
50/60
SENSOR REJECTION
OP.
TEMP
(°C)
PKG.
OPTION
ADX112AMSOP10
2(4)
16
MSOP-10
3× 3
ADX112
860
SPI
No
Yes
No
–40-125 T/R-3000
ADX112QAMSOP10(1)
2(4)
16
MSOP-10
3× 3
ADX112Q
860
SPI
No
Yes
No
–40-125 T/R-3000
ADX112AQFN10
2(4)
16
QFN-10
2 × 1.5
112
860
SPI
No
Yes
No
–40-125 T/R-4000
ADX113AMSOP10
2(4)
16
MSOP-10
3× 3
ADX113
860
I2C
Yes
No
Yes
–40-125 T/R-3000
ADX114AMSOP10
2(4)
16
MSOP-10
3× 3
ADX114
3571
SPI
No
Yes
Yes
–40-125 T/R-3000
ADX121AMSOP10
2(4)
20
MSOP-10
3× 3
ADX121
3571
I2C
Yes
No
Yes
–40-125 T/R-3000
ADX121AQFN10(1)
2(4)
20
QFN-10
2 × 1.5
121
3571
I2C
Yes
No
Yes
–40-125 T/R-4000
ADX122AMSOP10
2(4)
20
MSOP-10
3× 3
ADX122
3571
SPI
No
No
Yes
–40-125 T/R-3000
ADX122QAMSOP10(1)
2(4)
20
MSOP-10
3× 3
ADX122Q 3571
SPI
No
No
Yes
–40-125 T/R-3000
ADX122AQFN10(1)
2(4)
20
QFN-10
2 × 1.5
122
3571
SPI
No
No
Yes
–40-125 T/R-4000
ADX128AMSOP10(1)
2(4)
20
MSOP-10
3× 3
ADX128
7143
SPI
No
No
Yes
–40-125 T/R-3000
ADX128AQFN10(1)
2(4)
20
QFN-10
2 × 1.5
128
7143
SPI
No
No
Yes
–40-125 T/R-4000
ADX125AMSOP10
2(4)
20
MSOP-10
3× 3
ADX125
3571
I2C
Yes
Yes
Yes
–40-125 T/R-3000
ADX126AMSOP10
2(4)
20
MSOP-10
3× 3
ADX126
3571
SPI
No
Yes
Yes
–40-125 T/R-3000
ADX125AQFN10(1)
2(4)
20
QFN-10
2 × 1.5
125
3571
I2C
Yes
Yes
Yes
–40-125 T/R-4000
ADX126AQFN10(1)
2(4)
20
QFN-10
2 × 1.5
126
3571
SPI
No
Yes
Yes
–40-125 T/R-4000
ADX131AQFN10(1)
2(4)
20
QFN-10
2 × 1.5
131
440
I2C
Yes
No
Yes
–40-125 T/R-4000
ADX132AQFN10(1)
2(4)
20
QFN-10
2 × 1.5
132
440
SPI
No
No
Yes
–40-125 T/R-4000
ADX123AMSOP10(1)
2(4)
20
MSOP-10
3× 3
ADX123
No
No
Yes
–40-125 T/R-3000
3571 Daisy Chain
Note: Available in the future.
Devices can be ordered via the following two ways:
1. Place orders directly on our website (www.analogysemi.com), or;
2. Contact our sales team by mailing to sales@analogysemi.com.
Page 2 of 39 | www.analogysemi.com
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© 2023 AnalogySemi Ltd. All Rights Reserved.
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
4. PIN CONFIGURATION AND FUNCTIONS
10
SCL
Figure 1 illustrates the pin configuration.
1
10
SCL
ALERT/RDY
2
9
SDA
GND
3
8
VDD
AIN0
4
7
AIN3
AIN1
5
6
AIN2
ADDR
1
9
SDA
ALERT/RDY
2
8
VDD
GND
3
7
AIN3
AIN0
4
6
AIN2
AIN1
5
ADDR
MSOP-10 Package
QFN-10 Package
Figure 1. Pin Configuration
Table 3 lists the pin functions.
Table 3. Pin Functions
POSITION
NAME
TYPE
DESCRIPTION
1
ADDR
Digital input
2
ALERT/RDY
Digital output
I2C slave address select
Comparator output or conversion ready, open drain, connected to a pull-up
resistor
3
4
5
6
7
GND
AIN0
AIN1
AIN2
AIN3
Power
Analog input
Analog input
Analog input
Analog input
8
VDD
Power
9
10
SDA
SCL
Digital I/O
Digital input
© 2023 AnalogySemi Ltd. All Rights Reserved.
Ground
Analog input 0
Analog input 1
Analog input 2
Analog input 3
Power supply. Connects a 0.1μF, power-supply decoupling capacitor to
GND.
Serial data. Transmits and receives data.
Serial clock input. Locks data on SDA.
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www.analogysemi.com | Page 3 of 39
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
5. SPECIFICATIONS
5.1 ABSOLUTE MAXIMUM RATINGS
Table 4 lists the absolute maximum ratings of the ADX111(Q).
Table 4. Absolute Maximum Ratings
PARAMETER
DESCRIPTION
Power-Supply Voltage
Analog Input Voltage
Digital Input Voltage
VDD to GND
AIN0, AIN1, AIN2, AIN3
SDA, SCL, ADDR, ALERT/RDY
Any pin except power supply
pins
Operating ambient, TA
Junction, TJ
Storage, Tstg
Input Current, Continuous
Temperature
MIN
MAX
UNITS
–0.3
GND – 0.3
GND – 0.3
7
VDD + 0.3
5.5
V
V
V
–10
10
mA
–40
–40
–60
125
150
150
°C
Note: Stresses beyond those listed under Table 4 may cause permanent damage to the device. These are
stress ratings only, which do not imply functional operation of the device at these or any other
conditions beyond those indicated under Table 6. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
5.2 ESD RATINGS
Table 5 lists the ESD ratings of the ADX111(Q).
Table 5. ESD Ratings
PARAMETER
Electrostatic
Discharge
SYMBOL
V(ESD)
DESCRIPTION
Human-body model (HBM), per ANSI/ESDA/JEDEC
VALUE
JS-001(1)
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±6000
±1500
UNITS
V
Note 1: The JEDEC document JEP155 indicates that 500V HBM allows safe manufacturing with a standard
ESD control process.
Note 2: The JEDEC document JEP157 indicates that 250V CDM allows safe manufacturing with a standard
ESD control process.
Page 4 of 39 | www.analogysemi.com
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© 2023 AnalogySemi Ltd. All Rights Reserved.
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
5.3 RECOMMENDED OPERATING CONDITIONS
Table 6 lists the recommended operating conditions for the ADX111(Q).
Table 6. Recommended Operating Conditions
PARAMETER
POWER SUPPLY
Power Supply
ANALOG INPUTS(1)
Full-Scale Input Voltage
Range(2)
DESCRIPTION
SYMBOL
MAX
UNITS
2
5.5
V
FSR
±0.256
±6.144
V
V(AINx)
GND
VDD
V
VDIG
GND
5.5
V
TA
–40
125
°C
VDD to GND
VIN = V(AINP) – V(AINN)
Absolute Input Voltage
DIGITAL INPUTS
Digital Input Voltage
TEMPERATURE RANGE
Operating Ambient
Temperature
MIN
NOM
Note 1: AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four
available analog inputs.
Note 2: This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3V must be
applied to the analog inputs of the device. See Table 12 for more information.
5.4 THERMAL INFORMATION
Table 7 lists the thermal information for the ADX111(Q).
Table 7. Thermal Information
PARAMETER
Junction-to-Ambient Thermal Resistance
Junction-to-Case (Top) Thermal Resistance
Junction-to-Board Thermal Resistance
Junction-to-Top Characterization Parameter
Junction-to-Board Characterization Parameter
Junction-to-Case (Bottom) Thermal Resistance
© 2023 AnalogySemi Ltd. All Rights Reserved.
Public
SYMBOL
MSOP-10
QFN-10
UNITS
RθJA
RθJC(top)
RθJB
ψJT
ψJB
RθJC(bot)
150
54
90
3
86
90
119
60
39
4
39
45
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
www.analogysemi.com | Page 5 of 39
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
5.5 ELECTRICAL CHARACTERISTICS
Table 8 lists the electrical characteristics of ADX111(Q). At VDD = 3.3V, data rate = 8SPS, and full-scale input
voltage range (FSR) = ±2.048V (unless otherwise noted). Maximum and minimum specifications apply from
TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
Table 8. Electrical Characteristics
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
FSR = ±6.144V(1)
FSR = ±4.096V(1)
FSR = ±2.048V
FSR = ±1.024V
FSR = ±0.512V, FSR = ±0.256V
FSR = ±6.144V(1)
FSR = ±4.096V(1)
FSR = ±2.048V
FSR = ±1.024V
FSR = ±0.512V, ±0.256V
Common-Mode Input
Impedance
Differential Input Impedance
SYSTEM PERFORMANCE
Resolution (No Missing Codes)
Data Rate
Data Rate Variation
DR
All data rates
Output Noise
Integral Nonlinearity
INL
Offset Error
Offset Drift Over Temperature
Offset Power-Supply Rejection
Offset Channel Match
Gain Error(3)
Gain Drift Over Temperature(3)
Long-Term Gain Drift(3)
Gain Power-Supply Rejection
Gain Match(3)
Gain Channel Match
Common-Mode Rejection
Ratio
CMRR
DIGITAL INPUT/OUTPUT
High-Level Input Voltage
Low-Level Input Voltage
Low-Level Output Voltage
Input Leakage Current
VIH
VIL
VOL
MΩ
0.5
1
LSB
0
2
–2
LSB
±2
0.005
LSB/°C
0.5
LSB
0.5
LSB/V
2
0.01%
8
8
8
LSB
0.10%
30
±0.05
70
0.01%
0.03%
>110
At DC, FSR = ±2.048V
At DC, FSR = ±6.144V(1)
fCM = 60Hz, DR = 8SPS
fCM = 50Hz, DR = 8SPS
>105
100
103
104
Public
MΩ
Bits
SPS
Match between any two gains
Match between any two inputs
At DC, FSR = ±0.256V
IOL = 3mA
GND < VDIG < VDD
MΩ
16
8, 16, 32, 64, 128, 250, 475, 860
–7%
6%
See NOISE PERFORMANCE
section
FSR = ±2.048V
FSR = ±2.048V, TA = 125°C,
1000 hrs
FSR = ±2.048V, DC supply
variation
Match between any two inputs
FSR = ±2.048V, TA = 25°C
FSR = ±0.256V
FSR = ±2.048V
FSR = ±6.144V(1)
FSR = ±2.048V, TA = 125°C,
1000 hrs
Long-Term Offset Drift
Page 6 of 39 | www.analogysemi.com
DR = 8SPS, FSR = ±2.048V(2)
FSR = ±2.048V, differential
inputs
FSR = ±2.048V, single-ended
inputs
9
7
6
5
6
26
17
3
1.5
0.9
0.7 VDD
GND
GND
–10
0.15
ppm/°C
%
ppm/V
0.05%
0.05%
dB
5.5
0.3 VDD
0.4
10
V
V
V
µA
© 2023 AnalogySemi Ltd. All Rights Reserved.
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TA = 25°C
0.65
TA = 25°C
145
1
3.5
170
300
µA
POWER SUPPLY
Power-down
Supply Current
IVDD
Operating
Power Dissipation
PD
VDD = 5.0V
VDD = 3.3V
VDD = 2.0V
0.9
0.5
0.3
mW
Note 1: This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3V must be
applied to the analog inputs of the device. See Table 11 for more information.
Note 2: Best-fit INL; covers 98% of full-scale.
Note 3: Includes all errors from onboard PGA and voltage reference.
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
5.6 TIMING REQUIREMENTS: I2C INTERFACE
Table 9 lists the timing requirements for the I2C interface.
Table 9. Timing Requirements: I2C Interface
PARAMETER
FAST MODE
MIN
MAX
SYMBOL
SCL Clock Frequency
Bus Free Time Between START and STOP
Condition
Hold Time After Repeated START
Condition. (After this period, the first
clock is generated.)
Setup Time for A Repeated START
Condition
Setup Time for STOP Condition
Data Hold Time
Data Setup Time
Low Period of the SCL Clock Pin
High Period for the SCL Clock Pin
Rise Time for Both SDA and SCL Signals(1)
Fall Time for Both SDA and SCL Signals(1)
HIGH-SPEED MODE
MIN
MAX
0.4
0.01
UNITS
fSCL
0.01
3.4
MHz
tBUF
600
160
ns
tHDSTA
600
160
ns
tSUSTA
600
160
ns
tSUSTO
tHDDAT
tSUDAT
tLOW
600
0
100
1300
160
0
10
160
ns
ns
ns
ns
tHIGH
tF
tR
600
60
300
300
ns
ns
ns
160
160
Note: For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400pF.
Figure 2 shows the I2C interface timing.
tLOW
tR
tHDSTA
tF
SCL
tHIGH
tHDSTA
tHDDAT
SDA
tSUSTO
tSUSTA
tSUDAT
tBUF
P
S
S
P
Figure 2. I2C Interface Timing
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
5.7 TYPICAL CHARACTERISTICS
TA = 25°C, VDD = 3.3V, FSR = ±2.048V, DR = 8SPS, unless otherwise noted.
Figure 3. Operating Current vs. Temperature
Figure 4. Power-Down Current vs. Temperature
Figure 5. Single-Ended Offset Error vs. Temperature
Figure 6. Differential Offset vs. Temperature
Figure 7. Gain Error vs. Temperature
Figure 8. Gain Error vs. Supply Voltage
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
5.8 TYPICAL CHARACTERISTICS (CONTINUED)
TA = 25°C, VDD = 3.3V, FSR = ±2.048V, DR = 8SPS, unless otherwise noted.
Figure 9. INL vs. Supply Voltage
Figure 10. INL vs. Temperature
Figure 11. Noise vs. Supply Voltage
Figure 12. Data Rate vs. Temperature
Figure 13. Gain Error Histogram
Figure 14. Offset Histogram
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© 2023 AnalogySemi Ltd. All Rights Reserved.
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
5.9 TYPICAL CHARACTERISTICS (CONTINUED)
TA = 25°C, VDD = 3.3V, FSR = ±2.048V, DR = 8SPS, unless otherwise noted.
Figure 15. Digital Filter Frequency Response
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
6.
6.1
Table 10
Table 11
Table 11
(
ADX111(Q)
)
TA = 25 C
Table 10
μVRMS
Equation 1
μVRMS
RMS
ADC
μVPP
Equation 2
Effective Resolution = In (FSR / VRMS-Noise ) / In(2)
(1)
Noise-Free Resolution = In (FSR / VPP-Noise ) / In (2)
(2)
Table 10. Noise in μVRMS (μVPP) at VDD = 3.3V
FSR (Full-Scale Range)
±2.048V
±1.024V
DATA RATE
(SPS)
±6.144V
±4.096V
8
16
32
64
128
250
475
187.5 (187.5)
187.5 (187.6)
187.5 (187.7)
187.5 (187.8)
187.5 (187.9)
187.5 (375)
187.5 (375)
125 (125)
125 (125)
125 (125)
125 (125)
125 (125)
125 (250)
125 (250)
62.5 (62.5)
62.5 (62.5)
62.5 (62.5)
62.5 (62.5)
62.5 (62.5)
62.5 (125)
62.5 (125)
860
187.5 (520.8)
125 (319.4)
62.5 (152.7)
±0.512V
±0.256V
31.25 (31.25)
31.25 (31.25)
31.25 (31.25)
31.25 (31.25)
31.25 (31.25)
31.25 (62.5)
31.25 (62.5)
15.625 (15.625)
15.625 (15.625)
15.625 (15.625)
15.625 (15.625)
15.625 (17.333)
15.625 (31.25)
15.625 (31.25)
7.8125 (7.8125)
7.8125 (7.8125)
7.8125 (7.8125)
7.8125 (13.889)
7.8125 (15.625)
7.8125 (23.4375)
7.8125 (32.986)
31.25 (90.2)
15.625 (38.19)
8.6799 (45.138)
Table 11. Effective Resolution from RMS Noise (Noise-Free Resolution from Peak-to-Peak
Noise) at VDD = 3.3V
DATA RATE
(SPS)
±6.144V
8
16
32
64
128
250
475
860
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15)
16 (15)
16 (14.52)
Page 12 of 39 | www.analogysemi.com
±4.096V
FSR (Full-Scale Range)
±2.048V
±1.024V
±0.512V
±0.256V
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15)
16 (15)
16 (14.64)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15)
16 (15)
16 (14.7)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.85)
16 (15)
16 (15)
16 (14.71)
16 (16)
16 (16)
16 (16)
16 (15.17)
16 (15)
16 (14.41)
16 (13.92)
15.9 (13.47)
Public
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15)
16 (15)
16 (14.47)
© 2023 AnalogySemi Ltd. All Rights Reserved.
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.
7.1
ADX111(Q)
16
Δ-Σ (ΔΣ)
(ADC) ADX111(Q)
(PGA)
I 2C
23
ΔΣ ADC
Figure
ADX111(Q)
ADX111(Q) ADC
VIN
V(AINP)
V(AINN)
ADX111(Q)
ΔΣ
ADC
ADC
7.2
VDD
Comparator
Device
ALERT/RDY
Voltage
Reference
MUX
AIN0
ADDR
AIN1
16-Bit ΔΣ
ADC
PGA
I2C
Interface
SCL
SDA
AIN2
Oscillator
AIN3
GND
Figure 16. Functional Block Diagram
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.3
7.3.1
ADX111(Q)
AIN1
(MUX)
Figure 17
CONFIG REGISTER
GND
AIN3
AIN0
ADC
MUX[2:0]
Device
VDD
AIN0
VDD
GND
AINP
AIN1
AINN
VDD
GND
AIN2
VDD
GND
AIN3
GND
GND
Figure 17. Input Multiplexer
VDD
GND
(ESD)
ADX111(Q)
Equation 3
ESD
(3)
GND – 0.3V < V(AINx) < VDD + 0.3V
(
Table 4)
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.3.2
ADX111(Q)
AINP
(fMOD)
250kHz
ADX111(Q)
AINN
1MHz
4
fMOD
Figure 19
Figure 18
V(AINP) CA2
V(AINN) CB
(V(AINP) – V(AINN))
0.7V CB
0V
ADX111(Q)
(Zeff)
Zeff = VIN / IAVERAGE
Figure 18
S1
S2
S1
CA1
CA1
CA2
0.7V
CA1
AINP
S1
S2
CB
ZCM
Equivalent
Circuit
0.7V
AINP
ZDIFF
S2
S1
AINN
AINN
0.7V
ZCM
fMOD = 250kHz
CA2
0.7V
Figure 18. Simplified Analog Input Circuit
tSAMPLE
ON
S1
OFF
ON
S2
OFF
Figure 19. S1 and S2 Switch Timing
AINP
AINN
6M
AINP
Figure 18
ZCM
AINN
0.7V
Figure 18
0.7V
ZDIFF
ADX111(Q)
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.3.3
(FSR)
LSB
(PGA) ADX111(Q) ΔΣ ADC
CONFIG REGISTER
±6.144V ±4.096V ±2.048V ±1.024V ±0.512V ±0.256V Table 12
FSR
Equation 4
LSB
LSB = FSR / 2
PGA[2:0]
LSB
16
(4)
Table 12. Full-Scale Range and Corresponding LSB Size
FSR
LSB SIZE
±6.144V(1)
187.5μV
125μV
62.5μV
31.25μV
15.625μV
7.8125μV
±4.096V(1)
±2.048V
±1.024V
±0.512V
±0.256V
ADC
|VIN|
VDD + 0.3V
ABSOLUTE MAXIMUM RATINGS
ADC
VDD = 3.3V
>
3.3V
VDD
FSR = ±4.096V
VDD
±2.048V
VDD = 2V
VIN = ±3.3V
±2.048V
7.3.4
ADX111(Q)
ELECTRICAL CHARACTERISTICS
7.3.5
ADX111(Q)
1MHz
7.3.6
ADX111(Q)
128SPS 250SPS 475SPS
CONFIG REGISTER
DR[2:0]
8SPS 16SPS 32SPS 64SPS
860SPS
ADX111(Q)
1/DR
7.3.7
ADX111(Q)
ALERT/RDY
ALERT/RDY
(
CONFIG REGISTER
COMP_MODE
(Hi_thresh)
(Lo_thresh)
Lo_thresh
ALERT/RDY
)
Hi_thresh
CONFIG REGISTER
CONVERSION REGISTER
ALERT/RDY
Figure 20
CONFIG REGISTER
(Hi_thresh
CONFIG REGISTER
COMP_QUE[1:0]
COMP_QUE[1:0]
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COMP_LAT
Public
SMBus
COMP_POL
Lo_thresh)
ALERT/RDY
ALERT/RDY
ALERT/RDY
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.3.8
ALERT/RDY
Hi_thresh
COMP_POL
0
11
COMP_MODE
2
COMP_LAT
ADX111(Q)
ALERT/RDY
1
ALERT/RDY
ALERT/RDY
COMP_POL
Lo_thresh
COMP_QUE[1:0]
ALERT/RDY
ALERT/RDY
8µs
Figure 21
0
TH_H
TH_H
Input Signal
Input Signal
TH_L
TH_L
Time
Time
Latching
Comparator
Output
Successful
SMBus Alert
Response
Latching
Comparator
Output
Successful
SMBus Alert
Response
Successful
SMBus Alert
Response
Time
Time
Non-Latching
Comparator
Output
Non-Latching
Comparator
Output
Time
Time
Traditional Comparator Mode
Window Comparator Mode
Figure 20. ALERT Pin Timing Diagram
ADX111(Q)
Status
Converting
Converting
Converting
Conversion Ready
Conversion Ready
Converting
Conversion Ready
8µ s
ALERT/RDY
(Active
High)
Figure 21. Conversion Ready Pulse in Continuous-Conversion Mode
7.3.9 SMBUS
(COMP_LAT = 1)
ALERT/RDY
I2C
ALERT/RDY
SMBus
ALERT/RDY
ALERT/RDY
ADX111(Q)
SMBus
I 2C
SMBus
2
IC
SMBus
(00011001) I2C
ALERT/RDY
ADX111(Q)
I 2C
SMBus
1
0
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.4
7.4.1
ADX111(Q)
ADX111(Q)
ADC
CONFIG REGISTER
ADX111(Q)
I2C
ADX111(Q)
ADX111(Q)
(06h)
7.4.2
ADX111(Q)
CONFIG REGISTER
7.4.2.1
CONFIG REGISTER
MODE
1
ADX111(Q)
ADX111(Q)
CONFIG REGISTER
(OS)
OS
ADC
0
ADC
0
CONFIG REGISTER
ADX111(Q)
25 s
OS
1
OS
1
7.4.2.2
(MODE
0) ADX111(Q)
ADX111(Q)
CONVERSION
REGISTER
1
CONFIG REGISTER
MODE
7.4.3
ΔΣ ADC
ADX111(Q)
ADX111(Q)
125
ADX111(Q)
860SPS
860SPS
(8SPS)
123.8ms
ADX111(Q)
1.2ms
1/100
ADX111(Q)
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.5
7.5.1 I2C
I2C
ADX111(Q)
I2C
I2C
I 2C
master
ADX111(Q)
I2C
master
I 2C
I 2C
SDA
1) SDA
SCL SDA
SCL
slave
I2C
SCL
SDA
SCL
SCL
slave
(SDA
SDA
0
I2C
25
I 2C
SDA
START
START
master
ADX111(Q)
slave
slave
SCL
STOP
START
I 2C
START
7
I 2C
(
)
(
SDA
)
SDA
SDA
SDA
START
START
ADX111(Q) I2C
TIMING REQUIREMENTS
7.5.1.1 I2C
ADX111(Q)
I 2C
ADDR
Table 13
SCL
SDA
ADDR
SDA
100ns
GND VDD SDA
SCL
GND VDD
I 2C
SCL
Table 13. ADDR Pin Connection and Corresponding Slave Address
ADDR PIN CONNECTION
SLAVE ADDRESS
GND
VDD
SDA
1001000
1001001
1001010
SCL
1001011
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.5.1.2 I2C
0
ADX111(Q)
I2C
00000110 (06h) ADX111(Q)
(0000000)
7.5.1.3 I2C
100kHz
Hs
)
Hs
400kHz
(
3.4MHz ADX111(Q)
ADX111(Q)
00001xxx
xxx
/
ADX111(Q)
3.4MHz
START
Hs
Hs
I2C
ADX111(Q)
Hs
ADX111(Q)
Hs
I 2C
7.5.2
ADX111(Q)
ADX111(Q)
SCL
7.5.2.1
7
R/W
ADDRESS
P[1:0]
POINTER REGISTER
ADX111(Q)
ADX111(Q)
7.5.2.2
7
R/W
ADX111(Q)
P[1:0]
START
STOP
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.5.3
ADX111(Q)
P[1:0]
ADDRESS POINTER REGISTER
R/W
STOP
START
ADX111(Q)
P[1:0]
P[1:0]
P[1:0]
R/W
STOP
R/W
Figure 22
P[1:0]
ADX111(Q)
1
9
1
9
SCL
SDA
1
0
0
1
0
A1(1)
A0(1)
R/W
Start By
Master
0
0
0
0
0
0
P1
P0
ACK By
Device
ACK By
Device
Frame 1: Slave Address Byte
Stop By
Master
Frame 2: Address Pointer Register
1
9
1
9
SCL
(Continued)
SDA
(Continued)
1
0
0
1
0
A1(1)
A0(1)
R/W
Start By
Master
D15
ACK By
Device
Frame 3: Slave Address Byte
1
D14
D13
D12
D11
D10
D9
D8
From
Device
ACK By
Master(2)
Frame 4: Data Byte 1 Read Register
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
From
Device
ACK By
Master(3)
Stop By
Master
Frame 5: Data Byte 2 Read Register
(1) The values of A0 and A1 are determined by the ADDR pin.
(2) Master can leave SDA high to terminate a single-byte read operation.
(3) Master can leave SDA high to terminate a two-byte read operation.
Figure 22. Timing Diagram for Reading from ADX111(Q)
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
1
9
1
9
SCL
1
SDA
0
0
1
0
A1(1)
A0(1)
R/W
Start By
Master
0
0
0
0
0
0
P1
P0
ACK By
Device
ACK By
Device
Frame 1: Slave Address Byte
Frame 2: Address Pointer Register
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
ACK By
Device
D0
ACK By
Device
Frame 3: Data Byte 1
Stop By
Master
Frame 4: Data Byte 2
(1) The values of A0 and A1 are determined by the ADDR pin.
Figure 23. Timing Diagram for Writing to ADX111(Q)
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
R/W
Start By
Master
1
ACK By
Device
Frame 1: SMBus ALERT Response Address Byte
0
0
1
A1
A0
From
Device
Status
NACK By
Master
Stop By
Master
Frame 2: Slave Address
(1) The values of A0 and A1 are determined by the ADDR pin.
Figure 24. Timing Diagram for SMBus Alert Response
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
7.5.4
ADX111(Q)
8000h
16
(+FS)
7FFFh
Table 14
( FS)
Table 14. Input Signal versus Ideal Output Code
INPUT SIGNAL
VIN = (VAINP – VAINN)
IDEAL OUTPUT CODE
(EXCLUDES THE EFFECTS OF NOISE, INL, OFFSET, AND GAIN ERRORS)
≥ +FS (215 – 1) / 215
+FS / 215
0
–FS / 215
≤ –FS
7FFFh
0001h
0000h
FFFFh
8000h
Figure 25
7FFFh
7FFEh
Output
Code
..
.
0001h
0000h
FFFFh
..
.
8001h
8000h
–FS
–FS
+FS
0
Input Voltage VIN
215 – 1
215
+FS
215 – 1
215
Figure 25. Code Transition Diagram
ADX111(Q)
VAINN = 0V VAINP = 0V
VAINP
0V
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+FS
0000h
Public
7FFFh
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
8. REGISTER MAPS
The ADX111(Q) has four registers that are accessible through the I2C interface using the ADDRESS
POINTERREGISTER. The CONVERSION REGISTER contains the result of the last conversion. The CONFIG REGISTER
is used to change the ADX111(Q) operating modes and query the status of the device. The other two registers,
Lo_thresh and Hi_thresh, set the threshold values used for the comparator function.
8.1.1 ADDRESS POINTER REGISTER (ADDRESS = N/A) [RESET = N/A]
All four registers are accessed by writing to the Address Pointer register; see Figure 22.
Table 15. Address Pointer Register
7
6
5
4
3
0
0
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
0
W-0h
W-0h
0
P[1:0]
W-0h
Table 16. Address Pointer Field Descriptions
BIT
FIELD
TYPE
RESET
7:2
Reserved
W
0h
1:0
P[1:0]
W
0h
DESCRIPTION
Always write 0h
Register address pointer
00: Conversion register
01: Config register
10: Lo_thresh register
11: Hi_thresh register
8.1.2 CONVERSION REGISTER (P[1:0] = 0H) [RESET = 0000H]
The 16-bit Conversion register contains the result of the last conversion in binary two's complement format.
Following power-up, the Conversion register is cleared to 0, and remains 0 until the first conversion is
completed.
Table 17. Conversion Register
15
14
13
12
11
10
9
8
D15
R-0h
D14
R-0h
D13
R-0h
D12
R-0h
D11
R-0h
D10
R-0h
D9
R-0h
D8
R-0h
7
6
5
4
3
2
1
0
D2
R-0h
D1
R-0h
D0
R-0h
D7
D6
D5
D4
D3
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Conversion Register Field Descriptions
BIT
FIELD
TYPE
RESET
15:0
D[15:0]
R
0000h
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DESCRIPTION
16-bit conversion result
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
8.1.3 CONFIG REGISTER (P[1:0] = 1H) [RESET = 8583H]
The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range,
and comparator modes.
Table 19. Config Register
15
14
OS
R/W-1h
13
12
11
MUX[2:0]
R/W-0h
7
6
10
9
PGA[2:0]
R/W-2h
5
4
3
DR[2:0]
COMP_MODE COMP_POL
R/W-4h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8
MODE
R/W-1h
2
1
COMP_LAT
R/W-0h
0
COMP_QUE[1:0]
R/W-3h
Table 20. Config Register Field Descriptions
BIT
FIELD
TYPE
RESET
15
OS
R/W
1h
14:12
MUX[2:0]
R/W
0h
11:9
PGA[2:0]
R/W
2h
8
MODE
R/W
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1h
DESCRIPTION
Operational status or single-shot conversion start
This bit determines the operational status of the device. OS can only
be written when in power-down state and has no effect when a
conversion is ongoing.
When writing:
0: No effect
1: Start a single conversion (when in power-down state)
When reading:
0: Device is currently performing a conversion.
1: Device is not currently performing a conversion.
Input multiplexer configuration
These bits configure the input multiplexer.
000: AINP = AIN0 and AINN = AIN1 (default)
001: AINP = AIN0 and AINN = AIN3
010: AINP = AIN1 and AINN = AIN3
011: AINP = AIN2 and AINN = AIN3
100: AINP = AIN0 and AINN = GND
101: AINP = AIN1 and AINN = GND
110: AINP = AIN2 and AINN = GND
111: AINP = AIN3 and AINN = GND
Programmable gain amplifier configuration
These bits set the FSR of the programmable gain amplifier.
000: FSR = ±6.144V(1)
001: FSR = ±4.096V(1)
010: FSR = ±2.048V (default)
011: FSR = ±1.024V
100: FSR = ±0.512V
101: FSR = ±0.256V
110: FSR = ±0.256V
111: FSR = ±0.256V
Note: This parameter expresses the full-scale range of the ADC
scaling. Do not apply more than VDD + 0.3V to the analog inputs of
the device.
Device operating mode
This bit controls the operating mode.
0: Continuous-conversion mode
1: Single-shot mode or power-down state (default)
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
BIT
7:5
4
3
FIELD
DR[2:0]
COMP_MODE
COMP_POL
TYPE
R/W
R/W
R/W
RESET
4h
0h
Comparator mode
This bit configures the comparator operating mode.
0: Traditional comparator (default)
1: Window comparator
0h
Comparator polarity
This bit controls the polarity of the ALERT/RDY pin.
0: Active low (default)
1: Active high
2
COMP_LAT
R/W
0h
1:0
COMP_QUE[1:0]
R/W
3h
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DESCRIPTION
Data rate
These bits control the data rate setting.
000: 8SPS
001: 16SPS
010: 32SPS
011: 64SPS
100: 128SPS (default)
101 : 250SPS
110: 475SPS
111 : 860SPS
Latching comparator
This bit controls whether the ALERT/RDY pin latches after being
asserted or clears after conversions are within the margin of the
upper and lower threshold values.
0: Nonlatching comparator. The ALERT/RDY pin does not latch when
asserted (default).
1: Latching comparator. The asserted ALERT/RDY pin remains
latched until conversion data are read by the master or an
appropriate SMBus alert response is sent by the master. The device
responds with its address, and it is the lowest address currently
asserting the ALERT/RDY bus line.
Comparator queue and disable
These bits perform two functions. When set to 11, the comparator is
disabled and the ALERT/RDY pin is set to a high-impedance state.
When set to any other value, the ALERT/RDY pin and the
comparator function are enabled, and the set value determines
the number of successive conversions exceeding the upper or
lower threshold required before asserting the ALERT/RDY pin.
00: Assert after one conversion
01: Assert after two conversions
10: Assert after four conversions
11: Disable comparator and set ALERT/RDY pin to high-impedance
(default)
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
8.1.4 LO_THRESH (P[1:0] = 2H) [RESET = 8000H] AND HI_THRESH (P[1:0] = 3H)
[RESET = 7FFFH] REGISTERS
The upper and lower threshold values used by the comparator are stored in two 16-bit registers in two's
complement format. The comparator is implemented as a digital comparator; therefore, the values in these
registers must be updated whenever the PGA settings are changed.
The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1 and
the Lo_thresh register MSB to 0. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register
value must always be greater than the Lo_thresh register value. The threshold register formats are shown in
Table 21. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and provides
a continuous-conversion ready pulse when in continuous-conversion mode.
Table 21. Lo_thresh Register
15
14
13
12
11
10
9
8
Lo_thresh15
R/W-1h
Lo_thresh14
R/W-0h
Lo_thresh13
R/W-0h
Lo_thresh12
R/W-0h
Lo_thresh11
R/W-0h
Lo_thresh10
R/W-0h
Lo_thresh9
R/W-0h
Lo_thresh8
R/W-0h
7
6
5
4
3
2
1
0
Lo_thresh2
R/W-0h
Lo_thresh1
R/W-0h
Lo_thresh0
R/W-0h
Lo_thresh7
Lo_thresh6
Lo_thresh5
Lo_thresh4
Lo_thresh3
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Hi _thresh Register
15
14
13
12
11
10
9
8
Hi_thresh15
Hi_thresh14
Hi_thresh13
Hi_thresh12
Hi_thresh11
Hi_thresh10
Hi_thresh9
Hi_thresh8
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
7
6
5
4
3
2
1
0
Hi_thresh2
R/W-1h
Hi_thresh1
R/W-1h
Hi_thresh0
R/W-1h
Hi_thresh7
Hi_thresh6
Hi_thresh5
Hi_thresh4
Hi_thresh3
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Lo_thresh and Hi_thresh Register Field Descriptions
BIT
FIELD
TYPE
RESET
15:0
15:0
Lo_thresh[15:0]
Hi_thresh[15:0]
R/W
R/W
8000h
7FFFh
© 2023 AnalogySemi Ltd. All Rights Reserved.
DESCRIPTION
Low threshold value
High threshold value
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
9.
AnalogySemi
AnalogySemi
9.1
ADX111(Q)
9.1.1
ADX111(Q)
I2C
Figure 26
10
Device
VDD
1kΩ to 10kΩ (typ)
Pullup Resistors
Microcontroller or
Microprocessor
with I2C Port
VDD
SCL
1
ADDR
SDA
9
2
ALERT/RDY
VDD
8
3
GND
AIN3
7
4
AIN0
AIN2
6
0.1µ F (typ)
AIN1
5
SCL
SDA
GPIO
Inputs Selected
from Configuration
Register
Figure 26. Typical Connections of the ADX111(Q)
ADX111(Q)
ADX111(Q)
ADX111(Q)
0.1μF
I2C
ADX111(Q)
ADX111(Q)
ADX111(Q)
I2C
(
I 2C
)
I2C
SDA
SCL
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I2C
Public
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
9.1.2
ADX111(Q)
Figure 27
ADX111(Q)
ADX111(Q)
CONFIG REGISTER
0V
+FS
ADX111(Q)
ADX111(Q)
ADX111(Q)
MUX[2:0]
FSR
ADC
VDD
10
Device
Output Codes
0-32767
SCL
1 ADDR
SDA 9
2 ALERT/RDY
VDD 8
3 GND
AIN3 7
4 AIN0
AIN2 6
0.1µ F (typ)
AIN1
5
Inputs Selected
from Configuration
Register
NOTE: Digital pin connections omitted for clarity.
Figure 27. Measuring Single-Ended Inputs
MUX[2:0]
ADX111(Q)
ADX111(Q)
GND < V(AIN3) < VDD
AIN3
AIN0
AIN1
AIN2
AIN3
AIN3
9.1.3
ADX111(Q)
ADX111(Q)
ADX111(Q)
300mV
10mA
9.1.4
VDD
ALERT/RDY
© 2023 AnalogySemi Ltd. All Rights Reserved.
GND
VDD
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
9.1.5
1.
2.
ADC
(
)
(fMOD)
Figure 28
Magnitude
Sensor
Signal
Output
Data Rate
Magnitude
Unwanted
Signals
Unwanted
Signals
fMOD / 2
fMOD
Frequency
fMOD
Frequency
fMOD
Frequency
Digital Filter
Aliasing of
Unwanted Signals
Output
Data Rate
fMOD / 2
Magnitude
External
Antialiasing Filter
Roll-Off
Output
Data Rate
fMOD / 2
Figure 28. Effect of Aliasing
ΔΣ ADC
(EMI)
(RC)
(
fMOD/2
(RFI)
(PCB)
)
ADC
ADX111(Q)
10
RC
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
9.1.6
SDA
I2 C
GND VDD
ADX111(Q)
I2C
100ns
I 2C
ADX111(Q)
SCL
Figure 29
SDA
SCL
I 2C
ADX111(Q)
VDD
GND
10
Device
SCL
1 ADDR
1kΩ to 10kΩ (typ)
I2C Pullup Resistors
Microcontroller or
Microprocessor
with I2C Port
VDD
SDA
9
2 ALERT/RDY
VDD
8
3 GND
AIN3
7
AIN2
6
1 ADDR
SDA
9
2 ALERT/RDY
VDD
8
3 GND
AIN3
7
AIN2
6
1 ADDR
SDA
9
2 ALERT/RDY
VDD
8
3 GND
AIN3
7
AIN2
6
1 ADDR
SDA
9
2 ALERT/RDY
VDD
8
3 GND
AIN3
7
AIN2
6
4 AIN0
AIN1
5
SCL
SDA
10
Device
SCL
4 AIN0
AIN1
5
10
Device
SCL
4 AIN0
AIN1
5
10
Device
SCL
4 AIN0
AIN1
5
NOTE: Device power and input connections omitted for clarity. The ADDR pin selects the I 2C address.
Figure 29. Connecting Multiple ADX111(Q) Devices
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
9.1.7
I2C
ADX111(Q)
1001000
ADX111(Q)
Figure 30
ADX111(Q)
ADX111(Q)
I2C
I2C
(
2V
)
SCL
5V
SDA
SCL
ADX111(Q)
ADX111(Q)
POINTER REGISTER
22
Figure 23
R/W
P[1:0]
START
ADX111(Q)
ADDRESS
Figure
STOP
ADX111(Q)
1.
2.
3.
Config register
0b10010000 (
0b00000001 (
0b10000100 (
0b10000011 (
Address Pointer register
0b10010000 (
0b00000000 (
7
I2C
Config register)
Config
Config
R/W )
MSB)
LSB)
7
I2C
Conversion
R/W
)
Conversion register
0b10010001 (
7
I 2C
ADX111(Q)
Conversion register
ADX111(Q)
Conversion register
)
R/W
MSB
LSB
)
3.3V
Device
VDD
0.1μF
GND
3.3V
AIN0
I2C-Capable Master
AIN1
ADDR
AIN2
AIN3
10kΩ
3.3V
10kΩ
SCL
SCL
SDA
SDA
VDD
0.1μF
GND
ALERT
JTAG
Serial/UART
Figure 30. Basic Hardware Configuration
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
10.
VDD
10.1
VDD
50µs
10.2
VDD
(ESR)
0.1µF
Figure 31
(ESL)
0.1µF
(MLCC)
VDD
ADDR
1
10
SCL
ALERT/RDY
2
9
SDA
3
8
AIN0
4
7
AIN3
AIN1
5
6
AIN2
GND
VDD
0.1µ F
Figure 31. ADX111(Q) Power-Supply Decoupling
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
11.
11.1
ADX111(Q)
ADC
•
•
•
AIN0
AIN1
AIN2
AIN3
C0G (NPO)
11.2
EVM
AnalogySemi
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
12. PACKAGE INFORMATION
The ADX111(Q) is available in the MSOP-10 and QFN-10 packages.
12.1 MSOP-10 PACKAGE
Figure 32 shows the MSOP-10 package view.
b
c
E1
E
L
e
A2
A1
A
D
Figure 32. MSOP-10 Package View
Table 24 provides detailed information about the dimensions of the MSOP-10 package.
Table 24. Dimensions of the MSOP-10 Package
SYMBOL
DIMENSIONS IN MILLIMETERS
MIN
MAX
DIMENSIONS IN INCHES
MIN
MAX
A
A1
A2
b
--0.020
0.750
0.180
1.100
0.150
0.950
0.330
--0.001
0.030
0.007
0.043
0.006
0.037
0.013
c
D
e
E
E1
L
θ
0.090
2.900
0.230
3.100
0.004
0.114
0.009
0.122
5.050
3.100
0.800
6°
0.187
0.114
0.016
0°
0.500 (BSC)
4.750
2.900
0.400
0°
© 2023 AnalogySemi Ltd. All Rights Reserved.
0.020 (BSC)
Public
0.199
0.122
0.031
6°
www.analogysemi.com | Page 35 of 39
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
12.2 QFN-10 PACKAGE
Figure 33 shows the QFN-10 package view.
N9
L1
D
N1
N6
N4
b2
b
E
e
L
b1
Top View
A3
A
A1
Bottom View
Figure 33. QFN-10 Package View
Table 25 provides detailed information about the dimensions of the QFN-10 package.
Table 25. Dimensions of the QFN-10 Package
SYMBOL
A
A1
A3
b
b1
b2
D
E
e
L
L1
Page 36 of 39 | www.analogysemi.com
DIMENSIONS IN MILLIMETERS
MIN
MAX
0.500
0.000
DIMENSIONS IN INCHES
MIN
MAX
0.600
0.050
0.020
0.000
0.250
0.350
0.300
1.550
2.050
0.006
0.010
0.008
0.057
0.077
0.400
0.450
0.012
0.014
0.152REF.
0.150
0.250
0.200
1.450
1.950
0.006REF.
0.500TYP.
0.300
0.350
0.024
0.002
0.010
0.014
0.012
0.061
0.081
0.020TYP.
Public
0.016
0.018
© 2023 AnalogySemi Ltd. All Rights Reserved.
ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
13. TAPE AND REEL INFORMATION
13.1 MSOP-10 PACKAGE
Figure 34 illustrates the carrier tape of the MSOP-10 package.
8.00± 0.10
+0.10
4.00± 0.10
1.50 0
2.00± 0.05
1.75± 0.10
0.25± 0.02
+0.30
12.00 –0.10
A
5.50± 0.05
B
A
3.30± 0.10
7º MAX
+0.25
1.50 –0
1.50± 0.10
8º MAX
B-B
1.20
3.20
B
5.20±0.10
A-A
Notes:
1. Cover tape width: 9.5 ± 0.10.
2. Cumulative tolerance of 10 sprocket hole pitch: ± 0.20 (max).
3. Camber: not to exceed 1mm in 100mm.
4. Mold#: MSOP-10 (3*3).
5. All dimensions: mm.
6. Direction of view:
Figure 34. Carrier Tape Drawing (MSOP-10 Package)
Table 26 provides information about tape and reel (MSOP-10 package).
Table 26. Tape and Reel Information (MSOP-10 Package)
PACKAGE
TYPE
REEL
QTY/REEL
REEL/
INNER BOX
INNER BOX/
CARTON
QTY/CARTON
INNER BOX
SIZE (MM)
CARTON
SIZE (MM)
MSOP-10
3*3
13’’
3000
1
8
24000
358*340*50
430*380*390
Figure 35 shows the product loading orientation—pin 1 is assigned on the upper left corner.
Pin 1
Figure 35. Product Loading Orientation (MSOP-10 Package)
© 2023 AnalogySemi Ltd. All Rights Reserved.
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
13.2 QFN-10 PACKAGE
Figure 36 illustrates the carrier tape (QFN-10 package).
4± 0.1
4± 0.1
2.3± 0.08
+0.3
8 –0.1
3.5± 0.05
1.75± 0.1
2± 0.05
0.2± 0.03
0.75± 0.05
1.7± 0.08
Notes:
1. Cover tape width: 5.5 ± 0.10.
2. Cumulative tolerance of 10 sprocket hole pitch: ± 0.20 (max).
3. Camber: not to exceed 1mm in 100mm.
4. Mold#: QFN-10 (1.5*2).
5. All dimensions: mm.
6. Direction of view:
Figure 36. Carrier Tape Drawing (QFN-10 Package)
Table 27 provides information about tape and reel (QFN-10 package).
Table 27. Tape and Reel Information (QFN-10 Package)
PACKAGE
TYPE
REEL
QTY/REEL
REEL/
INNER BOX
INNER BOX/
CARTON
QTY/CARTON
INNER BOX
SIZE (MM)
CARTON
SIZE (MM)
QFN-10
1.5*2
7’’
4000
10
4
160000
210*208*203
440*440*230
Figure 37 shows the product loading orientation—pin 1 is assigned on the upper left corner.
Pin 1
Figure 37. Product Loading Orientation (QFN-10 Package)
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ADX111/ADX111Q
Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs
With Internal Reference, Oscillator, and Programmable Comparator
REVISION HISTORY
REVISION
DATE
Rev A
13 January 2023
© 2023 AnalogySemi Ltd. All Rights Reserved.
DESCRIPTION
Rev A release.
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