System-on-Module datasheet
Version 1.11
Features
●
●
●
●
●
●
●
●
●
●
●
●
NXP iMX 8M SoC
○ Quad-core ARM Cortex-A53, plus Cortex-M4F
○ 2D/3D Vivante GC7000 Lite GPU and VPU
Google Edge TPU ML accelerator
Cryptographic coprocessor
Wi-Fi 2x2 MIMO (802.11b/g/n/ac 2.4/5 GHz)
Bluetooth 4.2
8 or 16 GB eMMC
1, 2, or 4 GB LPDDR4
USB 3.0
Gigabit Ethernet
HDMI and MIPI-DSI
MIPI-CSI-2
Up to 95x GPIO (including SPI, I2C, PWM, UART, SAI, and SDIO)
Description
The Coral System-on-Module (SoM) is a fully-integrated system that helps you build embedded systems that demand fast
machine learning (ML) inferencing. It contains NXP's iMX 8M system-on-chip (SoC), eMMC memory, LPDDR4 RAM, Wi-Fi,
and Bluetooth, but its unique power comes from Google's Edge TPU coprocessor.
The Edge TPU is a small ASIC designed by Google that accelerates TensorFlow Lite models in a power efficient manner: it's
capable of performing 4 trillion operations per second (4 TOPS), using 2 watts of power—that's 2 TOPS per watt. For
example, the Edge TPU can execute state-of-the-art mobile vision models such as MobileNet v2 at almost 400 frames per
second. This on-device ML processing reduces latency, increases data privacy, and removes the need for a constant
internet connection.
Key benefits of the SoM:
● High-speed and low-power ML inferencing (4 TOPS @2 W)
● A complete Linux system (running Mendel, a Debian derivative)
● Small footprint (40 x 48 mm)
The SoM is also included in the Coral Dev Board, which is a single-board computer that enables fast prototyping and
evaluation of the standalone SoM.
Coral.ai | Copyright 2019 Google LLC.
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Ordering information
Part number
Description
G650-04474-01
Coral System-on-Module with 1 GB RAM (8 GB eMMC)
G650-05369-01
Coral System-on-Module with 2 GB RAM (8 GB eMMC)
G650-05370-01
Coral System-on-Module with 4 GB RAM (16 GB eMMC)
Coral.ai | Copyright 2019 Google LLC.
2
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Table of contents
Features
1
Description
1
Ordering information
2
Table of contents
3
1 System components
4
1.1 Block diagrams
7
2 Mechanical dimensions
9
3 System power
9
3.1 Power signals
3.2 Power consumption
3.3 Edge TPU power characteristics
10
11
12
4 Boot mode
13
5 Peripheral interfaces
13
5.1 MIPI camera (CSI)
5.2 MIPI display (DSI)
5.3 HDMI
5.4 Ethernet
5.5 PCIe
5.6 USB
5.7 Digital audio (SAI)
5.8 Sony/Philips audio (SPDIF)
5.9 Micro-SD card
5.10 JTAG debugging
5.11 I2C
5.12 UART
5.13 SPI
5.14 GPIO
5.15 PWM
14
14
15
15
16
16
17
19
20
20
21
21
22
22
23
6 Wi-Fi and Bluetooth
23
7 Baseboard developer guide
24
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Reference design
Baseboard connectors
Connectors, keepouts, and component max heights
Trace impedance recommendations
MIPI trace length compensation
Thermal management
Other recommendations
24
24
24
25
26
27
27
8 Pinout schematic
28
9 Environmental reliability
28
10 Document revisions
29
Coral.ai | Copyright 2019 Google LLC.
3
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
1 System components
Table 1. Available SoM components and features
Feature
Details
Main system-on-chip (iMX 8M)
Arm Cortex-A53 MPCore platform
Quad symmetric Cortex-A53 processors:
● 32 KB L1 Instruction Cache
● 32 KB L1 Data Cache
● Support L1 cache RAMs protection with parity/ECC
Support of 64-bit Armv8-A architecture:
● 1 MB unified L2 cache
● Support L2 cache RAMs protection with ECC
● Frequency of 1.5 GHz
Arm Cortex-M4 core platform
●
●
●
16 KB L1 Instruction Cache
16 KB L1 Data Cache
256 KB tightly coupled memory (TCM)
Graphic Processing Unit (GPU)
●
●
●
●
●
●
Vivante GC7000Lite
4 shaders
267 million triangles/sec
1.6 Gigapixel/sec
32 GFLOPs 32-bit or 64 GFLOPs 16-bit
Supports OpenGL ES 1.1, 2.0, 3.0, 3.1, Open CL 1.2, and Vulkan
Video Processing Unit (VPU)
●
●
4Kp60 HEVC/H.265 main, and main 10 decoder
4Kp60 VP9 and 4Kp30 AVC/H.264 decoder (requires full system
resources)
1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263
decoder
●
I/O connectivity
●
●
●
●
●
●
●
●
●
2x USB 3.0/2.0 controllers with integrated PHY interfaces
1x Ultra Secure Digital Host Controller (uSDHC) interfaces
1x Gigabit Ethernet controller with support for EEE, Ethernet AVB,
and IEEE 1588
2x UART modules
2x I2C modules
2x SPI modules
16x GPIO lines with interrupt capability
4x PWM lines
Input/output multiplexing controller (IOMUXC) to provide centralized
pad control
Note: The list above is the number of signals available to the baseboard
(after considering SoC signals used by the SoM).
On-chip memory
●
●
Boot ROM (128 KB)
On-chip RAM (128 KB + 32 KB)
Coral.ai | Copyright 2019 Google LLC.
4
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Display
Audio
HDMI Display Interface:
● HDMI 2.0a supporting one display up to 1080p
● Upscale and downscale between 4K and HD video (requires full
system resources)
● 20+ Audio interfaces 32-bit @ 384 kHz fs, with Time Division
Multiplexing (TDM) support
● SPDIF input and output
● Audio Return Channel (ARC) on HDMI
MIPI-DSI Display Interface:
● MIPI-DSI 4 channels supporting one display, resolution up to
1920 x 1080 at 60 Hz
● LCDIF display controller
● Output can be LCDIF output or DC display controller output
●
●
1x SPDIF input and output
2x synchronous audio interface (SAI) modules supporting I2S, AC97,
TDM, and codec/DSP interfaces
1x SAI for 8 Tx channels for HDMI output audio
1x SPDIF input for HDMI ARC input
Camera
●
2x MIPI-CSI2 camera inputs (4-lane each)
Security
●
Resource Domain Controller (RDC) supports four domains and up to
eight regions
Arm TrustZone (TZ) architecture
On-chip RAM (OCRAM) secure region protection using OCRAM
controller
High Assurance Boot (HAB)
Cryptographic acceleration and assurance (CAAM) module
Secure non-volatile storage (SNVS): Secure real-time clock (RTC)
Secure JTAG controller (SJC)
●
●
●
●
●
●
●
●
ML accelerator
Edge TPU coprocessor
●
●
●
ASIC designed by Google that provides high performance ML
inferencing for TensorFlow Lite models
Uses PCIe Gen2 x1 and I2C/GPIO to interface with the iMX 8M SoC
4 trillion operations per second (TOPS)
2 TOPS per watt
Random access memory (SDRAM)
●
●
●
1, 2, or 4 GB LPDDR4 SDRAM (4-channel, 32-bit bus width)
1600 MHz maximum DDR clock
Interfaces directly to the iMX 8M build-in DDR controller
Flash memory (eMMC)
●
8 GB eMMC (KLMBG4GEND-B031) for the 1 and 2 GB RAM models
or 16 GB eMMC (EMMC16G-TB29-PZ90) for the 4 GB RAM model
8-bits MMC mode
Conforms to JEDEC version 5.0 and 5.1
●
Memory and storage
●
●
Expandable flash support
●
●
●
Meets SD/SDIO 3.0 standard
Runs at 4-bits SDIO mode
Supports system boot from SD card
Coral.ai | Copyright 2019 Google LLC.
5
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Network & wireless
Ethernet
●
●
10/100/1000 Mbps Ethernet/IEEE 802.3 networks
Reduced gigabit media-independent interface (RGMII)
Wi-Fi
Murata LBEE5U91CQ module:
● Wi-Fi 2x2 MIMO (802.11a/b/g/n/ac 2.4/5 GHz)
● Supports PCIe host interface for W-LAN
Bluetooth
Murata LBEE5U91CQ module:
● Bluetooth 4.2 (supports Bluetooth low-energy)
● Supports UART interface
Security
Cryptographic coprocessor
Microchip ATECC608A cryptographic coprocessor:
● Asymmetric (public/private) key cryptographic signature solution
based on Elliptic Curve Cryptography and ECDSA signature
protocols
Hardware interface
Baseboard connectors
3x 100-pin connectors (Hirose DF40C-100DP-0.4V)
Coral.ai | Copyright 2019 Google LLC.
6
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
1.1 Block diagrams
Figures 1 and 2 illustrate the core components on the SoM and SoC.
Figure 1. Block diagram of the SoM components
Coral.ai | Copyright 2019 Google LLC.
7
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Figure 2. Block diagram of iMX 8M SoC components, provided by NXP (some I/O signals on the SoC are consumed on the
SoM, so refer to table 1 for availability)
Coral.ai | Copyright 2019 Google LLC.
8
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
2 Mechanical dimensions
Table 2. SoM mechanical dimensions
Measurement
Value
Size
48 x 40 x 5.11 mm
Weight
13 g
Figure 3 illustrates all of the SoM's dimensions. For a top-down view of the baseboard connector locations and component
height restrictions, see the Baseboard developer guide.
Figure 3. SoM dimensions (in millimeters)
3 System power
The SoM requires 5 V as power input (at VSYS_5V). The SoM then generates the local voltage rails for all SoM components
through on-board PMICs.
Table 3. SoM power requirements
Power input
Voltage
Main power supply (VSYS_5V)
5 V ± 5%
Caution: Do not connect the 1.8/3.3 V power output pins to any high current devices or you might brownout the system.
These power lines are shared with internal SoM circuits, so there is no safe limit for a high current device, but you can
safely use them for low current tasks such as for a level shifter or pull-up/down.
Caution: Do not connect any of the 3.3 V I/O pins to a device that draws more than ~82 mA of power or you will
brownout the system.
Coral.ai | Copyright 2019 Google LLC.
9
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
3.1 Power signals
Even though there are multiple power signals defined in the board-to-board connectors, only the VSYS_5V and ground
connections are required. All others are optional.
Note: Make sure to route all the VSYS_5V and GND pins, and add decoupling (bypass) capacitors between VSYS_5V
and GND near the mating connector pins.
Table 4. Power and reset pin signals
Name
Type
Connector Pins
Voltage
Description
VSYS_5V
Power
J1312
93, 94, 95, 96, 97, 98, 99, 100
5 V
Main 5 V power input to SoM.
Must be connected.
GND
Power
J1312
9, 10, 65, 66, 71, 72, 77, 78, 83,
84
Common ground.
Must be connected.
GND
Power
J1311
1, 2, 7, 8, 13, 14, 19, 20, 25, 26,
31, 32, 37, 38, 43, 44, 49, 50,
55, 56, 61, 62, 67, 68, 73, 74,
79, 80, 86, 89, 90, 94, 99, 100
Common ground.
Must be connected.
GND
Power
J1310
1, 2, 7, 25, 39, 40, 42, 44, 45,
46, 50, 51, 56, 57, 62, 63, 64,
65, 66, 67, 68, 69, 70, 71, 72,
73, 74, 75, 76, 77, 78, 80
Common ground.
Must be connected.
DCDC_3V3
Power
J1310
84, 86, 88, 90
3.3 V
3.3 V output from SoM. Can be left
floating if not used. Not for
high-current usage; can be used to
pull-up GPIO.
VDD_3V3
Power
J1310
94, 96, 98 100
3.3 V
3.3 V output from SoM. Can be left
floating if not used. Not for
high-current usage; can be used to
pull-up GPIO.
VDDA_1V8
Power
J1310
91, 93, 95, 97, 99
1.8 V
1.8 V output from SoM. Can be left
floating if not used. Not for
high-current usage; can be used to
pull-up GPIO.
POR_B
Output
J1310
79
3.3 V
"Power_On_Reset" signal from iMX
8M PMIC to reset the SoC
(active-low open-drain output).
Available to enable sequencing.
PWRON_B
Input
J1312
86
3.3 V
"Power_On" (active-low input).
Triggers a reset of the iMX 8M
PMIC power cycle.
Pull-up in SoM.
SYS_nRST
Input
J1312
63
3.3 V
System reset (active-low input).
Recommended for reset button on
baseboard.
Pull-up in SoM.
Coral.ai | Copyright 2019 Google LLC.
10
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
3.2 Power consumption
Caution: You must provide a cooling solution to ensure the SoM surface maintains an operational temperature as
specified in the Environmental reliability section. Unlike the Coral Dev Board, the standalone SoM does not include a
cooling solution (the SoM components are covered only with an EMI shield).
The power consumption numbers listed in this section are based on a high performance test that includes the following:
● GPU: 3D rendering
● CPU: 2 of 4 cores 100% loaded
● Active Wi-Fi download
● 7" HDMI display on
● DDR: 800 MHz
● Edge TPU running MobileNet V1 at 500 MHz
● Fan intermittently on
Table 5 lists the power draw measurements during different operational tests both for both the SoM, and for the Dev Board
baseboard and SoM working together.
Table 5. SoM power draw measurements
Operational test
SoM power
System power (SoM + Dev Board baseboard)*
Idle
2.6 W
4.0 W
Idle with HDMI display on
3.0 W
4.3 W
High performance
6.2 W
8.5 W
* Tested with Coral Dev Board—performance on your custom baseboard may vary.
During the high performance test, the top power-consuming components (top heat sources) are as indicated in figure 4.
Figure 4. Power draw and ordinate locations (in millimeters) of top power components during high performance test
Coral.ai | Copyright 2019 Google LLC.
11
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
3.3 Edge TPU power characteristics
The current drawn by the Edge TPU is highly variable and depends on the model being executed. Although the average
current drawn by the Edge TPU may be less than 500 mA, it can repeatedly and rapidly spike up to 3 A, depending on the
model you're running. These spikes also occur suddenly: even a simple model can generate current transients in excess of
1 A/μs, which can last several tens of microseconds.
The Edge TPU dissipates power roughly proportional to its computational load. The resulting heat in the Edge TPU die must
be safely and reliably conducted away to avoid excessive die temperatures that can affect performance and reliability.
The Edge TPU’s junction temperature Tj must stay below the maximum operating specification:
● Maximum Edge TPU junction temperature Tj: 115 °C
Warning: Exceeding the maximum temperature can result in permanent damage to the Edge TPU and surrounding
components, and can possibly cause fire and serious damage, injury, or death.
For information about thermal management strategies for the Edge TPU, see section 7.6.
Coral.ai | Copyright 2019 Google LLC.
12
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
4 Boot mode
Use the BOOT_MODE[1:0] pins to configure the SoM boot mode setting as indicated in the following tables.
Table 6. Boot mode pin signals
Name
Type
Connector
Pins
Voltage
Description
BOOT_MODE0
Input
J1312
64
3.3 V
SoC BOOT_MODE0 signal (can be set by
switch or pin-strap on baseboard)
BOOT_MODE1
Input
J1312
62
3.3 V
SoC BOOT_MODE1 signal (can be set by
switch or pin-strap on baseboard)
Table 7. Boot mode pin settings
BOOT_MODE[1:0] bits
Boot type
00
Boot from fuses (default behavior)
01
Serial downloader
10
Internal boot
11
Reserved
The boot configuration is specified by the iMX 8M SoC, so for more details, refer to the iMX 8M SoC documentation.
Note: If BOOT_MODE[1:0] is "10" (internal boot), then GPIO pins SAI1_RX[7:0] and SAI1_TX[7:0] are used to enable boot
configuration overrides (such as whether to boot from eMMC or SD card) by latching them to the BOOT_CFG[15:0] bits in
the SoC. For further details, such as information about GPIO boot overrides and boot fuses, see the iMX 8M SoC
documentation.
5 Peripheral interfaces
The following interfaces are available from the SoM, through the three 100-pin board-to-board connectors.
This section is organized based on the default pin functions when running the Mendel operating system. For information
about alternative pin functions you may enable with your own device tree overlay, see the iMX 8M SoC documentation.
Note: All I/O pins have a 90 k pull-down resistor in the SoC that are used by default during bootup, which you can
reconfigure with a device tree overlay after bootup. However, some pins (such as I2C, some SAI, and some SD2 pins)
also have pull-up resistors inside the SoM, as noted in the following tables, which you cannot reconfigure with a device
tree overlay.
Caution: Do not connect any of the 3.3 V I/O pins to a device that draws more than ~82 mA of power or you will
brownout the system.
Coral.ai | Copyright 2019 Google LLC.
13
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
5.1 MIPI camera (CSI)
There are two channels for MIPI camera serial interface (CSI-2), each with four lanes and a maximum bit rate of 1.5 Gbps.
Table 8. CSI channel 1 pins
Name
Type
Connector
Pins
Voltage
Description
MIPI_CSI1_CLK_P/N
Input
J1311
18/16
0.2-1.2 V
MIPI CSI1 clock (positive/negative)
MIPI_CSI1_D0_P/N
Input
J1311
12/10
0.2-1.2 V
MIPI CSI1 data (positive/negative)
MIPI_CSI1_D1_P/N
Input
J1311
23/21
0.2-1.2 V
MIPI CSI1 data (positive/negative)
MIPI_CSI1_D2_P/N
Input
J1311
6/4
0.2-1.2 V
MIPI CSI1 data (positive/negative)
MIPI_CSI1_D3_P/N
Input
J1311
29/27
0.2-1.2 V
MIPI CSI1 data (positive/negative)
Name
Type
Connector
Pins
Voltage
Description
MIPI_CSI2_CLK_P/N
Input
J1311
36/34
0.2-1.2 V
MIPI CSI2 clock (positive/negative)
MIPI_CSI2_D0_P/N
Input
J1311
35/33
0.2-1.2 V
MIPI CSI2 data (positive/negative)
MIPI_CSI2_D1_P/N
Input
J1311
30/28
0.2-1.2 V
MIPI CSI2 data (positive/negative)
MIPI_CSI2_D2_P/N
Input
J1311
24/22
0.2-1.2 V
MIPI CSI2 data (positive/negative)
MIPI_CSI2_D3_P/N
Input
J1311
41/39
0.2-1.2 V
MIPI CSI2 data (positive/negative)
Table 9. CSI channel 2 pins
5.2 MIPI display (DSI)
The four-lane MIPI display serial interface (DSI) offers the following features:
● Resolution up to 1920 x 1080 at 60 Hz
● LCDIF display controller
● Maximum bit rate of 1.5 Gbps
Table 10. DSI pins
Name
Type
Connector
Pins
Voltage
Description
MIPI_DSI1_CLK_P/N
Output
J1311
59/57
0.2-1.2 V
MIPI DSI clock (positive/negative)
MIPI_DSI1_D0_P/N
Output
J1311
47/45
0.2-1.2 V
MIPI DSI data (positive/negative)
MIPI_DSI1_D1_P/N
Output
J1311
54/52
0.2-1.2 V
MIPI DSI data (positive/negative)
MIPI_DSI1_D2_P/N
Output
J1311
42/40
0.2-1.2 V
MIPI DSI data (positive/negative)
MIPI_DSI1_D3_P/N
Output
J1311
48/46
0.2-1.2 V
MIPI DSI data (positive/negative)
Coral.ai | Copyright 2019 Google LLC.
14
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
5.3 HDMI
The High-Definition Multimedia Interface (HDMI) connection provides the following features:
● HDMI 2.0a supporting one display up to 1080p
● Upscale and downscale between 4K and HD video (requires full system resources)
● 20+ Audio interfaces 32-bit @ 384 kHz fs, with Time Division Multiplexing (TDM) support
● SPDIF input and output
● Audio Return Channel (ARC) on HDMI
Table 11. HDMI pins
Name
Type
Connector
Pins
Voltage
Description
HDMI_REFCLKP/N
Output
J1310
58/60
3.3 V
HDMI reference clock (27 MHz) (positive/negative).
Required for bootup, even if you don't use HDMI.
For detail, see the reference design schematic.
HDMI_CLKP/N
Output
J1312
68/70
3.3 V
HDMI clock (positive/negative)
HDMI_TX0_P/N
Output
J1312
75/73
3.3 V
HDMI transmit (positive/negative)
HDMI_TX1_P/N
Output
J1312
79/81
3.3 V
HDMI transmit (positive/negative)
HDMI_TX2_P/N
Output
J1312
76/74
3.3 V
HDMI transmit (positive/negative)
HDMI_AUX_P/N
Output
J1312
82/80
3.3 V
HDMI AUX (positive/negative)
HDMI_HPD
Output
J1312
89
3.3 V
HDMI Hot Plug Detect
HDMI_DDC_SDA
Output
J1312
85
3.3 V
HDMI Display Data Channel data
HDMI_DDC_SCL
Output
J1312
87
3.3 V
HDMI Display Data Channel clock
HDMI_CEC
Output
J1312
91
3.3 V
HDMI Consumer Electronic Control
5.4 Ethernet
The Ethernet Media Access Controller (MAC) supports 10/100/1000 Mbps Ethernet/IEEE 802.3 networks with reduced
gigabit media-independent interface (RGMII). Requires an Ethernet PHY on the baseboard.
Table 12. Ethernet pins
Name
Type
Connector
Pins
Voltage
Description
ENET_RD0
Input
J1310
33
1.8 V
RGMII receive from PHY
ENET_RD1
Input
J1310
35
1.8 V
RGMII receive from PHY
ENET_RD2
Input
J1310
31
1.8 V
RGMII receive from PHY
ENET_RD3
Input
J1310
37
1.8 V
RGMII receive from PHY
ENET_RX_CTL
Input
J1310
29
1.8 V
RGMII receive from PHY
ENET_RXC
Input
J1310
27
1.8 V
RGMII receive from PHY
Coral.ai | Copyright 2019 Google LLC.
15
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
ENET_TD0
Output
J1310
19
1.8 V
RGMII transmit to PHY
ENET_TD1
Output
J1310
21
1.8 V
RGMII transmit to PHY
ENET_TD2
Output
J1310
17
1.8 V
RGMII transmit to PHY
ENET_TD3
Output
J1310
15
1.8 V
RGMII transmit to PHY
ENET_TX_CTL
Output
J1310
13
1.8 V
RGMII transmit to PHY
ENET_TXC
Output
J1310
23
1.8 V
RGMII transmit to PHY
ENET_MDC
Output
J1310
11
1.8 V
RGMII clock for PHY
ENET_MDIO
Output
J1310
9
1.8 V
RGMII MDIO data for PHY
ENET_nRST
(GPIO1_IO09)
Output
J1312
43
3.3 V
PHY reset
ENET_nINT
(GPIO1_IO11)
Input
J1312
39
3.3 V
PHY interrupt
ENET_WoL
(GPIO1_IO10)
Input
J1312
41
3.3 V
PHY Wake-on-Lan
CLKO_25M
(GPIO1_IO15)
Output
J1310
54
3.3 V
Optional 25 Mhz clock to PHY
5.5 PCIe
The SoC includes PCIE1 and PCIE2 lines that are routed to the baseboard connectors, but you should not need to connect
these and you should not remap these with your own device tree because both are used on the SoM for Wi-Fi (PCIE1) and
the Edge TPU (PCIE2).
5.6 USB
There are two USB controllers and corresponding PHYs on the SoM. Each USB instance contains USB 3.0 (USB 3.1 Gen 1)
core, which can operate in both USB 3.0 and 2.0 mode.
Table 13. USB channel 1 pins
Name
Type
Connector
Pins
Voltage
Description
USB1_DP/N
I/O
J1311
51/53
3.3 V
USB 2.0 (positive/negative)
USB1_TXP/N
Output
J1311
58/60
1.8 V
USB 3.0 transmit (positive/negative)
USB1_RXP/N
Input
J1311
64/66
1.8 V
USB 3.0 receive (positive/negative)
USB1_VBUS
Input
J1311
82/84
5 V
VBUS detect (same at both pins)
USB1_ID
Input
J1311
76
3.3 V
USB ID
Coral.ai | Copyright 2019 Google LLC.
16
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Table 14. USB channel 2 pins
Name
Type
Connector
Pins
Voltage
Description
USB2_DP/N
I/O
J1311
63/65
3.3 V
USB 2.0 (positive/negative)
USB2_TXP/N
Output
J1311
69/71
1.8 V
USB 3.0 transmit (positive/negative)
USB2_RXP/N
Input
J1311
70/72
1.8 V
USB 3.0 receive (positive/negative)
USB2_VBUS
Input
J1311
75/77
5 V
VBUS detect (same at both pins)
USB2_ID
Input
J1311
88
3.3 V
USB ID
5.7 Digital audio (SAI)
The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame
synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces.
Note: If booting the SoM in eFUSE mode (default behavior), all SAI pins are available during boot. However, when using
the other boot modes, pins SAI1_RX[7:0] and SAI1_TX[7:0] are used to enable boot configuration overrides by latching
them to the BOOT_CFG[15:0] bits in the SoC—that is, only until boot completes. The SoM uses internal pin strap (pull-up
and pull-down) resistors to select the different boot configuration, so you should be careful if you add any pull-up/down
resistors for these pins on your baseboard. For details, see the iMX 8M SoC documentation.
Table 15. SAI 1 signals
Name
Type
Connector
Pins
Voltage
Description
SAI1_MCLK
I/O
J1312
26
3.3 V
Audio master clock
SAI1_RXC
Input
J1312
17
3.3 V
Receive bit clock
SAI1_RXFS
Input
J1312
19
3.3 V
Receive frame sync
SAI1_RXD0
Input
J1312
33
3.3 V
Receive channel.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD1
Input
J1312
35
3.3 V
Receive channel.
Pull-up in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD2
Input
J1312
27
3.3 V
Receive channel.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD3
Input
J1312
31
3.3 V
Receive channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD4
Input
J1312
29
3.3 V
Receive channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
Coral.ai | Copyright 2019 Google LLC.
17
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
SAI1_RXD5
Input
J1312
21
3.3 V
Receive channel.
Pull-up in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD6
Input
J1312
25
3.3 V
Receive channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD7
Input
J1312
23
3.3 V
Receive channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXC
Output
J1312
40
3.3 V
Transmit bit clock.
SAI1_TXFS
Output
J1312
46
3.3 V
Transmit frame sync.
SAI1_TXD0
Output
J1312
44
3.3 V
Transmit channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXD1
Output
J1312
42
3.3 V
Transmit channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXD2
Output
J1312
30
3.3 V
Transmit channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXD3
Output
J1312
36
3.3 V
Transmit channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXD4
Output
J1312
38
3.3 V
Transmit channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXD5
Output
J1312
34
3.3 V
Transmit channel.
Pull-up in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXD6
Output
J1312
28
3.3 V
Transmit channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_TXD7
Output
J1312
32
3.3 V
Transmit channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
Coral.ai | Copyright 2019 Google LLC.
18
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Table 16. SAI 2 signals
Name
Type
Connector
Pins
Voltage
Description
SAI2_TXD
Output
J1312
14
3.3 V
Transmit channel
SAI2_RXD
Input
J1312
20
3.3 V
Receive channel
SAI2_TXC
Output
J1312
18
3.3 V
Transmit bit clock
SAI2_TXFS
Output
J1312
16
3.3 V
Transmit frame sync
SAI2_MCLK
I/O
J1312
12
3.3 V
Audio master clock
SAI2_RXFS
Input
J1312
24
3.3 V
Receive frame sync
SAI2_RXC
Input
J1312
23
3.3 V
Receive bit clock
Note: The SoC includes SAI3 lines, but most of these are used by the SoM for Wi-Fi, so you should not remap these with
your device tree. Only SAI3_RXC and SAI3_RXFS are provided by the SoM baseboard connectors and available for use
as GPIO.
The SoC also includes SAI5 lines that are all provided by the SoM connectors, but three of them are pin-strapped inside
the SoM (SAI5_RXD1, SAI5_RXD3, and SAI5_RXFS), and their level is latched by the U-Boot bootloader to determine the
SoM SKU (LPDDR4 memory size). We recommend that you do not use these three pins for any other purpose and do
not connect them. The remaining SAI5 pins (SAI5_MCLK, SAI5_RXC, SAI5_RXD0, and SAI5_RXD2) are available for use
as GPIO.
5.8 Sony/Philips audio (SPDIF)
Sony/Philips Digital Interface (SPDIF) is a standard audio file transfer format that supports Transmitter and Receiver
functionality. Refer to NXP iMX 8M documentation for additional details.
Table 17. SPDIF pin signals
Name
Type
Connector
Pins
Voltage
Description
SPDIF_EXT_CLK
Output
J1311
92
3.3 V
External clock signal
SPDIF_TX
Output
J1311
96
3.3 V
Transmit data channel
SPDIF_RX
Input
J1311
98
3.3 V
Receive data channel
Coral.ai | Copyright 2019 Google LLC.
19
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
5.9 Micro-SD card
An Ultra Secure Digital Host Controller (uSDHC) module provides the interface between the host and SD/SDIO/MMC cards,
with the following features:
● SD/SDIO standard, up to version 3.0
● MMC standard, up to version 5.0
● 3.3 V operation only
● 1- and 4-bit SD/SDIO/MMC modes
Table 18. SD/MMC pin signals
Name
Type
Connector
Pins
Voltage
Description
SD2_CLK
Output
J1310
48
3.3 V
Serial clock
SD2_CMD
Output
J1310
26
3.3 V
Command line
Pull-up in SoM: 10k Ohm
SD2_nCD
(SD2_CD_B)
Output
J1310
24
3.3 V
Card detect
SD2_DAT0
I/O
J1310
28
3.3 V
Data bit 0
Pull-up in SoM: 10k Ohm
SD2_DAT1
I/O
J1310
32
3.3 V
Data bit 1
SD2_DAT2
I/O
J1310
34
3.3 V
Data bit 2
SD2_DAT3
I/O
J1310
38
3.3 V
Data bit 3
SD2_nRST
(SD2_RESET_B)
Output
J1310
36
3.3 V
Card reset
SDIO_WAKE
(SD2_WP)
Output
J1310
30
3.3 V
Write protect or GPIO
5.10 JTAG debugging
5-pin JTAG debugging with a Secure JTAG Controller (SJC) for secure debugging.
Table 19. JTAG pin signals
Name
Type
Connector
Pins
Voltage
Description
JTAG_TMS
Output
J1312
59
3.3 V
Test mode select
JTAG_TDI
Input
J1312
61
3.3 V
Test data in
JTAG_TDO
Output
J1312
57
3.3 V
Test data out
JTAG_TCK
Output
J1312
53
3.3 V
Test clock
JTAG_nTRST
Input
J1312
55
3.3 V
Test reset
Coral.ai | Copyright 2019 Google LLC.
20
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
5.11 I2C
Two I2C bus interfaces are available.
Table 20. I2C pin signals
Name
Type
Connector
Pins
Voltage
Description
I2C2_SCL
Input
J1311
87
3.3 V
Serial clock
Pull-up in SoM: 4.7k Ohm
I2C2_SDA
Output
J1311
85
3.3 V
Serial data
Pull-up in SoM: 4.7k Ohm
I2C3_SCL
Input
J1311
83
3.3 V
Serial clock
Pull-up in SoM: 4.7k Ohm
I2C3_SDA
Output
J1311
81
3.3 V
Serial data
Pull-up in SoM: 4.7k Ohm
Note: The SoC also includes I2C1 and I2C4 lines, but these are used by the SoM for power management and wireless
controls, so you should not remap these with your own device tree.
5.12 UART
Two UART v2 modules are available with the following features:
● 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none).
● Programmable baud rates up to 4 Mbps.
● 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud.
Note: By default, the Mendel operating system configures UART1 for use with the the serial console.
The SoC also includes UART2 and UART4 lines, but these are used by the SoM for Bluetooth, so you should not remap
these with your own device tree.
Table 21. UART pin signals
Name
Type
Connector
Pins
Voltage
Description
UART1_TXD
Output
J1311
93
3.3 V
Transmit channel
UART1_RXD
Input
J1311
95
3.3 V
Receive channel
UART3_TXD
Output
J1311
91
3.3 V
Transmit chanel
UART3_RXD
Input
J1311
97
3.3 V
Receive channel
Coral.ai | Copyright 2019 Google LLC.
21
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
5.13 SPI
Two full-duplex eSPI interfaces are available, with data rates up to 52 Mbit/s and two chip select lines.
Table 22. SPI channel 1 pin signals
Name
Type
Connector
Pins
Voltage
Description
ECSPI1_MISO
Input
J1312
5
3.3 V
Master input
ECSPI1_MOSI
Output
J1312
7
3.3 V
Master output
ECSPI1_SCLK
Output
J1312
4
3.3 V
Serial clock
ECSPI1_SS0
Output
J1312
8
3.3 V
Chip select
ECSPI1_SS1
Output
J1310
6
3.3 V
Chip select
Table 23. SPI channel 2 pin signals
Name
Type
Connector
Pins
Voltage
Description
ECSPI2_MISO
Input
J1312
3
3.3 V
Master input
ECSPI2_MOSI
Output
J1312
6
3.3 V
Master output
ECSPI2_SCLK
Output
J1312
2
3.3 V
Serial clock
ECSPI2_SS0
Output
J1312
1
3.3 V
Chip select
ECSPI2_SS1
Output
J1310
4
3.3 V
Chip select
5.14 GPIO
The following pins are configured for general purpose input/output, by default. Additionally, you can reconfigure other pins
(SAI, SPDIF, SDIO, I2C, UART, SPI, and PWM) to behave as GPIO, using a device tree overlay.
Table 24. GPIO pin signals
Name
Type
Connector
Pins
Voltage
Description
GPIO6
I/O
J1312
49
3.3 V
GPIO
GPIO7
I/O
J1312
45
3.3 V
GPIO
GPIO8
I/O
J1312
47
3.3 V
GPIO
GPIO12
I/O
J1312
51
3.3 V
GPIO
NAND_CLE
I/O
J1310
10
3.3 V
GPIO
NAND_DATA02
I/O
J1310
12
3.3 V
GPIO
NAND_ALE
I/O
J1310
16
3.3 V
GPIO
NAND_DATA07
I/O
J1310
18
3.3 V
GPIO
Coral.ai | Copyright 2019 Google LLC.
22
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
NAND_DATA06
I/O
J1310
20
3.3 V
GPIO
NAND_DATA03
I/O
J1310
22
3.3 V
GPIO
SAI3_RXC
I/O
J1312
13
3.3 V
GPIO
SAI3_RXFS
I/O
J1312
15
3.3 V
GPIO
SAI5_MCLK
I/O
J1312
50
3.3 V
GPIO
SAI5_RXC
I/O
J1312
56
3.3 V
GPIO
SAI5_RXD0
I/O
J1312
58
3.3 V
GPIO
SAI5_RXD2
I/O
J1312
54
3.3 V
GPIO
SAI5_RXD1
I/O
J1312
48
3.3 V
SAI5_RXD3
I/O
J1312
52
3.3 V
SAI5_RXFS
I/O
J1312
60
3.3 V
GPIO
Do not pin-strap.
Pin-strapped in SoM for latch from bootloader. We
recommend you do not connect.
5.15 PWM
There are four PWM output pins available with 16-bit resolution and 4x16 data FIFO.
Table 25. PWM pin signals
Name
Type
Connector
Pins
Voltage
Description
PWM1 (GPIO1_IO01)
Output
J1312
88
3.3 V
PWM or GPIO
PWM2 (GPIO1_IO013)
Output
J1312
90
3.3 V
PWM or GPIO
PWM3 (GPIO1_IO014)
Output
J1312
92
3.3 V
PWM or GPIO
PWM4 (SAI3_MCLK)
Output
J1312
11
3.3 V
PWM or GPIO
6 Wi-Fi and Bluetooth
The SoM includes the Murata LBEE5U91CQ module, which provides Wi-Fi (IEEE 802.11 a/b/g/n/ac WLAN, 2.4/5 GHz) and
Bluetooth 4.2 (with Bluetooth Low Energy support), using wireless antennas integrated into the board.
Coral.ai | Copyright 2019 Google LLC.
23
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
7 Baseboard developer guide
This section provides details to help you integrate the Coral SoM into your own baseboard (carrier board) hardware.
7.1 Reference design
If you'd like to see a reference baseboard design that uses the System-on-Module, download the following schematic and
layout files for the Coral Dev Board.
Table 26. Dev Board schematics, layout, and 3D files
File
Description
Coral-Dev-Board-baseboard-schematic.pdf
Baseboard schematic in PDF
Coral-Dev-Board-baseboard-schematic-Altium.zip
Baseboard schematic files in Altium format
Coral-Dev-Board-baseboard-layout-Allegro.brd
Baseboard CAD layout in BRD format
Coral-Dev-Board.STEP
Dev Board (baseboard and SoM) 3D CAD file in STEP format
Coral-SoM.STEP
SoM-only 3D CAD file in STEP format
7.2 Baseboard connectors
The SoM connects to the host baseboard with three 100-pin connectors.
Table 27. SoM and baseboard connectors
SoM
Baseboard
3x 100-position plug
Hirose Electric DF40C-100DP-0.4V(51)
3x 100-position receptacle
Hirose Electric DF40HC(3.0)-100DS-0.4V(51)
The location of each connector plug on the SoM is illustrated in figure 3, and the corresponding position for each
receptacle on your baseboard is illustrated in figure 5.
7.3 Connectors, keepouts, and component max heights
Figure 5 illustrates the area of your baseboard where the SoM connects. The measurements are relative to the standoff in
the bottom-left corner, indicating the position for the three board-to-board (B2B) connectors (Hirose DF40C-100DP-0.4V),
two standoffs, and the following component regions:
A. Antenna keepout: Place no components and no copper in this region. This area of your baseboard is directly below
the SoM's Wi-Fi and Bluetooth antennas, so it must be kept clear of any metals to ensure strong radio signals.
B. Max height of baseboard components in this region is 2.8mm.
C. Max height of baseboard components in this region is 1.5mm.
Additionally, figure 5 indicates the location of pin 1 on your baseboard connectors. To see all the pin assignments, refer to
the pinout schematic.
Coral.ai | Copyright 2019 Google LLC.
24
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Figure 5. Top view of baseboard connectors and component restrictions (measured in millimeters)
7.4 Trace impedance recommendations
The following table lists the recommended impedance for high-speed signals on the baseboard.
Table 28. Trace impedance recommendation
Signal group
Impedance
PCB manufacture tolerance (±)
All single-ended signal, unless specified
50 Ohm single-ended
10%
PCIe TX/RX data pair
85 Ohm differential
10%
USB differential signals
90 Ohm differential
10%
Differential signals: including Ethernet, PCIe clocks, 100 Ohm differential
HDMI, MIPI (CSI and DSI)
10%
Coral.ai | Copyright 2019 Google LLC.
25
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
7.5 MIPI trace length compensation
MIPI signals for the CSI/DSI interfaces are high-speed signals that require the total etched trace lengths for each line within
a group (the paired clock lanes and four data lanes) be equal to each other. Due to space constraints on the SoM, the MIPI
signal traces lengths currently are not equal (as indicated in the following tables). You must incorporate the length
difference on your baseboard traces such that the trace lengths for each MIPI group match each other.
Table 29. CSI channel 1 signal trace length on SoM
Name
Etch length (mils)
Manhattan length (mils)
MIPI_CSI1_CLKN
306.1
287.89
MIPI_CSI1_CLKP
309.4
297.73
MIPI_CSI1_D0N
310.97
309.53
MIPI_CSI1_D0P
315.24
319.38
MIPI_CSI1_D1N
242.48
209.15
MIPI_CSI1_D1P
241.23
250.5
MIPI_CSI1_D2N
354.22
356.78
MIPI_CSI1_D2P
351.84
392.21
MIPI_CSI1_D3N
246.25
230.81
MIPI_CSI1_D3P
250.2
272.16
Table 30. CSI channel 2 signal trace length on SoM
Name
Etch length (mils)
Manhattan length (mils)
MIPI_CSI2_CLKN
299.51
282.39
MIPI_CSI2_CLKP
301.92
323.73
MIPI_CSI2_D0N
258.48
252.46
MIPI_CSI2_D0P
258.58
293.81
MIPI_CSI2_D1N
289.71
260.74
MIPI_CSI2_D1P
292.95
302.08
MIPI_CSI2_D2N
293.48
266.24
MIPI_CSI2_D2P
298.18
280.42
MIPI_CSI2_D3N
265.86
274.12
MIPI_CSI2_D3P
268.14
315.46
Coral.ai | Copyright 2019 Google LLC.
26
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
Table 31. DSI signal trace length on SoM
Name
Etch length (mils)
Manhattan length (mils)
MIPI_DSI_CLKN
296.45
339.08
MIPI_DSI_CLKP
297.41
380.43
MIPI_DSI_D0N
212.5
219
MIPI_DSI_D0P
211.9
260.34
MIPI_DSI_D1N
322.16
347.35
MIPI_DSI_D1P
326.95
388.69
MIPI_DSI_D2N
305.05
304.05
MIPI_DSI_D2P
309.08
345.38
MIPI_DSI_D3N
297.15
274.52
MIPI_DSI_D3P
298.16
315.86
7.6 Thermal management
Caution: You must provide a cooling solution to ensure the SoM surface maintains an operational temperature as
specified in section 9.
You can use the SoM's threaded standoffs (indicated in figure 3) to mount a passive or active cooling solution.
The Edge TPU includes an internal temperature sensor and the Coral PCIe driver provides a programmable interface to
help you make power management decisions. Using the PCIe device interface, you can read the Edge TPU temperature
and make your own thermal-management decisions such as when to activate a fan. Additionally, you can configure some
Edge TPU parameters to specify the temperature at which the Edge TPU should shut down, and specify trip-points for
dynamic frequency scaling (DFS). For more information, read the app note, Manage the PCIe module temperature.
7.7 Other recommendations
●
●
●
Make sure to route all the VSYS_5V and GND pins, and add decoupling (bypass) capacitors between VSYS_5V and
GND near the mating connector pins.
When placing a pull-up or pull-down resistor on some of the SoM signals, such as I/O pins (especially SAI1_TXD[7:0]
and SAI1_RXD[7:0]), review the signal description for each peripheral interface, because some of them already have
pull-up/down resistor in the SoM for initialization purposes.
Make sure to connect the HDMI reference clock (HDMI_REFCLK) to a 27 MHz source. Even if you do not use HDMI,
this is required during bootup for a DRM-related software check. For detail, see the reference design schematic.
Coral.ai | Copyright 2019 Google LLC.
27
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
8 Pinout schematic
Caution: The signal directions in figure 6 are not all accurate. Instead refer to the "type" of each pin in the tables from the
Peripheral interfaces section.
Figure 6. SoM connector schematic (see large image)
9 Environmental reliability
Table 32. SoM environmental and mechanical limits
Measurement
Limits
Shock
50 G / 20 ms
Vibration
20 G / 0-600 Hz
MTTF
>200,000 hours
Operating temperature
-20 to +85 °C 1
Storage temperature
-40 to +85 °C
Relative humidity
10% to 90% (operation)
5% to 95% (storage)
The operating temperature range is for the SoM's ambient environment, and assumes that the Edge TPU junction
temperature (Tj) does not exceed its absolute maximum rating, as specified in section 3.3. It's your responsibility to provide
thermal solution that maintains the maximum junction temperature for all SoM components.
1
Coral.ai | Copyright 2019 Google LLC.
28
System-on-Module datasheet v1.11
G650-04474-01 / G650-05369-01 / G650-05370-01
10 Document revisions
Table 33. History of changes to this document
Version
Changes
1.11 (January 2021)
Changed the operating temperature to reflect the true SoM limits (previous limit of 0 to 50 °C
was incorrectly based on performance with the heatsink and fan on the Dev Board).
Added section 3.3 and section 7.6 to elaborate on the Edge TPU's power/thermal behaviors.
Added detail about 16 GB eMMC included with the 4 GB RAM model, and eMMC PNs.
Removed misleading "External memory" section about the SoC from table 1.
1.10 (October 2020)
Fixed MIPI_DSI1_D2_N pin position in table 10.
1.9 (August 2020)
Added detail about HDMI_REFCLK requirement.
Removed list of certifications (instead see website).
Updated document styles.
1.8 (July 2020)
Added part numbers for all SKU variants.
1.7 (June 2020)
Corrected J1311 list of grounds: changed pin 33 to 32.
1.6 (April 2020)
Added detail about SAI5 pins that are pin-strapped in the SoM.
1.5 (February 2020)
Clarified and enhanced documentation of SAI, power and reset pin signals.
Added information about PWRON_B pin.
1.4 (January 2020)
Fixed USB2_RXP/N pin position.
1.3 (December 2019)
Fixed HDMI_TX1 pin positions.
1.2 (August 2019)
Added PDF download of this datasheet and the Dev Board baseboard schematic.
1.1 (July 2019)
Removed wireless antenna connector details.
1.0 (June 2019)
Initial release.
Coral.ai | Copyright 2019 Google LLC.
29
工商网监
湘ICP备2023018690号
