GigaDevice Semiconductor Inc.
GD32F101xx
ARM® Cortex™-M3 32-bit MCU
Datasheet
GD32F101xx
Table of Contents
List of Figures ............................................................................................................................. 3
List of Tables ............................................................................................................................... 4
1
General description ......................................................................................................... 5
2
Device overview ............................................................................................................... 6
2.1
Device information .............................................................................................................................. 6
2.2
Block diagram ...................................................................................................................................... 9
2.3
Pinouts and pin assignment ............................................................................................................ 11
2.4
Memory map ...................................................................................................................................... 15
2.5
Clock tree ........................................................................................................................................... 16
2.6
Pin definitions .................................................................................................................................... 17
Functional description .................................................................................................. 25
3
®
3.1
ARM Cortex™-M3 core .................................................................................................................. 25
3.2
On-chip memory................................................................................................................................ 25
3.3
Clock, reset and supply management ........................................................................................... 26
3.4
Boot modes ........................................................................................................................................ 26
3.5
Power saving modes ........................................................................................................................ 27
3.6
Analog to digital converter (ADC) ................................................................................................... 27
3.7
DMA .................................................................................................................................................... 28
3.8
General-purpose inputs/outputs (GPIOs) ...................................................................................... 28
3.9
Timers and PWM generation........................................................................................................... 28
3.10
Real time clock (RTC) ...................................................................................................................... 30
3.11
Inter-integrated circuit (I2C) ............................................................................................................. 30
3.12
Serial peripheral interface (SPI)...................................................................................................... 31
3.13
Universal synchronous asynchronous receiver transmitter (USART) ....................................... 31
3.14
External memory controller (EXMC) .............................................................................................. 31
3.15
Debug mode ...................................................................................................................................... 32
3.16
Package and operation temperature.............................................................................................. 32
Electrical characteristics .............................................................................................. 33
4
4.1
Absolute maximum ratings .............................................................................................................. 33
4.2
Recommended DC characteristics ................................................................................................. 33
4.3
Power consumption .......................................................................................................................... 34
4.4
EMC characteristics .......................................................................................................................... 35
4.5
Power supply supervisor characteristics ....................................................................................... 35
4.6
Electrical sensitivity........................................................................................................................... 36
4.7
External clock characteristics .......................................................................................................... 36
4.8
Internal clock characteristics ........................................................................................................... 37
4.9
PLL characteristics ........................................................................................................................... 38
4.10
Memory characteristics .................................................................................................................... 38
1 / 47
GD32F101xx
4.11
GPIO characteristics......................................................................................................................... 38
4.12
ADC characteristics .......................................................................................................................... 39
4.13
I2C characteristics ............................................................................................................................ 39
4.14
SPI characteristics ............................................................................................................................ 40
Package information ..................................................................................................... 41
5
5.1
QFN package outline dimensions .................................................................................................. 41
5.2
LQFP package outline dimensions ................................................................................................ 42
6
Ordering Information ..................................................................................................... 44
7
Revision History............................................................................................................. 46
2 / 47
GD32F101xx
List of Figures
Figure 1. GD32F101x4/6/8/B block diagram ........................................................................................................... 9
Figure 2. GD32F101xC/D/E/F/G/I/K block diagram.............................................................................................. 10
Figure 3. GD32F101Zx LQFP144 pinouts ............................................................................................................. 11
Figure 4. GD32F101Vx LQFP100 pinouts ............................................................................................................. 12
Figure 5. GD32F101Rx LQFP64 pinouts ............................................................................................................... 13
Figure 6. GD32F101Cx LQFP48 pinouts ............................................................................................................... 14
Figure 7. GD32F101Tx QFN36 pinouts ................................................................................................................. 14
Figure 8. GD32F101xx memory map ..................................................................................................................... 15
Figure 9. GD32F101xx clock tree............................................................................................................................ 16
Figure 10. QFN package outline.............................................................................................................................. 41
Figure 11. LQFP package outline ............................................................................................................................ 42
3 / 47
GD32F101xx
List of Tables
Table 1. GD32F101xx devices features and peripheral list ................................................................................... 6
Table 2. GD32F101xx pin definitions ...................................................................................................................... 17
Table 3. Absolute maximum ratings ........................................................................................................................ 33
Table 4. DC operating conditions ............................................................................................................................ 33
Table 5. Power consumption characteristics ......................................................................................................... 34
Table 6. EMS characteristics ................................................................................................................................... 35
Table 7. EMI characteristics ..................................................................................................................................... 35
Table 8 Power supply supervisor characteristics .................................................................................................. 35
Table 9. ESD characteristics .................................................................................................................................... 36
Table 10. Static latch-up characteristics ................................................................................................................ 36
Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics ...................... 36
Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics ....................... 37
Table 13. High speed internal clock (HSI) characteristics ................................................................................... 37
Table 14. Low speed internal clock (LSI) characteristics ..................................................................................... 37
Table 15. PLL characteristics ................................................................................................................................... 38
Table 16. Flash memory characteristics ................................................................................................................. 38
Table 17. I/O port characteristics ............................................................................................................................. 38
Table 18. ADC characteristics .................................................................................................................................. 39
Table 19. I2C characteristics .................................................................................................................................... 39
Table 20. SPI characteristics .................................................................................................................................... 40
Table 21. QFN package dimensions ....................................................................................................................... 41
Table 22. LQFP package dimensions ..................................................................................................................... 43
Table 23. Part ordering code for GD32F101xx devices ....................................................................................... 44
Table 24. Revision history......................................................................................................................................... 46
4 / 47
GD32F101xx
1
General description
®
The GD32F101xx device is a 32-bit general-purpose microcontroller based on the ARM
Cortex™-M3 RISC core with best ratio in terms of processing power, reduced power
consumption and peripheral set. The Cortex™-M3 is a next generation processor core which
is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and
advanced debug support.
The GD32F101xx device incorporates the ARM
®
Cortex™-M3 32-bit processor core
operating at 56 MHz frequency with Flash accesses zero wait states to obtain maximum
efficiency. It provides up to 3 MB on-chip Flash memory and up to 80 KB SRAM memory. An
extensive range of enhanced I/Os and peripherals connected to two APB buses. The
devices offer up to two 12-bit ADCs, up to ten general-purpose 16-bit timers and two basic
timers, as well as standard and advanced communication interfaces: up to three USARTs,
2
two UARTs, three SPIs and two I Cs,
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32F101xx devices suitable for a wide range of applications,
especially in areas such as industrial control, user interface, power monitor and alarm
systems, consumer and handheld equipment, touch panel, PC peripherals and so on.
5 / 47
GD32F101xx
2
Device overview
2.1
Device information
Table 1. GD32F101xx devices features and peripheral list
GD32F101xx
Part Number
T6
T8
TB
C4
C6
C8
CB
R4
R6
R8
RB
V8
VB
Flash (KB)
16
32
64
128
16
32
64
128
16
32
64
128
64
128
SRAM (KB)
4
6
10
16
4
6
10
16
4
6
10
16
10
16
GPTM
2
2
3
3
2
2
3
3
2
2
3
3
3
3
SysTick
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
USART
2
2
2
2
2
2
3
3
2
2
3
3
3
3
I2C
1
1
1
1
1
1
2
2
1
1
2
2
2
2
SPI
1
1
1
1
1
1
2
2
1
1
2
2
2
2
GPIO
26
26
26
26
37
37
37
37
51
51
51
51
80
80
EXMC
0
0
0
0
0
0
0
0
0
0
0
0
1
1
EXTI
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Units
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Channels
10
10
10
10
10
10
10
10
16
16
16
16
16
16
ADC
Connectivity
Timers
T4
Package
QFN36
LQFP48
LQFP64
LQFP100
6 / 47
GD32F101xx
Table 1. GD32F101xx devices features and peripheral list (continued)
GD32F101xx
Part Number
RC
RD
RE
RF
RG
RI
RK
VC
VD
VE
VF
VG
VI
VK
256 384 512
768 1024 2048 3072 256
384 512 768 1024 2048 3072
SRAM (KB)
32
48
48
80
80
80
80
32
48
48
80
80
80
80
GPTM
4
4
4
10
10
10
10
4
4
4
10
10
10
10
SysTick
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Basic Timer
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Watchdog
2
2
2
2
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
USART
3
3
3
3
3
3
3
3
3
3
3
3
3
3
UART
2
2
2
2
2
2
2
2
2
2
2
2
2
2
I2C
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SPI
3
3
3
3
3
3
3
3
3
3
3
3
3
3
GPIO
51
51
51
51
51
51
51
80
80
80
80
80
80
80
EXMC
0
0
0
0
0
0
0
1
1
1
1
1
1
1
EXTI
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Units
1
1
1
2
2
2
2
1
1
1
2
2
2
2
Channels
16
16
16
16
16
16
16
16
16
16
16
16
16
16
ADC
Connectivity
Timers
Flash (KB)
Package
LQFP64
LQFP100
7 / 47
GD32F101xx
Table 1. GD32F101xx devices features and peripheral list (continued)
GD32F101xx
Part Number
ZD
ZE
ZF
ZG
ZI
ZK
Flash (KB)
256
384
512
768
1024
2048
3072
SRAM (KB)
32
48
48
80
80
80
80
GPTM
4
4
4
10
10
10
10
SysTick
1
1
1
1
1
1
1
Basic Timer
2
2
2
2
2
2
2
Watchdog
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
USART
3
3
3
3
3
3
3
UART
2
2
2
2
2
2
2
I2C
2
2
2
2
2
2
2
SPI
3
3
3
3
3
3
3
GPIO
112
112
112
112
112
112
112
EXMC
1
1
1
1
1
1
1
EXTI
16
16
16
16
16
16
16
Units
1
1
1
2
2
2
2
Channels
16
16
16
16
16
16
16
ADC
Connectivity
Timers
ZC
Package
LQFP144
8 / 47
GD32F101xx
2.2
Block diagram
Figure 1. GD32F101x4/6/8/B block diagram
TPIU
SW/JTAG
NVIC
ICode DCode System
ARM Cortex-M3
Processor
Fmax: 56MHz
Flash
Memory
Controller
Ibus
Flash
Memory
PLL
Fmax: 56MHz
Dbus
FMC Control
Registers
Master
Master
Slave
EXMC
Slave
Slave
LDO
1.1V
RST/CLK Control
Registers
AHB Peripherals
Slave
AHB Matrix
GP DMA
7chs
POR/PDR
SRAM
Controller
AHB to APB
Bridge 2
HSI
8MHz
SRAM
HSE
4-16MHz
AHB to APB
Bridge 1
LVD
Interrput request
Powered By VDDA
USART1
Slave
Slave
WDG
SPI1
TM2
12-bit
SAR ADC
Powered By V DDA
ADC1
TM3
GPIOC
GPIOD
APB1: Fmax = 56MHz
GPIOB
APB2: Fmax = 56MHz
GPIOA
TM4
SPI2
USART2
USART3
GPIOE
I2C1
EXTI
I2C2
9 / 47
GD32F101xx
Figure 2. GD32F101xC/D/E/F/G/I/K block diagram
POR/PDR
TPIU
SW/JTAG
GP DMA 1
7chs
GP DMA 2
5chs
Ibus
Dbus
Flash
Memory
Flash Memory
Controller 2
Flash
Memory
FMC Control
Registers
Master
AHB Matrix
NVIC
ICode DCode System
ARM Cortex-M3
Processor
Fmax: 56MHz
PLL
Flash Memory
Controller 1
Fmax: 144MHz
LDO
1.1V
RST/CLK Control
Registers
HSI
8MHz
AHB Peripherals
Slave
EXMC
HSE
4-16MHz
Slave
Slave
SRAM
Controller
Slave
AHB to APB
Bridge 2
SRAM
Master
Master
LVD
AHB to APB
Bridge 1
Powered By V DDA
Interrput request
WDG
USART1
Slave
SPI1
12-bit
SAR ADC
Slave
GP TM2
ADC1
GP TM3
ADC2
GP TM4
GP TM5
GPIOB
GPIOC
APB1: Fmax = 56MHz
GPIOA
APB2: Fmax = 56MHz
Powered By V DDA
GPIOD
GP TM12
GP TM13
GP TM14
SPI2
SPI3
GPIOE
USART2
GPIOF
USART3
GPIOG
UART4
GP TM9
UART5
GP TM10
I2C1
GP TM11
BSC TM6
I2C2
EXTI
BSC TM7
: Blocks are available in GD32F101xF/G/I/K devices
10 / 47
GD32F101xx
2.3
Pinouts and pin assignment
Figure 3. GD32F101Zx LQFP144 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109
108
PE3
PE4
2
107
VSS_2
3
NC
PE5
PE6
4
106
105
5
104
VBAT
6
103
PA12
PA11
PC13-TAMPER-RTC
PC14-OSC32_IN
7
102
PA10
8
PA9
PC15-OSC32_OUT
9
101
100
10
99
PC9
PF1
11
98
PC8
PF2
12
97
PC7
PF3
PF4
PF5
13
96
PC6
14
95
VDD_9
15
94
VSS_9
93
PG8
VDD_5
16
17
PF6
18
PF7
19
PF8
PF9
20
21
PF10
22
PF0
VSS_5
GigaDevice GD32F101Zx
LQFP144
VDD_2
PA13
PA8
92
PG7
91
90
PG6
89
PG4
PG5
88
PG3
87
PG2
OSC_IN
23
86
PD15
OSC_OUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
28
82
PD13
PD12
PC3
VSSA
29
80
79
PD11
VREFVREF+
31
32
78
PD9
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
PC2
81
30
PD10
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE8
PE9
PE7
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
11 / 47
GD32F101xx
Figure 4. GD32F101Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
NC
PE5
PE6
4
73
72
5
71
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32_IN
7
70
69
PC15-OSC32_OUT
VSS_5
PA13
PA12
PA11
PA10
PA9
9
68
67
10
66
PC9
8
PA8
65
PC8
64
PC7
63
PC6
14
62
PD15
15
61
PD14
16
17
60
PD13
59
PD12
18
58
57
PD11
56
PD9
VDD_5
11
OSC_IN
12
OSC_OUT
NRST
PC0
13
PC1
PC2
PC3
VDD_2
GigaDevice GD32F101Vx
LQFP100
VSSA
19
VREFVREF+
20
21
55
PD8
VDDA
22
54
PB15
PD10
PA0-WKUP
23
53
PA1
24
52
PB14
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
12 / 47
GD32F101xx
Figure 5. GD32F101Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
VDD_2
2
47
VSS_2
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
PD0-OSC_IN
4
45
PA12
5
44
PA11
PD1 OSC_OUT
6
43
PA10
NRST
PC0
7
8
42
PA9
PC1
9
PC2
PC3
VSSA
10
VBAT
1
PC13-TAMPER-RTC
GigaDevice GD32F101Rx
LQFP64
41
PA8
40
39
PC9
PC8
11
12
38
PC7
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PA1
15
34
PB14
PB13
PA2
16
33
PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PB11
PB10
PB2
PB1
PC5
PB0
PC4
PA7
PA6
PA5
PA4
VDD_4
VSS_4
PA3
13 / 47
GD32F101xx
Figure 6. GD32F101Cx LQFP48 pinouts
PA14
PB3
PA15
PB4
PB5
PB6
PB7
PB8
BOOT0
PB9
VSS_3
VDD_3
48 47 46 45 44 43 42 41 40 39 38 37
VBAT
1
36
VDD_2
PC13-TAMPER-RTC
2
35
VSS_2
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
PD0-OSC_IN
4
33
PA12
5
GigaDevice GD32F101Cx
LQFP48
6
32
PA11
31
PA10
30
PA9
29
PA8
PB15
PD1-OSC_OUT
NRST
VSSA
7
8
VDDA
9
PA0-WKUP
10
28
27
PA1
PA2
11
12
26
PB14
PB13
25
PB12
13 14 15 16 17 18 19 20 21 22 23 24
PB11
PA15
PA14
VDD_1
PB10
VSS_1
PB2
PB3
PB4
PB0
PB1
PA7
PA6
PA5
PA4
PA3
Figure 7. GD32F101Tx QFN36 pinouts
OSC_IN/PD0
OSC_OUT/PD1
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
PB5
PB6
PB7
BOOT0
VSS_3
VDD_3
36 35 34 33 32 31 30 29 28
1
27
2
26
3
4
VDD_2
VSS_2
25
PA13
24
GigaDevice
GD32F101Tx
5
23
QFN36
6
22
7
21
PA12
PA9
8
PA8
20
19
9
10 11 12 13 14 15 16 17 18
PA11
PA10
VDD_1
VSS_1
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
14 / 47
GD32F101xx
2.4
Memory map
Figure 8. GD32F101xx memory map
0x 5FFF FFFF
0x 4002 3400
0x 4002 3000
0x 4002 2400
0x 4002 2000
0x 4002 1400
0x 4002 0400
DMA2
0x 4002 0000
DMA1
reserved
0x 4001 5400
0x 4001 5000
0x 4001 4C00
0x 4001 3C00
0x 4001 3800
0x 4001 3400
0x 4001 3000
0x 4001 2800
0x 4001 2400
0x 4001 2000
0x 4001 1C00
Cortex-M3 Internal
Peripherals
0x1FFF FFFF
0x1FFF F80F
reserved
Option
Bytes
0x 4001 1800
0x 4001 1400
0xE010 0000
0x 4001 1000
0xE000 0000
6
0x1FFF F800
0x 4001 0C00
0x 4001 0800
reserved
0x 4001 0400
0x 4001 0000
0xC000 0000
System
memory
0x1FFF F000
0x 4000 7800
0x 4000 7400
5
EXMC register
0x 4000 7000
0xA000 1000
0x 4000 6C00
0xA000 0000
0x 4000 5C00
0x 4000 5800
reserved
4
reserved
0x8000 0000
EXMC bank
3
reserved
0x 4000 5400
0x 4000 5000
0x 4000 4C00
0x 4000 4800
0x 4000 4400
0x 4000 4000
0x 4000 3C00
0x6000 0000
2
0x 4000 3800
reserved
0x 4000 3400
0x 4000 3000
0x 4000 2C00
0x4000 0000
0x0810 0000
0x0808 0000
0x0800 0000
Peripherals
Flash memory
bank 2 (512KB)
1
Flash memory
bank 1 (512KB)
0x2001 4000
0x2000 0000
SRAM (80KB)
0
reserved
reserved
0x0010 0000
Aliased to Flash or
system memory
according to BOOT
0x0000 0000 pins configuration
0x0000 0000
reserved
Flash Interface
reserved
0x 4002 0800
0x 4001 5800
7
CRC
reserved
RCC
reserved
0x 4002 1000
0xFFFF FFFF
reserved
0x 4000 2800
0x 4000 2400
0x 4000 2000
0x 4000 1C00
0x 4000 1800
0x 4000 1400
0x 4000 1000
0x 4000 0C00
0x 4000 0800
0x 4000 0400
0x 4000 0000
TM11
TM10
TM9
reserved
USART1
reserved
SPI1
ADC2
ADC1
Port G
Port F
Port E
Port D
Port C
Port B
Port A
EXTI
AFIO
reserved
reserved
PWR
BKP
reserved
I2C2
I2C1
UART5
UART4
USART3
USART2
reserved
SPI3
SPI2
reserved
IWDG
WWDG
RTC
reserved
TM14
TM13
TM12
TM7
TM6
TM5
TM4
TM3
TM2
15 / 47
GD32F101xx
2.5
Clock tree
Figure 9. GD32F101xx clock tree
CK_FMCU
SCS[1:0]
FMCU enable
(by hardware)
(to FMCU)
CK_EXMC
CK_HSI
EXMC
enable
00
8 MHz
HSI RC
0
/2
PLLPREDV
1
PLL
× 2...9
PLLSEL
PLLEN
CK_PLL
10
CK_SYS
56 MHz max
AHB
÷Prescaler
(1,2...512)
(to EXMC)
CK_AHB
56 MHz max
HCLK
AHB enable
(to AHB bus,Cortex-M3,SRAM,DMA)
01
CK_CST
÷8
(to Cortex-M3 SysTick)
/2
4-16 MHz
HSE XTAL
1
Clock
Monitor
0
CK_HSE
/128
32.768 KHz
LSE OSC
FCLK
(free running clock)
TM2,3,4
× 1 or × 2
to TM2,3,4
11
01
CK_RTC
(to RTC)
APB1
÷Prescaler
(1,2,4,8,16)
RTCSRC[1:0]
CK_APB1
PCLK1
56 MHz max
Peripheral enable
10
40 KHz
LSI RC
CK_TMX
TMX enable
CK_IWDG
(to IWDG)
APB2
÷Prescaler
(1,2,4,8,16)
CK_APB2
PCLK2
56 MHz max
Peripheral enable
CK_SYS
CK_HSI
CK_OUT
ADC
÷Prescaler
(2,4,6,8)
to APB1
peripherals
to APB2
peripherals
CK_ADCX to ADC1,ADC2
14 MHz max
CK_HSE
CK_PLL/2
Legend:
HSE = High speed external clock
HSI = High speed internal clock
LSE = Low speed external clock
LSI = Low speed internal clock
16 / 47
GD32F101xx
2.6
Pin definitions
LQFP100
LQFP64
LQFP48
QFN36
Pin Type
PE2
1
1
-
-
-
I/O
5VT
PE3
2
2
-
-
-
I/O
5VT
PE4
3
3
-
-
-
I/O
5VT
Functions description
I/O
Pin Name
(2)
LQFP144
(1)
Pins
Level
Table 2. GD32F101xx pin definitions
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
PE5
4
4
-
-
-
I/O
5VT Alternate:TRACED2, EXMC_A21
Remap: TM9_CH1
(4)
Default: PE6
PE6
5
5
-
-
-
I/O
5VT Alternate:TRACED3, EXMC_A22
Remap: TM9_CH2
VBAT
PC13-TAMPE
R-RTC
PC14-OSC32
_IN
PC15OSC32_OUT
PF0
PF1
6
6
1
1
-
P
7
7
2
2
-
I/O
8
8
3
3
-
I/O
9
9
4
4
-
I/O
10
I/O
11
I/O
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
Default: PC14
Alternate: OSC32_IN
Default: PC15
Alternate: OSC32_OUT
5VT
5VT
Default: PF0
(3)
Alternate: EXMC_A0
Default: PF1
Alternate: EXMC_A1
Default: PF2
I/O
5VT
PF3
13
I/O
5VT
PF4
14
I/O
5VT
PF5
15
I/O
5VT
VSS_5
16
10
-
-
-
P
Default: VSS_5
VDD_5
17
11
-
-
-
P
Default: VDD_5
Alternate: EXMC_A2
18
I/O
19
I/O
(3)
(3)
(3)
Alternate: EXMC_NIORD
Remap: TM10_CH1
PF7
(3)
(3)
Alternate: EXMC_A5
Default: PF6
(3)
(3)
Alternate: EXMC_A4
Default: PF5
(3)
(3)
Alternate: EXMC_A3
Default: PF4
(3)
(3)
12
Default: PF3
(3)
(3)
PF2
PF6
(4)
Default: PF7
(4)
(3)
(3)
Alternate: EXMC_NREG
17 / 47
(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F101xx
Default: PF8
PF8
20
I/O
(3)
(3)
Alternate: EXMC_NIOWR
Remap: TM13_CH1
Default: PF9
PF9
21
I/O
(4)
(3)
(3)
Alternate: EXMC_CD
Remap: TM14_CH1
(4)
(3)
I/O
Default: PF10
PF10
22
OSC_IN
23
12
5
5
2
I
OSC_OUT
24
13
6
6
3
O
NRST
25
14
7
7
4
I/O
PC0
26
15
8
-
-
I/O
PC1
27
16
9
-
-
I/O
PC2
28
17
10
-
-
I/O
PC3
29
18
11
-
-
I/O
VSSA
30
19
12
8
5
P
Default: VSSA
VREF-
31
20
-
-
-
P
Default: VREF-
VREF+
32
21
-
-
-
P
Default: VREF+
VDDA
33
22
13
9
6
P
Default: VDDA
PA0-WKUP
34
23
14
10
7
I/O
(3)
Alternate: EXMC_INTR
Default: OSC_IN
Remap: PD0
(4)
Default: OSC_OUT
Remap: PD1
(4)
Default: NRST
Default: PC0
Alternate: ADC_IN10
Default: PC1
Alternate: ADC_IN11
Default: PC2
Alternate: ADC_IN12
Default: PC3
Alternate: ADC_IN13
Default: PA0
Alternate: WKUP, USART2_CTS, ADC_IN0, TM2_CH1_ETR,
TM5_CH1
PA1
35
24
15
11
8
I/O
(3)
Default: PA1
Alternate: USART2_RTS, ADC_IN1, TM2_CH2, TM5_CH2
(3)
Default: PA2
PA2
36
25
16
12
9
I/O
Alternate: USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3
TM9_CH1
(3)
,
(3)
,
(4)
Default: PA3
PA3
37
26
17
13
10
I/O
Alternate: USART2_RX, ADC_IN3, TM2_CH4, TM5_CH4
TM9_CH2
(4)
VSS_4
38
27
18
-
-
P
Default: VSS_4
VDD_4
39
28
19
-
-
P
Default: VDD_4
PA4
40
29
20
14
11
I/O
PA5
41
30
21
15
12
I/O
Default: PA4
Alternate: SPI1_NSS, USART2_CK, ADC_IN4
Default: PA5
Alternate: SPI1_SCK, ADC_IN5
18 / 47
LQFP64
LQFP48
QFN36
Pin Type
42
31
22
16
13
I/O
PA7
43
32
23
17
14
I/O
PC4
44
33
24
-
-
I/O
Functions description
(2)
LQFP100
PA6
Pin Name
I/O
LQFP144
(1)
Pins
Level
GD32F101xx
Default: PA6
Alternate: SPI1_MISO, ADC_IN6, TM3_CH1, TM13_CH1
(4)
Default: PA7
Alternate: SPI1_MOSI, ADC_IN7, TM3_CH2, TM14_CH1
(4)
Default: PC4
Alternate: ADC_IN14
Default: PC5
PC5
45
34
25
-
-
I/O
PB0
46
35
26
18
15
I/O
PB1
47
36
27
19
16
I/O
PB2
48
37
28
20
17
I/O
5VT Default: PB2/BOOT1
PF11
49
I/O
5VT
PF12
50
I/O
5VT
VSS_6
51
P
Default: VSS_6
VDD_6
52
P
Default: VDD_6
PF13
53
I/O
5VT
PF14
54
I/O
5VT
PF15
55
I/O
5VT
PG0
56
I/O
5VT
PG1
57
I/O
5VT
PE7
58
38
-
-
-
I/O
5VT
PE8
59
39
-
-
-
I/O
5VT
PE9
60
40
-
-
-
I/O
5VT
VSS_7
61
P
Default: VSS_7
VDD_7
62
P
Default: VDD_7
PE10
63
41
-
-
-
I/O
5VT
PE11
64
42
-
-
-
I/O
5VT
PE12
65
43
-
-
-
I/O
5VT
Alternate: ADC_IN15
Default: PB0
Alternate: ADC_IN8, TM3_CH3
Default: PB1
Alternate: ADC_IN9, TM3_CH4
(3)
Default: PF11
Alternate: EXMC_NIOS16
(3)
(3)
Default: PF12
Alternate: EXMC_A6
(3)
(3)
Default: PF13
Alternate: EXMC_A7
(3)
(3)
Default: PF14
Alternate: EXMC_A8
(3)
(3)
Default: PF15
Alternate: EXMC_A9
Default: PG0
(3)
(3)
Alternate: EXMC_A10
Default: PG1
(3)
(3)
Alternate: EXMC_A11
(3)
Default: PE7
Alternate: EXMC_D4
Default: PE8
Alternate: EXMC_D5
Default: PE9
Alternate: EXMC_D6
Default: PE10
Alternate: EXMC_D7
Default: PE11
Alternate: EXMC_D8
Default: PE12
Alternate: EXMC_D9
19 / 47
LQFP100
LQFP64
LQFP48
QFN36
Pin Type
PE13
66
44
-
-
-
I/O
5VT
PE14
67
45
-
-
-
I/O
5VT
PE15
68
46
-
-
-
I/O
5VT
Functions description
I/O
Pin Name
(2)
LQFP144
(1)
Pins
Level
GD32F101xx
Default: PE13
Alternate: EXMC_D10
Default: PE14
Alternate: EXMC_D11
Default: PE15
Alternate: EXMC_D12
Default: PB10
PB10
69
47
29
21
-
I/O
5VT Alternate: I2C2_SCL, USART3_TX
Remap: TM2_CH3
Default: PB11
PB11
70
48
30
22
-
I/O
5VT Alternate: I2C2_SDA, USART3_RX
Remap: TM2_CH4
VSS_1
71
49
31
23
18
P
Default: VSS_1
VDD_1
72
50
32
24
19
P
Default: VDD_1
PB12
73
51
33
25
-
I/O
5VT
PB13
74
52
34
26
-
I/O
5VT
PB14
75
53
35
27
-
I/O
5VT
PB15
76
54
36
28
-
I/O
5VT
PD8
77
55
-
-
-
I/O
5VT Alternate: EXMC_D13
Default: PB12
Alternate: SPI2_NSS, I2C2_SMBAI, USART3_CK
Default: PB13
Alternate: SPI2_SCK, USART3_CTS
Default: PB14
Alternate: SPI2_MISO, USART3_RTS, TM12_CH1
(4)
Default: PB15
Alternate: SPI2_MOSI, TM12_CH2
(4)
Default: PD8
Remap: USART3_TX
Default: PD9
PD9
78
56
-
-
-
I/O
5VT Alternate: EXMC_D14
Remap: USART3_RX
Default: PD10
PD10
79
57
-
-
-
I/O
5VT Alternate: EXMC_D15
Remap: USART3_CK
Default: PD11
PD11
80
58
-
-
-
I/O
5VT Alternate: EXMC_A16
Remap: USART3_CTS
Default: PD12
PD12
81
59
-
-
-
I/O
5VT Alternate: EXMC_A17
Remap: TM4_CH1, USART3_RTS
Default: PD13
PD13
82
60
-
-
-
I/O
5VT Alternate: EXMC_A18
Remap: TM4_CH2
VSS_8
83
P
Default: VSS_8
VDD_8
84
P
Default: VDD_8
PD14
85
61
-
-
-
I/O
5VT Default: PD14
20 / 47
(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F101xx
Alternate: EXMC_D0
Remap: TM4_CH3
Default: PD15
PD15
86
62
-
-
-
I/O
5VT Alternate: EXMC_D1
Remap: TM4_CH4
PG2
87
I/O
5VT
PG3
88
I/O
5VT
PG4
89
I/O
5VT
PG5
90
I/O
5VT
PG6
91
I/O
5VT
PG7
92
I/O
PG8
93
I/O
5VT
Default: PG2
(3)
Alternate: EXMC_A12
Default: PG3
(3)
Alternate: EXMC_A13
Default: PG4
Alternate: EXMC_INT2
Default: PG7
Alternate: EXMC_INT3
5VT Default: PG8
P
Default: VSS_9
95
P
Default: VDD_9
PC6
96
-
I/O
5VT
PC7
97
64
38
-
-
I/O
5VT
PC8
98
65
39
-
-
I/O
5VT
PC9
99
66
40
-
-
I/O
5VT
PA8
100 67
41
29
20
I/O
5VT
PA9
101 68
42
30
21
I/O
5VT
PA10
102 69
43
31
22
I/O
5VT
PA11
103 70
44
32
23
I/O
5VT
PA12
104 71
45
33
24
I/O
5VT
PA13
105 72
46
34
25
NC
106 73
-
-
-
VSS_2
107 74
47
35
26
I/O
5VT
(3)
(3)
94
-
(3)
(3)
VSS_9
37
(3)
(3)
VDD_9
63
(3)
(3)
Alternate: EXMC_A15
Default: PG6
(3)
(3)
Alternate: EXMC_A14
Default: PG5
(3)
Default: PC6
Remap: TM3_CH1
Default: PC7
Remap: TM3_CH2
Default: PC8
Remap: TM3_CH3
Default: PC9
Remap: TM3_CH4
Default: PA8
Alternate: USART1_CK, MCO
Default: PA9
Alternate: USART1_TX
Default: PA10
Alternate: USART1_RX
Default: PA11
Alternate: USART1_CTS
Default: PA12
Alternate: USART1_RTS
Default: JTMS, SWDIO
Remap: PA13
-
P
Default: VSS_2
21 / 47
QFN36
Pin Type
48
36
27
P
PA14
109 76
49
37
28
I/O
(2)
LQFP48
108 75
Functions description
I/O
LQFP64
VDD_2
Pin Name
LQFP144
LQFP100
(1)
Pins
Level
GD32F101xx
Default: VDD_2
5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
110 77
50
38
29
I/O
(3)
5VT Alternate: SPI3_NSS
Remap: TM2_CH1_ETR, PA15, SPI1_NSS
Default: PC10
PC10
111 78
51
-
-
I/O
(3)
5VT Alternate: UART4_TX
Remap: USART3_TX
Default: PC11
PC11
112 79
52
-
-
I/O
(3)
5VT Alternate: UART4_RX
Remap: USART3_RX
Default: PC12
PC12
113 80
53
-
-
I/O
(3)
5VT Alternate: UART5_TX
Remap: USART3_CK
Default: PD0
PD0
114 81
5
5
2
I/O
5VT
PD1
115 82
6
6
3
I/O
5VT
PD2
116 83
54
I/O
5VT
PD3
117 84
-
I/O
5VT Alternate: EXMC_CLK
Alternate: EXMC_D2
Default: PD1
Alternate: EXMC_D3
Default: PD2
(3)
Alternate: TM3_ETR, UART5_RX
Default: PD3
-
-
Remap: USART2_CTS
Default: PD4
PD4
118 85
-
-
-
I/O
5VT Alternate: EXMC_NOE
Remap: USART2_RTS
Default: PD5
PD5
119 86
-
-
-
I/O
5VT Alternate: EXMC_NWE
Remap: USART2_TX
VSS_10
120
Default: VSS_10
VDD_10
121
Default: VDD_10
Default: PD6
PD6
122 87
-
-
-
I/O
5VT Alternate: EXMC_NWAIT
Remap: USART2_RX
Default: PD7
PD7
123 88
-
-
-
I/O
5VT Alternate: EXMC_NE1/EXMC_NCE2
Remap: USART2_CK
Default: PG9
(3)
PG9
124
I/O
5VT
PG10
125
I/O
5VT
PG11
126
I/O
5VT Default: PG11
(3)
Alternate: EXMC_NE2 , EXMC_NCE3
Default: PG10
(3)
(3)
(3)
Alternate: EXMC_NCE4_1 , EXMC_NE3
(3)
(3)
22 / 47
(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F101xx
Alternate: EXMC_NCE4_2
Default: PG12
PG12
127
I/O
5VT
PG13
128
I/O
5VT
PG14
129
I/O
5VT
VSS_11
130
P
Default: VSS_10
VDD_11
131
P
Default: VDD_10
PG15
132
I/O
5VT Default: PG15
I/O
5VT Alternate:SPI3_SCK
Alternate: EXMC_NE4
Default: PG13
(3)
(3)
Alternate: EXMC_A24
Default: PG14
(3)
(3)
(3)
(3)
Alternate: EXMC_A25
(3)
Default: JTDO
PB3
133 89
55
39
30
(3)
Remap: PB3, TRACESWO, TM2_CH2, SPI1_SCK
Default: NJTRST
PB4
134 90
56
40
31
I/O
(3)
5VT Alternate: SPI3_MISO
Remap: TM3_CH1, PB4, SPI1_MISO
Default: PB5
PB5
135 91
57
41
32
Alternate: I2C1_SMBAI, SPI3_MOSI
I/O
(3)
Remap: TM3_CH2, SPI1_MOSI
Default: PB6
PB6
136 92
58
42
33
I/O
5VT Alternate: I2C1_SCL, TM4_CH1,
Remap: USART1_TX
Default: PB7
PB7
137 93
59
43
34
I/O
(3)
5VT Alternate: I2C1_SDA , TM4_CH2, EXMC_NADV
Remap: USART1_RX
BOOT0
138 94
60
44
35
I
PB8
139 95
61
45
-
I/O
Default: BOOT0
Default: PB8
5VT Alternate: TM4_CH3, TM10_CH1
(4)
Remap: I2C1_SCL
Default: PB9
PB9
140 96
62
46
-
I/O
5VT Alternate: TM4_CH4, TM11_CH1
(4)
Remap: I2C1_SDA
Default: PE0
PE0
141 97
-
-
-
I/O
5VT
PE1
142 98
-
-
-
I/O
5VT
VSS_3
143 99
63
47
36
P
Default: VSS_3
VDD_3
144 100 64
48
1
P
Default: VDD_3
Alternate: TM4_ETR, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
23 / 47
GD32F101xx
Notes:
1.
Type: I = input, O = output, P = power.
2.
I/O Level: 5VT = 5 V tolerant.
3.
Functions are available in GD32F101xC, GD32F101xD, GD32F101xE, GD32F101xF, GD32F101xG,
GD32F101xI, GD32F101xK devices.
4.
Functions are available in GD32F101xF, GD32F101xG, GD32F101xI, GD32F101xK devices.
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GD32F101xx
3
Functional description
3.1
ARM® Cortex™-M3 core
®
The Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
®
32-bit ARM Cortex™-M3 processor core
Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex™-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
On-chip memory
Up to 3072 Kbytes of Flash memory
Up to 80 Kbytes of SRAM
®
The ARM
™
Cortex -M3 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash and 80
Kbytes of inner SRAM at most is available for storing programs and data, both accessed
(R/W) at CPU clock speed with zero wait states. The Figure 8. GD32F101xx memory map
shows the memory map of the GD32F101xx series of devices, including code, SRAM,
peripheral, and other pre-defined regions.
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GD32F101xx
3.3
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 16 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types. Several prescalers allow the configuration of the AHB frequency, the high-speed
APB (APB2) and the low-speed APB (APB1) domains. The maximum allowed frequency of
the AHB and APB domain is 56 MHz. See Figure 9 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the
processor core and peripheral IP components. Power-on reset (POR) and power-down reset
(PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The
device remains in reset mode when VDD is below a specified threshold. The embedded low
voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and
generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the Flash memory by using USART1 in device mode. It also can be used to
transfer and update the Flash memory code, the data and the vector table sections. In
default condition, boot from bank 1 of Flash memory is selected. It also supports to boot from
bank 2 of Flash memory by setting a bit in option bytes.
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GD32F101xx
3.5
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.1V domain are off, and all of the high speed
crystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the Deep-sleep mode including the 16 external lines, the RTC alarm, the
LVD output. When exiting the Deep-sleep mode, the HSI is selected as the system
clock.
Standby mode
In Standby mode, the whole 1.1V domain is power off, the LDO is shut down, and all of
HSI, HSE and PLL are disabled. The contents of SRAM and registers (except Backup
Registers) are lost. There are four wakeup sources for the Standby mode, including the
external reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge on
WKUP pin.
3.6
Analog to digital converter (ADC)
12-bit SAR ADC engine
Up to 1 MSPS conversion rate
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
Up to two 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of up to
16 multiplexed external channels. An analog watchdog block can be used to detect the
channels, which are required to remain within a specific threshold window. A configurable
channel management block of analog inputs also can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced usages.
The ADCs can be triggered from the events generated by the general-purpose timers (TMx)
with internal connection. The temperature sensor has to generate a voltage that varies
linearly with temperature. The conversion range is between 2.6 V < VDDA < 3.6 V. The
temperature sensor is internally connected to the ADC_IN16 input channel which is used to
convert the sensor output voltage into a digital value.
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GD32F101xx
3.7
DMA
7 channel DMA 1 controller and 5 channel DMA 2 controller
Peripherals supported: Timers, ADC, SPIs, I Cs, USARTs
2
The flexible general-purpose DMA controllers provide a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby freeing
up bandwidth for other system functions. Four types of access method are supported:
peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.8
General-purpose inputs/outputs (GPIOs)
Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable
There are up to 112 general purpose I/O pins (GPIO) in GD32F101xx, named PA0 ~ PA15
and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and
configuration registers to satisfy the requirements of specific applications. The external
interrupts on the GPIO pins of the device have related control and configuration registers in
the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other
alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the
GPIO pins can be configured by software as output (push-pull or open-drain), as input (with
or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are
shared with digital or analog alternate functions. All GPIOs are high-current capable except
for analog inputs.
3.9
Timers and PWM generation
Up to ten 16-bit general-purpose timers (GPTM), and two 16-bit basic timer (TM6 & TM7)
Up to 4 independent channels of PWM, output compare or input capture for each GPTM
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Independent watchdog and window watchdog)
and external trigger input
The general-purpose timer (GPTM), known as TM2 ~ TM5, TM9 ~ TM11, TM12 ~ TM14 can
be used for a variety of purposes including general time, input signal pulse width
measurement or output waveform generation such as a single pulse generation or PWM
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GD32F101xx
output, up to 4 independent channels for input capture/output compare. The GPTM also
supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TM6 and TM7, are mainly used to generate analog trigger and
can also be used as simple 16-bit time base.
The GD32F101xx have two watchdog peripherals, Independent watchdog and window
watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit
prescaler, It is clocked from an independent 40 kHz internal RC and as it operates
independently of the main clock, it can operate in stop and standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It
features:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
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GD32F101xx
3.10
Real time clock (RTC)
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
The real time clock is an independent timer which provides a set of continuously running
counters which can be used with suitable software to provide a clock calendar function, and
provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit
programmable counter for long-term measurement using the compare register to generate
an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.
3.11
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 400 kHz
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400
kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the
situation where more than one master attempts to transmit data to the I2C bus at the same
time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking
for I2C data.
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GD32F101xx
3.12
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including
simplex synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
3.13
Universal synchronous asynchronous receiver transmitter
(USART)
Up to three USARTs and two UARTs with operating frequency up to 4.5 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface
The USART (USART1, USART2 and USART3) and UART (UART4 & UART5) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data
exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232
standard communication. The USART includes a programmable baud rate generator which
is capable of dividing the system clock to produce a dedicated clock for the USART
transmitter and receiver. The USART also supports DMA function for high speed data
communication except UART5.
3.14
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
CF card
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory except NAND Flash and CF card. The EXMC also can be
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
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GD32F101xx
3.15
Debug mode
Serial wire JTAG debug port (SWJ-DP)
®
The ARM SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.16
Package and operation temperature
LQFP144 (GD32F101Zx), LQFP100 (GD32F101Vx), LQFP64 (GD32F101Rx), LQFP48
(GD32F101Cx) and QFN36 (GD32F101Tx)
Operation temperature range: -40°C to +85°C (industrial level)
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GD32F101xx
4
Electrical characteristics
4.1
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without
permanently damaging the device. Note that the device is not guaranteed to operate properly
at the maximum ratings. Exposure to the absolute maximum rating conditions for extended
periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol
Min
Max
Unit
VDD
External voltage range
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V tolerant pin
VSS - 0.3
VDD + 4.0
V
Input voltage on other I/O
VSS - 0.3
4.0
V
VIN
IIO
Maximum current for GPIO pins
—
25
mA
TA
Operating temperature range
-40
+85
°C
Storage temperature range
-55
+150
°C
Maximum junction temperature
—
125
°C
TSTG
TJ
4.2
Parameter
Recommended DC characteristics
Table 4. DC operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
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GD32F101xx
4.3
Power consumption
The power measurements specified in the tables represent that code with data executing
from on-chip Flash with the following specifications.
Table 5. Power consumption characteristics
Symbol
Parameter
Conditions
VDD=VBAT=3.3V, HSE=8MHz, System
Min
Typ
Max
Unit
—
24.2
—
mA
—
18.7
—
mA
-—
17.8
—
mA
—
13.6
—
mA
—
12.9
—
mA
—
8.9
—
mA
—
0.41
1.4
mA
—
6.5
—
μA
—
4.6
—
μA
—
2.8
—
μA
clock=56 MHz, All peripherals enabled
VDD=VBAT=3.3V, HSE=8MHz, System clock
Supply current
=56 MHz, All peripherals disabled
(Run mode)
VDD=VBAT=3.3V, HSE=8MHz, System clock
=36MHz, All peripherals enabled
VDD=VBAT=3.3V, HSE=8MHz, System
Clock =36 MHz, All peripherals disabled
VDD=VBAT=3.3V, HSE=8MHz, CPU clock
IDD
Supply current
(Sleep mode)
off, All peripherals enabled
VDD=VBAT=3.3V, HSE=8MHz, CPU clock
off, All peripherals disabled
Supply current
(Deep-Sleep
mode)
Supply current
VDD=VBAT=3.3V, All clock off, LSI on, RTC
on, All GPIOs analog mode
VDD=VBAT=3.3V, LDO off, LSE off, LSI on,
(Standby mode) RTC on
Battery supply
IBAT
current
(Standby mode)
VDD not available, VBAT=3.3V, LDO off,
LSE on, LSI off, RTC on
VDD not available, VBAT=3.3 V, LDO off,
LSE off, LSI on, RTC on
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GD32F101xx
4.4
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the following table, based on the EMS levels and classes compliant with IEC 61000
series standard.
Table 6. EMS characteristics
Symbol
VESD
Parameter
Conditions
Voltage applied to all device pins to
VDD = 3.3 V, TA = +25 °C
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
Level/Class
induce a functional disturbance through
100 pF on VDD and VSS pins
3B
VDD = 3.3 V, TA = +25 °C
4A
conforms to IEC 61000-4-4
EMI (Electromagnetic Interference) emission testing result is given in the following table,
compliant with IEC 61967-2 standard which specifies the test board and the pin loading.
Table 7. EMI characteristics
Symbol
Parameter
Conditions
VDD = 3.3 V,
SEMI
Peak level
TA = +25 °C,
compliant with IEC
61967-2
4.5
Conditions
Tested
frequency band
Unit
8M
36M
56M
0.1 to 2 MHz
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