GD32F150C6T6

GigaDevice Semiconductor Inc. GD32F150xx ARM® Cortex®-M3 32-bit MCU Datasheet GD32F150xx Table of Contents List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 General description ......................................................................................................... 5 2 Device overview ............................................................................................................... 6 2.1 Device information .............................................................................................................................. 6 2.2 Block diagram ...................................................................................................................................... 7 2.3 Pinouts and pin assignment .............................................................................................................. 8 2.4 Memory map ...................................................................................................................................... 10 2.5 Clock tree ........................................................................................................................................... 11 2.6 Pin definitions .................................................................................................................................... 12 Functional description .................................................................................................. 18 3 ® ® 3.1 ARM Cortex -M3 core .................................................................................................................... 18 3.2 On-chip memory................................................................................................................................ 18 3.3 Clock, reset and supply management ........................................................................................... 19 3.4 Boot modes ........................................................................................................................................ 19 3.5 Power saving modes ........................................................................................................................ 20 3.6 Analog to digital converter (ADC) ................................................................................................... 20 3.7 Digital to analog converter (DAC) ................................................................................................... 21 3.8 DMA .................................................................................................................................................... 21 3.9 General-purpose inputs/outputs (GPIOs) ...................................................................................... 21 3.10 Timers and PWM generation........................................................................................................... 22 3.11 Real time clock (RTC) ...................................................................................................................... 23 3.12 Inter-integrated circuit (I2C) ............................................................................................................. 23 3.13 Serial peripheral interface (SPI)...................................................................................................... 24 3.14 Universal synchronous asynchronous receiver transmitter (USART) ....................................... 24 3.15 Inter-IC sound (I2S) .......................................................................................................................... 24 3.16 HDMI CEC ......................................................................................................................................... 25 3.17 Universal serial bus full-speed (USB 2.0 FS) ............................................................................... 25 3.18 Touch sensing interface (TSI) ......................................................................................................... 25 3.19 Comparators (CMP) ......................................................................................................................... 26 3.20 Debug mode ...................................................................................................................................... 26 3.21 Package and operation temperature.............................................................................................. 26 Electrical characteristics .............................................................................................. 27 4 4.1 Absolute maximum ratings .............................................................................................................. 27 4.2 Recommended DC characteristics ................................................................................................. 27 4.3 Power consumption .......................................................................................................................... 28 4.4 EMC characteristics .......................................................................................................................... 29 4.5 Power supply supervisor characteristics ....................................................................................... 29 1 / 41 GD32F150xx 4.6 Electrical sensitivity........................................................................................................................... 30 4.7 External clock characteristics .......................................................................................................... 30 4.8 Internal clock characteristics ........................................................................................................... 31 4.9 PLL characteristics ........................................................................................................................... 32 4.10 Memory characteristics .................................................................................................................... 32 4.11 GPIO characteristics......................................................................................................................... 32 4.12 ADC characteristics .......................................................................................................................... 33 4.13 DAC characteristics .......................................................................................................................... 33 4.14 I2C characteristics ............................................................................................................................ 33 4.15 SPI characteristics ............................................................................................................................ 34 Package information ..................................................................................................... 35 5 5.1 QFN package outline dimensions .................................................................................................. 35 5.3 LQFP package outline dimensions ................................................................................................ 37 6 Ordering Information ..................................................................................................... 39 7 Revision History............................................................................................................. 40 2 / 41 GD32F150xx List of Figures Figure 1. GD32F150xx block diagram ...................................................................................................................... 7 Figure 2. GD32F150Rx LQFP64 pinouts ................................................................................................................. 8 Figure 3. GD32F150Cx LQFP48 pinouts ................................................................................................................. 8 Figure 4. GD32F150Kx QFN32 pinouts ................................................................................................................... 9 Figure 5. GD32F150Gx QFN28 pinouts ................................................................................................................... 9 Figure 6. GD32F150xx memory map ..................................................................................................................... 10 Figure 7. GD32F150xx clock tree............................................................................................................................ 11 Figure 8. QFN package outline ................................................................................................................................ 35 Figure 9. LQFP package outline .............................................................................................................................. 37 3 / 41 GD32F150xx List of Tables Table 1. GD32F150xx devices features and peripheral list ................................................................................... 6 Table 2. GD32F150xx pin definitions ...................................................................................................................... 12 Table 3. Port A alternate functions summary ........................................................................................................ 16 Table 4. Port B alternate functions summary ........................................................................................................ 17 Table 5. Absolute maximum ratings ........................................................................................................................ 27 Table 6. DC operating conditions ............................................................................................................................ 27 Table 7. Power consumption characteristics ......................................................................................................... 28 Table 8. EMS characteristics ................................................................................................................................... 29 Table 9. EMI characteristics ..................................................................................................................................... 29 Table 10 Power supply supervisor characteristics................................................................................................ 29 Table 11. ESD characteristics.................................................................................................................................. 30 Table 12. Static latch-up characteristics ................................................................................................................ 30 Table 13. High speed external clock (HSE) generated from a crystal/ceramic characteristics ...................... 30 Table 14. Low speed external clock (LSE) generated from a crystal/ceramic characteristics ....................... 31 Table 15. High speed internal clock (HSI) characteristics ................................................................................... 31 Table 16. Low speed internal clock (LSI) characteristics ..................................................................................... 31 Table 17. PLL characteristics ................................................................................................................................... 32 Table 18. Flash memory characteristics ................................................................................................................. 32 Table 19. I/O port characteristics ............................................................................................................................. 32 Table 20. ADC characteristics .................................................................................................................................. 33 Table 21. DAC characteristics ................................................................................................................................. 33 Table 22. I2C characteristics .................................................................................................................................... 33 Table 23. SPI characteristics .................................................................................................................................... 34 Table 25. QFN package dimensions ....................................................................................................................... 36 Table 26. LQFP package dimensions ..................................................................................................................... 38 Table 27. Part ordering code for GD32F150xx devices ....................................................................................... 39 Table 28. Revision history......................................................................................................................................... 40 4 / 41 GD32F150xx 1 General description The GD32F150xx device belongs to the value line of GD32 MCU family. It is a 32-bit ® ® general-purpose microcontroller based on the high performance ARM Cortex -M3 RISC core with best ratio in terms of processing power, reduced power consumption and ® peripheral set. The Cortex -M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. ® ® The GD32F150xx device incorporates the ARM Cortex -M3 32-bit processor core operating at 72 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 64 KB on-chip Flash memory and up to 8 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, one 12-bit DAC and two comparators, up to five general-purpose 16-bit timers, a general-purpose 32-bit timer, a basic timer, a PWM advanced-control timer, as well as 2 standard and advanced communication interfaces: up to two SPIs, two I Cs, two USARTs, a 2 I S, a HDMI-CEC a TSI and an USB 2.0 FS. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F150xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on. 5 / 41 GD32F150xx 2 Device overview 2.1 Device information Table 1. GD32F150xx devices features and peripheral list GD32F150xx Part Number G6 G8 K4 K6 K8 C4 C6 C8 R4 R6 R8 Flash (KB) 16 32 64 16 32 64 16 32 64 16 32 64 SRAM (KB) 4 6 8 4 6 8 4 6 8 4 6 8 32-bit GP 1 1 1 1 1 1 1 1 1 1 1 1 16-bit GP 5 5 5 5 5 5 5 5 5 5 5 5 16-bit Adv. 1 1 1 1 1 1 1 1 1 1 1 1 16-bit Basic 1 1 1 1 1 1 1 1 1 1 1 1 SysTick 1 1 1 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 1 1 USART 1 2 2 1 2 2 1 2 2 1 2 2 I2C 1 1 2 1 1 2 1 1 2 1 1 2 SPI 1 1 2 1 1 2 1 1 2 1 1 2 I2S 1 1 1 1 1 1 1 1 1 1 1 1 USB 2.0 FS 1 1 1 1 1 1 1 1 1 1 1 1 HDMI CEC 1 1 1 1 1 1 1 1 1 1 1 1 GPIO 24 24 24 27 27 27 39 39 39 55 55 55 Capacitive Touch Channels 14 14 14 14 14 14 17 17 17 18 18 18 Analog Comparator 2 2 2 2 2 2 2 2 2 2 2 2 EXTI 16 16 16 16 16 16 16 16 16 16 16 16 Units 1 1 1 1 1 1 1 1 1 1 1 1 Channels (Ext.) 10 10 10 10 10 10 10 10 10 16 16 16 Channels (Int.) 3 3 3 3 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 1 ADC Connectivity Timers G4 DAC Package QFN28 QFN32 LQFP48 LQFP64 6 / 41 GD32F150xx 2.2 Block diagram Figure 1. GD32F150xx block diagram LDO 1.2V TPIU SW AHB Matrix NVIC ICode DCode System ARM Cortex-M3 Processor Fmax: 72MHz AHB2: Fmax = 72MHz IBus GPIO Ports A, B, C, D, F SRAM Controller SRAM Flash Memory Controller Flash Memory POR/PDR LVD PLL Touch Sensing Controller DBus GP DMA 7chs AHB1: Fmax = 72MHz AHB to APB Bridge 2 CRC AHB to APB Bridge 1 Fmax: 72MHz HSE 4-32MHz HSI 8MHz RST/CLK Controller HSI14 14MHz LSI 40KHz Powered by LDO (1.2V) Powered by V DD/VDDA PWR EXTI IWDG 12-bit SAR ADC ADC WWDG RTC USART1 USB SRAM SPI/I2S1 CMP TM1 TM15 APB1: Fmax = 72MHz Comparator 2 APB2: Fmax = 72MHz SYS Config Comparator 1 USB FS HDMI-CEC I2C1 I2C2 DAC TM16 12-bit DAC USART2 TM17 SPI2 TM6 TM2 TM3 TM14 7 / 41 GD32F150xx 2.3 Pinouts and pin assignment Figure 2. GD32F150Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PC12 PD2 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 PC13 2 47 PF6 PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT PF0-OSC_IN 4 45 PA12 5 44 PA11 PF1-OSC_OUT 6 43 PA10 PA9 PC0 7 8 42 41 PA8 PC1 9 10 40 39 PC9 PC2 PC3 VSSA 11 12 38 PC7 37 PC6 VDDA 13 36 PB15 NRST GigaDevice GD32F150Rx LQFP64 PF7 PC8 PA0 14 35 PA1 15 34 PB14 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VSS PB11 PB10 PB2 PB1 PC5 PB0 PC4 PA7 PA5 PA6 PA4 PF5 PF4 PA3 Figure 3. GD32F150Cx LQFP48 pinouts PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD 48 47 46 45 44 43 42 41 40 39 38 37 1 36 PF7 PC13 2 35 PF6 PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT PF0-OSC_IN 4 33 PA12 5 32 PA11 31 PA10 30 PA9 29 PA8 PB15 VBAT GigaDevice GD32F150Cx LQFP48 6 PF1-OSC_OUT NRST VSSA 7 8 VDDA 9 PA0 10 28 27 PA1 PA2 11 12 26 PB14 PB13 25 PB12 13 14 15 16 17 18 19 20 21 22 23 24 VDD VSS PB11 PB10 PB2 PB1 PA7 PB0 PA6 PA5 PA4 PA3 8 / 41 GD32F150xx Figure 4. GD32F150Kx QFN32 pinouts 3 4 VDDA PA0 5 PA1 7 PA2 PA15 PB3 PB4 PB5 OSC_OUT/PF1 NRST PB6 PB7 BOOT0 PB8 OSC_IN/PF0 1 2 VDD 32 31 30 29 28 27 26 25 24 PA14 23 PA13 22 PA12 21 PA11 20 PA10 GigaDevice GD32F150Kx QFN32 6 19 18 8 17 9 10 11 12 13 14 15 16 VSS, VSSA PA9 PA8 VDD PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 Figure 5. GD32F150Gx QFN28 pinouts VDDA 5 PA0 6 PA1 7 PA14 PA15 3 4 PB3 PB4 OSC_OUT/PF1 NRST PB5 PB6 PB7 OSC_IN/PF0 1 2 BOOT0 28 27 26 25 24 23 22 21 PA13 GigaDevice GD32F150Gx QFN28 VSS,VSSA 8 20 PA12 19 PA11 18 17 PA10 PA9 16 15 9 10 11 12 13 14 VDD PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 9 / 41 GD32F150xx 2.4 Memory map Figure 6. GD32F150xx memory map 0x5000 0000 0x4800 1800 0x4800 1400 0x4800 1000 0x4800 0C00 0x4800 0800 0x4800 0400 0x4800 0000 0x4002 4400 0x4002 4000 0x4002 3400 0x4002 3000 0x4002 2400 0x4002 2000 0x4002 1400 0x4002 1000 0x4002 0400 0x4002 0000 0x4001 4C00 0x4001 4800 0x4001 4400 0x4001 4000 0x4001 3C00 0x4001 3800 0x4001 3400 0x4001 3000 0x4001 2C00 0xFFFF FFFF 7 0xE010 0000 0x1FFF FFFF 0x1FFF F80F reserved Option Bytes reserved 0xE000 0000 Cortex-M3 Internal Peripherals 6 reserved 0x1FFF F800 0x4001 2800 0x4001 2400 0x4001 0800 0x4001 0400 0x4001 0000 0x4000 C400 0x4000 C000 0xC000 0000 System memory 0x4000 7C00 0x4000 7800 5 reserved 0x4000 7400 0x4000 7000 0x1FFF EC00 0xA000 0000 0x4000 6400 0x4000 6000 4 reserved 0x4000 5C00 0x4000 5800 reserved 0x8000 0000 0x4000 5400 0x4000 4800 3 reserved 0x4000 4400 0x4000 4000 0x6000 0000 2 0x5000 0000 0x4000 3C00 reserved Peripherals 0x4000 0000 0x0801 FFFF 1 Flash memory 0x0800 0000 Aliased to Flash or system memory according to BOOT 0x0000 0000 pins configuration 0x2000 0000 0x4000 3800 0x4000 3400 0x4000 3000 0x4000 2C00 reserved SRAM 0x4000 2800 0x4000 2400 0x4000 2000 0x4000 1400 0x4000 1000 0 reserved 0x4000 0800 0x4000 0400 0x0000 0000 0x4000 0000 reserved Port F reserved Port D Port C Port B Port A reserved TSI reserved CRC reserved Flash Interface reserved RCC reserved DMA reserved TM17 TM16 TM15 reserved USART1 reserved SPI/I2S1 TM1 reserved ADC reserved EXTI SYS Config + CMP reserved reserved reserved CEC DAC PWR reserved USB SRAM (512B) USB registers I2C2 I2C1 reserved USART2 reserved reserved SPI2 reserved IWDG WWDG RTC reserved TM14 reserved TM6 reserved TM3 TM2 10 / 41 GD32F150xx 2.5 Clock tree Figure 7. GD32F150xx clock tree CK_LSE ÷244 1 CK_CEC 0 (to CEC) CECSEL USB Prescaler ÷1,1.5,2 CK_USB (to USB) CK_I2S (to I2S) CK_FLITF SCS[1:0 ] FLITF enable (by hardware) (to FLITF) HCLK CK_HSI 00 8 MHz HSI RC 0 /2 PLL 1 1 CK_PLL 0 AHB enable CK_SYS 72 MHz max AHB Prescaler ÷1,2...512 (to AHB bus,Cortex-M3,SRAM,DMA) CK_CST CK_AHB 72 MHz max ÷8 (to Cortex-M3 SysTick) FCLK HSEPRED V 4-32 MHz HSE XTAL PLLSEL PLLEN 01 Clock Monitor ÷1,2. ..16 (free running clock) TIM2,3,6,14 ÷[apb1 prescaler/2] CK_TIMX TIMX enable to TIM2,3,6,14 CK_HSE /32 APB1 Prescaler ÷1,2,4,8,16 11 CK_APB1 PCLK1 72 MHz max Peripheral enable 32.768 KHz LSE OSC 0 1 CK_RTC (to RTC) 10 40 KHz LSI RC RTCSRC[1:0] CK_IWDG (to IWDG) TIM1,15,16,1 7 ÷[apb2 prescaler/2] APB2 Prescaler ÷1,2,4,8,16 CK_TIM1 TIM1 enable to TIM1,15,16,17 CK_APB2 PCLK2 72 MHz max Peripheral enable CK_OUT ÷1,2,4...128 CKOUTDIV 0 CK_HSI14 CK_LSI CK_LSE CK_SYS CK_HSI CK_HSE *1,2 CK_PLL ADC Prescaler ÷2,4,8,12,16 to APB1 peripherals to APB2 peripherals 1 CK_ADCX to ADC1 0 14 MHz max ADCSEL 14 MHz HSI RC CK_HSI 11 CK_LSE 10 0 1 00 CK_SYS CK_USART1 to USART1 Legend: HSE = High speed external clock HSI = High speed internal clock LSE = Low speed external clock LSI = Low speed internal clock 11 / 41 GD32F150xx 2.6 Pin definitions Table 2. GD32F150xx pin definitions PC14-OSC32 _IN PC15OSC32_OUT PF0-OSC_IN PF1-OSC_O UT NRST Level 1 1 - - P 2 2 - - I/O 3 3 - - I/O 4 4 - - I/O 5 5 2 2 I/O 5VT 6 6 3 3 I/O 5VT 7 7 4 4 I/O Functions description I/O (2) Pin Type R-RTC QFN28 PC13-TAMPE QFN32 VBAT LQFP48 Pin Name LQFP64 (1) Pins Default: VBAT Default: PC13 Additional: RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2 Default: PC14 Additional: OSC32_IN Default: PC15 Additional: OSC32_OUT Default: PF0 Additional: OSC_IN Default: PF1 Additional: OSC_OUT Default: NRST Default: PC0 PC0 8 - - - I/O Alternate: EVENTOUT Additional: ADC_IN10 Default: PC1 PC1 9 - - - I/O Alternate: EVENTOUT Additional: ADC_IN11 Default: PC2 PC2 10 - - - I/O Alternate: EVENTOUT Additional: ADC_IN12 Default: PC3 PC3 11 - - - I/O Alternate: EVENTOUT Additional: ADC_IN13 VSSA 12 8 0 0 P Default: VSSA VDDA 13 9 5 5 P Default: VDDA Default: PA0 (3) PA0-WKUP 14 10 6 6 I/O (4) Alternate: USART1_CTS , USART2_CTS , TM2_CH1_ETR, CMP1_OUT, TSI_G1_IO1, I2C2_SCL Additional: ADC_IN0, CMP1_INM6, RTC_TAMP2, WKUP1 Default: PA1 (3) PA1 15 11 7 7 I/O (4) Alternate: USART1_RTS , USART2_RTS , TM2_CH2, TSI_G1_IO2, I2C2_SDA, EVENTOUT Additional: ADC_IN1, CMP1_INP Default: PA2 PA2 16 12 8 8 I/O (3) (4) Alternate: USART1_TX , USART2_TX , TM2_CH3, TM15_CH1 , CMP2_OUT, 12 / 41 GD32F150xx Level (2) Functions description I/O Pin Type QFN28 QFN32 LQFP48 Pin Name LQFP64 (1) Pins TSI_G1_IO3 Additional: ADC_IN2, CMP2_INM6 Default: PA3 (3) PA3 17 13 9 9 (4) Alternate: USART1_RX , USART2_RX , TM2_CH4, TM15_CH2, I/O TSI_G1_IO4 Additional: ADC_IN3/CMP2_INP PF4 PF5 18 19 - - - I/O I/O 5VT 5VT Default: PF4 Alternate: SPI2_NSS, EVENTOUT Default: PF5 Alternate: EVENTOUT Default: PA4 (3) PA4 20 14 10 10 (4) Alternate: SPI1_NSS, I2S1_WS, USART1_RX , USART2_RX , I/O TM14_CH1, TSI_G2_IO1, SPI2_NSS Additional: ADC_IN4, CMP1_INM4, CMP2_INM4, DAC1_OUT Default: PA5 PA5 21 15 11 11 Alternate: SPI1_SCK, I2S1_CK, CEC, TM2_CH1_ETR, TSI_G2_IO2 I/O Additional: ADC_IN5, CMP1_INM5, CMP2_INM5 Default: PA6 PA6 22 16 12 12 Alternate: SPI1_MISO, I2S1_MCK, TM3_CH1, TM1_BKIN, TM16_CH1, I/O CMP1_OUT, TSI_G2_IO3, EVENTOUT Additional: ADC_IN6 Default: PA7 PA7 23 17 13 13 Alternate: SPI1_MOSI, I2S1_SD, TM3_CH2, TM14_CH1, TM1_CH1N, I/O TM17_CH1, CMP2_OUT, TSI_G2_IO4, EVENTOUT Additional: ADC_IN7 Default: PC4 PC4 24 - - - Alternate: EVENTOUT I/O Additional: ADC_IN14 Default: PC5 PC5 25 - - - Alternate: TSI_G3_IO1 I/O Additional: ADC_IN15 Default: PB0 PB0 26 18 14 14 Alternate: TM3_CH3, TM1_CH2N, TSI_G3_IO2, USART2_RX, I/O EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 27 19 15 15 Alternate: TM3_CH4, TM14_CH1, TM1_CH3N, TSI_G3_IO3, SPI2_SCK I/O Additional: ADC_IN9 Default: PB2 PB2 28 20 16 - I/O 5VT PB10 29 21 - - I/O 5VT PB11 30 22 - - I/O 5VT Default: PB11 Alternate: TSI_G3_IO4 Default: PB10 Alternate: I2C2_SCL, CEC, TM2_CH3, TSI_SYNC 13 / 41 GD32F150xx Level (2) Functions description I/O Pin Type QFN28 QFN32 LQFP48 Pin Name LQFP64 (1) Pins Alternate: I2C2_SDA, TM2_CH4, TSI_G6_IO1, EVENTOUT VSS 31 23 - - VDD 32 24 17 16 P Default: VSS P Default: VDD Default: PB12 (3) (4) (3) (4) PB12 33 25 - - I/O 5VT Alternate: SPI1_NSS , SPI2_NSS , TM1_BKIN, TSI_G6_IO2, I2C2_SMBA, EVENTOUT PB13 34 26 - - I/O 5VT Default: PB13 Alternate: SPI1_SCK , SPI2_SCK , TM1_CH1N, TSI_G6_IO3 Default: PB14 PB14 35 27 - - I/O (3) (4) (3) (4) 5VT Alternate: SPI1_MISO , SPI2_MISO , TM1_CH2N, TM15_CH1, TSI_G6_IO4 Default: PB15 Alternate: SPI1_MOSI , SPI2_MOSI , TIM1_CH3N, TM15_CH1N, PB15 36 28 - - I/O 5VT TM15_CH2 Additional: RTC_REFIN PC6 37 - - - I/O 5VT PC7 38 - - - I/O 5VT PC8 39 - - - I/O 5VT PC9 40 - - - I/O 5VT PA8 41 29 18 - I/O 5VT PA9 42 30 19 17 I/O 5VT PA10 43 31 20 18 I/O 5VT Default: PC6 Alternate: TM3_CH1 Default: PC7 Alternate: TM3_CH2 Default: PC8 Alternate: TM3_CH3 Default: PC9 Alternate: TM3_CH4 Default: PA8 Alternate: USART1_CK, TM1_CH1, MCO, USART2_TX, EVENTOUT Default: PA9 Alternate: USART1_TX, TM1_CH2, TM15_BKIN, TSI_G4_IO1, I2C1_SCL Default: PA10 Alternate: USART1_RX, TM1_CH3, TM17_BKIN, TSI_G4_IO2, I2C1_SDA Default: PA11 PA11 44 32 21 19 I/O 5VT Alternate: USART1_CTS, TM1_CH4, CMP1_OUT, TSI_G4_IO3, EVENTOUT Additional: USBDM Default: PA12 PA12 45 33 22 20 I/O 5VT Alternate: USART1_RTS, TM1_ETR, CMP2_OUT, TSI_G4_IO4, EVENTOUT Additional: USBDP Default: PA13 PA13 46 34 23 21 I/O 5VT PF6 47 35 - - I/O 5VT Default: I2C2_SCL PF7 48 36 - - I/O 5VT Default: I2C2_SDA PA14 49 37 24 22 I/O 5VT Default: PA14 Alternate: IR_OUT, SWDAT, SPI2_MISO 14 / 41 GD32F150xx Level (2) Functions description I/O Pin Type QFN28 QFN32 LQFP48 Pin Name LQFP64 (1) Pins (3) (4) Alternate: USART1_TX , USART2_TX , SWCLK, SPI2_MOSI Default: PA15 (3) (4) I/O 5VT Alternate: SPI1_NSS, I2S1_WS, USART1_RX , USART2_RX , - I/O 5VT Default: PC10 - - I/O 5VT Default: PC11 - - - I/O 5VT Default: PC12 - - - I/O 5VT 39 26 24 I/O 5VT 40 27 25 I/O 5VT PA15 50 38 25 23 PC10 51 - - PC11 52 - PC12 53 PD2 54 PB3 55 PB4 56 TM2_CH1_ETR, SPI2_NSS, EVENTOUT PB5 57 41 28 26 I/O 5VT PB6 58 42 29 27 I/O 5VT 5VT Default: PD2 Alternate: TM3_ETR Default: PB3 Alternate: SPI1_SCK/I2S1_CK, TM2_CH2, TSI_G5_IO1, EVENTOUT Default: PB4 Alternate: SPI1_MISO/I2S1_MCK, TM3_CH1, TSI_G5_IO2, EVENTOUT Default: PB5 Alternate: SPI1_MOSI/I2S1_SD, I2C1_SMBA, TM16_BKIN, TM3_CH2 Default: PB6 Alternate: I2C1_SCL, USART1_TX, TM16_CH1N, TSI_G5_IO3 Default: PB7 PB7 59 43 30 28 I/O BOOT0 60 44 31 1 I PB8 61 45 32 - I/O 5VT PB9 62 46 - - I/O 5VT VSS 63 47 0 0 P Default: VSS VDD 64 48 1 - P Default: VDD Alternate: I2C1_SDA, USART1_RX, TM17_CH1N,TSI_G5_IO4 Default: BOOT0 Default: PB8 Alternate: I2C1_SCL, CEC, TM16_CH1, TSI_SYNC Default: PB9 Alternate: I2C1_SDA, IR_OUT, TM17_CH1, EVENTOUT Notes: 1. Type: I = input, O = output, P = power. 2. I/O Level: 5VT = 5 V tolerant. 3. This feature is available on GD32F150x4 devices only. 4. This feature is available on GD32F150x8 and GD32F150x6 devices only. 15 / 41 GD32F150xx Table 3. Port A alternate functions summary Pin Name AF0 AF1 AF2 USART1_CTS(1) PA0 USART2_CTS (2) AF3 AF4 TSI_G1_IO1 I2C2_SCL TM2_CH2 TSI_G1_IO2 I2C2_SDA TM2_CH3 TSI_G1_IO3 TM2_CH4 TSI_G1_IO4 AF5 AF6 AF7 TM2_CH1_ CMP1_OUT ETR USART1_RTS(1) PA1 EVENTOUT PA2 TM15_CH1 PA3 TM15_CH2 USART2_RTS(2) USART1_TX(1) USART2_TX(2) CMP2_OUT USART1_RX(1) USART2_RX(2) SPI1_NSS/ USART1_CK(1) I2S1_WS USART2_CK(2) PA4 TM14_CH1 SPI2_NSS TM2_CH1_ SPI1_SCK/ PA5 TSI_G2_IO1 TSI_G2_IO2 CEC ETR I2S1_CK SPI1_MISO/ PA6 TM3_CH1 TM1_BKIN TSI_G2_IO3 TM3_CH2 TM1_CH1N TSI_G2_IO4 TM14_CH1 TM16_CH1 EVENTOUT CMP1_OUT TM17_CH1 EVENTOUT CMP2_OUT I2S1_MCK SPI1_MOSI/ PA7 I2S1_SD PA8 MCO USART1_CK TM1_CH1 EVENTOUT USART2_TX PA9 TM15_BKIN USART1_TX TM1_CH2 TSI_G4_IO1 I2C1_SCL PA10 TM17_BKIN USART1_RX TM1_CH3 TSI_G4_IO2 I2C1_SDA PA11 EVENTOUT USART1_CTS TM1_CH4 TSI_G4_IO3 CMP1_OUT PA12 EVENTOUT USART1_RTS TM1_ETR TSI_G4_IO4 CMP2_OUT PA13 SWDAT IR_OUT SPI2_MISO (1) USART1_TX PA14 SWCLK SPI1_NSS/ PA15 I2S1_WS SPI2_MOSI USART2_TX(2) USART1_RX(1) (2) USART2_RX TM2_CH1_ EVENTOUT SPI2_NSS ETR 1. This feature is available on GD32F150x4 devices only. 2. This feature is available on GD32F150x8 and GD32F150x6 devices only. 16 / 41 GD32F150xx Table 4. Port B alternate functions summary Pin AF0 AF1 AF2 AF3 AF4 PB0 EVENTOUT TM3_CH3 TM1_CH2N TSI_G3_IO2 USART2_RX PB1 TM14_CH1 TM3_CH4 TM1_CH3N TSI_G3_IO3 Name PB2 PB3 PB4 PB5 AF5 AF6 SPI2_SCK TSI_G3_IO4 SPI1_SCK / I2S1_CK SPI1_MISO / I2S1_MCK SPI1_MOSI / I2S1_SD EVENTOUT TM2_CH2 TSI_G5_IO1 TM3_CH1 EVENTOUT TSI_G5_IO2 TM3_CH2 TM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TM16_CH1N TSI_G5_IO3 PB7 USART1_RX I2C1_SDA TM17_CH1N TSI_G5_IO4 PB8 CEC I2C1_SCL TM16_CH1 TSI_SYNC PB9 IR_OUT I2C1_SDA TM17_CH1 EVENTOUT PB10 CEC I2C2_SCL TM2_CH3 TSI_SYNC PB11 EVENTOUT I2C2_SDA TM2_CH4 TSI_G6_IO1 EVENTOUT TM1_BKIN TSI_G6_IO2 TM1_CH1N TSI_G6_IO3 TM15_CH1 TM1_CH2N TSI_G6_IO4 TM15_CH2 TM1_CH3N TM15_CH1N (1) PB12 SPI1_NSS (2) SPI2_NSS I2C2_SMBA (1) PB13 SPI1_SCK (2) SPI2_SCK (1) PB14 PB15 SPI1_MISO (2) SPI2_MISO SPI1_MOSI (1) SPI2_MOSI (2) 1. This feature is available on GD32F150x4 devices only. 2. This feature is available on GD32F150x8 and GD32F150x6 devices only. 17 / 41 GD32F150xx 3 Functional description 3.1 ARM® Cortex®-M3 core ® The Cortex -M3 processor is the latest generation of ARM ® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. ® ®  32-bit ARM Cortex -M3 processor core  Up to 72 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer ® The Cortex -M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by ® Cortex -M3:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 64 Kbytes of Flash memory  Up to 8 Kbytes of SRAM with hardware parity checking ® The ARM ® Cortex -M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 64 Kbytes of inner Flash and 8 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Figure 7. GD32F150xx memory map shows the memory map of the GD32F150xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 18 / 41 GD32F150xx 3.3 Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB and two APB domains is 72 MHz. See Figure 9 for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default)  Boot from system memory  Boot from on-chip SRAM In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART1 in device mode. 19 / 41 GD32F150xx 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the HSI is selected as the system clock.  Standby mode In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of HSI, HSE and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge on WKUP pin. 3.6 Analog to digital converter (ADC)  12-bit SAR ADC engine with up to 1 MSPS conversion rate  Conversion range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor One 12-bit 1 μs multi-channel ADC is integrated in the device. It is a total of up to 16 multiplexed external channels and 3 internal channels for temperature sensor, voltage reference, VBAT voltage measurement. The conversion range is between 2.6 V < VDDA < 3.6 V. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages. The ADC can be triggered from the events generated by the general-purpose timers (TMx) and the advanced-control timers (TM1) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. Each device is factory-calibrated to improve the accuracy and the calibration data are stored in the system memory area. 20 / 41 GD32F150xx 3.7 Digital to analog converter (DAC)  12-bit DAC converter of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+. 3.8 DMA  7 channel DMA controller  Peripherals supported: Timers, ADC, SPIs, I Cs, USARTs, DAC and I S 2 2 The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9 General-purpose inputs/outputs (GPIOs)  Up to 55 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 55 general purpose I/O pins (GPIO) in GD32F150xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 21 / 41 GD32F150xx 3.10 Timers and PWM generation  One 16-bit advanced-control timer (TM1), one 32-bit general-purpose timer (TM2), five 16-bit general-purpose timers (TM3, TM14 ~ TM17), and one 16-bit basic timer (TM6)  Up to 4 independent channels of PWM, output compare or input capture for each general-purpose timer (GPTM) and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Independent watchdog and window watchdog) The advanced-control timer (TM1) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM) can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM14 ~ TM17 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TM6, is mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F150xx have two watchdog peripherals, Independent watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in stop and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It 22 / 41 GD32F150xx features: 3.11  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.  Calendar with subsecond, seconds, minutes, hours, week day, date, year and month automatically correction  Alarm function with wake up from deep-sleep and standby mode capability  On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy. The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.12 Inter-integrated circuit (I2C)  Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 23 / 41 GD32F150xx 3.13 Serial peripheral interface (SPI)  Up to two SPI interfaces with a frequency of up to 18 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14 Universal synchronous asynchronous receiver transmitter (USART)  Up to two USARTs with operating frequency up to 9 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART1, USART2) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication. 3.15 Inter-IC sound (I2S)  One I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with SPI1  Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F150xx contain a I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error. 24 / 41 GD32F150xx 3.16 HDMI CEC  Hardware support Consumer Electronics Control (CEC) protocol (HDMI standard rev1.4) The CEC protocol provides high-level control functions between the audiovisual products linked with HDMI cables. GD32F150xx contain a HDMI-CEC controller which has an independent clock domain and can wake up the MCU from deep-sleep mode on data reception. 3.17 Universal serial bus full-speed (USB 2.0 FS)  One full-speed USB Interface with frequency up to 12 Mbit/s  Internal main PLL for USB CLK compliantly The Universal Serial Bus (USB) is a 4-wire bus that supports communication between one or more devices. Full-speed peripheral is compliant with the USB 2.0 specification. The device controller enables 12 Mbit/s data exchange with a USB Host controller. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above. 3.18 Touch sensing interface (TSI)  Supports up to 18 external electrodes by the sensing channels distributed over 6 analog I/O groups  Programmable charging frequency and I/O pins  Capability to wake up the MCU from power saving modes Capacitive sensing technology can be used for the detection of a finger (or any conductive object) presence near an electrode. The capacitive variation of the electrode introduced by the finger can be measured by charging and detecting the voltage across the sampling capacitor. GD32F150xx contain a hardware touch sensing interface (TSI) and only requires few external components to operate. The sensing channels are distributed over 6 analog I/O groups including: Group1 (PA0 ~ PA3), Group2 (PA4 ~ PA7), Group3 (PC5, PB0 ~ PB2), Group4 (PA9 ~ PA12), Group5 (PB3,PB4, PB6,PA7) and Group6 (PB11 ~ PB14), 25 / 41 GD32F150xx 3.19 Comparators (CMP)  Two fast rail-to-rail low-power comparators with software configurable  Programmable reference voltage (internal, external I/O or DAC output pin) Two Comparators (CMP) are implemented within the devices. Both comparators can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC. 3.20 Debug mode  Serial wire JTAG debug port (SWJ-DP) ® The ARM SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.21 Package and operation temperature  LQFP64 (GD32F150Rx), LQFP48 (GD32F150Cx), QFN32 (GD32F150Kx) and QFN28 (GD32F150Gx)  Operation temperature range: -40°C to +85°C (industrial level) 26 / 41 GD32F150xx 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Min Max Unit VDD External voltage range VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V Input voltage on 5V tolerant pin VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V VIN IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Storage temperature range -55 +150 °C Maximum junction temperature — 125 °C TSTG TJ 4.2 Parameter Recommended DC characteristics Table 6. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V 27 / 41 GD32F150xx 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 7. Power consumption characteristics Symbol Parameter Conditions Min Typ — 26.10 — mA — 17.69 — mA -— 17.81 — mA — 12.21 — mA — 14.86 — mA — 5.19 — mA — 172.49 — μA — 160.84 — μA VDD=VDDA=3.3V, LSE off, LSI on, RTC on — 7.39 — μA VDD=VDDA=3.3V, LSE off, LSI on, RTC off — 6.93 — μA VDD=VDDA=3.3V, LSE off, LSI off, RTC off — 5.72 — μA — 3.12 — μA — 2.80 — μA — 2.16 — μA — 1.40 — μA — 1.29 — μA — 1.10 — μA VDD=VDDA=3.3V, HSE=8MHz, System Max Unit clock=72 MHz, All peripherals enabled VDD=VDDA=3.3V, HSE=8MHz, System clock Supply current =72 MHz, All peripherals disabled (Run mode) VDD=VDDA=3.3V, HSE=8MHz, System clock =48 MHz, All peripherals enabled VDD=VDDA=3.3V, HSE=8MHz, System Clock =48 MHz, All peripherals disabled VDD=VDDA=3.3V, HSE=8MHz, CPU clock off, System clock =72 MHz, All peripherals IDD Supply current enabled (Sleep mode) VDD=VDDA=3.3V, HSE=8MHz, CPU clock off, System clock =72 MHz, All peripherals disabled VDD=VDDA=3.3V, Regulator in run mode, LSI Supply current on, RTC on, All GPIOs analog mode (Deep-Sleep VDD=VDDA=3.3V, Regulator in low power mode) mode, LSI on, RTC on, All GPIOs analog mode Supply current (Standby mode) VDD not available, VBAT=3.6 V, LSE on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.3 V, LSE on with external crystal, RTC on, Higher driving VDD not available, VBAT=2.6 V, LSE on with IBAT Battery supply external crystal, RTC on, Higher driving current VDD not available, VBAT=3.6 V, LSE on with external crystal, RTC on, Lower driving VDD not available, VBAT=3.3 V, LSE on with external crystal, RTC on, Lower driving VDD not available, VBAT=2.6 V, LSE on with external crystal, RTC on, Lower driving 28 / 41 GD32F150xx 4.4 EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 8. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB Level/Class induce a functional disturbance through 100 pF on VDD and VSS pins 3B VDD = 3.3 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 9. EMI characteristics Symbol Parameter Conditions VDD = 3.3 V, SEMI Peak level TA = +25 °C, compliant with IEC 61967-2 4.5 Tested frequency band Conditions Unit 48M 72M 0.1 to 2 MHz