DDR4 SDRAM
GDQ2BFAA
GDQ2BFAA
DATASHEET
DS-00808-GDQ2BFAA-Rev1.4DS-00808-GDQ2BFAA-Rev1.4.docx
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June 2022
DDR4 SDRAM
GDQ2BFAA
Contents
1
2
3
FEATURES ....................................................................................................................................................................... 5
1.1
SPEED BINS ....................................................................................................................................................................... 6
1.2
ADDRESS TABLE ................................................................................................................................................................. 6
ORDERING INFORMATION ............................................................................................................................................. 7
2.1
PART NUMBER DECODING ................................................................................................................................................... 7
2.2
VALID PART NUMBERS ........................................................................................................................................................ 8
PACKAGE INFORMATION ................................................................................................................................................ 9
3.1
4
PACKAGE 96-BALL FBGA (X16) ........................................................................................................................................... 9
BALL ASSIGNMENTS ..................................................................................................................................................... 10
4.1
96-BALL FBGA (X16) BALL ASSIGNMENTS ............................................................................................................................ 10
4.2
BALL DESCRIPTION ............................................................................................................................................................ 11
5
FUNCTIONAL BLOCK DIAGRAM .................................................................................................................................... 14
6
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................... 15
7
6.1
ABSOLUTE MAXIMUM DC RATINGS ..................................................................................................................................... 15
6.2
RECOMMENDED DC OPERATING CONDITIONS ....................................................................................................................... 15
6.3
DRAM COMPONENT OPERATING TEMPERATURE RANGE ......................................................................................................... 15
AC AND DC INPUT MEASUREMENT LEVELS .................................................................................................................. 17
7.1
AC AND DC LOGIC INPUT LEVELS FOR SINGLE-ENDED SIGNALS .................................................................................................. 17
7.2
AC AND DC LOGIC INPUT MEASUREMENT LEVELS: VREF TOLERANCES ........................................................................................ 18
7.3
AC AND DC LOGIC INPUT LEVELS FOR DIFFERENTIAL SIGNALS ................................................................................................... 18
7.3.1
AC and DC Logic Input Levels for Differential Signals .............................................................................................. 18
7.3.2
Differential Swing Requirements for Clock (CK_t - CK_c) ........................................................................................ 19
7.3.3
Differential Swing Requirements for Clock (CK_t - CK_c) ........................................................................................ 21
7.3.4
Address, Command, and Control Overshoot/Undershoot Specifications ............................................................... 22
7.3.5
Address, Command, and Control Overshoot/Undershoot Specifications ............................................................... 23
7.3.6
Data, Strobe and Mask Overshoot/Undershoot Specifications ............................................................................... 24
7.4
7.4.1
7.4.2
SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS...................................................................................................... 25
Slew Rate Definitions for Differential Input Signals ................................................................................................. 25
Slew Rate Definitions for Differential Input Signals (CMD/ADD) ............................................................................. 25
7.5
CK DIFFERENTIAL INPUT POINT VOLTAGE .............................................................................................................................. 26
7.6
CMOS RAIL TO RAIL INPUT LEVELS FOR RESET_N ................................................................................................................. 27
7.7
AC&DC LOGIC INPUT LEVELS FOR DQS SIGNALS.................................................................................................................... 28
7.7.1
Differential Signal Definition.................................................................................................................................... 28
7.7.2
Differential Swing Requirements for DQS (DQS_t – DQS_c) .................................................................................... 28
7.7.3
Peak Voltage Calculation Method ........................................................................................................................... 29
7.7.4
Differential Input Cross Point Voltage ..................................................................................................................... 29
7.7.5
Differential Input Slew Rate Definition .................................................................................................................... 31
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DDR4 SDRAM
8
AC&DC OUTPUT MEASUREMENT LEVELS ..................................................................................................................... 32
8.1
9
GDQ2BFAA
OUTPUT DRIVER DC ELECTRONIC CHARACTERISTICS ................................................................................................................ 32
8.1.1
Alert_n Output Driver Characteristic ....................................................................................................................... 34
8.1.2
Output Driver Characteristic of Connectivity Test (CT) Mode ................................................................................. 35
8.2
SINGLE-ENDED AC& DC OUTPUT LEVELS .............................................................................................................................. 36
8.3
DIFFERENTIAL AC&DC OUTPUT LEVELS ................................................................................................................................ 36
8.4
SINGLE-ENDED OUTPUT SLEW RATE ..................................................................................................................................... 37
8.5
DIFFERENTIAL OUTPUT SLEW RATE ...................................................................................................................................... 38
8.6
SINGLE-ENDED AC& DC OUTPUT LEVELS OF CONNECTIVITY TEST MODE .................................................................................... 39
8.7
REFERENCE LOAD FOR CONNECTIVITY TEST MODE TIMING ....................................................................................................... 39
SPEED BIN .................................................................................................................................................................... 40
9.1
DDR4-1600 SPEED BINS AND OPERATIONS.......................................................................................................................... 40
9.2
DDR4-1866 SPEED BINS AND OPERATIONS.......................................................................................................................... 41
9.3
DDR4-2133 SPEED BINS AND OPERATIONS.......................................................................................................................... 42
9.4
DDR4-2400 SPEED BINS AND OPERATIONS.......................................................................................................................... 43
9.5
DDR4-2666 SPEED BINS AND OPERATIONS.......................................................................................................................... 44
9.6
DDR4-3200 SPEED BINS AND OPERATIONS.......................................................................................................................... 45
9.7
TREFI AND TRFC PARAMETERS ........................................................................................................................................... 47
10
IDD AND IDDQ SPECIFICATION PARAMETERS AND TEST CONDITIONS ...................................................................... 48
10.1
IDD, IPP AND IDDQ MEASUREMENT CONDITIONS................................................................................................................. 48
10.1.1
IDD0, IDD0A and IPP0 Measurement-Loop Pattern ............................................................................................ 58
10.1.2
IDD1, IDD1A and IPP1 Measurement-Loop Pattern ............................................................................................ 59
10.1.3
IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2, IDD3N, IDD3NA and IDD3P Measurement-Loop
Pattern
61
10.1.4
IDD2NT and IDDQ2NT Measurement-Loop Pattern ............................................................................................ 62
10.1.5
IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1 ................................................................. 63
10.1.6
IDD4W, IDDR4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern ........................................................ 65
10.1.7
IDD4WC Measurement-Loop Pattern .................................................................................................................. 67
10.1.8
IDD5B Measurement-Loop Pattern ..................................................................................................................... 69
10.1.9
IDD7 Measurement-Loop Pattern ....................................................................................................................... 71
10.2
IDD SPECIFICATIONS ......................................................................................................................................................... 73
11
INPUT/OUTPUT CAPACITANCE ................................................................................................................................. 75
12
ELECTRICAL CHARACTERISTICS & AC TIMING ........................................................................................................... 77
12.1
REFERENCE LOAD FOR AC TIMING AND OUTPUT SLEW RATE .................................................................................................... 77
12.2
TREFI ............................................................................................................................................................................ 77
12.3
CLOCK SPECIFICATION........................................................................................................................................................ 77
12.3.1
Definition for tCK(abs) ......................................................................................................................................... 77
12.3.2
Definition for tCK(avg) ......................................................................................................................................... 78
12.3.3
Definition for tCH(avg) and Tcl(avg) ..................................................................................................................... 78
12.3.4
Definition for tERR(nper) ..................................................................................................................................... 78
12.4
TIMING PARAMETERS BY SPEED GRADE ................................................................................................................................ 79
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DDR4 SDRAM
13
GDQ2BFAA
12.4.1
Timing Parameters by Speed Bin for DDR4-1600 to 2400 ................................................................................... 79
12.4.2
Timing Parameters by Speed Bin for DDR4-2666 to 3200 ................................................................................... 89
12.5
ROUNDING ALGORITHMS .................................................................................................................................................101
12.6
THE DQ INPUT RECEIVER COMPLIANCE MASK FOR VOLTAGE AND TIMING.................................................................................101
12.7
COMMAND, CONTROL, AND ADDRESS SETUP, HOLD, AND DERATING .......................................................................................106
REVISION HISTORY ................................................................................................................................................. 109
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DDR4 SDRAM
GDQ2BFAA
1 FEATURES
◆ Power supply : VDD = VDDQ = 1.2V (1.14V to 1.26V); VPP = 2.5V (2.375V to 2.75V)
◆ JEDEC standard package: x16 96-ball FBGA
◆ Array Configuration : 8 banks (x16) 2 groups of 4 banks
◆ 8n-bit prefetch architecture
◆ Burst Length (BL): 8 and 4 with Burst Chop (BC)
◆ Programmable CAS Latency (CL)
◆ Programmable CAS Write Latency (CWL)
◆ Internal generated Vref for data inputs
◆ On-Die Termination (ODT) : Support Nominal, Park and Dynamic ODT
◆ Differential clock and data strobe inputs (CK_t ,CK_c; DQS_t, DQS_c)
◆ Interface: 1.2V Pseudo Open Drain (POD) IO
◆ Per DRAM Addressability (PDA)
◆ Data Bus Inversion (DBI)
◆ Data Mask (DM) for write data
◆ Maximum Power Saving Mode (MPSM)
◆ Asynchronous reset for power up
◆ Precharge: Auto precharge option for each burst access
◆ Operating case temperature :-40°C ≤ TCase ≤95°C
◆ Support auto-refresh and self-refresh mode
◆ Average Refresh Period:
- 7.8μs at -40°C ≤ TCase ≤ 85°C
- 3.9μs at 85°C < TCase ≤ 95°C
◆ Fine granularity refresh 2x, 4x mode for smaller tRFC
◆ Programmable data strobe preambles
◆ Command Address (CA) Parity is supported
◆ Write Cyclic Redundancy Code (CRC) is supported
◆ Connectivity test mode (TEN) is supported
◆ Gear Down Mode
◆ Output driver calibration through ZQ pin (RZQ: 240ohm ± 1%)
◆ JEDEC JESD-79-4 compliant
◆ RoHS compliant
Note:
The functionality described and the timing specifications included in this datasheet are for the DLL Enabled mode of operation
(normal operation), unless specifically stated otherwise.
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DDR4 SDRAM
1.1
GDQ2BFAA
Speed Bins
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-3200
11-11-11
13-13-13
15-15-15
17-17-17
19-19-19
22-22-22
tCK (min)
1.25
1.071
0.937
0.833
0.75
0.625
ns
CAS Latency
11
13
15
17
19
22
nCK
tRCD (min)
13.75
13.92
14.06
14.16
14.25
13.75
ns
tRP (min)
13.75
13.92
14.06
14.16
14.25
13.75
ns
tRAS (min)
35
34
33
32
32
33
ns
tRC (min)
48.75
47.92
47.06
46.16
46.25
46.75
ns
Speed
1.2
Unit
Address Table
Parameter
256 Mb x16
Number of Bank Groups
2
Number of Banks per Bank Group
4
Bank Group Address
BG0
Bank Address per Bank Group
BA0~BA1
Row Address
A0~A14
Column Address
A0~A9
Page Size
2KB
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DDR4 SDRAM
GDQ2BFAA
2 ORDERING INFORMATION
2.1
G
Part Number Decoding
D
Q
2
B
F
A
A
-
C
Q
Speed Type
J: 3200 Mbps 22-22-22
Q: 2666 Mbps 19-19-19
E: 2400 Mbps 17-17-17
Operating Temperature
C: Commercial Temperature (0°C ~ 95°C)
W：Wide Temp. (-40 ~ 95°C)
Product Version
M: 1st version
A: 2nd version
Voltage
A: 1.2V
Bit Organization
F: x16
Package Type
B: 96-ball FBGA
Density
2: 4Gb
Product Type
Q: DDR4
Product Family
D: DRAM
Company
G: GigaDevice
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DDR4 SDRAM
2.2
GDQ2BFAA
Valid Part Numbers
Part Number
Organization
Data Rate
CL-tRCD-tRP
GDQ2BFAA-CE
256 Mb x 16
2400 Mbps
17-17-17
GDQ2BFAA-CQ
256 Mb x 16
2666 Mbps
19-19-19
GDQ2BFAA-CJ
256 Mb x 16
3200 Mbps
22-22-22
GDQ2BFAA-WQ
256 Mb x 16
2666 Mbps
19-19-19
GDQ2BFAA-WJ
256 Mb x 16
3200 Mbps
22-22-22
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DDR4 SDRAM
GDQ2BFAA
3 PACKAGE INFORMATION
3.1
Package 96-Ball FBGA (x16)
96*φ0.47 ± 0.05
φ0.15
CMM
φ0.05 M
BC
A
Unit mm
PIN AI INDEX
0.1
PIN AI INDEX
3 2 1
9 8 7
0.8 TYP
13 ±0.10
12CTR
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
B
0.34 ±0.10
0.8 TYP
1.2 Max
6.4 CTR
C
7.5 ±0.10
Bottom view
Side view
Top view
A
DS-00808-GDQ2BFAA-Rev1.4DS-00808-GDQ2BFAA-Rev1.4.docx
2 ±0.10
9
0.78 ±0.05
0.1
0.155 ±0.02
0.1 A
June 2022
DDR4 SDRAM
GDQ2BFAA
4 BALL ASSIGNMENTS
4.1
96-Ball FBGA (x16) ball assignments
1
2
3
4
5
6
7
8
9
A
A
VDDQ
VSSQ
DQU0
DQSU_c VSSQ
VPP
VSS
VDD
DQSU_t DQU1
VDDQ
VDD
B
B
C
C
VDDQ
DQU4
DQU2
DQU3
DQU5
VSSQ
DQU7
VSSQ
VDDQ
D
D
VDD
VSSQ
DQU6
E
E
VSS DMU_n VSSQ
DBIU_n
DML_n VSSQ
DBIL_n
VSS
VSSQ VDDQ DQSL_c
DQL1 VDDQ
ZQ
VDDQ
DQL0
DQSL_t
VDD
VSS
VDDQ
VSSQ
DQL4
DQL2
DQL3
DQL5
VSSQ
VDD
VDDQ
DQL6
DQL7
VDDQ
VDD
VSS
CKE
ODT
CK_t
CK_c
VSS
VDD
WE_n/
A14
ACT_n
CS_n
F
F
G
G
H
H
J
J
K
K
L
L
RAS_n/ VDD
A16
M
M
VREFCA BG0
A12/ CAS_n/
BC_n
A15
A10/AP
VSS
N
N
VSS
BA0
A4
A3
BA1
TEN
A0
A1
A5
ALERT_n
A7
VPP
P
P
RESET_n A6
R
R
VDD
A8
A2
A9
VSS
A11
PAR
NC
A13
VDD
2
3
7
8
9
T
T
1
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DDR4 SDRAM
4.2
GDQ2BFAA
Ball Description
Symbol
CK_t,
CK_c
Type
Input
Function
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
Clock Enable: CKE High activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power- Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE
Input
CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become
stable during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout Read and Write
accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self- Refresh.
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n
CS_n
Input
provides for external Rank selection on systems with multiple Ranks. CS_n is
considered part of the command code.
On Die Termination: ODT (registered High) enables RTT_NOM termination resistance
internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c
and DM_n/DBI_n/TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in
ODT
Input
MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU_t,
DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if MR1
is programmed to disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being entered along
ACT_n
Input
with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/ A14 will be considered as Row
Address A16, A15 and A14.
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
command being entered. These balls have multi function. For example, for activation with
RAS_n/A16,
CAS_n/A15,
Input
ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation command with
ACT_n High, those are Command pins for Read, Write and other command defined in
WE_n/A14
command truth table.
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input
data is masked when DM_n is sampled LOW coincident with that input data during a Write
access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function by Mode
DM_n, DBI_n
(DMU_n, DBIU_n
DML_n, DBIL_n)
I/O
Register A10, A11, A12 setting in MR5. For x8 device, the function of DM or TDQS is enabled
by Mode Register A11 setting in MR1. DBI_n is an input/output identifying whether to
store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after
inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported
in X8.
Bank Group Inputs: BG0-BG1 define to which bank group an Active, Read, Write or
BG0-BG1
Input
Precharge command is being applied. BG0 also determines which mode register is to be
accessed during a MRS cycle. x4/x8 have BG0 and BG1, but x16 has only BG0.
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DDR4 SDRAM
Symbol
Type
BA0-BA1
Input
GDQ2BFAA
Function
Bank Address Inputs: BA0-BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE commands and the column address
for Read/Write commands to select one location out of the memory array in the respective
A0-A16
Input
bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions,
see other rows. The address inputs also provide the op-code during Mode Register Set
commands. A17 is only defined for the x4 configuration.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
A10/AP
Input
Auto-precharge; LOW: no Auto-precharge). A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by bank addresses.
Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst
A12/BC_n
Input
chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See
“Command Truth Table” of Operation Guide for details.
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive
RESET_n
Input
when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD.
Data Input/Output: Bi-directional data bus. If CRC is enabled via mode register, then CRC
code is added at the end of Data Burst. Any DQ from DQ3~DQ0 may indicate the internal Vref
DQ
I/O
level during test via Mode Register Setting MR4 A4=High. During this mode, RTT value should
be set to Hi-Z. Refer to vendor specific data sheets to determine which DQ is used.
DQS_t,
Data Strobe: Output with Read data, input with Write data. Edge-aligned with Read data,
DQS_c,
centered-aligned with Write data. For x16, DQSL corresponds to the data on DQL0-DQL7;
DQSU_t,
DQSU_c,
DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and
I/O
DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to
DQSL_t,
provide differential pair signaling to the system during Reads and Writes. DDR4 SDRAM
DQSL_c
supports differential data strobe only and does not support single-ended.
Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled
via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
TDQS_t,
TDQS_c
Output
function on TDQS_t/TDQS_c that is applied to DQS_t/DQS_c. When disabled via mode
register A11 = 0 in MR1, DM/DBI/TDQS will provide the data mask function or Data Bus
Inversion depending on MR5; A11, A12, A10 and TDQS_c is not used. x4/ x16 DRAMs must
dis able the TDQS function via mode register A11 = 0 in MR1.
Command and Address Parity Input: DDR4 Supports Even Parity Check in DRAMs with
MR setting. Once it is enabled via Register in MR5, then DRAM calculates Parity with ACT_n,
PAR
Input
RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A0-A16. Command and address
inputs shall have parity check performed when commands are latched via the rising edge of
CK_t and when CS_n is low
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DDR4 SDRAM
Symbol
GDQ2BFAA
Type
Function
ALERT: It has multi functions such as CRC error flag, Command and Address Parity error flag
as output signal. If there is error in CRC, then Alert_n goes LOW for the period time interval
and goes back HIGH. If there is error in Command Address Parity Check, then ALERT_n goes
ALERT_n
I/O
LOW for relatively long period until on going DRAM internal recovery transaction to complete.
During Connectivity Test mode, this pin works as an input. Using this signal or not is dependent
on system. In case of not connected as Signal, ALERT_n pin must be bounded to VDD on
board.
Connectivity Test Mode Enable: Required on X16 devices and optional input on x4/x8 with
densities equal to or greater than 8Gb. High in this pin will enable Connectivity Test Mode
TEN
Input
operation along with other pins. It is a CMOS rail to rail signal with AC high and low at 80%
and 20% of VDD. Using this signal or not is dependent on system. This pin may be DRAM
internally pulled low through a weak pull-down resistor to VSS.
NC
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.2 V +/- 0.06 V
VSS
Supply
Ground
VPP
Supply
DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max)
VREFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference Pin for ZQ calibration
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DDR4 SDRAM
GDQ2BFAA
5 Functional Block Diagram
DDR4 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 16-bank (4-banks per
Bank Group) DRAM.
Figure 5-1. 256 Meg x 16 Functional Block Diagram
CRC and
parity control
ODT
To ODT/output drivers
ZQ CAL
RESET_n
PAR
TEN
ODT
control
Bank 3
Bank 2
Bank 1
Bank 0
BG1
2(A12,A10)
CS_n
Command decode
RAS_n, CAS_n,WE_n
ACT_n
Mode registers
15
Refresh
counter
15
Rowaddress
MUX
15
2
BG
and
BA
control
logic
1
A[16:0]
BA[1:0]
BG[0]
20
Address
register
2
1
4
16
RTTN RTTW
(0...15)
DQ[15:0]
Read
drivers
LDQS_t/LDQS_c; UDQS_t/UDQS_c
DQ[7:0]
DQ[15:8]
VDDQ
128
128
READ
FIFO
and data
MUX
BC4
CK_t,CK_c
Global
I/O gating
DBI
RTTP
RTTN RTTW
CRC
16
LDQS_t/
LDQS_c
Write
drivers
and Input
logic
UDQS_t/
UDQS_c
VDDQ
128
8
10
RTTP
DLL
Columns
0,1,and 2
OTF
I/O gating
DM mask logic
ZQ
VDDQ
CK_t,CK_c
BC4
8192
16384
4
Column
address
counter/
latch
Bank 3
Bank 2
Bank 1
Bank 0
Bank Group 1
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank
Bank
Bank 00 Sense amplifiers
Bank 0
0
Bank
BG2
Bank Group
Group 20
BG0
RowMemory array
address
32,768(32,768 x 128 x 128)
latch 32,768
and
Sense amplifiers
decoder
3(A16,A15,A14)
20
ZQ
control
To ZQ Control
VrefDQ
BC4
OTF
CRC
Parity
Control
logic
CKE
CK_t,CK_c
ALERT
VDDQ
7
128
128
x64
x128
Column 2
(BC4 nlbble)
3
Columns 0,1,and 2
DS-00808-GDQ2BFAA-Rev1.4DS-00808-GDQ2BFAA-Rev1.4.docx
RTTP
Data
Interface
Column
decoder
VrefDQ
RTTN RTTW
LDBI_n/
LDM_n
UDBI_n/
UDM_n
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June 2022
DDR4 SDRAM
GDQ2BFAA
6 ABSOLUTE MAXIMUM RATINGS
6.1
Absolute Maximum DC Ratings
Table 6-1. Absolute Maximum DC Ratings
Symbol
Parameter
Min
Max
Unit
Note
VDD
Voltage on VDD pin relative to Vss
-0.3
1.5
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
-0.3
1.5
V
1,3
VPP
Voltage on VPP pin relative to Vss
-0.3
3.0
V
4
VIN, VOUT
Voltage on any pin except VrefCA relative to Vss
-0.3
1.5
V
1,3,5
TSTG
Storage Temperature
-55
100
°C
1,2
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When
VDD and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV.
4. VPP must be equal or greater than VDD/VDDQ at all times.
5. Overshoot area above 1.5V is specified in Section 7.3.5 and Section 7.3.6.
6.2
Recommended DC Operating Conditions
Table 6-2. Recommended DC Operating Conditions
Symbol
Parameter
VDD
Ratings
Unit
Note
1.26
V
1,2,3
1.2
1.26
V
1,2,3
2.5
2.75
V
3
Min
Typ.
Max
Supply voltage
1.14
1.2
VDDQ
Supply voltage for output
1.14
VPP
Wordline supply voltage
2.375
Note:
1.
Under all conditions VDDQ must be less than or equal to VDD.
2.
VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3.
DC bandwidth is limited to 20MHz.
6.3
DRAM Component Operating Temperature Range
Table 6-3. Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Unit
Note
Normal Temperature Range
-40~85
°C
1,2
Extended Temperature Range
85~95
°C
1,3
Note:
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement
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DDR4 SDRAM
GDQ2BFAA
conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation,
the DRAM case temperature must be maintained between 0 - 85°C under all operating conditions for the commercial offering;
The industrial and automotive temperature offerings allow the case temperature to go below 0°C to -40°C.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case
temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
•
Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs. It is also possible
to specify a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature Range. Please refer to the DIMM SPD
for option availability.
•
If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0 and MR2 A7 = 1)
the Manual
or enable the optional
Auto Self-Refresh mode (MR2 A6 = 1 and MR2 A7 = 1).
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DDR4 SDRAM
GDQ2BFAA
7 AC AND DC INPUT MEASUREMENT LEVELS
7.1
AC and DC Logic Input Levels for Single-ended Signals
Table 7-1. Single-ended AC and DC Input Levels for Command and Address
1600/1866/2133/2400
Symbol
2666/3200
Parameter
Unit
Min
VREFCA +
Max
Min
Max
VDD
-
-
V
-
-
V
VDD
V
Note
VIH.CA(DC75)
DC input logic high
VIL.CA(DC75)
DC input logic low
VSS
VIH.CA(DC65)
DC input logic high
-
-
VIL.CA(DC65)
DC input logic low
-
-
VSS
VIH.CA(AC100)
AC input logic high
VREF + 0.1
Note 2
-
-
V
1
VIL.CA(AC100)
AC input logic low
Note 2
VREF - 0.1
-
-
V
1
VIH.CA(AC90)
AC input logic high
-
-
Note 2
V
1
VIL.CA(AC90)
AC input logic low
-
-
Note 2
VREF - 0.09
V
1
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
2,3
VREFCA(DC)
Reference voltage for
ADD, CMD inputs
0.075
VREFCA 0.075
VREFCA +
0.065
VREF +
0.09
VREFCA 0.065
V
Note:
1.
See “Overshoot and Undershoot Specifications”
2.
The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1%VDD (for reference:
approx. ± 12mV)
3.
For reference: approx. VDD/2 ± 12 mV
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DDR4 SDRAM
7.2
GDQ2BFAA
AC and DC Logic Input Measurement Levels: Vref Tolerances
The DC-tolerance limits and AC-noise limits for the reference voltages VrefCA is illustrated in the Figure 7-1 below. It shows a
valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA).
Vref(DC) is the linear average of Vref(t) over a very long period of time (for example, 1 second). This average has to meet the
min/max requirement in Figure 7-1. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ± 1% VDD
Voltage
VDD
Vref(t)
Vref AC-noise
Vref(DC)max
Vref(DC)
VDD/2
Vref(DC)min
VSS
Time
Figure 7-1. Illustration of Vref(DC) Tolerance and Vref AC-noise Limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on Vref.
“Vref” should be understood as Vref(DC)
This clarifies that DC-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level, and
therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for Vref(DC)
deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with
Vref AC-noise. Timing and voltage effects due to AC-noise on Vref up to the specified limit (± 1% of VDD) are included in DRAM
timings and their associated deratings.
7.3
AC and DC Logic Input Levels for Differential Signals
Differential Input Voltage(CK_t, CK_c)
7.3.1
AC and DC Logic Input Levels for Differential Signals
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
half cycle
0.0
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
Time
Figure 7-2. Definition of Differential AC-Swing and “Time above AC-Level” tDVAC
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DDR4 SDRAM
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Note:
1.
Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2.
Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
7.3.2
Differential Swing Requirements for Clock (CK_t - CK_c)
Table 7-2. Differential Input Levels Requirements for CK_t - CK_c
1600/1866/2133
Symbol
VIHdiff
VILdiff
VIHdiff(AC)
VILdiff(AC)
2400/2666
3200
Parameter
differential
input high
differential
input low
differential
input high ad
differential
input low ac
Unit
Note
Note 3
V
1
- 0.110
V
1
Note 3
V
2
V
2
Min
Max
Min
Max
Min
Max
+ 0.150
Note 3
+ 0.135
Note 3
+ 0.110
Note 3
- 0.150
Note 3
- 0.135
Note 3
Note 3
(VIH(AC) -
Note 3
(VIH(AC)
2x
2x
(VIH(AC) VREF
VREF
2x
Note 3
2x
(VIL(AC) -
- VREF
2x
Note 3
VREF
(VIL(AC) VREF
2x
Note 3
(VIL(AC) VREF
Note:
1. Used to define a differential signal slew-rate.
2. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIH.CA(DC)
max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.
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DDR4 SDRAM
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Table 7-3. Allowed Time before Ringback (tDVAC) for CK_t - CK_c
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = TBDmV
Min
Max
Min
Max
> 4.0
120
-
TBD
-
4.0
115
-
TBD
-
3.0
110
-
TBD
-
2.0
105
-
TBD
-
1.8
100
-
TBD
-
1.6
95
-
TBD
-
1.4
90
-
TBD
-
1.2
85
-
TBD
-
1.0
80
-
TBD
-
VDD/2 + 145 mV
Differential Input Cross
VIX(CK)
Point Voltage relative to
VDD/2 for CK_t, CK_c
VDD/2 + 100mV ≤ VSEH ≤
VDD/2 + 145 mV
VDD/2 - 145 mV ≤ VSEL ≤
VDD/2 – 100 mV
VSEL < VDD/2 - 145mV
Min
Max
N/A
120mV
N/A
(VSEH-VDD/2) – 25mV
- (VDD/2-VSEL) + 25mV
N/A
-120mV
N/A
Table 7-10. Cross Point Voltage for CK Differential Input Signals at DDR4-2666
Symbol
Parameter
DDR4 – 2666/3200
Input Level
VSEH > VDD/2 + 145 mV
Differential Input Cross
VIX(CK)
Point Voltage relative to
VDD/2 for CK_t, CK_c
VDD/2 + 90mV ≤ VSEH ≤
VDD/2 + 145 mV
VDD/2 - 145 mV ≤ VSEL ≤
VDD/2 – 90 mV
VSEL < VDD/2 - 145mV
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26
Min
Max
N/A
110mV
N/A
(VSEH-VDD/2) – 30mV
- (VDD/2-VSEL) + 30mV
N/A
-110mV
N/A
June 2022
DDR4 SDRAM
7.6
GDQ2BFAA
CMOS Rail to Rail Input Levels for RESET_n
Table 7-11. CMOS Rail to Rail Input Levels for RESET_n
Parameter
Symbol
Min
Max
Unit
Note
AC Input High Voltage
VIH(AC)_RESET
0.8*VDD
VDD
V
6
DC Input High Voltage
VIH(DC)_RESET
0.7*VDD
VDD
V
2
AC Input Low Voltage
VIL(AC)_RESET
VSS
0.2VDD
V
7
DC Input Low Voltage
VIL(DC)_RESET
VSS
0.3VDD
V
1
Rising Time
TR_RESET
-
1.0
μs
4
RESET Pulse Width
tPW_RESET
1.0
-
μs
3,5
Note:
1.
After RESET_n is registered Low, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_
RESET, otherwise, SDRAM may not be reset.
2.
Once RESET_n is registered High, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM
operation will not be guaranteed until it is reset asserting RESET_n signal Low.
3.
RESET is destructive to data contents.
4.
No slope reversal (ringback) requirement during its level transition from Low to High.
5.
This definition is applied only “Reset Procedure at Power Stable”.
6.
Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
7.
Undershoot might occur. It should be limited by Absolute Maximum DC Ratings.
tPW_RESET
0.8*VDD
0.7*VDD
0.3*VDD
0.2*VDD
TR_RESET
Figure 7-10. RESET_n Input Slew Rate Definition
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DDR4 SDRAM
7.7
GDQ2BFAA
AC&DC Logic Input Levels for DQS Signals
Differential Signal Definition
Differential Input Voltage: DQS_t, DQS_c
7.7.1
VIHDiffPeak
0.0
Half cycle
VILDiffPeak
Time
Figure 7-11 DQS Differential Input Signal AC-swing Level
7.7.2
Differential Swing Requirements for DQS (DQS_t – DQS_c)
Table 7-12. Differential Input Swing Requirements for DQS
1600/1866/2133
Symbol
2400
2666
3200
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Note
VIHDiffPeak
VIH.DIFF.Peak Voltage
186
Note2
160
Note2
150
Note2
140
Note2
mV
1
VILDiffPeak
VIL.DIFF.Peak Voltage
Note2
-186
Note2
-160
Note2
-150
Note2
-140
mV
1
Note:
1.
Used to define a differential signal slew-rate.
2.
These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits of
Overshoot, Undershoot Specification for single-ended signals.
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DDR4 SDRAM
7.7.3
GDQ2BFAA
Peak Voltage Calculation Method
The peak voltage of Differential DQS signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS_t - VDQS_c
The Max(f(t)) or Min(f(t)) used to determine the midpoint which to reference the +/-35% window of the exempt non-monotonic
Single Ended Input Voltage: DQS_t and DQS_c
signaling shall be the smallest peak voltage observed in all UI’s.
DQS_t
Max (f(t))
DQS_c
+35%
+50%
+35%
+50%
Min (f(t))
Time
Figure 7-12. Definition of Differential DQS Peak Voltage and Range of Exempt Nonmonotonic Signaling
7.7.4
Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of
differential input signals (DQS_t, DQS_c) must meet the requirements in Table 7-13. The differential input cross point voltage
VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c relative to the VDQSmid
of the DQS_t and DQS_c signals.
VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by
VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS
signals and the highest horizontal tangent below VDQSmid of the transitioning DQS signals.
A nonmonotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provided the said ledge
occurs within +/- 35% of the midpoint of either VIH.DIFF. Peak Voltage (DQS_t rising) or VIL.DIFF.Peak Voltage (DQS_c rising),
refer to Figure 7-12. A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a
horizontal tangent. That is, a falling transition’s horizontal tangent is derived from its negative slope to zero slope transition (point
A in Figure 7-13) and a ring-back’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure
7-13) is not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope to zero slope
transition (point C in Figure 7-13) and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition
(point D in Figure 7-13) is not a valid horizontal tangent.
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GDQ2BFAA
Lowest horizontal tangent above VDQSmid of the transitioning signals
D
VIX_DQS,FR
VIX_DQS,RF
VDQSmid
VIX_DQS,RF
VIX_DQS,FR
B
DQS_c
VDQS_trans
C
DQS_t
VDQS_trans2
DQS_t and DQS_c: Single-ended Input Voltage
DDR4 SDRAM
A
Lowest horizontal tangent below VDQSmid of the transitioning signals
VSSQ
Time
Figure 7-13. Vix Definition (DQS)
Table 7-13. Cross Point Voltage for DQS Differential Input Signals
1600/1866/2133/2400/2666/3200
Symbol
Vix_DQS_ratio
VDQSmid_to_Vcent
Parameter
DQS Differential input crosspoint voltage ratio
VDQSmid offset relative to
Vcent_DQ(midpoint)
Unit
Note
25
%
1,2
min(VIHdiff,50)
mV
3,4,5
Min
Max
-
Note:
1. Vix_DQS_Ratio is DQS Vix crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the difference
between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest horizontal tangent
below VDQSmid of the transitioning DQS signals.
2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs drivers and
paths are matched.
3. The maximum limit shall not exceed the smaller of VIHdiff minimum limit or 50mV.
4. Vix measurements are only applicable for transitioning DQS_t and DQS_c signals when toggling data, preamble and high-z
states are not applicable conditions.
5
The parameter VDQSmid is defined for simulation and ATE testing purposes, it is not expected to be tested in a system.
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DDR4 SDRAM
7.7.5
GDQ2BFAA
Differential Input Slew Rate Definition
Differential Input Voltage: DQS_t, DQS_c
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure 7-14 and Table 7-14.
VIHDiffPeak
VIHDiff_DQS
0.0
VILDiff_DQS
VILDiffPeak
Delta TRdiff
Delta TFdiff
Time
Figure 7-14. Differential Input Slew Rate Definition for DQS_t, DQS_c
Note:
1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.
2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.
Table 7-14. Differential Input Slew Rate Definition for DQS_t, DQS_c
Description
Differential input slew rate for rising
edge(DQS_t – DQS_c)
Differential input slew rate for falling
edge(DQS_t – DQS_c)
From
To
Defined by
VILdiff_DQS
VIHdiff_DQS
|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff
VIHdiff_DQS
VILdiff_DQS
|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff
Table 7-15. Differential Input Level for DQS_t, DQS_c
1600/1866/2133
Symbol
2400/2666
Parameter
Unit
Min
Max
Min
Max
VIHdiff_DQS
DC input logic high
136
-
130
-
mV
VILdiff_DQS
DC input logic low
-
-136
-
-130
mV
Table 7-16. Differential Input Slew Rate for DQS_t, DQS_c
1600/1866/2133/2400
Symbol
SRIdiff
2666/3200
Parameter
Differential input slew rate
DS-00808-GDQ2BFAA-Rev1.4DS-00808-GDQ2BFAA-Rev1.4.docx
Unit
Min
Max
Min
Max
3
18
2.5
18
31
V/ns
June 2022
DDR4 SDRAM
GDQ2BFAA
8 AC&DC OUTPUT MEASUREMENT LEVELS
8.1
Output Driver DC Electronic Characteristics
The DDR4 driver supports two different RON values. These RON values are referred as strong (low RON) and weak mode (high
RON). A functional representation of the output buffer is shown in Figure 8-1 below. Output driver impedance RON is defined as
the individual pull-up and pull- down resistors (RONPu and RONPd).
RONPu=
RONPd=
VDDQ-Vout
under the condition that RONPd is off
| Iout |
Vout
under the condition that RONPu is off.
| Iout |
Chip In Drive Mode
Output Drive
VDDQ
IPu
To
other
circuity
like
RCV, ...
RONPu
DQ
RONPd
IPd
Iout
Vout
VSSQ
Figure 8-1. Output Driver
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Table 8-1. Output Driver DC Electronical Characteristics, Assuming RZQ = 240ohm; Entire Operating Temperature
Range; after Proper ZQ Calibration
RONNOM
Resistor
RON34Pd
34Ω
RON34Pu
RON48Pd
48Ω
RON48Pu
Mismatch between pull-up and
pull-down, MMPuPd
Mismatch DQ-DQ within byte
variation pull-up, MMPudd
Mismatch DQ-DQ within byte
variation pull-up, MMPddd
Vout
Min
Nom
Max
Unit
Note
VOLdc=0.5*VDDQ
0.73
1.0
1.1
RZQ/7
1,2
VOMdc=0.8*VDDQ
0.83
1.0
1.1
RZQ/7
1,2
VOHdc=1.1*VDDQ
0.83
1.0
1.25
RZQ/7
1,2
VOLdc=0.5*VDDQ
0.9
1.0
1.25
RZQ/7
1,2
VOMdc=0.8*VDDQ
0.9
1.0
1.1
RZQ/7
1,2
VOHdc=1.1*VDDQ
0.8
1.0
1.1
RZQ/7
1,2
VOLdc=0.5*VDDQ
0.73
1.0
1.1
RZQ/5
1,2
VOMdc=0.8*VDDQ
0.83
1.0
1.1
RZQ/5
1,2
VOHdc=1.1*VDDQ
0.83
1.0
1.25
RZQ/5
1,2
VOLdc=0.5*VDDQ
0.9
1.0
1.25
RZQ/5
1,2
VOMdc=0.8*VDDQ
0.9
1.0
1.1
RZQ/5
1,2
VOHdc=1.1*VDDQ
0.8
1.0
1.1
RZQ/5
1,2
VOMdc=0.8*VDDQ
-10
17
%
1,2,3,4
VOMdc=0.8*VDDQ
10
%
1,2,4
VOMdc=0.8*VDDQ
10
%
1,2,4
Note:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits
if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity (TBD).
2. Pull-up and pull-dn output driver impedances are recommended to be calibrated at 0.8*VDDQ. Other calibration schemes may
be used to achieve the linearity spec shown above, e.g. calibration at 0.5*VDDQ and 1.1*VDDQ.
3. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPD both at
0.8*VDD separately; RONnom is the nominal RON value.
4. MMPuPdd =[(RONPu–RONPd/RONNOM)] * 100
5. RON variance range ratio to RON Nominal value in a given component, including DQS_t and DQS_c.
6.
MMPuPdd =[(RONPuMax–RONPuMin/RONNOM)] * 100
7.
MMPdPdd =[(RONPdMax–RONPdMin/RONNOM)] * 100
8.
This parameter of x16 device is specified for Upper byte and Lower byte.
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DDR4 SDRAM
8.1.1
GDQ2BFAA
Alert_n Output Driver Characteristic
A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:
RONPd=
Vout
under the condition that RONPu is off.
| Iout |
Alert Driver
DRAM
Alert
RONPd
IPd
Iout
Vout
VSSQ
Resister
RONPd
Vout
Min
Max
Unit
Note
VOLdc=0.1*VDDQ
0.3
1.2
34Ω
1
VOMdc=0.8*VDDQ
0.4
1.2
34Ω
1
VOHdc=1.1*VDDQ
0.4
1.4
34Ω
1
Note:
VDDQ voltage is at VDDQ DC. VDDQ DC definition is TBD.
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DDR4 SDRAM
GDQ2BFAA
Output Driver Characteristic of Connectivity Test (CT) Mode
8.1.2
Following output driver impedance RON will be applied Test Output Pin during Connectivity Test (CT) Mode. The individual pullup and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows:
RONPu_CT =
VDDQ-Vout
| Iout |
RONPd_CT =
Vout
| Iout |
Chip In Drive Mode
Output Drive
VDDQ
Ipu_CT
To
other
circuity
like
RCV, ...
RONPu_CT
DQ
RONPd_CT
Iout
Ipd_CT
Vout
VSSQ
RONNOM_CT
Vout
Max
Unit
VOBdc=0.2*VDDQ
1.9
34Ω
VOLdc=0.5*VDDQ
2.0
34Ω
VOMdc=0.8*VDDQ
2.2
34Ω
VOHdc=1.1*VDDQ
2.5
34Ω
VOBdc=0.2*VDDQ
2.5
34Ω
VOLdc=0.5*VDDQ
2.2
34Ω
VOMdc=0.8*VDDQ
2.0
34Ω
VOHdc=1.1*VDDQ
1.9
34Ω
Resister
RONPd_CT
34Ω
RONPu_CT
Note:
Connectivity test mode uses un-calibrated drivers, showing the full range over PVT. No mismatch between pull up and pull down
is defined.
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DDR4 SDRAM
8.2
GDQ2BFAA
Single-ended AC& DC Output Levels
Table 8-2. Single-ended AC&DC Output Levels
Symbol
Parameter
DDR4-1600 to DDR4-3200
Unit
VOH(DC)
DC output high measurement level (for IV curve linearity)
1.1 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
(0.7+0.15) x VDDQ
V
VOL(AC)
AC output low measurement level (for output SR)
(0.7-0.15) x VDDQ
V
Note:
The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver
impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ.
8.3
Differential AC&DC Output Levels
Table 8-3. Differential AC&DC Output Levels
Symbol
Parameter
DDR4-1600 to DDR4-3200
Unit
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+ 0.3 x VDDQ
V
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.3 x VDDQ
V
Note:
The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver
impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the differential outputs.
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DDR4 SDRAM
GDQ2BFAA
Single-ended Output Slew Rate
8.4
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between
VOL(AC) and VOH(AC) for single ended signals as shown in Table 8-4 and Figure 8-2.
Table 8-4. Single-ended Output Slew Rate Definition
Measured
Description
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)- VOL(AC)]/Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)- VOL(AC)]/Delta TFse
Note:
Output slew rate is verified by designed and characterization, and may not be subject to production test.
VOH(AC)
VOL(AC)
delta TFse
delta TRse
Figure 8-2. Single-ended Output Slew Rate Definition
Table 8-5. Single-ended Output Slew Rate
Parameter
Symbol
Single ended output slew rate
SRQse
DDR4-1600 to DDR4-3200
Min
Max
4
9
Unit
V/ns
Description:
SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Singnals; For RON =
RZQ/7 setting
Note:
In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.
•
Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
•
Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e.
from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 9 V/ns applies).
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DDR4 SDRAM
8.5
GDQ2BFAA
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between
VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 8-6 and Figure 8-3.
Table 8-6. Differential Output Slew Rate Definition
Measured
Description
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC)- VOLdiff(AC)]/Delta TRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC)- VOLdiff(AC)]/Delta TFdiff
Note:
Output slew rate is verified by design and characterization, and may not be subject to production test.
VOHdiff(AC)
VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 8-3. Differential Output Slew Rate Definition
Table 8-7. Differential Output Slew Rate
Parameter
Symbol
Differential output slew rate
SRQdiff
DDR4-1600 to DDR4-3200
Min
Max
8
18
Unit
V/ns
Description:
SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-Output);
Diff: Differential Singnals; For RON = RZQ/7 setting
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DDR4 SDRAM
8.6
GDQ2BFAA
Single-ended AC& DC Output Levels of Connectivity Test Mode
Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.
Table 8-8. Single-ended AC&DC Output Level of Connectivity Test Mode
Symbol
Parameter
DDR4-1600 to DDR4-3200
Unit
Note
VOH(DC)
DC output high measurement level (for IV curve linearity)
1.1 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOB(DC)
DC output below measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR )
VTT + (0.1 x VDDQ)
V
1
VOL(AC)
AC output below measurement level (for output SR)
VTT - (0.1 x VDDQ)
V
1
Note:
The effective test load is 50Ω terminated by VTT = 0.5*VDDQ.
VOH(AC)
VTT
0.5*VDDQ
VOL(AC)
TR_output_CT
TR_output_CT
Figure 8-4. Output Slew Rate Definition of Connectivity Test Mode
Table 8-9. Single-ended Output Slew Rate of Connectivity Test Mode
8.7
Parameter
Symbol
Output signal Falling time
Output signal Rising time
DDR4-1600 to DDR4-3200
Unit
Min
Max
TF_output_CT
-
10
ns/V
TR_output_CT
-
10
ns/V
Reference Load for Connectivity Test Mode Timing
The reference load for ODT timings is defined in Figure 8-5.
DQ,DM
DQSL_t,DQSL_c
DQSU_t,DQSU_c
DQS_t,DQS_c
CT_INPUTS
DUT
0.5*VDDQ
Rterm=50 ohm
VSSD
Timing Reference Points
Figure 8-5. Connectivity Test Mode Timing Reference Load
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DDR4 SDRAM
GDQ2BFAA
9 SPEED BIN
9.1
DDR4-1600 Speed Bins and Operations
Table 9-1. DDR4-1600 Speed Bins and Operations
Speed Bin
DDR4-1600
CL-nRCD-nRP
11-11-11
Parameter
Symbol
Internal Read command to first data
Internal Read command to first data with
Read DBI enabled
ACT to internal Read or write delay time
PRE command period
Normal
CWL = 9
CWL = 9,11
CL = 9
ns
11
tAA(max) + 2nCK
ns
11
-
ns
11
-
ns
11
9 x tREFI
ns
11
-
ns
11
1.6
ns
1,2,3,4,10,13
(13.50)5,11
tAA(min) + 2nCK
13.7513
tRCD
(13.50)5,11
13.75
(13.50)5,11
tRAS
ACT to ACT or REF command period
18
Max
13.7513
tRP
ACT to PRE command period
Note
Min
tAA
tAA_DBI
Unit
35
48.75
tRC
(48.50)5,11
Read DBI
CL = 11
(Optional)5
1.5
tCK(AVG)
(Optional)5
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4,10
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 11
CL = 13
tCK(AVG)
1.25
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