GigaDevice Semiconductor Inc.
GD32F305xx
ARM® Cortex®-M4 32-bit MCU
Datasheet
GD32F305xx Datasheet
Table of Contents
Table of Contents ........................................................................................................... 1
List of Figures ................................................................................................................ 4
List of Tables .................................................................................................................. 5
1. General description ................................................................................................. 7
2. Device overview ....................................................................................................... 8
2.1.
Device information ...................................................................................................... 8
2.2.
Block diagram .............................................................................................................. 9
2.3.
Pinouts and pin assignment ..................................................................................... 10
2.4.
Memory map .............................................................................................................. 13
2.5.
Clock tree ................................................................................................................... 17
2.6. Pin definitions ............................................................................................................ 18
2.6.1. GD32F305Zx LQFP144 pin definitions.................................................................. 18
2.6.2. GD32F305Vx LQFP100 pin definitions ................................................................. 27
2.6.3. GD32F305Rx LQFP64 pin definitions ................................................................... 34
3. Functional description .......................................................................................... 38
3.1.
ARM® Cortex®-M4 core .............................................................................................. 38
3.2.
On-chip memory ........................................................................................................ 38
3.3.
Clock, reset and supply management ...................................................................... 39
3.4.
Boot modes ................................................................................................................ 39
3.5.
Power saving modes ................................................................................................. 40
3.6.
Analog to digital converter (ADC) ............................................................................ 40
3.7.
Digital to analog converter (DAC) ............................................................................. 41
3.8.
DMA ............................................................................................................................ 41
3.9.
General-purpose inputs/outputs (GPIOs) ................................................................ 41
3.10.
Timers and PWM generation ................................................................................. 42
3.11.
Real time clock (RTC) ............................................................................................ 43
3.12.
Inter-integrated circuit (I2C) .................................................................................. 43
3.13.
Serial peripheral interface (SPI) ............................................................................ 43
3.14.
Universal synchronous asynchronous receiver transmitter (USART) ............... 44
3.15.
Inter-IC sound (I2S) ................................................................................................ 44
1
GD32F305xx Datasheet
3.16.
Universal serial bus full-speed interface (USBFS) ............................................... 44
3.17.
Controller area network (CAN) .............................................................................. 45
3.18.
External memory controller (EXMC) ..................................................................... 45
3.19.
Debug mode ........................................................................................................... 45
3.20.
Package and operation temperature ..................................................................... 46
4. Electrical characteristics ....................................................................................... 47
4.1.
Absolute maximum ratings ....................................................................................... 47
4.2.
Operating conditions characteristics ....................................................................... 47
4.3.
Power consumption .................................................................................................. 49
4.4.
EMC characteristics .................................................................................................. 56
4.5.
Power supply supervisor characteristics ................................................................ 56
4.6.
Electrical sensitivity .................................................................................................. 57
4.7.
External clock characteristics .................................................................................. 58
4.8.
Internal clock characteristics ................................................................................... 60
4.9.
PLL characteristics.................................................................................................... 61
4.10.
Memory characteristics ......................................................................................... 63
4.11.
NRST pin characteristics ....................................................................................... 63
4.12.
GPIO characteristics .............................................................................................. 64
4.13.
ADC characteristics ............................................................................................... 65
4.14.
Temperature sensor characteristics ..................................................................... 67
4.15.
DAC characteristics ............................................................................................... 67
4.16.
I2C characteristics ................................................................................................. 69
4.17.
SPI characteristics ................................................................................................. 69
4.18.
I2S characteristics.................................................................................................. 70
4.19.
USART characteristics ........................................................................................... 70
4.20.
CAN characteristics ............................................................................................... 71
4.21.
USBFS characteristics ........................................................................................... 71
4.22.
EXMC characteristics............................................................................................. 72
4.23.
TIMER characteristics ............................................................................................ 76
4.24.
WDGT characteristics ............................................................................................ 76
4.25.
Parameter conditions............................................................................................. 76
5. Package information.............................................................................................. 77
2
GD32F305xx Datasheet
5.1.
LQFP144 package outline dimensions..................................................................... 77
5.2.
LQFP100 package outline dimensions..................................................................... 78
5.3.
LQFP64 package outline dimensions....................................................................... 79
6. Ordering information ............................................................................................. 80
5. Revision history ..................................................................................................... 81
3
GD32F305xx Datasheet
List of Figures
Figure 2-1. GD32F305xx block diagram ............................................................................................................... 9
Figure 2-2. GD32F305Zx LQFP144 pinouts ....................................................................................................... 10
Figure 2-3. GD32F305Vx LQFP100 pinouts ....................................................................................................... 11
Figure 2-4. GD32F305Rx LQFP64 pinouts ......................................................................................................... 12
Figure 2-5. GD32F305xx clock tree ..................................................................................................................... 17
Figure 4-1. Recommended power supply decoupling capacitors (1) (2) ....................................................... 48
Figure 4-2. Typical supply current consumption in Run mode ................................................................... 54
Figure 4-3. Typical supply current consumption in Sleep mode ................................................................ 54
Figure 4-4. Recommended external NRST pin circuit .................................................................................... 64
Figure 4-5. I/O port AC characteristics definition ............................................................................................ 65
Figure 4-6. USBFS timings: definition of data signal rise and fall time ..................................................... 72
Figure 5-1. LQFP144 package outline ................................................................................................................ 77
Figure 5-2. LQFP100 package outline ................................................................................................................ 78
Figure 5-3. LQFP64 package outline .................................................................................................................. 79
4
GD32F305xx Datasheet
List of Tables
Table 2-1. GD32F305xx devices features and peripheral list ......................................................................... 8
Table 2-2. GD32F305xx memory map ................................................................................................................. 13
Table 2-3. GD32F305Zx LQFP144 pin definitions ............................................................................................ 18
Table 2-4. GD32F305Vx LQFP100 pin definitions ............................................................................................ 27
Table 2-5. GD32F305Rx LQFP64 pin definitions.............................................................................................. 34
Table 4-1. Absolute maximum ratings (1)(4) ........................................................................................................ 47
Table 4-2. DC operating conditions .................................................................................................................... 47
Table 4-3. Clock frequency(1) ................................................................................................................................ 48
Table 4-4. Operating conditions at Power up/ Power down (1) ...................................................................... 48
Table 4-5. Start-up timings of Operating conditions (1)(2)(3) ............................................................................. 48
Table 4-6. Power saving mode wakeup timings characteristics(1) (2) .......................................................... 48
Table 4-7. Power consumption characteristics (2)(3)(4)(5) .................................................................................. 49
Table 4-8. Peripheral current consumption characteristics(1) ...................................................................... 55
Table 4-9. EMS characteristics(1) ......................................................................................................................... 56
Table 4-10. Power supply supervisor characteristics .................................................................................... 56
Table 4-11. ESD characteristics(1) ........................................................................................................................ 57
Table 4-12. Static latch-up characteristics(1)..................................................................................................... 58
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics .. 58
Table 4-14. High speed external clock characteristics (HXTAL in bypass mode) .................................. 58
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ... 59
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode) .......................... 59
Table 4-17. High speed internal clock (IRC8M) characteristics ................................................................... 60
Table 4-18. Low speed internal clock (IRC40K) characteristics .................................................................. 60
Table 4-19. High speed internal clock (IRC48M) characteristics ................................................................. 61
Table 4-20. PLL characteristics............................................................................................................................ 61
Table 4-21. PLL1 characteristics ......................................................................................................................... 62
Table 4-22. PLL2 characteristics ......................................................................................................................... 62
Table 4-23. Flash memory characteristics ........................................................................................................ 63
Table 4-24. NRST pin characteristics ................................................................................................................. 63
Table 4-25. I/O port DC characteristics(1) (3) ....................................................................................................... 64
Table 4-26. I/O port AC characteristics(1)(2) ........................................................................................................ 65
Table 4-27. ADC characteristics .......................................................................................................................... 65
Table 4-28. ADC RAIN max for fADC = 40 MHz ......................................................................................................... 66
Table 4-29. ADC dynamic accuracy at fADC = 14 MHz(1) .................................................................................. 66
Table 4-30. ADC dynamic accuracy at fADC = 40 MHz(1) .................................................................................. 67
Table 4-31. ADC static accuracy at fADC = 14 MHz(1) ........................................................................................ 67
Table 4-32. Temperature sensor characteristics(1) .......................................................................................... 67
Table 4-33. DAC characteristics .......................................................................................................................... 67
Table 4-34. I2C characteristics(1)(2)....................................................................................................................... 69
Table 4-35. Standard SPI characteristics(1) ....................................................................................................... 69
5
GD32F305xx Datasheet
Table 4-36. I2S characteristics(1) (2) ...................................................................................................................... 70
Table 4-37. USART characteristics(1) .................................................................................................................. 70
Table 4-38. USBFS start up time .......................................................................................................................... 71
Table 4-39. USBFS DC electrical characteristics ............................................................................................ 71
Table 4-40. USBFS full speed-electrical characteristics(1) ............................................................................ 71
Table 4-41. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)(3)(4) ........................ 72
Table 4-42. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)(3)(4) ....................... 72
Table 4-43. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)(3)(4) ............................................. 73
Table 4-44. Asynchronous multiplexed PSRAM/NOR write timings
Table 4-45. Synchronous multiplexed PSRAM/NOR read timings
Table 4-46. Synchronous multiplexed PSRAM write timings
(1)(2)(3)(4)
(1)(2)(3)(4)
(1)(2)(3)(4)
............................................. 73
................................................ 74
......................................................... 74
Table 4-47. Synchronous non-multiplexed PSRAM/NOR read timings (1)(2)(3)(4) ....................................... 75
Table 4-48. Synchronous non-multiplexed PSRAM write timings (1)(2)(3)(4) ................................................ 75
Table 4-49. TIMER characteristics(1).................................................................................................................... 76
Table 4-50. FWDGT min/max timeout period at 40 kHz (IRC40K)(1) ............................................................ 76
Table 4-51. WWDGT min-max timeout value at 60 MHz (fPCLK1)(1) ................................................................ 76
Table 5-1. LQFP144 package dimensions ......................................................................................................... 77
Table 5-2. LQFP100 package dimensions ......................................................................................................... 78
Table 5-3. LQFP64 package dimensions ........................................................................................................... 79
Table 6-1. Part ordering code for GD32F305xx devices ................................................................................ 80
Table 7-1. Revision history ................................................................................................................................... 81
6
GD32F305xx Datasheet
1.
General description
The GD32F305xx device belongs to the mainstream line of GD32 MCU Family. It is a new
32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best
cost-performance ratio in terms of enhanced processing capacity, reduced power
consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP
instructions to address digital signal control markets that demand an efficient, easy-to-use
blend of control and signal processing capabilities. It also provides a Memory Protection Unit
(MPU) and powerful trace technology for enhanced application security and advanced debug
support.
The GD32F305xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating
at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It
provides up to 1024 KB on-chip Flash memory and 96 KB SRAM memory. An extensive range
of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two
12-bit 2.6 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM
advanced timers, and two 16-bit basic timers, as well as standard and advanced
communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two
I2Ss, two CANs and a USBFS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make GD32F305xx devices suitable for a wide range of interconnection
and advanced applications, especially in areas such as industrial control, consumer and
handheld equipment, communication networks, embedded modules, human machine
interface, security and alarm systems, graphic display, automotive navigation, IoT and so on.
7
GD32F305xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32F305xx devices features and peripheral list
GD32F305xx
Part Number
Code area
Flash
(KB)
Data area
(KB)
Total (KB)
Timers
SRAM (KB)
RB
RC
RE
RG
VC
VE
VG
ZC
ZE
ZG
128
256
256
256
256
256
256
256
256
256
0
0
256
768
0
256
768
0
256
768
128
256
512
1024
256
512
1024
256
512
1024
64
96
96
96
96
96
96
96
96
96
General
4
4
4
10
4
4
10
4
4
10
timer(16-bit)
(1-4)
(1-4)
(1-4)
(1-4,8-13)
(1-4)
(1-4)
(1-4,8-13)
(1-4)
(1-4)
(1-4,8-13)
Advanced
1
1
2
2
1
2
2
2
2
2
timer(16-bit)
(0)
(0)
(0,7)
(0,7)
(0)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
Basic
2
2
2
2
2
2
2
2
2
2
timer(16-bit)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
SysTick
1
1
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
USART
3
3
3
3
3
3
3
3
3
3
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
2
2
2
2
2
2
2
2
2
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
2
2
2
2
2
2
2
2
2
2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
CAN
2
2
2
2
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
1
1
1
1
GPIO
51
51
51
51
80
80
80
112
112
112
EXMC
0
0
0
0
1
1
1
1
1
1
EXTI
16
16
16
16
16
16
16
16
16
16
ADC Unit (CHs)
2(16)
2(16)
2(16)
2(16)
2(16)
2(16)
2(16)
2(21)
2(21)
2(21)
DAC
2
2
2
2
2
2
2
2
2
2
Connectivity
2
(3-4)
UART
I2C
SPI/I2S
Package
LQFP64
LQFP100
LQFP144
8
GD32F305xx Datasheet
2.2.
Block diagram
Figure 2-1. GD32F305xx block diagram
SW/JTAG
TPIU
Flash
Memory
Controller
IBus
Flash
Memory
PLL
F max : 120MHz
DBus
FMC
Master
DMA0 7chs
Master
DMA1 5chs
Master
EXMC
AHB: Fmax = 120MHz
NVIC
ICode DCode System
ARM Cortex-M4
Processor
Fmax:120MHz
POR/ PDR
Slave
CRC
LDO
1.2V
RCU
AHB Peripherals
Slave
Slave
USBFS
SRAM
Controller
AHB to APB
Bridge2
IRC
8MHz
SRAM
HXTAL
4-32MHz
AHB to APB
Bridge1
LVD
Slave
Interrput request
CAN0
USART0
Slave
12-bit
SAR ADC
Slave
SPI0
WWDGT
ADC0~1
TIMER1~3
EXTI
SPI1~2\
I2S1~2
GPIOA
USART1~2
GPIOB
I2C0
Powered By V DDA
GPIOE
APB1: Fmax = 60MHz
GPIOD
APB2: Fmax = 120MHz
GPIOC
Powered By VDDA
I2C1
FWDGT
RTC
GPIOF
DAC
GPIOG
TIMER4~6
TIMER0
UART3~4
TIMER7
CAN1
TIMER8~10
TIMER
11~13
CTC
9
GD32F305xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32F305Zx LQFP144 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109
PE2
1
108
PE3
PE4
2
107
VSS_2
3
106
NC
PE5
PE6
4
105
PA13
5
104
PA12
VBAT
6
103
PA11
PC13-TAMPER-RTC
PC14-OSC32IN
7
102
PA10
8
101
PA9
PC15-OSC32OUT
9
100
PA8
PF0
10
99
PC9
PF1
11
98
PC8
PF2
12
97
PC7
PF3
PF4
13
96
PC6
14
95
VDD_9
PF5
15
94
VSS_9
VSS_5
16
93
PG8
92
PG7
91
PG6
90
PG5
89
PG4
88
PG3
VDD_2
VDD_5
17
PF6
18
PF7
19
PF8
20
PF9
21
PF10
22
87
PG2
OSCIN
23
86
PD15
OSCOUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
82
PD13
PC2
28
81
PD12
PC3
VSSA
29
80
PD11
30
79
PD10
VREFVREF+
31
78
PD9
32
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
GigaDevice GD32F305Zx
LQFP144
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE8
PE9
PE7
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
10
GD32F305xx Datasheet
Figure 2-3. GD32F305Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32IN
7
70
69
PA10
8
68
PA9
PC15-OSC32OUT
9
67
PA8
VSS_5
10
66
PC9
VDD_5
11
65
PC8
64
PC7
63
PC6
14
62
PD15
OSCIN
12
GigaDevice GD32F305Vx
LQFP100
VDD_2
PA11
OSCOUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
11
GD32F305xx Datasheet
Figure 2-4. GD32F305Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32IN
3
46
PA13
PC15-OSC32OUT
PD0-OSCIN
4
45
PA12
5
44
PA11
PD1-OSCOUT
6
43
PA10
7
42
PA9
41
PA8
NRST
PC0
GigaDevice GD32F305Rx
LQFP64
8
PC1
9
40
PC9
PC2
PC3
VSSA
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_1
VSS_1
PB11
PB10
PB2
PB1
PB0
PC5
PC4
PA7
PA6
PA5
PA4
VDD_4
PA3
VSS_4
12
GD32F305xx Datasheet
2.4.
Memory map
Table 2-2. GD32F305xx memory map
Pre-defined
Regions
Bus
External device
External RAM
AHB3
AHB1
Peripheral
APB2
Address
Peripherals
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
0x9000 0000 - 0x9FFF FFFF
EXMC - PC CARD
0x7000 0000 - 0x8FFF FFFF
EXMC - NAND
0x6000 0000 - 0x6FFF FFFF
EXMC - NOR/PSRAM/SRAM
0x5000 0000 - 0x5003 FFFF
USBFS
0x4008 0000 - 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
Reserved
0x4002 BC00 - 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Reserved
0x4002 A000 - 0x4002 AFFF
Reserved
0x4002 8000 - 0x4002 9FFF
Reserved
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
Reserved
0x4002 6000 - 0x4002 63FF
Reserved
0x4002 5000 - 0x4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Reserved
0x4002 3800 - 0x4002 3BFF
Reserved
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
Reserved
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1C00 - 0x4002 1FFF
Reserved
0x4002 1800 - 0x4002 1BFF
Reserved
0x4002 1400 - 0x4002 17FF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA1
0x4002 0000 - 0x4002 03FF
DMA0
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
Reserved
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
Reserved
0x4001 7400 - 0x4001 77FF
Reserved
13
GD32F305xx Datasheet
Pre-defined
Regions
Bus
APB1
Address
Peripherals
0x4001 7000 - 0x4001 73FF
Reserved
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
Reserved
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
Reserved
0x4001 5400 - 0x4001 57FF
TIMER10
0x4001 5000 - 0x4001 53FF
TIMER9
0x4001 4C00 - 0x4001 4FFF
TIMER8
0x4001 4800 - 0x4001 4BFF
Reserved
0x4001 4400 - 0x4001 47FF
Reserved
0x4001 4000 - 0x4001 43FF
Reserved
0x4001 3C00 - 0x4001 3FFF
Reserved
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
TIMER7
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
0x4001 2000 - 0x4001 23FF
GPIOG
0x4001 1C00 - 0x4001 1FFF
GPIOF
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
CTC
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
0x4000 6000 - 0x4000 63FF
CAN SRAM 512 bytes
14
GD32F305xx Datasheet
Pre-defined
Regions
SRAM
Bus
AHB
Address
Peripherals
0x4000 5C00 - 0x4000 5FFF
Reserved
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
0x4000 1C00 - 0x4000 1FFF
TIMER12
0x4000 1800 - 0x4000 1BFF
TIMER11
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2007 0000 - 0x3FFF FFFF
Reserved
0x2006 0000 - 0x2006 FFFF
Reserved
0x2003 0000 - 0x2005 FFFF
Reserved
0x2001 8000 - 0x2002 FFFF
Reserved
0x2000 0000 - 0x2001 7FFF
SRAM
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF F000 - 0x1FFF F7FF
0x1FFF C010 - 0x1FFF EFFF
0x1FFF C000 - 0x1FFF C00F
Code
AHB
Boot loader
0x1FFF B000 - 0x1FFF BFFF
0x1FFF 7A10 - 0x1FFF AFFF
Reserved
0x1FFF 7800 - 0x1FFF 7A0F
Reserved
0x1FFF 0000 - 0x1FFF 77FF
Reserved
0x1FFE C010 - 0x1FFE FFFF
Reserved
0x1FFE C000 - 0x1FFE C00F
Reserved
15
GD32F305xx Datasheet
Pre-defined
Regions
Bus
Address
Peripherals
0x1001 0000 - 0x1FFE BFFF
Reserved
0x1000 0000 - 0x1000 FFFF
Reserved
0x083C 0000 - 0x0FFF FFFF
Reserved
0x0830 0000 - 0x083B FFFF
Reserved
0x0810 0000 - 0x082F FFFF
Reserved
0x0800 0000 - 0x080F FFFF
Main Flash
0x0030 0000 - 0x07FF FFFF
Reserved
0x0010 0000 - 0x002F FFFF
0x0002 0000 - 0x000F FFFF
Aliased to Main Flash or Boot
loader
0x0000 0000 - 0x0001 FFFF
16
GD32F305xx Datasheet
2.5.
Clock tree
Figure 2-5. GD32F305xx clock tree
CTC
CK_IRC48M
CK_CTC
48 MHz
IRC48M
48 MHz
CK48MSEL
USB OTG
Prescaler
1,1.5,2,2.5
3,3.5,4
1
SCS[1:0]
CK_IRC8M
8 MHz
IRC8M
0
1
PLLSEL
PREDV0
0
4-32 MHz
HXTAL
0
1
CK_USBFS
0
(to USBFS)
00
/2
PLLPRESEL
CK_IRC48M
1
1
×2,3,4
…,63
PLL
CK_PLL
10
AHB
Prescaler
÷1,2...512
CK_SYS
120 MHz max
CK_AHB
120 MHz max
CK_EXMC
EXMC enable
(by hardware)
(to EXMC)
HCLK
01
PLLMF
AHB enable
/1,2,3…
15,16
(to AHB bus,Cortex-M4,SRAM,DMA,FMC)
CK_CST
Clock
Monitor
÷8
(to Cortex-M4 SysTick)
FCLK
PREDV0SEL
EXT1 to
CK_OUT
(free running clock)
CK_HXTAL
APB1
Prescaler
÷1,2,4,8,16
CK_APB1
PCLK1
to APB1 peripherals
60 MHz max
Peripheral enable
×8,9,10…,
14,16,20
PLL1
TIMER1,2,3,4,5,6,
11,12,13 if(APB1
prescale =1)x1
else x 2
CK_PLL1
×8..14,16,
18..32,40
PLL2
PREDV1
0
CK_PLL2
x2
CK_I2S
1
APB2
Prescaler
÷1,2,4,8,16
CK_RTC
01
(to RTC)
10
RTCSRC[1:0]
40 KHz
IRC40K
CK_OUT0
00xx
0100
0101
0110
0111
1000
1001
1010
1011
TIMER0,7,8,9,10
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,6,8,12,1
6
CK_FWDGT
(to FWDGT)
CK_APB2
PCLK2
to APB2 peripherals
120 MHz max
Peripheral enable
I2S1/2SEL
PLL2MF
11
32.768 KHz
LXTAL
to TIMER1,2,3,4,
5,6,11,12,13
PLL1MF
/1,2,3…
15,16
/128
CK_TIMERx
TIMERx
enable
ADC
Prescaler
÷5,6,10,20
CK_TIMERx
TIMERx
enable
to
TIMER0,7,8,9,10
ADCPSC[3]
0
1
CK_ADCx to ADC0,1
40 MHz max
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
/2
CK_PLL
CK_PLL1
/2
CK_PLL2
EXT1
CK_PLL2
CKOUT0SEL[3:0]
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC8M: Internal 8M RC oscillators
IRC40K: Internal 40K RC oscillator
IRC48M: Internal 48M RC oscillators
17
GD32F305xx Datasheet
2.6.
Pin definitions
2.6.1.
GD32F305Zx LQFP144 pin definitions
Table 2-3. GD32F305Zx LQFP144 pin definitions
Pin
I/O
Type(1)
Level(2)
1
I/O
5VT
PE3
2
I/O
5VT
PE4
3
I/O
5VT
Pin Name
Pins
PE2
Functions description
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
PE5
4
I/O
5VT
Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0(3)
Default: PE6
PE6
5
I/O
5VT
Alternate:TRACED3, EXMC_A22
Remap: TIMER8_CH1(3)
VBAT
6
P
7
I/O
8
I/O
9
I/O
10
I/O
Default: VBAT
PC13TAMPER-
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OUT
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: PF0
PF0
5VT
Alternate: EXMC_A0
Remap: CTC_SYNC
Default: PF1
PF1
11
I/O
5VT
PF2
12
I/O
5VT
PF3
13
I/O
5VT
PF4
14
I/O
5VT
PF5
15
I/O
5VT
VSS_5
16
P
Default: VSS_5
VDD_5
17
P
Default: VDD_5
Alternate: EXMC_A1
Default: PF2
Alternate: EXMC_A2
Default: PF3
Alternate: EXMC_A3
Default: PF4
Alternate: EXMC_A4
Default: PF5
Alternate: EXMC_A5
18
GD32F305xx Datasheet
Pin Name
Pins
PF6
18
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PF6
I/O
Alternate: EXMC_NIORD
Remap: TIMER9_CH0(3)
Default: PF7
PF7
19
I/O
Alternate: EXMC_NREG
Remap: TIMER10_CH0(3)
Default: PF8
PF8
20
I/O
Alternate: EXMC_NIOWR
Remap: TIMER12_CH0(3)
Default: PF9
PF9
21
I/O
Alternate: EXMC_CD
Remap: TIMER13_CH0(3)
Default: PF10
PF10
22
I/O
OSCIN
23
I
OSCOUT
24
O
NRST
25
I/O
PC0
26
I/O
PC1
27
I/O
PC2
28
I/O
PC3
29
I/O
VSSA
30
P
Default: VSSA
VREF-
31
P
Default: VREF-
VREF+
32
P
Default: VREF+
VDDA
33
P
Default: VDDA
Alternate: EXMC_INTR
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC01_IN10
Default: PC1
Alternate: ADC01_IN11
Default: PC2
Alternate: ADC01_IN12
Default: PC3
Alternate: ADC01_IN13
Default: PA0
PA0-WKUP
34
I/O
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,
TIMER7_ETI
Default: PA1
PA1
35
I/O
Alternate: USART1_RTS, ADC01_IN1,
TIMER1_CH1, TIMER4_CH1
Default: PA2
PA2
36
I/O
Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2,
TIMER4_CH2, TIMER8_CH0(3), SPI0_IO2
PA3
37
I/O
Default: PA3
19
GD32F305xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: USART1_RX, ADC01_IN3,
TIMER1_CH3, TIMER4_CH3,
TIMER8_CH1(3),
SPI0_IO3
VSS_4
38
P
Default: VSS_4
VDD_4
39
P
Default: VDD_4
Default: PA4
PA4
40
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
I/O
DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
41
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
42
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN, TIMER12_CH0(3)
Remap: TIMER0_BRKIN
Default: PA7
PA7
43
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON, TIMER13_CH0(3)
Remap: TIMER0_CH0_ON
PC4
44
I/O
PC5
45
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
46
Alternate: ADC01_IN8, TIMER2_CH2,
I/O
TIMER7_CH1_ON
Remap: TIMER0_CH1_ON
Default: PB1
Alternate: ADC01_IN9, TIMER2_CH3,
PB1
47
I/O
PB2
48
I/O
5VT
PF11
49
I/O
5VT
PF12
50
I/O
5VT
TIMER7_CH2_ON
Remap: TIMER0_CH2_ON
Default: PB2, BOOT1
Default: PF11
Alternate: EXMC_NIOS16
Default: PF12
Alternate: EXMC_A6
VSS_6
51
P
Default: VSS_6
VDD_6
52
P
Default: VDD_6
PF13
53
I/O
5VT
PF14
54
I/O
5VT
Default: PF13
Alternate: EXMC_A7
Default: PF14
Alternate: EXMC_A8
20
GD32F305xx Datasheet
Pin
I/O
Type(1)
Level(2)
55
I/O
5VT
PG0
56
I/O
5VT
PG1
57
I/O
5VT
Pin Name
Pins
PF15
Functions description
Default: PF15
Alternate: EXMC_A9
Default: PG0
Alternate: EXMC_A10
Default: PG1
Alternate: EXMC_A11
Default: PE7
PE7
58
I/O
5VT
Alternate: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
59
I/O
5VT
Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
5VT
Alternate: EXMC_D6
PE9
60
I/O
VSS_7
61
P
Default: VSS_7
VDD_7
62
P
Default: VDD_7
Remap: TIMER0_CH0
Default: PE10
PE10
63
I/O
5VT
Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
64
I/O
5VT
Alternate: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
65
I/O
5VT
Alternate: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
66
I/O
5VT
Alternate: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
67
I/O
5VT
Alternate: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
68
I/O
5VT
Alternate: EXMC_D12
Remap: TIMER0_BRKIN
Default: PB10
PB10
69
I/O
5VT
Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
Default: PB11
PB11
70
I/O
5VT
Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
71
P
Default: VSS_1
VDD_1
72
P
Default: VDD_1
21
GD32F305xx Datasheet
Pin Name
Pins
PB12
73
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PB12
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
Default: PB13
PB13
74
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK, CAN1_TX
Default: PB14
PB14
75
I/O
5VT
Alternate: SPI1_MISO, USART2_RTS,
TIMER0_CH1_ON, TIMER11_CH0(3)
Default: PB15
PB15
76
I/O
5VT
Alternate: SPI1_MOSI, TIMER0_CH2_ON,
I2S1_SD, TIMER11_CH1(3)
Default: PD8
PD8
77
I/O
5VT
Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
78
I/O
5VT
Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
79
I/O
5VT
Alternate: EXMC_D15
Remap: USART2_CK
Default: PD11
PD11
80
I/O
5VT
Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
81
I/O
5VT
Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
5VT
Alternate: EXMC_A18
PD13
82
I/O
VSS_8
83
P
Default: VSS_8
VDD_8
84
P
Default: VDD_8
PD14
85
I/O
Remap: TIMER3_CH1
Default: PD14
5VT
Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
86
I/O
5VT
Alternate: EXMC_D1
Remap: TIMER3_CH3, CTC_SYNC
PG2
87
I/O
5VT
PG3
88
I/O
5VT
PG4
89
I/O
5VT
Default: PG2
Alternate: EXMC_A12
Default: PG3
Alternate: EXMC_A13
Default: PG4
22
GD32F305xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: EXMC_A14
Default: PG5
PG5
90
I/O
5VT
PG6
91
I/O
5VT
PG7
92
I/O
5VT
PG8
93
I/O
5VT
VSS_9
94
P
Default: VSS_9
VDD_9
95
P
Default: VDD_9
PC6
96
I/O
Alternate: EXMC_A15
Default: PG6
Alternate: EXMC_INT1
Default: PG7
Alternate: EXMC_INT2
Default: PG8
Default: PC6
5VT
Alternate: I2S1_MCK, TIMER7_CH0
Remap: TIMER2_CH0
Default: PC7
PC7
97
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1
Remap: TIMER2_CH1
Default: PC8
PC8
98
I/O
5VT
Alternate: TIMER7_CH2
Remap: TIMER2_CH2
Default: PC9
PC9
99
I/O
5VT
Alternate: TIMER7_CH3
Remap: TIMER2_CH3
Default: PA8
PA8
100
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF, CTC_SYNC
Default: PA9
PA9
101
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1,
USBFS_VBUS
PA10
102
I/O
5VT
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
103
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
104
I/O
5VT
Alternate: USART0_RTS, USBFS_DP, CAN0_TX,
TIMER0_ETI
5VT
Default: JTMS, SWDIO
PA13
105
I/O
NC
106
-
-
VSS_2
107
P
Default: VSS_2
VDD_2
108
P
Default: VDD_2
PA14
109
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
23
GD32F305xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Remap: PA14
Default: JTDI
PA15
110
I/O
5VT
Alternate: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0, TIMER1_ETI, PA15,
SPI0_NSS
Default: PC10
PC10
111
I/O
5VT
Alternate: UART3_TX
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
112
I/O
5VT
Alternate: UART3_RX
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
113
I/O
5VT
Alternate: UART4_TX
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
114
I/O
5VT
Alternate: EXMC_D2
Remap: CAN0_RX, OSCIN
Default: PD1
PD1
115
I/O
5VT
Alternate: EXMC_D3
Remap: CAN0_TX, OSCOUT
PD2
116
I/O
5VT
PD3
117
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, UART4_RX
Default: PD3
Alternate: EXMC_CLK
Remap: USART1_CTS
Default: PD4
PD4
118
I/O
5VT
Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
119
I/O
5VT
Alternate: EXMC_NWE
Remap: USART1_TX
VSS_10
120
P
Default: VSS_10
VDD_10
121
P
Default: VDD_10
PD6
122
I/O
Default: PD6
5VT
Alternate: EXMC_NWAIT
Remap: USART1_RX
Default: PD7
PD7
123
I/O
5VT
Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
PG9
124
I/O
5VT
PG10
125
I/O
5VT
Default: PG9
Alternate: EXMC_NE1, EXMC_NCE2
Default: PG10
Alternate: EXMC_NCE3_0, EXMC_NE2
24
GD32F305xx Datasheet
Pin
I/O
Type(1)
Level(2)
126
I/O
5VT
PG12
127
I/O
5VT
PG13
128
I/O
5VT
PG14
129
I/O
5VT
Pin Name
Pins
PG11
Functions description
Default: PG11
Alternate: EXMC_NCE3_1
Default: PG12
Alternate: EXMC_NE3
Default: PG13
Alternate: EXMC_A24
Default: PG14
Alternate: EXMC_A25
VSS_11
130
P
Default: VSS_11
VDD_11
131
P
Default: VDD_11
PG15
132
I/O
5VT
Default: PG15
Default: JTDO
PB3
133
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, TIMER1_CH1,
SPI0_SCK
Default: NJTRST
PB4
134
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
135
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
136
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX, SPI0_IO2
Default: PB7
PB7
137
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
BOOT0
138
I
PB8
139
I/O
Default: BOOT0
Default: PB8
5VT
Alternate: TIMER3_CH2, TIMER9_CH0(3)
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
140
I/O
5VT
Alternate: TIMER3_CH3, TIMER10_CH0(3)
Remap: I2C0_SDA, CAN0_TX
Default: PE0
PE0
141
I/O
5VT
PE1
142
I/O
5VT
VSS_3
143
P
Default: VSS_3
VDD_3
144
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
Notes:
(1)Type: I = input, O = output, P = power.
25
GD32F305xx Datasheet
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available in GD32F305ZG devices.
26
GD32F305xx Datasheet
2.6.2.
GD32F305Vx LQFP100 pin definitions
Table 2-4. GD32F305Vx LQFP100 pin definitions
Pin
I/O
Type(1)
Level(2)
1
I/O
5VT
PE3
2
I/O
5VT
PE4
3
I/O
5VT
PE5
4
I/O
5VT
Pin Name
Pins
PE2
Functions description
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0(3)
Default: PE6
PE6
5
I/O
5VT
Alternate:TRACED3, EXMC_A22
Remap: TIMER8_CH1(3)
VBAT
Default: VBAT
6
P
7
I/O
8
I/O
9
I/O
VSS_5
10
P
Default: VSS_5
VDD_5
11
P
Default: VDD_5
OSCIN
12
I
OSCOUT
13
O
NRST
14
I/O
PC0
15
I/O
PC1
16
I/O
PC2
17
I/O
PC3
18
I/O
VSSA
19
P
Default: VSSA
VREF-
20
P
Default: VREF-
VREF+
21
P
Default: VREF+
PC13TAMPER-
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OUT
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC01_IN10
Default: PC1
Alternate: ADC01_IN11
Default: PC2
Alternate: ADC01_IN12
Default: PC3
Alternate: ADC01_IN13
27
GD32F305xx Datasheet
Pin Name
Pins
VDDA
22
Pin
I/O
Type(1)
Level(2)
Functions description
Default: VDDA
P
Default: PA0
PA0-WKUP
23
Alternate: WKUP, USART1_CTS, ADC01_IN0,
I/O
TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,
TIMER7_ETI(4)
Default: PA1
PA1
24
Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1,
I/O
TIMER4_CH1
Default: PA2
PA2
25
Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2,
I/O
TIMER4_CH2, TIMER8_CH0(3), SPI0_IO2
Default: PA3
PA3
26
Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3,
I/O
TIMER4_CH3,
VSS_4
27
P
Default: VSS_4
VDD_4
28
P
Default: VDD_4
TIMER8_CH1(3), SPI0_IO3
Default: PA4
PA4
29
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
I/O
DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
30
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
31
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN(4), TIMER12_CH0(3)
Remap: TIMER0_BRKIN
Default: PA7
PA7
32
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON(4), TIMER13_CH0(3)
Remap: TIMER0_CH0_ON
PC4
33
I/O
PC5
34
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
35
Alternate: ADC01_IN8, TIMER2_CH2,
I/O
TIMER7_CH1_ON(4)
Remap: TIMER0_CH1_ON
Default: PB1
PB1
36
Alternate: ADC01_IN9, TIMER2_CH3,
I/O
TIMER7_CH2_ON(4)
Remap: TIMER0_CH2_ON
PB2
37
I/O
5VT
Default: PB2, BOOT1
28
GD32F305xx Datasheet
Pin Name
Pins
PE7
38
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PE7
Alternate: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
39
I/O
5VT
Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
PE9
40
I/O
5VT
Alternate: EXMC_D6
Remap: TIMER0_CH0
Default: PE10
PE10
41
I/O
5VT
Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
42
I/O
5VT
Alternate: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
43
I/O
5VT
Alternate: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
44
I/O
5VT
Alternate: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
45
I/O
5VT
Alternate: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
46
I/O
5VT
Alternate: EXMC_D12
Remap: TIMER0_BRKIN
Default: PB10
PB10
47
I/O
5VT
Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
Default: PB11
PB11
48
I/O
5VT
Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
49
P
Default: VSS_1
VDD_1
50
P
Default: VDD_1
PB12
51
I/O
Default: PB12
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
Default: PB13
PB13
52
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK, CAN1_TX
PB14
53
I/O
5VT
Default: PB14
Alternate: SPI1_MISO, USART2_RTS,
29
GD32F305xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER0_CH1_ON, TIMER11_CH0(3)
Default: PB15
PB15
54
I/O
5VT
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1(3)
Default: PD8
PD8
55
I/O
5VT
Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
56
I/O
5VT
Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
57
I/O
5VT
Alternate: EXMC_D15
Remap: USART2_CK
Default: PD11
PD11
58
I/O
5VT
Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
59
I/O
5VT
Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
60
I/O
5VT
Alternate: EXMC_A18
Remap: TIMER3_CH1
Default: PD14
PD14
61
I/O
5VT
Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
62
I/O
5VT
Alternate: EXMC_D1
Remap: TIMER3_CH3, CTC_SYNC
Default: PC6
PC6
63
I/O
5VT
Alternate: I2S1_MCK, TIMER7_CH0(4)
Remap: TIMER2_CH0
Default: PC7
PC7
64
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1(4)
Remap: TIMER2_CH1
Default: PC8
PC8
65
I/O
5VT
Alternate: TIMER7_CH2(4)
Remap: TIMER2_CH2
Default: PC9
PC9
66
I/O
5VT
Alternate: TIMER7_CH3(4)
Remap: TIMER2_CH3
Default: PA8
PA8
67
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF, CTC_SYNC
30
GD32F305xx Datasheet
Pin Name
Pins
PA9
68
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PA9
Alternate: USART0_TX, TIMER0_CH1,
USBFS_VBUS
PA10
69
I/O
5VT
PA11
70
I/O
5VT
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
71
I/O
5VT
Alternate: USART0_RTS, USBFS_DP, CAN0_TX,
TIMER0_ETI
5VT
Default: JTMS, SWDIO
PA13
72
I/O
NC
73
-
-
VSS_2
74
P
Default: VSS_2
VDD_2
75
P
Default: VDD_2
PA14
76
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
77
I/O
5VT
Alternate: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0, TIMER1_ETI, PA15,
SPI0_NSS
Default: PC10
PC10
78
I/O
5VT
Alternate: UART3_TX
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
79
I/O
5VT
Alternate: UART3_RX
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
80
I/O
5VT
Alternate: UART4_TX
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
81
I/O
5VT
Alternate: EXMC_D2
Remap: CAN0_RX, OSCIN
Default: PD1
PD1
82
I/O
5VT
Alternate: EXMC_D3
Remap: CAN0_TX, OSCOUT
PD2
83
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, UART4_RX
Default: PD3
PD3
84
I/O
5VT
Alternate: EXMC_CLK
Remap: USART1_CTS
PD4
85
I/O
5VT
Default: PD4
31
GD32F305xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
86
I/O
5VT
Alternate: EXMC_NWE
Remap: USART1_TX
Default: PD6
PD6
87
I/O
5VT
Alternate: EXMC_NWAIT
Remap: USART1_RX
Default: PD7
PD7
88
I/O
5VT
Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
Default: JTDO
PB3
89
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, TIMER1_CH1,
SPI0_SCK
Default: NJTRST
PB4
90
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
91
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
92
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX, SPI0_IO2
Default: PB7
PB7
93
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
BOOT0
94
Default: BOOT0
I
Default: PB8
PB8
95
I/O
5VT
Alternate: TIMER3_CH2, TIMER9_CH0(3)
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
96
I/O
5VT
Alternate: TIMER3_CH3, TIMER10_CH0(3)
Remap: I2C0_SDA, CAN0_TX
Default: PE0
PE0
97
I/O
5VT
PE1
98
I/O
5VT
VSS_3
99
P
Default: VSS_3
VDD_3
100
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
Notes:
(1)Type: I = input, O = output, P = power.
32
GD32F305xx Datasheet
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available in GD32F305VG devices.
(4)Functions are available in GD32F305VE/G devices.
33
GD32F305xx Datasheet
2.6.3.
GD32F305Rx LQFP64 pin definitions
Table 2-5. GD32F305Rx LQFP64 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
OSCIN
5
I
OSCOUT
6
O
NRST
7
I/O
PC0
8
I/O
PC1
9
I/O
PC2
10
I/O
PC3
11
I/O
VSSA
12
P
Default: VSSA
VDDA
13
P
Default: VDDA
PC13TAMPER-
Functions description
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OUT
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0(5)
Default: OSCOUT
Remap: PD1(5)
Default: NRST
Default: PC0
Alternate: ADC01_IN10
Default: PC1
Alternate: ADC01_IN11
Default: PC2
Alternate: ADC01_IN12
Default: PC3
Alternate: ADC01_IN13
Default: PA0
PA0-WKUP
14
I/O
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,
TIMER7_ETI(4)
Default: PA1
PA1
15
I/O
Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1,
TIMER4_CH1
Default: PA2
PA2
16
I/O
Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2,
TIMER4_CH2, TIMER8_CH0(3), SPI0_IO2
Default: PA3
PA3
17
I/O
Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3,
TIMER4_CH3,
VSS_4
18
P
Default: VSS_4
VDD_4
19
P
Default: VDD_4
TIMER8_CH1(3), SPI0_IO3
34
GD32F305xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PA4
PA4
20
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
I/O
DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
21
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
22
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN(4), TIMER12_CH0(3)
Remap: TIMER0_BRKIN
Default: PA7
PA7
23
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON(4), TIMER13_CH0(3)
Remap: TIMER0_CH0_ON
PC4
24
I/O
PC5
25
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
26
Alternate: ADC01_IN8, TIMER2_CH2,
I/O
TIMER7_CH1_ON(4)
Remap: TIMER0_CH1_ON
Default: PB1
PB1
27
Alternate: ADC01_IN9, TIMER2_CH3,
I/O
TIMER7_CH2_ON(4)
Remap: TIMER0_CH2_ON
PB2
28
I/O
5VT
PB10
29
I/O
5VT
Default: PB2, BOOT1
Default: PB10
Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
Default: PB11
PB11
30
I/O
5VT
Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
31
P
Default: VSS_1
VDD_1
32
P
Default: VDD_1
PB12
33
I/O
Default: PB12
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
Default: PB13
PB13
34
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK, CAN1_TX
PB14
35
I/O
5VT
Default: PB14
Alternate: SPI1_MISO, USART2_RTS,
35
GD32F305xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER0_CH1_ON, TIMER11_CH0(3)
Default: PB15
PB15
36
I/O
5VT
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1(3)
Default: PC6
PC6
37
I/O
5VT
Alternate: I2S1_MCK, TIMER7_CH0(4)
Remap: TIMER2_CH0
Default: PC7
PC7
38
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1(4)
Remap: TIMER2_CH1
Default: PC8
PC8
39
I/O
5VT
Alternate: TIMER7_CH2(4)
Remap: TIMER2_CH2
Default: PC9
PC9
40
I/O
5VT
Alternate: TIMER7_CH3(4)
Remap: TIMER2_CH3
Default: PA8
PA8
41
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF, CTC_SYNC
Default: PA9
PA9
42
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1,
USBFS_VBUS
PA10
43
I/O
5VT
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
44
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
45
I/O
5VT
Alternate: USART0_RTS, USBFS_DP, CAN0_TX,
TIMER0_ETI
PA13
46
I/O
5VT
Default: JTMS, SWDIO
Remap: PA13
VSS_2
47
P
Default: VSS_2
VDD_2
48
P
Default: VDD_2
PA14
49
I/O
5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
50
I/O
5VT
Alternate: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0, TIMER1_ETI, PA15,
SPI0_NSS
Default: PC10
PC10
51
I/O
5VT
Alternate: UART3_TX
Remap: USART2_TX, SPI2_SCK, I2S2_CK
36
GD32F305xx Datasheet
Pin Name
Pins
PC11
52
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PC11
Alternate: UART3_RX
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
53
I/O
5VT
Alternate: UART4_TX
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
PD2
54
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, UART4_RX
Default: JTDO
PB3
55
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, TIMER1_CH1,
SPI0_SCK
Default: NJTRST
PB4
56
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
57
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
58
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX, SPI0_IO2
Default: PB7
PB7
59
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1
Remap: USART0_RX, SPI0_IO3
BOOT0
60
I
PB8
61
I/O
Default: BOOT0
Default: PB8
5VT
Alternate: TIMER3_CH2, TIMER9_CH0(3)
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
62
I/O
5VT
Alternate: TIMER3_CH3, TIMER10_CH0(3)
Remap: I2C0_SDA, CAN0_TX
VSS_3
63
P
Default: VSS_3
VDD_3
64
P
Default: VDD_3
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)Functions are available in GD32F305RG devices.
(4)Functions are available in GD32F305RE/G devices.
(5)PD0/PD1 cannot be used for EXTI in this package.
37
GD32F305xx Datasheet
3.
Functional description
3.1.
ARM® Cortex®-M4 core
The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP
instructions which allow efficient signal processing and complex algorithm execution. It brings
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital
signal control markets demand. The processor is highly configurable enabling a wide range
of implementations from those requiring floating point operations, memory protection and
powerful trace technology to cost sensitive devices requiring minimal area, while delivering
outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2.
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
Floating Point Unit (FPU)
On-chip memory
Up to 1024 Kbytes of Flash memory, including code Flash and data Flash
Up to 96 KB of SRAM
The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 1024 Kbytes of inner flash at most,
which includes code Flash that available for storing programs and data, and accessed (R/W)
at CPU clock speed with zero wait states. An extra data Flash is also included for storing data
mainly. Table 2-2. GD32F305xx memory map shows the memory of the GD32F305xx
38
GD32F305xx Datasheet
series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.
3.3.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include internal RC oscillator and external crystal oscillator, high speed and low speed two
types. Several prescalers allow the frequency configuration of the AHB and two APB domains.
The maximum frequency of the two AHB domains are 120 MHz The maximum frequency of
the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz See Figure 2-5.
GD32F305xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are
always active, and ensures proper operation starting from/down to 2.6 V. The device remains
in reset mode when VDD is below a specified threshold. The embedded low voltage detector
(LVD) monitors the power supply, compares it to the voltage threshold and generates an
interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PD5 and PD6)
and USBFS (PA9, PA11 and PA12) is also available for boot functions. It also can be used to
transfer and update the Flash memory code, the data and the vector table sections. In default
39
GD32F305xx Datasheet
condition, boot from bank0 of Flash memory is selected. It also supports to boot from bank1
of Flash memory by setting a bit in option bytes.
3.5.
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are sleep mode, deep-sleep mode and standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the deep-sleep mode including the 16 external lines, the RTC alarm, the
LVD output and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected
as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except
backup registers) are lost. There are four wakeup sources for the standby mode,
including the external reset from NRST pin, the RTC, the FWDG reset, and the rising
edge on WKUP pin.
3.6.
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 2.6 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
Up to two 12-bit 2.6 MSPS multi-channel ADCs are integrated in the device. It has a total of
18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor
(VSENSE), and 1 channel for internal reference voltage (VREFINT). The input voltage range is
between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance
while off-loading the related computational burden from the CPU. An analog watchdog block
can be used to detect the channels, which are required to remain within a specific threshold
window. A configurable channel management block can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced use.
40
GD32F305xx Datasheet
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx)
and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature
sensor can be used to generate a voltage that varies linearly with temperature. It is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output voltage
in a digital value.
3.7.
Digital to analog converter (DAC)
Two 12-bit DACs with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller
The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC
channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel
operation, conversions could be done independently or simultaneously. The maximum output
value of the DAC is VREF+.
3.8.
DMA
7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9.
General-purpose inputs/outputs (GPIOs)
Up to 112 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 112 general purpose I/O pins (GPIO) in GD32F305xx, named PA0 ~ PA15
and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and
configuration registers to satisfy the requirements of specific applications. The external
interrupts on the GPIO pins of the device have related control and configuration registers in
the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative
functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can
be configured by software as output (push-pull or open-drain), as input (with or without pull41
GD32F305xx Datasheet
up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with
digital or analog alternate functions. All GPIOs are high-current capable except for analog
inputs.
3.10.
Timers and PWM generation
Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~
TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Free watchdog timer and window watchdog timer)
The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed
on 6 channels. It has complementary PWM outputs with programmable dead-time generation.
It can also be used as a complete general timer. The 4 independent channels can be used
for input capture, output compare, PWM generation (edge-aligned or center-aligned counting
modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same
functions as the TIMERx timer. It can be synchronized with external signals or to interconnect
with other general timers together which have the same architecture and features.
The general timer, can be used for a variety of purposes including general time, input signal
pulse width measurement or output waveform generation such as a single pulse generation
or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 ~
TIMER4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~
TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer
also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation.
They can also be used as a simple 16-bit time base.
The GD32F305xx have two watchdog peripherals, free watchdog timer and window watchdog
timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is
clocked from an independent 40 KHz internal RC and as it operates independently of the
main clock, it can operate in deep-sleep and standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for application
timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early wakeup interrupt capability and the counter can be frozen in
42
GD32F305xx Datasheet
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.11.
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC)
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wakeup event
The real time clock is an independent timer which provides a set of continuously running
counters which can be used with suitable software to provide a clock calendar function, and
provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit
programmable counter for long-term measurement using the compare register to generate an
alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
3.12.
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides several data transfer rates of up to 100 KHz in standard
mode, up to 400 KHz in fast mode and up to 1 MHz in the fast mode plus. The I2C module
also has an arbitration detect function to prevent the situation where more than one master
attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided
in I2C interface to perform packet error checking for I2C data.
3.13.
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
43
GD32F305xx Datasheet
Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking. Quad-SPI master mode is also supported in SPI0.
3.14.
Universal synchronous asynchronous receiver transmitter
(USART)
Up to three USARTs and two UARTs with operating frequency up to 7.5M Bits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface
The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data
exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232
standard communication. The USART/UART includes a programmable baud rate generator
which is capable of dividing the system clock to produce a dedicated clock for the USART
transmitter and receiver. The USART/UART also supports DMA function for high speed data
communication except UART4.
3.15.
Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32F305xx contain two I2S-bus interfaces that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and
SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported.
3.16.
Universal serial bus full-speed interface (USBFS)
One USB device/host/full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator (IRC48M) support crystal-less operation
Internal main PLL for USB CLK compliantly
Internal USBFS PHY support
44
GD32F305xx Datasheet
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction
formatting is performed by the hardware, including CRC generation and checking. It supports
both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and
Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For
full-speed or low-speed operation, no more external PHY chip is needed. It supports all the
four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol.
The required precise 48 MHz clock which can be generated from the internal main PLL (the
clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator
(IRC48M) in automatic trimming mode that allows crystal-less operation.
3.17.
Controller area network (CAN)
Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The
CAN protocol has been used extensively in industrial automation and automotive applications.
It can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three
message deep for reception. It also provides 28 scalable/configurable identifier filter banks
for selecting the incoming messages needed and discarding the others.
3.18.
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
PC card
Provide ECC calculating hardware module for NAND Flash memory block
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory except NAND Flash and PC card. The EXMC also can be
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
3.19.
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
45
GD32F305xx Datasheet
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.20.
Package and operation temperature
LQFP144 (GD32F305Zx), LQFP100 (GD32F305Vx) and LQFP64 (GD32F305Rx)
Operation temperature range: -40°C to +85°C (industrial level)
46
GD32F305xx Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 4-1. Absolute maximum ratings (1)(4)
Symbol
VDD
Parameter
External voltage
range(2)
Min
Max
Unit
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VSS - 0.3
VDD + 3.6
V
Input voltage on other I/O
VSS - 0.3
3.6
V
|ΔVDDX|
Variations between different VDD power pins
—
50
mV
|VSSX −VSS|
Variations between different ground pins
—
50
mV
IIO
Maximum current for GPIO pins
—
±25
mA
TA
Operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
Input voltage on 5V tolerant pin
(3)
(1). Guaranteed by design, not tested in production.
(2). All main power and ground pins should be connected to an external power source within the allowable range.
(3). VIN maximum value cannot exceed 6.5 V.
(4). It is recommended that VDD and VDDA are powered by the same source. The maximum difference between
VDD and VDDA does not exceed 300 mV during power-up and operation.
4.2.
Operating conditions characteristics
Table 4-2. DC operating conditions
Min(1) Typ Max(1) Unit
Symbol
Parameter
Conditions
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
(1). Based on characterization, not tested in production.
47
GD32F305xx Datasheet
Figure 4-1. Recommended power supply decoupling capacitors(1) (2)
VBAT
100 nF
VSS
N * VDD
4.7 μF + N * 100 nF
VSS
VDDA
1 μF
10 nF
VSSA
VREF+
1 μF
10 nF
VREF-
(1). The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins
are not available and internally connected to VDDA and VSSA pins.
(2). All decoupling capacitors need to be as close as possible to the pins on the PCB board.
Table 4-3. Clock frequency(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
AHB clock frequency
—
—
120
MHz
fAPB1
APB1 clock frequency
—
—
60
MHz
fAPB2
APB2 clock frequency
—
—
120
MHz
Min
Max
Unit
0
∞
20
∞
(1). Guaranteed by design, not tested in production.
Table 4-4. Operating conditions at Power up/ Power down(1)
Symbol
tVDD
Parameter
Conditions
VDD rise time rate
—
VDD fall time rate
μs/ V
(1). Guaranteed by design, not tested in production.
Table 4-5. Start-up timings of Operating conditions (1)(2)(3)
Symbol
Parameter
tstart-up
Start-up time
Conditions
Typ
Clock source from HXTAL
154
Clock source from IRC8M
154
Unit
ms
(1). Based on characterization, not tested in production.
(2). After power-up, the start-up time is the time between the rising edge of NRST high and the main function.
(3). PLL is off.
Table 4-6. Power saving mode wakeup timings characteristics(1) (2)
Symbol
Parameter
Typ
tSleep
Wakeup from Sleep mode
3.4
tDeep-sleep
Wakeup from Deep-sleep mode（LDO On）
5.8
Unit
μs
48
GD32F305xx Datasheet
Symbol
Parameter
Typ
Wakeup from Deep-sleep mode（LDO in low power mode）
5.8
Wakeup from Standby mode
154
tStandby
Unit
ms
(1). Based on characterization, not tested in production.
(2). The wakeup time is measured from the wakeup event to the point at which the application code reads the first
instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz.
4.3.
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 4-7. Power consumption characteristics (2)(3)(4)(5)
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
—
45.1
—
mA
—
25.5
—
mA
—
40.7
—
mA
—
23.2
—
mA
—
36.4
—
mA
—
20.8
—
mA
—
27.9
—
mA
—
16.1
—
mA
—
19.3
—
mA
—
11.4
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
IDD+IDDA
Supply current
enabled
(Run mode)
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
disabled
49
GD32F305xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
—
15.0
—
mA
—
9.1
—
mA
—
10.6
—
mA
—
6.7
—
mA
—
7.8
—
mA
—
5.2
—
mA
—
4.9
—
mA
—
3.6
—
mA
—
1.4
—
mA
—
0.9
—
mA
—
0.8
—
mA
—
0.6
—
mA
—
31.4
—
mA
—
10.5
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System clock = 2 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
Supply current
(Sleep mode)
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
All peripherals disabled
50
GD32F305xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
—
28.4
—
mA
—
9.6
—
mA
—
25.5
—
mA
—
8.8
—
mA
—
19.7
—
mA
—
7.1
—
mA
—
13.8
—
mA
—
5.4
—
mA
—
10.8
—
mA
—
4.5
—
mA
—
7.9
—
mA
—
3.7
—
mA
—
5.9
—
mA
—
3.2
—
mA
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals disabled
51
GD32F305xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
—
4.0
—
mA
—
2.6
—
mA
—
1.0
—
mA
—
0.5
—
mA
—
0.6
—
mA
—
0.3
—
mA
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, LDO in run mode,
IRC40K off, RTC off, All GPIOs analog
—
137.8 1100
μA
—
109.1 1100
μA
—
124.2 1100
μA
—
94.9
1100
μA
—
5.2
22
μA
—
4.9
22
μA
—
4.3
22
μA
—
1.7
—
μA
—
1.5
—
μA
mode
VDD = VDDA = 3.3 V, LDO in low power
Supply current
(Deep-Sleep
mode)
mode, IRC40K off, RTC off, All GPIOs
analog mode
VDD = VDDA = 3.3 V, Main LDO in under
drive mode, IRC40K off, RTC off, All
GPIOs analog mode
VDD = VDDA = 3.3 V, Low Power LDO in
under drive mode, IRC40K off, RTC off, All
GPIOs analog mode
VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
RTC on
Supply current VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
(Standby mode)
RTC off
VDD = VDDA = 3.3 V, LXTAL off, IRC40K off,
RTC off
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
Battery supply
IBAT
current (Backup
mode)
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
52
GD32F305xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL High
—
1.3
—
μA
—
1.2
—
μA
—
1.4
—
μA
—
1.2
—
μA
—
1.1
—
μA
—
1.0
—
μA
—
1.1
—
μA
—
0.9
—
μA
—
0.8
—
μA
—
0.7
—
μA
—
1.0
—
μA
—
0.9
—
μA
—
0.7
—
μA
—
0.6
—
μA
driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
(1). Based on characterization, not tested in production.
(2). Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value.
53
GD32F305xx Datasheet
(3). When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed,
no PLL.
(4). When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed,
using PLL.
(5). When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional
power consumption should be considered.
Figure 4-2. Typical supply current consumption in Run mode
Figure 4-3. Typical supply current consumption in Sleep mode
54
GD32F305xx Datasheet
Table 4-8. Peripheral current consumption characteristics(1)
Peripherials(4)
APB1
ADDAPB1
APB2
Typical consumption at TA = 25 ℃
（TYP）
DAC(2)
0.81
PMU
1.41
BKPI
1.93
CAN1
1.39
CAN0
1.41
I2C1
1.23
I2C0
1.21
UART4
1.24
UART3
1.25
USART2
1.23
USART1
1.24
SPI2
1.17
SPI1
1.23
WWDGT
1.13
TIMER13
1.47
TIMER12
1.44
TIMER11
1.47
TIMER6
1.14
TIMER5
1.12
TIMER4
1.52
TIMER3
2.25
TIMER2
2.23
TIMER1
2.25
CTC
1.13
TIMER10
2.25
TIMER9
2.23
TIMER8
2.24
USART0
2.15
TIMER7
2.66
SPI0
1.87
TIMER0
2.63
ADC1(3)
0.8
ADC0(3)
0.8
GPIOG
1.99
GPIOF
2
GPIOE
1.99
GPIOD
2
GPIOC
2
GPIOB
2
Unit
mA
55
GD32F305xx Datasheet
Typical consumption at TA = 25 ℃
Peripherials(4)
（TYP）
GPIOA
1.29
USBFS
3.58
EXMC
2.59
CRC
1.81
DMA1
1.48
DMA0
1.61
AHB
Unit
(1). Based on characterization, not tested in production.
(2). DEN0 and DEN1 bits in the DAC_CTL register are set to 1, and the converted value set to 0x800.
(3). system clock = fHCLK = 120 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit is set to 1.
(4). If there is no other description, then HXTAL = 25 MHz, system clock = fHCLK = 120 MHz, fAPB1 = fHCLK/2, fAPB2 =
fHCLK.
4.4.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the Table 4-9. EMS characteristics(1), based on the EMS levels and classes
compliant with IEC 61000 series standard.
Table 4-9. EMS characteristics(1)
Symbol
VESD
VFTB
Parameter
Conditions
Voltage applied to all device pins to
induce a functional disturbance
Level/Class
VDD = 3.3 V, TA = 25 °C
LQFP144, fHCLK = 120 MHz
3A
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VDD = 3.3 V, TA = 25 °C
induce a functional disturbance through
LQFP144, fHCLK = 120 MHz
100 pF on VDD and VSS pins
conforms to IEC 61000-4-4
4A
(1). Based on characterization, not tested in production.
4.5.
Power supply supervisor characteristics
Table 4-10. Power supply supervisor characteristics
Symbol
VLVD(1)
Parameter
Conditions
Min
Typ
Max
LVDT = 000(rising edge)
—
2.15
—
LVDT = 000(falling edge)
—
2.04
—
Low voltage
LVDT = 001(rising edge)
—
2.29
—
Detector level selection
LVDT = 001(falling edge)
—
2.19
—
LVDT = 010(rising edge)
—
2.43
—
LVDT = 010(falling edge)
—
2.33
—
Unit
V
56
GD32F305xx Datasheet
Symbol
Parameter
VLVDhyst(2)
LVD hystersis
VPOR(1)
Power on reset threshold
VPDR(1)
Conditions
Min
Typ
Max
LVDT = 011(rising edge)
—
2.57
—
LVDT = 011(falling edge)
—
2.47
—
LVDT = 100(rising edge)
—
2.71
—
LVDT = 100(falling edge)
—
2.6
—
LVDT = 101(rising edge)
—
2.85
—
LVDT = 101(falling edge)
—
2.74
—
LVDT = 110(rising edge)
—
2.99
—
LVDT = 110(falling edge)
—
2.89
—
LVDT = 111(rising edge)
—
3.13
—
LVDT = 111(falling edge)
—
3.03
—
—
—
100
—
mV
—
2.34
—
V
—
1.82
—
V
Power down reset
threshold
—
Unit
VPDRhyst(2)
PDR hysteresis
—
600
—
mV
tRSTTEMPO(2)
Reset temporization
—
2
—
ms
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
4.6.
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up
(LU) test is based on the two measurement methods.
Table 4-11. ESD characteristics(1)
Symbol
VESD(HBM)
VESD(CDM)
Parameter
Conditions
Electrostatic discharge
TA = 25 °C;
voltage (human body model)
JESD22-A114
Electrostatic discharge
TA = 25 °C;
voltage (charge device model)
JESD22-C101
Min
Typ
Max2
Unit
—
—
4000
V
—
—
800
V
(1). Based on characterization, not tested in production.
57
GD32F305xx Datasheet
Table 4-12. Static latch-up characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max2
Unit
—
—
±200
mA
—
—
5.4
V
I-test
LU
TA = 25 °C; JESD78
Vsupply over voltage
(1). Based on characterization, not tested in production.
4.7.
External clock characteristics
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics
Symbol
fHXTAL
RF
(1)
(2)
Parameter
Conditions
Min
Typ
Max
Unit
Crystal or ceramic frequency
2.6 V ≤ VDD ≤ 3.6 V
4
8
32
MHz
Feedback resistor
VDD = 3.3 V
—
400
—
kΩ
—
—
20
30
pF
Recommended matching
CHXTAL
(2) (3)
capacitance on OSCIN and
OSCOUT
Ducy(HXTAL)(2)
Crystal or ceramic duty cycle
—
30
50
70
%
gm(2)
Oscillator transconductance
Startup
—
25
—
mA/V
—
1.25
—
mA
—
1.8
—
ms
Crystal or ceramic operating
IDDHXTAL(1)
VDD = 3.3 V, fHCLK =
fIRC8M = 8 MHz
current
TA = 25 °C
VDD = 3.3 V, fHCLK =
tSUHXTAL(1)
Crystal or ceramic startup time
fIRC8M = 8 MHz
TA = 25 °C
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN
and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer.
For CS, it is PCB and MCU pin stray capacitance.
Table 4-14. High speed external clock characteristics (HXTAL in bypass mode)
Symbol
Parameter
fHXTAL_ext(1)
Typ
Max
Unit
2.6 V ≤ VDD ≤ 3.6 V
1
—
50
MHz
0.7 VDD
—
VDD
V
VSS
—
0.3 VDD
V
voltage
OSCIN input pin low level
(2)
VDD = 3.3 V
voltage
tH/L(HXTAL) (2)
tR/F(HXTAL)
oscillator frequency
Min
OSCIN input pin high level
VHXTALH(2)
VHXTALL
External clock source or
Conditions
(2)
CIN(2)
Ducy(HXTAL)
(2)
OSCIN high or low time
—
5
—
—
ns
OSCIN rise or fall time
—
—
—
10
ns
OSCIN input capacitance
—
—
5
—
pF
Duty cycle
—
40
—
60
%
(1). Based on characterization, not tested in production.
58
GD32F305xx Datasheet
(2). Guaranteed by design, not tested in production.
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic
characteristics
Symbol
Parameter
Crystal or ceramic
fLXTAL(1)
frequency
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
—
32.768
—
kHz
—
—
10
—
pF
—
30
—
70
%
—
4
—
—
6
—
Recommended matching
CLXTAL
(2)(3)
capacitance on OSC32IN
and OSC32OUT
Ducy(LXTAL)(2)
Crystal or ceramic duty
cycle
Lower driving
capability
Medium low driving
gm(2)
Oscillator transconductance
capability
Medium high driving
—
12
—
—
18
—
LXTALDRI[1:0] = 00
—
0.7
—
Crystal or ceramic operating
LXTALDRI[1:0] = 01
—
0.8
—
current
LXTALDRI[1:0] = 10
—
1.0
—
LXTALDRI[1:0] = 11
—
1.3
—
—
—
1.8
—
capability
Higher driving
capability
IDDLXTAL(1)
tSULXTAL(1)(4)
μA/V
Crystal or ceramic startup
time
μA
s
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN
and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic
manufacturer. For CS, it is PCB and MCU pin stray capacitance.
(4). tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator
stabilization flags is SET. This value varies significantly with the crystal manufacturer.
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode)
Symbol
Parameter
fLXTAL_ext(1)
oscillator frequency
Min
Typ
Max
Unit
VDD = 3.3 V
—
32.768
1000
kHz
—
0.7 VDD
—
VDD
OSC32IN input pin high level
VLXTALH(2)
VLXTALL
External clock source or
Conditions
voltage
OSC32IN input pin low level
(2)
voltage
V
—
VSS
—
0.3 VDD
tH/L(LXTAL) (2)
OSC32IN high or low time
—
450
—
—
tR/F(LXTAL) (2)
OSC32IN rise or fall time
—
—
—
50
CIN(2)
OSC32IN input capacitance
—
—
5
—
pF
Duty cycle
—
30
50
70
%
Ducy(LXTAL)
(2)
ns
(1). Based on characterization, not tested in production.
59
GD32F305xx Datasheet
(2). Guaranteed by design, not tested in production.
4.8.
Internal clock characteristics
Table 4-17. High speed internal clock (IRC8M) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = VDDA = 3.3 V
—
8
—
MHz
-2.5
—
+2.5
%
-1.8
—
+1.8
%
VDD = VDDA = 3.3 V, TA = 25 °C -1.0
—
+1.0
%
High Speed Internal
fIRC8M
Oscillator (IRC8M)
frequency
VDD = VDDA = 3.3 V,
TA = -40 °C ~ +85 °C(1)
IRC8M oscillator Frequency
VDD = VDDA = 3.3 V,
accuracy, Factory-trimmed
ACCIRC8M
TA = 0 °C ~ +85 °C(1)
IRC8M oscillator Frequency
—
—
0.5
—
%
DucyIRC8M(2) IRC8M oscillator duty cycle
VDD = VDDA = 3.3 V
45
50
55
%
IRC8M oscillator operating
VDD = VDDA = 3.3 V,
current
fHCLK = fHXTAL_PLL = 120 MHz
—
66
—
μA
IRC8M oscillator startup
VDD = VDDA = 3.3 V,
time
fHCLK = fHXTAL_PLL = 120 MHz
—
5
—
μs
Min
Typ
Max Unit
20
40
45
kHz
—
0.4
—
μA
—
110
—
μs
accuracy, User trimming
step(1)
IDDAIRC8M(1)
tSUIRC8M(1)
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
Table 4-18. Low speed internal clock (IRC40K) characteristics
Symbol
fIRC40K(1)
IDDAIRC40K(2)
tSUIRC40K(2)
Parameter
Conditions
Low Speed Internal oscillator
VDD = VDDA = 3.3 V,
(IRC40K) frequency
TA = -40°C ~ +85 °C
IRC40K oscillator operating
current
IRC40K oscillator startup
time
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 120 MHz
TA = 25 °C
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 120 MHz
TA = 25 °C
(1). Guaranteed by design, not tested in production.
(2). Based on characterization, not tested in production.
60
GD32F305xx Datasheet
Table 4-19. High speed internal clock (IRC48M) characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
High Speed Internal
fIRC48M
Oscillator (IRC48M)
—
48
—
MHz
-4.0
—
+5.0
%
-3.0
—
+3.0
%
-2.0
—
+2.0
%
—
—
0.12
—
%
VDD = VDDA = 3.3 V
45
50
55
%
—
356
—
μA
—
2.7
—
μs
VDD = 3.3 V
frequency
VDD = VDDA = 3.3 V,
TA = -40°C ~+85 °C(1)
IRC48M oscillator
VDD = VDDA = 3.3 V,
Frequency accuracy,
TA = 0 °C ~ +85 °C (1)
Factory-trimmed
VDD = VDDA = 3.3 V,
ACCIRC48M
TA = 25 °C
IRC48M oscillator
Frequency accuracy,
User trimming
DIRC48M(2)
step(1)
IRC48M oscillator duty
cycle
IDDAIRC48M(
IRC48M oscillator
VDD = VDDA = 3.3 V,
1)
operating current
fHCLK = fHXTAL_PLL = 120 MHz
IRC48M oscillator
VDD = VDDA = 3.3 V,
startup time
fHCLK = fHXTAL_PLL = 120 MHz
tSUIRC48M(1)
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
4.9.
PLL characteristics
Table 4-20. PLL characteristics
Symbol
fPLLIN
(1)
fPLLOUT
fVCO
tLOCK(2)
IDDA(1)(3)
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
1
—
25
MHz
PLL output clock frequency
—
16
—
120
MHz
—
32
—
240
MHz
—
—
—
300
μs
VCO freq = 240 MHz
—
680
—
μA
—
35
—
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
Cycle to cycle Jitter
（peak to peak）
ps
System clock
—
371
—
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). System clock = IRC8M = 8 MHz, PLL clock source = IRC8M/2 = 4 MHz, fPLLOUT = 120 MHz.
(4). Value given with main PLL running.
61
GD32F305xx Datasheet
Table 4-21. PLL1 characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLIN(1)
PLL input clock frequency
—
1
—
25
MHz
fPLLOUT
PLL output clock frequency
—
16
—
120
MHz
—
32
—
200
MHz
—
—
—
300
μs
VCO freq = 200 MHz
—
520
—
μA
—
35
—
fVCO
tLOCK(2)
IDDA(1)(3)
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
Cycle to cycle Jitter
System clock
ps
—
（peak to peak）
371
—
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). System clock = IRC8M = 8 MHz, PLL1 clock source = IRC48M = 48 MHz, fPLLOUT = 120 MHz.
(4). Value given with main PLL running.
Table 4-22. PLL2 characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLIN(1)
PLL input clock frequency
—
1
—
25
MHz
fPLLOUT
PLL output clock frequency
—
16
—
120
MHz
—
32
—
200
MHz
—
—
—
300
μs
VCO freq = 200 MHz
—
520
—
μA
—
35
—
fVCO
tLOCK(2)
IDDA(1)(3)
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
Cycle to cycle Jitter
（peak to peak）
System clock
ps
—
371
—
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). System clock = IRC8M = 8 MHz, PLL2 clock source = IRC48M = 48 MHz, fPLLOUT = 120 MHz.
(4). Value given with main PLL running.
62
GD32F305xx Datasheet
4.10.
Memory characteristics
Table 4-23. Flash memory characteristics
Symbol
Parameter
Conditions
Min(1) Typ(1)
Max(2)
Number of guaranteed
PECYC
program /erase cycles
TA = -40 °C ~ +85 °C
100
—
—
before failure (Endurance)
Unit
kcycle
s
tRET
Data retention time
—
—
20
—
years
tPROG
Word programming time
TA = -40°C ~ +85 °C
—
37.5
86
μs
TA = -40°C ~ +85 °C
—
45
200/300(3)
ms
TA = -40°C ~ +85 °C
—
1
4.8/8.0(4)
s
TA = -40°C ~ +85 °C
—
4
19.2/32(5)
s
TA = -40°C ~ +85 °C
—
6
28.8/48(6)
s
Min
Typ
Max
-0.5
—
0.3 VDD
tERASE
tMERASE(256K)
tMERASE(512K)
tMERASE(1MB)
Page erase time
Mass erase time
Mass erase time
Mass erase time
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). Max value with 50K & MDy[1:0]=11 and
GPIOx_SPDy=1
（IO_Speed = MAX）
Maximum
frequency(4)
2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 70
MHz
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 50
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 120
2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 100 MHz
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 60
(1). Based on characterization, not tested in production.
(2). Unless otherwise specified, all test results given for TA = 25 ℃.
(3). The I/O speed is configured using the GPIOx_CTL -> MDy[1:0] bits. Refer to the GD32F30x user manual
which is selected to set the GPIO port output speed.
(4). The maximum frequency is defined in Figure 4-5, and maximum frequency cannot exceed 120 MHz.
Figure 4-5. I/O port AC characteristics definition
90%
EXTERNAL
OUTPU T
ON 50pF
90%
50%
50%
10%
tr(IO)out
10%
tf(IO)out
T
If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved .
The duty cycle is （45%-55%）when loaded by 50 pF
4.13.
ADC characteristics
Table 4-27. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.6
3.3
3.6
V
VIN(1)
ADC input voltage range
—
0
—
VREF+
V
VREF+(2)
Positive Reference Voltage
—
2.4
—
VDDA
V
—
—
VSSA
—
V
VREF-(2)
Negative Reference
Voltage
65
GD32F305xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC(1)
ADC clock
—
0.1
—
40
MHz
12-bit
0.007
—
2.86
10-bit
0.008
—
3.33
MSP
8-bit
0.01
—
4
S
6-bit
0.012
—
5
Analog input voltage
16 external; 2 internal
0
—
VDDA
V
External input impedance
See Equation 1
—
—
32.9
kΩ
—
—
—
0.55
kΩ
—
—
5.5
pF
fS(1)
VAIN(1)
(2)
RAIN
RADC(2)
Sampling rate
Input sampling switch
resistance
No pin/pad capacitance
CADC(2)
Input sampling capacitance
tCAL(2)
Calibration time
fADC = 40 MHz
—
3.275
—
μs
Sampling time
fADC = 40 MHz
0.0375
—
5.99
μs
12-bit
—
14
—
10-bit
—
12
—
1/
8-bit
—
10
—
fADC
6-bit
—
8
—
—
—
—
1
(2)
ts
included
Total conversion
tCONV(2)
time(including sampling
time)
tSU(2)
Startup time
μs
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
Equation 1: RAIN max formula R AIN <
Ts
fADC ∗CADC ∗ln(2N+2 )
− R ADC
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N=12 (from 12-bit resolution).
Table 4-28. ADC RAIN max for fADC = 40 MHz
Ts (cycles)
ts (μs)
RAIN max (kΩ)
1.5
0.0375
0.15
7.5
0.1875
2.96
13.5
0.3375
5.77
28.5
0.7125
12.8
41.5
1.0375
18.9
55.5
1.3875
25.4
71.5
1.7875
32.9
239.5
5.9875
N/A
Table 4-29. ADC dynamic accuracy at fADC = 14 MHz(1)
Symbol
Parameter
ENOB
SNDR
SNR
Test conditions
Min
Typ
Max
Unit
Effective number of bits
fADC = 14 MHz
—
10.8
—
bits
Signal-to-noise and distortion ratio
VDDA = VREF+ = 3.3 V
—
66.7
—
Signal-to-noise ratio
Input Frequency = 20
—
67.4
—
—
-76.3
—
kHz
THD
Total harmonic distortion
Temperature = 25℃
dB
66
GD32F305xx Datasheet
(1). Based on characterization, not tested in production.
Table 4-30. ADC dynamic accuracy at fADC = 40 MHz(1)
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
Effective number of bits
fADC = 40 MHz
—
10
—
SNDR
Signal-to-noise and distortion ratio
VDDA = VREF+ = 3.3 V
—
62
—
SNR
Signal-to-noise ratio
Input Frequency = 20 kHz
—
62.2
—
THD
Total harmonic distortion
Temperature = 25 ℃
—
-68.6
—
Typ
Max
±1
—
±0.9
—
±1
—
bits
dB
(1). Based on characterization, not tested in production.
Table 4-31. ADC static accuracy at fADC = 14 MHz(1)
Symbol
Parameter
Offset
Offset error
DNL
Differential linearity error
INL
Integral linearity error
Test conditions
fADC = 14 MHz
VDDA = VREF+ = 3.3 V
Unit
LSB
(1). Based on characterization, not tested in production.
4.14.
Temperature sensor characteristics
Table 4-32. Temperature sensor characteristics(1)
Symbol
Parameter
Min
Typ
Max
Unit
TL
VSENSE linearity with temperature
—
±1.5
—
℃
Avg_Slope
Average slope
—
4.1
—
mV/℃
V25
Voltage at 25 °C
—
1.45
—
V
ADC sampling time when reading the temperature
—
17.1
—
μs
tS_temp
(2)
(1). Based on characterization, not tested in production.
(2). Shortest sampling time can be determined in the application by multiple iterations.
4.15.
DAC characteristics
Table 4-33. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.6
3.3
3.6
V
VREF+(2)
Positive Reference Voltage
—
2.4
—
VDDA
V
—
—
VSSA
—
V
5
—
—
kΩ
—
—
15
kΩ
—
—
50
pF
0.2
—
—
V
VREF-(2)
RLOAD(2)
Ro(2)
CLOAD(2)
Negative Reference
Voltage
Load resistance
Impedance output with
buffer OFF
Load capacitance
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer ON
Resistive load with
buffer ON
—
No pin/pad capacitance
included
—
67
GD32F305xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
—
—
—
—
—
0.5
—
—
—
—
470
—
uA
—
500
—
uA
—
86
—
uA
—
298
—
uA
DAC in 12-bit mode
—
—
±3
LSB
Integral non-linearity
DAC in 12-bit mode
—
—
±4
LSB
Offset
Offset error
DAC in 12-bit mode
—
—
±12
LSB
GE(1)
Gain error
DAC in 12-bit mode
—
—
±0.5
%
Settling time
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
—
0.3
1
μs
Wakeup from off state
—
—
5
10
μs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
—
—
4
MS/ s
—
55
80
—
dB
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer ON
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer OFF
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer OFF
Max
VDDA0.2
—
VDDA1LSB
Unit
V
mV
V
With no load, middle
code(0x800) on the input, VREF+
IDDA(1)
DAC current consumption
= 3.6 V
in quiescent mode
With no load, worst
code(0xF1C) on the input, VREF+
= 3.6 V
With no load, middle
code(0x800) on the input, VREF+
IDDVREF+(1)
DAC current consumption
= 3.6 V
in quiescent mode
With no load, worst
code(0xF1C) on the input, VREF+
= 3.6 V
DNL(1)
INL(1)
(1)
Tsetting
(1)
Twakeup
(2)
Update
rate(2)
PSRR(2)
Differential non-linearity
error
Max frequency for a correct
DAC_OUT change from
code i to i±1LSBs
Power supply rejection
ratio (to VDDA)
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
68
GD32F305xx Datasheet
4.16.
I2C characteristics
Table 4-34. I2C characteristics(1)(2)
Symbol
Parameter
Conditions
Standard mode Fast mode
Min
Max
Min
Fast mode
plus
Unit
Max Min Max
tSCL(H)
SCL clock high time
—
4.0
—
0.6
—
0.2
—
μs
tSCL(L)
SCL clock low time
—
4.7
—
1.3
—
0.5
—
μs
tsu(SDA)
SDA setup time
—
2
—
0.8
0.1
—
μs
th(SDA)
SDA data hold time
—
250
—
250
—
130
—
ns
tr(SDA/SCL)
SDA and SCL rise time
—
—
1000
20
300
—
120
ns
tf(SDA/SCL)
SDA and SCL fall time
—
4
300
4
300
4
120
ns
—
4.0
—
0.6
—
0.26
—
μs
th(STA)
Start condition hold
time
(1). Guaranteed by design, not tested in production.
(2). Test condition: GPIO_SPEED set 2 MHz and external pull-up resistor value is 1 kΩ when operate EEPROM with
I2C.
4.17.
SPI characteristics
Table 4-35. Standard SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
30
MHz
tSCK(H)
SCK clock high time
tSCK(L)
SCK clock low time
Master mode, fPCLKx = 120 MHz,
presc = 8
Master mode, fPCLKx = 120 MHz,
presc = 8
31.83 33.33 34.83
ns
31.83 33.33 34.83
ns
SPI master mode
tV(MO)
Data output valid time
—
—
5
6
ns
tH(MO)
Data output hold time
—
3
—
—
ns
tSU(MI)
Data input setup time
—
1
—
—
ns
tH(MI)
Data input hold time
—
0
—
—
ns
SPI slave mode
tSU(NSS)
NSS enable setup time
—
0
—
—
ns
tH(NSS)
NSS enable hold time
—
1
—
—
ns
tA(SO)
Data output access time
—
5
—
9
ns
tDIS(SO)
Data output disable time
—
6
—
10
ns
tV(SO)
Data output valid time
—
—
10
12
ns
tH(SO)
Data output hold time
—
8
—
—
ns
tSU(SI)
Data input setup time
—
0
—
—
ns
tH(SI)
Data input hold time
—
1
—
—
ns
(1). Based on characterization, not tested in production.
69
GD32F305xx Datasheet
4.18.
I2S characteristics
Table 4-36. I2S characteristics(1) (2)
Symbol
Parameter
fCK
Clock frequency
Conditions
Master mode (data: 16 bits,
Audio frequency = 96 kHz)
Slave mode
Min
3.075
Typ
Max
3.077 3.079
Unit
MHz
0
—
10
162
—
—
ns
163
—
—
ns
tH
Clock high time
tL
Clock low time
tV(WS)
WS valid time
Master mode
0
—
—
ns
tH(WS)
WS hold time
Master mode
0
—
—
ns
tSU(WS)
WS setup time
Slave mode
0
—
—
ns
tH(WS)
WS hold time
Slave mode
2
—
—
ns
Slave mode
—
50
—
%
Ducy(SCK)
I2S slave input clock duty
cycle
—
tSU(SD_MR)
Data input setup time
Master mode
1
—
—
ns
tsu(SD_SR)
Data input setup time
Slave mode
0
—
—
ns
Master receiver
0
—
—
ns
Slave receiver
1
—
—
ns
—
—
12
ns
7
—
—
ns
—
—
6
ns
2
—
—
ns
tH(SD_MR)
tH(SD_SR)
Data input hold time
tv(SD_ST)
Data output valid time
th(SD_ST)
Data output hold time
tv(SD_MT)
Data output valid time
th(SD_MT)
Data output hold time
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
(1). Guaranteed by design, not tested in production.
(2). Based on characterization, not tested in production.
4.19.
USART characteristics
Table 4-37. USART characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 120 MHz
—
—
60
MHz
tSCK(H)
SCK clock high time
fPCLKx = 120 MHz
7.5
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 120 MHz
7.5
—
—
ns
(1). Guaranteed by design, not tested in production.
70
GD32F305xx Datasheet
4.20.
CAN characteristics
Refer to Table 4-25. I/O port DC characteristics(1) for more details on the input/output
alternate function characteristics (CANTX and CANRX).
4.21.
USBFS characteristics
Table 4-38. USBFS start up time
Symbol
Parameter
Max
Unit
tSTARTUP(1)
USBFS startup time
1
μs
(1). Guaranteed by design, not tested in production.
Table 4-39. USBFS DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
USBFS operating voltage
—
3
—
3.6
VDI Differential input sensitivity
—
0.2
—
—
Includes VDI range
0.8
—
2.5
—
1.3
—
2.0
VDD
Input
levels(1)
VCM
VSE
Differential common mode
range
Single ended receiver
threshold
Max Unit
Output VOL
Static output level low
RL of 1.0 kΩ to 3.6 V
—
0.064
0.3
levels (2)
Static output level high
RL of 15 kΩ to VSS
2.8
3.3
3.6
17
20.574
24
0.65
—
2.0
1.5
1.585
2.1
0.25
0.326 0.55
VOH
RPD(2)
RPU(2)
PA11, PA12(USB_DM/DP)
PA9(USB_VBUS)
PA11, PA12(USB_DM/DP)
PA9(USB_VBUS)
VIN = VDD
VIN = VSS
V
V
kΩ
(1). Guaranteed by design, not tested in production.
(2). Based on characterization, not tested in production.
Table 4-40. USBFS full speed-electrical characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tR
Rise time
CL = 50 pF
4
—
20
ns
tF
Fall time
CL = 50 pF
4
—
20
ns
tRFM
Rise / fall time matching
tR / tF
90
—
110
%
vCRS
Output signal crossover voltage
—
1.3
—
2.0
V
(1). Guaranteed by design, not tested in production.
71
GD32F305xx Datasheet
Figure 4-6. USBFS timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
VCRS
VSS
tf
4.22.
tr
EXMC characteristics
Table 4-41. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
40.5
42.5
ns
tV(NOE_NE)
EXMC_NEx low to EXMC_NOE low
0
—
ns
tw(NOE)
EXMC_NOE low time
40.5
42.5
ns
th(NE_NOE)
EXMC_NOE high to EXMC_NE high hold time
0
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tsu(DATA_NE)
Data to EXMC_NEx high setup time
32.2
—
ns
tsu(DATA_NOE)
Data to EXMC_NOEx high setup time
32.2
—
ns
th(DATA_NOE)
Data hold time after EXMC_NOE high
0
—
ns
th(DATA_NE)
Data hold time after EXMC_NEx high
0
—
ns
tv(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4). Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1;
Table 4-42. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
23.9
25.9
ns
tV(NWE_NE)
EXMC_NEx low to EXMC_NWE low
7.3
—
ns
tw(NWE)
EXMC_NWE low time
7.3
9.3
ns
th(NE_NWE)
EXMC_NWE high to EXMC_NE high hold time
7.3
9.3
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tV(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
15.6
—
ns
th(AD_NADV)
EXMC_AD(address) valid hold time after
EXMC_NADV high
th(A_NWE)
Address hold time after EXMC_NWE high
7.3
—
ns
th(BL_NWE)
EXMC_BL hold time after EXMC_NWE high
7.3
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
72
GD32F305xx Datasheet
tv(DATA_NADV)
EXMC_NADV high to DATA valid
0
—
ns
th(DATA_NWE)
Data hold time after EXMC_NWE high
7.3
—
ns
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4) .Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime= 1, DataSetupTime = 1.
Table 4-43. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
57.1
59.1
ns
tV(NOE_NE)
EXMC_NEx low to EXMC_NOE low
23.9
—
ns
tw(NOE)
EXMC_NOE low time
32.2
34.2
ns
th(NE_NOE)
EXMC_NOE high to EXMC_NE high hold time
0
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tv(A_NOE)
Address hold time after EXMC_NOE high
0
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
th(BL_NOE)
EXMC_BL hold time after EXMC_NOE high
0
—
ns
tsu(DATA_NE)
Data to EXMC_NEx high setup time
33.2
—
ns
tsu(DATA_NOE)
Data to EXMC_NOEx high setup time
33.2
—
ns
th(DATA_NOE)
Data hold time after EXMC_NOE high
0
—
ns
th(DATA_NE)
Data hold time after EXMC_NEx high
0
—
ns
tv(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
7.3
9.3
ns
Th(AD_NADV)
EXMC_AD(adress) valid hold time after
EXMC_NADV high
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4). Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
Table 4-44. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
40.5
42.5
ns
tV(NWE_NE)
EXMC_NEx low to EXMC_NWE low
7.3
—
ns
tw(NWE)
EXMC_NWE low time
23.9
25.9
ns
th(NE_NWE)
EXMC_NWE high to EXMC_NE high hold time
7.3
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tV(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
7.3
—
ns
th(AD_NADV)
EXMC_AD(address) valid hold time after
EXMC_NADV high
th(A_NWE)
Address hold time after EXMC_NWE high
7.3
—
ns
th(BL_NWE)
EXMC_BL hold time after EXMC_NWE high
7.3
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tv(DATA_NADV)
EXMC_NADV high to DATA valid
7.3
—
ns
73
GD32F305xx Datasheet
th(DATA_NWE)
Data hold time after EXMC_NWE high
—
7.3
ns
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4). Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime =1.
Table 4-45. Synchronous multiplexed PSRAM/NOR read timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NOEL)
EXMC_CLK low to EXMC_NOE low
0
—
ns
td(CLKH-NOEH)
EXMC_CLK high to EXMC_NOE high
15.6
—
ns
td(CLKL-ADV)
EXMC_CLK low to EXMC_AD valid
0
—
ns
td(CLKL-ADIV)
EXMC_CLK low to EXMC_AD invalid
0
—
ns
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4). Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; Memory Type = PSRAM; WriteBurst = Enable;
CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); Data Latency = 1.
Table 4-46. Synchronous multiplexed PSRAM write timings
(1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NWEL)
EXMC_CLK low to EXMC_NWE low
0
—
ns
td(CLKH-NWEH)
EXMC_CLK high to EXMC_NWE high
15.6
—
ns
td(CLKL-ADIV)
EXMC_CLK low to EXMC_AD invalid
0
—
ns
td(CLKL-DATA)
EXMC_A/D valid data after EXMC_CLK low
0
—
ns
th(CLKL-NBLH)
EXMC_CLK low to EXMC_NBL high
0
—
ns
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4). Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable;
CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
74
GD32F305xx Datasheet
Table 4-47. Synchronous non-multiplexed PSRAM/NOR read timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NOEL)
EXMC_CLK low to EXMC_NOE low
0
—
ns
td(CLKH-NOEH)
EXMC_CLK high to EXMC_NOE high
15.6
—
ns
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4). Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst =
Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
Table 4-48. Synchronous non-multiplexed PSRAM write timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NWEL)
EXMC_CLK low to EXMC_NWE low
0
—
ns
td(CLKH-NWEH)
EXMC_CLK high to EXMC_NWE high
15.6
—
ns
td(CLKL-DATA)
EXMC_A/D valid data after EXMC_CLK low
0
—
ns
th(CLKL-NBLH)
EXMC_CLK low to EXMC_NBL high
0
—
ns
(1). CL = 30 pF.
(2). Guaranteed by design, not tested in production.
(3). Based on characterization, not tested in production.
(4). Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst =
Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
75
GD32F305xx Datasheet
4.23.
TIMER characteristics
Table 4-49. TIMER characteristics(1)
Symbol
Parameter
tres
Timer resolution time
fEXT
Timer external clock frequency
RES
Timer resolution
tCOUNTER
Conditions
Min
Max
Unit
—
1
—
tTIMERxCLK
fTIMERxCLK = 120 MHz
8.4
—
ns
—
0
fTIMERxCLK/2
MHz
fTIMERxCLK = 120 MHz
0
60
MHz
—
—
16
bit
—
1
65536
tTIMERxCLK
546
μs
16-bit counter clock period
when internal clock is selected
tMAX_COUNT
fTIMERxCLK = 120 MHz 0.0084
Maximum possible count
—
—
fTIMERxCLK = 120 MHz
—
65536x65536 tTIMERxCLK
35.7
s
(1). Guaranteed by design, not tested in production.
4.24.
WDGT characteristics
Table 4-50. FWDGT min/max timeout period at 40 kHz (IRC40K)(1)
Prescaler divider
PR[2:0] bits
1/4
Min timeout RLD[11:0] = Max timeout RLD[11:0]
0x000
= 0xFFF
000
0.1
409.6
1/8
001
0.2
819.2
1/16
010
0.4
1638.4
1/32
011
0.8
3276.8
1/64
100
1.6
6553.6
1/128
101
3.2
13107.2
1/256
110 or 111
6.4
26214.4
Unit
ms
(1). Guaranteed by design, not tested in production.
Table 4-51. WWDGT min-max timeout value at 60 MHz (fPCLK1)(1)
Min timeout value
Prescaler divider
PSC[2:0]
1/1
00
68.27
1/2
01
136.53
1/4
10
273.07
1/8
11
546.13
CNT[6:0] = 0x40
Unit
Max timeout value
CNT[6:0] = 0x7F
Unit
4.37
μs
8.74
17.48
ms
34.96
(1). Guaranteed by design, not tested in production.
4.25.
Parameter conditions
Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 ℃.
76
GD32F305xx Datasheet
5.
Package information
5.1.
LQFP144 package outline dimensions
Figure 5-1. LQFP144 package outline
Table 5-1. LQFP144 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
D
21.80
22.0
22.20
D1
19.90
20.0
20.10
E
21.80
22.0
22.20
E1
19.90
20.0
20.10
θ
0°
3.5°
7°
c
0.13
—
0.17
c1
0.12
0.13
0.14
L
0.45
—
0.75
L1
—
1.0 REF
—
b
0.18
—
0.26
77
GD32F305xx Datasheet
Symbol
Min
Typ
Max
b1
0.17
0.20
0.23
e
—
0.50 BSC
—
(Original dimensions are in millimeters)
5.2.
LQFP100 package outline dimensions
Figure 5-2. LQFP100 package outline
Table 5-2. LQFP100 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
D
15.80
16.0
16.20
D1
13.90
14.0
14.10
E
15.80
16.0
16.20
E1
13.90
14.0
14.10
θ
0°
3.5°
7°
c
0.13
—
0.17
c1
0.12
0.13
0.14
78
GD32F305xx Datasheet
Symbol
Min
Typ
Max
L
0.45
0.6
0.75
L1
—
1.0 REF
—
b
0.18
0.20
0.26
b1
0.17
0.20
0.23
eB
15.05
—
15.35
e
—
0.50 BSC
—
(Original dimensions are in millimeters)
5.3.
LQFP64 package outline dimensions
Figure 5-3. LQFP64 package outline
Table 5-3. LQFP64 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
D
11.80
12.00
12.20
D1
9.90
10.00
10.10
E
11.80
12.00
12.20
E1
9.90
10.00
10.10
79
GD32F305xx Datasheet
Symbol
Min
Typ
Max
θ
0°
3.5°
7°
c
0.13
—
0.17
L
0.45
0.60
0.75
L1
—
1.00 REF
—
b
0.17
0.20
0.27
e
—
0.50 BSC
—
eB
11.25
—
11.45
(Original dimensions are in millimeters)
6.
Ordering information
Table 6-1. Part ordering code for GD32F305xx devices
Ordering code
Flash (KB)
Package
Package type
GD32F305RBT6
128
LQFP64
Green
GD32F305RCT6
256
LQFP64
Green
GD32F305RET6
512
LQFP64
Green
GD32F305RGT6
1024
LQFP64
Green
GD32F305VCT6
256
LQFP100
Green
GD32F305VET6
512
LQFP100
Green
GD32F305VGT6
1024
LQFP100
Green
GD32F305ZCT6
256
LQFP144
Green
GD32F305ZET6
512
LQFP144
Green
GD32F305ZGT6
1024
LQFP144
Green
Temperature
operating range
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
80
GD32F305xx Datasheet
7.
Revision history
Table 7-1. Revision history
Revision No.
Description
Date
1.0
Initial Release
Mar.20, 2017
1.1
Repair history accumulation error
Jan.24, 2018
1.2
Repair history accumulation error
Dec.16, 2018
Add functional description of PD0 and PD1 to the packages
1.3
below 100pin. Update electrical characteristics and package
Mar.6.2020
information.
81
GD32F305xx Datasheet
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