GD32F190C8T6

GigaDevice Semiconductor Inc. GD32F190xx ARM® Cortex®-M3 32-bit MCU Datasheet GD32F190xx Table of Contents List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 General description ......................................................................................................... 5 2 Device overview ............................................................................................................... 6 2.1 Device information .............................................................................................................................. 6 2.2 Block diagram ...................................................................................................................................... 7 2.3 Pinouts and pin assignment .............................................................................................................. 8 2.4 Memory map ...................................................................................................................................... 10 2.5 Clock tree ........................................................................................................................................... 11 2.6 Pin definitions .................................................................................................................................... 12 Functional description .................................................................................................. 20 3 3.1 ARM® Cortex®-M3 core .................................................................................................................... 20 3.2 On-chip memory................................................................................................................................ 20 3.3 Clock, reset and supply management ........................................................................................... 21 3.4 Boot modes ........................................................................................................................................ 21 3.5 Power saving modes ........................................................................................................................ 22 3.6 Analog to digital converter (ADC) ................................................................................................... 22 3.7 Digital to analog converter (DAC) ................................................................................................... 23 3.8 DMA .................................................................................................................................................... 23 3.9 General-purpose inputs/outputs (GPIOs) ...................................................................................... 23 3.10 Timers and PWM generation........................................................................................................... 24 3.11 Real time clock (RTC) ...................................................................................................................... 25 3.12 Inter-integrated circuit (I2C) ............................................................................................................. 25 3.13 Serial peripheral interface (SPI)...................................................................................................... 26 3.14 Universal synchronous asynchronous receiver transmitter (USART) ....................................... 26 3.15 Inter-IC sound (I2S) .......................................................................................................................... 26 3.16 HDMI CEC ......................................................................................................................................... 27 3.17 Touch sensing interface (TSI) ......................................................................................................... 27 3.18 Comparators (CMP) ......................................................................................................................... 27 3.19 Operational amplifiers (OP-AMP) ................................................................................................... 27 3.20 LCD controller (LCD) ........................................................................................................................ 28 3.21 Controller area network (CAN) ........................................................................................................ 28 3.22 Debug mode ...................................................................................................................................... 28 3.23 Package and operation temperature.............................................................................................. 28 Electrical characteristics .............................................................................................. 29 4 4.1 Absolute maximum ratings .............................................................................................................. 29 4.2 Recommended DC characteristics ................................................................................................. 29 4.3 Power consumption .......................................................................................................................... 30 1 / 46 GD32F190xx 4.4 EMC characteristics .......................................................................................................................... 31 4.5 Power supply supervisor characteristics ....................................................................................... 31 4.6 Electrical sensitivity........................................................................................................................... 32 4.7 External clock characteristics .......................................................................................................... 32 4.8 Internal clock characteristics ........................................................................................................... 33 4.9 PLL characteristics ........................................................................................................................... 34 4.10 Memory characteristics .................................................................................................................... 34 4.11 GPIO characteristics......................................................................................................................... 35 4.12 ADC characteristics .......................................................................................................................... 36 4.13 DAC characteristics .......................................................................................................................... 37 4.14 SPI characteristics ............................................................................................................................ 38 4.15 I2C characteristics ............................................................................................................................ 38 4.16 USART characteristics ..................................................................................................................... 38 4.17 Operational amplifier characteristics .............................................................................................. 39 4.18 Comparators characteristics............................................................................................................ 40 Package information ..................................................................................................... 41 5 5.1 QFN package outline dimensions .................................................................................................. 41 5.2 LQFP package outline dimensions ................................................................................................ 42 6 Ordering Information ..................................................................................................... 44 7 Revision History............................................................................................................. 45 2 / 46 GD32F190xx List of Figures Figure 1. GD32F190xx block diagram ...................................................................................................................... 7 Figure 2. GD32F190Rx LQFP64 pinouts ................................................................................................................. 8 Figure 3. GD32F190Cx LQFP48 pinouts ................................................................................................................. 8 Figure 4. GD32F190Tx QFN36 pinouts ................................................................................................................... 9 Figure 5. GD32F190xx memory map ..................................................................................................................... 10 Figure 6. GD32F190xx clock tree............................................................................................................................ 11 Figure 7. QFN package outline ................................................................................................................................ 41 Figure 8. LQFP package outline .............................................................................................................................. 42 3 / 46 GD32F190xx List of Tables Table 1. GD32F190xx devices features and peripheral list ................................................................................... 6 Table 2. GD32F190xx pin definitions ...................................................................................................................... 12 Table 3. Port A alternate functions summary ........................................................................................................ 17 Table 4. Port B alternate functions summary ........................................................................................................ 18 Table 5. Port C & D & F alternate functions summary ......................................................................................... 19 Table 6. Absolute maximum ratings ........................................................................................................................ 29 Table 7. DC operating conditions ............................................................................................................................ 29 Table 8. Power consumption characteristics ......................................................................................................... 30 Table 9. EMS characteristics ................................................................................................................................... 31 Table 10. EMI characteristics................................................................................................................................... 31 Table 11. Power supply supervisor characteristics .............................................................................................. 31 Table 12. ESD characteristics.................................................................................................................................. 32 Table 13. Static latch-up characteristics ................................................................................................................ 32 Table 14. High speed external clock (HSE) generated from a crystal/ceramic characteristics ...................... 32 Table 15. Low speed external clock (LSE) generated from a crystal/ceramic characteristics ....................... 33 Table 16. High speed internal clock (HSI) characteristics ................................................................................... 33 Table 17. Low speed internal clock (LSI) characteristics ..................................................................................... 33 Table 18. PLL characteristics ................................................................................................................................... 34 Table 19. Flash memory characteristics ................................................................................................................. 34 Table 20. I/O port characteristics ............................................................................................................................. 35 Table 21. ADC characteristics .................................................................................................................................. 36 Table 22. ADC RAIN max for fADC=28MHz ................................................................................................................. 36 Table 23. DAC characteristics ................................................................................................................................. 37 Table 24. SPI characteristics .................................................................................................................................... 38 Table 25. I2C characteristics .................................................................................................................................... 38 Table 26. USART characteristics ............................................................................................................................ 38 Table 27. OP-AMP characteristics .......................................................................................................................... 39 Table 28. CMP characteristics ................................................................................................................................. 40 Table 29. QFN package dimensions ....................................................................................................................... 41 Table 30. LQFP package dimensions ..................................................................................................................... 43 Table 31. Part ordering code for GD32F190xx devices ....................................................................................... 44 Table 32. Revision history......................................................................................................................................... 45 4 / 46 GD32F190xx 1 General description The GD32F190xx device belongs to the 5V value line of GD32 MCU family. It is a 32-bit general-purpose microcontroller based on the high performance ARM® Cortex®-M3 RISC core with best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F190xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating at 72 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 64 KB on-chip Flash memory and up to 8 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to five general-purpose 16-bit timers, a general-purpose 32-bit timer, a basic timer, a PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs and two USARTs, two I2S, two CAN2.0B with a CAN PHY, and a segment LCD controller. Advanced analog peripherals including one 12-bit ADC, two 12-bit DACs, three OP-AMPs and two comparators. The device operates from a 2.5 to 5.5V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F190xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, home appliances, E-bike and so on. 5 / 46 GD32F190xx 2 Device overview 2.1 Device information Table 1. GD32F190xx devices features and peripheral list GD32F190xx Part Number T6 T8 C4 C6 C8 R4 R6 R8 Flash (KB) 16 32 64 16 32 64 16 32 64 SRAM (KB) 4 6 8 4 6 8 4 6 8 32-bit GP 1 1 1 1 1 1 1 1 1 16-bit GP 5 5 5 5 5 5 5 5 5 16-bit Adv. 1 1 1 1 1 1 1 1 1 16-bit Basic 1 1 1 1 1 1 1 1 1 SysTick 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 USART 1 2 2 1 2 2 1 2 2 I2C 1 1 3 1 1 3 1 1 3 SPI 1 1 3 1 1 3 1 1 3 I2S 1 1 2 1 1 2 1 1 2 CAN 2.0B 2 2 2 2 2 2 2 2 2 LCD 0 0 0 4x18 4x18 4x18 8x32 8x32 8x32 GPIO 28 28 28 39 39 39 55 55 55 Capacitive Touch Channels 14 14 14 17 17 17 18 18 18 OP-AMP 2 2 2 2 2 2 3 3 3 Analog Comparator 2 2 2 2 2 2 2 2 2 EXTI 16 16 16 16 16 16 16 16 16 Units 1 1 1 1 1 1 1 1 1 Channels (Ext.) 10 10 10 10 10 10 16 16 16 Channels (Int.) 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 ADC Connectivity Timers T4 DAC Package QFN36 LQFP48 LQFP64 6 / 46 GD32F190xx 2.2 Block diagram Figure 1. GD32F190xx block diagram LDO 1.8V TPIU SW System NVIC AHB Matrix ICode DCode ARM Cortex-M3 Processor Fmax: 72MHz AHB2: Fma x = 72MHz IBus GPIO Ports A, B, C, D, F SRAM Controller SRAM Flash Memory Controller Flash Memory POR/PDR LVD PLL Touch Sensing Interface DBus GP DMA 7chs AHB1: Fma x = 72MHz AHB to APB Bridge 2 CRC AHB to APB Bridge 1 Fmax: 72MHz HSE 4-32MHz HSI 8MHz RST/CLK Controller HSI28 28MHz LSI 40KHz Powered by LDO (1.8V) Powered by V DD/VDDA PWR EXTI IWDG 12-bit SAR ADC ADC WWDG RTC USART1 BXCAN1 SPI1/I2S1 TIMER1 TIMER15 TIMER16 TIMER17 APB1: Fmax = 72MHz Comparator 2 CMP APB2: Fmax = 72MHz SYS Config Comparator 1 CAN SRAM BXCAN2 HDMI-CEC I2C1~3 DAC1~2 12-bit DAC USART2 SPI2 SPI3/I2S3 TIMER6 TIMER2 TIMER3 TIMER14 LCD OPAMP IVREF 7 / 46 GD32F190xx 2.3 Pinouts and pin assignment Figure 2. GD32F190Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PC12 PD2 PB3 PB4 PB6 PB5 PB7 BOOT0 PB8 PB9 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 PC13 2 47 PF6 PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT PF0-OSC_IN 4 45 PA12 5 44 PA11 PF1-OSC_OUT 6 43 PA10 7 42 PA9 NRST PC0 8 PC1 9 PC2 PC3 VSSA GigaDevice GD32F190Rx LQFP64 PF7 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VSS PB11 PB10 PB2 PB1 PB0 PC5 PA7 PC4 PA5 PA6 PA4 PF5 PF4 PA3 Figure 3. GD32F190Cx LQFP48 pinouts PA14 PA15 PB3 PB4 PB6 PB5 PB7 BOOT0 PB8 PB9 VSS VDD 48 47 46 45 44 43 42 41 40 39 38 37 VBAT 1 36 PF7 PF6 PC13 2 35 PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT PF0-OSC_IN 4 33 PA12 5 32 PA11 PF1-OSC_OUT NRST VSSA 6 31 PA10 30 PA9 8 29 VDDA 9 28 PA8 PB15 PA0 10 27 PB14 PA1 PA2 11 26 PB13 12 25 PB12 GigaDevice GD32F190Cx LQFP48 7 13 14 15 16 17 18 19 20 21 22 23 24 VDD VSS PB11 PB10 PB2 PB1 PA7 PB0 PA6 PA5 PA4 PA3 8 / 46 GD32F190xx Figure 4. GD32F190Tx QFN36 pinouts PA2 PA14 PA1 PA15 PA0-WKUP PB3 PB4 VDDA PB5 OSC_OUT/PF1 NRST VSSA PB6 OSC_IN/PF0 PB7 BOOT0 VSS VDD 36 35 34 33 32 31 30 29 28 1 27 2 26 PF7 PF6 3 25 PA13 4 24 PA12 5 GigaDevice GD32F190Tx 23 QFN36 6 22 7 21 PA11 PA9 8 PA8 20 9 19 10 11 12 13 14 15 16 17 18 PA10 VDD VSS PB2 PB1 PA7 PB0 PA6 PA5 PA4 PA3 9 / 46 GD32F190xx 2.4 Memory map Figure 5. GD32F190xx memory map 0x5000 0000 0x4800 1800 0x4800 1400 0x4800 1000 0x4800 0C00 0x4800 0800 0x4800 0400 0x4800 0000 0x4002 4400 0x4002 4000 0x4002 3400 0x4002 3000 0x4002 2400 0x4002 2000 0x4002 1400 0x4002 1000 0x4002 0400 0x4002 0000 0x4001 4C00 0x4001 4800 0x4001 4400 0x4001 4000 0x4001 3C00 0x4001 3800 0x4001 3400 0x4001 3000 0x4001 2C00 0x4001 2800 0x4001 2400 0x4001 0800 0xFFFF FFFF 7 0xE010 0000 0x1FFF FFFF 0x1FFF F80F reserved Option Bytes reserved 0xE000 0000 Cortex-M3 Internal Peripherals 6 reserved 0x1FFF F800 0x4001 0400 0x4001 0000 0x4000 C400 0x4000 C000 0x4000 8000 0x4000 7C00 0x4000 7800 0xC000 0000 System memory 0x4000 7400 0x4000 7000 5 reserved 0x4000 6C00 0x4000 6800 0x1FFF EC00 0xA000 0000 0x4000 6400 0x4000 6000 4 reserved 0x4000 5C00 0x4000 5800 reserved 0x8000 0000 0x4000 5400 0x4000 4800 3 reserved 0x4000 4400 0x4000 4000 0x6000 0000 2 0x5000 0000 0x4000 3C00 reserved Peripherals 0x4000 0000 0x0801 FFFF 1 Flash memory 0x0800 0000 Aliased to Flash or system memory according to BOOT 0x0000 0000 pins configuration 0x2000 0000 0x4000 3800 0x4000 3400 0x4000 3000 0x4000 2C00 reserved SRAM 0x4000 2800 0x4000 2400 0x4000 2000 0x4000 1400 0x4000 1000 0 reserved 0x4000 0800 0x4000 0400 0x0000 0000 0x4000 0000 reserved Port F reserved Port D Port C Port B Port A reserved TSI reserved CRC reserved FMC reserved RCC reserved DMA reserved TIMER17 TIMER16 TIMER15 reserved USART1 reserved SPI1/I2S1 TIMER1 reserved ADC reserved EXTI SYSCFG + CMP reserved I2C3 reserved OPAMP+IVREF CEC DAC1~2 PWR reserved BXCAN2 BXCAN1 CAN SRAM (256B) reserved I2C2 I2C1 reserved USART2 reserved SPI3/I2S3 SPI2 reserved IWDG WWDG RTC LCD TIMER14 reserved TIMER6 reserved TIMER3 TIMER2 10 / 46 GD32F190xx 2.5 Clock tree Figure 6. GD32F190xx clock tree CK_LSE ÷24 4 1 CK_CEC (to CEC) 0 CECSEL CK_I2S (to I2S) CK_FMC SCS[1:0 ] FMC enable (by hardware) (to FMC) HCLK CK_HSI 00 8 MHz HSI RC / 2 0 PLL 1 CK_PLL 1 0 AHB enable CK_SYS 72 MHz max AHB Prescaler ÷1,2...512 (to AHB bus,Cortex-M3,SRAM,DMA) CK_CST CK_AHB ÷8 72 MHz max (to Cortex-M3 SysTick) FCLK HSEPRED V 4-32 MHz HSE XTAL PLLSEL PLLEN 01 Clock Monitor ÷1,2. ..16 (free running clock) TIMER2,3,6,1 4 ÷[apb1 prescaler/2] CK_TIMERx TIMERx enable to TIM2,3,6,14 CK_HSE /32 APB1 Prescaler ÷1,2,4,8,16 11 CK_APB1 PCLK1 to APB1 peripherals 72 MHz max Peripheral enable 32.768 KHz LSE OSC 0 1 CK_RTC(CK_LCD) (to RTC or LCD) 10 RTCSRC[1:0] 40 KHz LSI RC CK_IWDG (to IWDG) TIMER1,15,1 6,17 ÷[apb2 prescaler/2] APB2 Prescaler ÷1,2,4,8,16 CK_TIMERx to TIM1,15,16,17 TIMERx enable CK_APB2 PCLK2 to APB2 peripherals 72 MHz max Peripheral enable CK_OUT ÷1,2,4...128 CKOUTDIV CK_OUT2 ÷1,2,3...64 CKOUT2DIV 0 CK_HSI28 CK_LSI CK_LSE CK_SYS CK_HSI CK_HSE CK_PLL *1,2 0 CK_HSI28 CK_LSI CK_LSE CK_SYS CK_HSI CK_HSE CK_PLL *1,2 ADC Prescaler ÷2,4,6,8 1 CK_ADCX to ADC1 0 28 MHz max ADCSEL 28 MHz HSI RC ÷1,2 CK_HSI 11 CK_LSE 10 0 1 00 CK_SYS CK_USART 1 to USART1 Legend: HSE = High speed external clock HSI = High speed internal clock LSE = Low speed external clock LSI = Low speed internal clock 11 / 46 GD32F190xx 2.6 Pin definitions Table 2. GD32F190xx pin definitions RTC PC14-OSC32_IN PC15OSC32_OUT PF0-OSC_IN 1 1 - P 2 2 - I/O 3 3 - I/O 4 4 - I/O 5 5 2 I/O PF1-OSC_OUT 6 6 3 I/O NRST 7 7 4 I/O I/O(2) Level Pin Type(1) PC13-TAMPER- QFN36 VLCD/VBAT LQFP48 Pin Name LQFP64 Pins Functions description Default: VLCD/VBAT Default: PC13 Additional: RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2 Default: PC14 Additional: OSC32_IN Default: PC15 Additional: OSC32_OUT HVT HVT Default: PF0 Additional: OSC_IN Default: PF1 Additional: OSC_OUT Default: NRST Default: PC0 PC0 8 - - I/O Alternate: EVENTOUT, I2C3_SCL, SEG18 Additional: ADC_IN10 Default: PC1 PC1 9 - - I/O Alternate: EVENTOUT, I2C3_SDA, SEG19 Additional: ADC_IN11, OPAMP3_VINP Default: PC2 PC2 10 - - I/O Alternate: EVENTOUT, I2C3_SMBA, SEG20 Additional: ADC_IN12, OPAMP3_VINM Default: PC3 PC3 11 - - I/O Alternate: EVENTOUT Additional: ADC_IN13, OPAMP3_VOUT, SEG21, I2C3_TXFRAME VSSA 12 8 5 P Default: VSSA VDDA 13 9 6 P Default: VDDA Default: PA0 PA0-WKUP 14 10 7 I/O Alternate: USART1_CTS(3), USART2_CTS(4), TM2_CH1_ETR, I2C2_SCL, CMP1_OUT, TSI_G1_IO1 Additional: ADC_IN0, RTC_TAMP2, WKUP1, CMP1_INM6 Default: PA1 PA1 15 11 8 I/O Alternate: USART1_RTS(3), USART2_RTS(4), TM2_CH2, I2C2_SDA, EVENTOUT, SEG0, TSI_G1_IO2 Additional: ADC_IN1, CMP1_INP, OPAMP1_VINP Default: PA2 PA2 16 12 9 I/O Alternate: USART1_TX(3), USART2_TX(4), TM2_CH3, TM15_CH1, SEG1, CMP2_OUT, TSC_G1_IO3, I2C2_SMBA 12 / 46 GD32F190xx I/O(2) Level Pin Type(1) QFN36 LQFP48 Pin Name LQFP64 Pins Functions description Additional: ADC_IN2, CMP2_INM6, OPAMP1_VINM Default: PA3 PA3 17 13 10 Alternate: USART1_RX(3), USART2_RX(4), TM2_CH4, TM15_CH2, I/O SEG2, TSI_G1_IO4, I2C2_TXFRAME Additional: ADC_IN3, CMP2_INP, OPAMP1_VOUT PF4 PF5 18 19 - - I/O I/O HVT HVT Default: PF4 Alternate: EVENTOUT, SEG28 Default: PF5 Alternate: EVENTOUT, SEG29 Default: PA4 PA4 20 14 11 I/O Alternate: SPI1_NSS, USART1_CK(3), USART2_CK(4), TM14_CH1, SPI2_NSS, I2S1_WS, TSI_G2_IO1, SPI3_NSS, I2S3_WS Additional: ADC_IN4, CMP1_INM4, CMP2_INM4, DAC1_OUT Default: PA5 PA5 21 15 12 I/O Alternate: SPI1_SCK, TM2_CH1_ETR, I2S1_CK, CEC, TSI_G2_IO2 Additional: ADC_IN5, CMP1_INM5, CMP2_INM5, DAC2_OUT, CANH Default: PA6 PA6 22 16 13 I/O Alternate: SPI1_MISO, TM3_CH1, TM1_BKIN, TM16_CH1, EVENTOUT, I2S1_MCK, CMP1_OUT, TSI_G2_IO3, SEG3 Additional: ADC_IN6, OPAMP2_VINP, CANL Default: PA7 Alternate: SPI1_MOSI, TM3_CH2, TM14_CH1, TM1_CH1N, PA7 23 17 14 I/O TM17_CH1, EVENTOUT, I2S1_SD, CMP2_OUT, TSI_G2_IO4, SEG4 Additional: ADC_IN7, OPAMP2_VINM Default: PC4 PC4 24 - - I/O Alternate: EVENTOUT, SEG22 Additional: ADC_IN14 Default: PC5 PC5 25 - - I/O Alternate: TSI_G3_IO1, SEG23 Additional: ADC_IN15 Default: PB0 PB0 26 18 15 I/O Alternate: TM3_CH3, TM1_CH2N, USART2_RX, EVENTOUT TSI_G3_IO2, SPI3_NSS, I2S3_WS, SEG5 Additional: ADC_IN8, VLCD_Rail3, IREF, OPAMP2_VOUT Default: PB1 PB1 27 19 16 I/O Alternate: TM3_CH4, TM14_CH1, TM1_CH3N, SPI2_SCK, TSI_G3_IO3, SEG6 Additional: ADC_IN9, VREF Default: PB2 PB2 28 20 17 I/O HVT Alternate: TSI_G3_IO4 Additional: VLCD_Rail2 13 / 46 GD32F190xx I/O(2) Level Pin Type(1) QFN36 LQFP48 Pin Name LQFP64 Pins Functions description Default: PB10 PB10 29 21 - I/O HVT Alternate: I2C2_SCL(4), CEC, TIM2_CH3, TSI_SYNC, I2C1_SCL(3), SEG10, SPI2_IO2 Default: PB11 PB11 30 22 - I/O HVT Alternate: I2C2_SDA(4), TM2_CH4, EVENTOUT, TSI_G6_IO1, I2C1_SDA(3), SEG11, SPI2_IO3 VSS 31 23 18 P Default: VSS VDD 32 24 19 P Default: VDD Default: PB12 Alternate: SPI1_NSS(3), SPI2_NSS(4), TM1_BKIN, I2C2_SMBA, PB12 33 25 - I/O HVT EVENTOUT, TSI_G6_IO2, SEG12, CAN2_RX Additional: VLCD_Rail1 Default: PB13 PB13 34 26 - I/O PB14 35 27 - I/O (3) (4) HVT Alternate: SPI1_SCK , SPI2_SCK , TM1_CH1N, TSI_G6_IO3, SEG13, I2C2_TXFRAME, CAN2_TX Default: PB14 HVT Alternate: SPI1_MISO(3), SPI2_MISO(4), TM1_CH2N, TM15_CH1 TSI_G6_IO4, SEG14 Default: PB15 Alternate: SPI1_MOSI(3), SPI2_MOSI(4), TIM1_CH3N, TM15_CH1N, PB15 36 28 - I/O HVT TM15_CH2, SEG15 Additional: RTC_REFIN PC6 37 - - I/O HVT PC7 38 - - I/O HVT PC8 39 - - I/O HVT PC9 40 - - I/O HVT Default: PC6 Alternate: TM3_CH1, SEG24, I2C3_TXFRAME Default: PC7 Alternate: TM3_CH2, I2C3_SCL, SEG25 Default: PC8 Alternate: TM3_CH3, I2C3_SDA, SEG26 Default: PC9 Alternate: TM3_CH4, I2C3_SMBA, SEG27, MCO2 Default: PA8 PA8 41 29 20 I/O HVT Alternate: USART1_CK, TM1_CH1, MCO, USART2_TX, EVENTOUT, COM0, I2C1_TXFRAME Default: PA9 PA9 42 30 21 I/O HVT Alternate: USART1_TX, TM1_CH2, TM15_BKIN , I2C1_SCL, TSI_G4_IO1, COM1, SPI2_IO2 Default: PA10 PA10 43 31 22 I/O HVT Alternate: USART1_RX, TM1_CH3, TM17_BKIN, I2C1_SDA, TSI_G4_IO2, COM2, SPI2_IO3 PA11 44 32 23 I/O HVT Alternate: USART1_CTS, TM1_CH4, EVENTOUT, CMP1_OUT, Default: PA11 TSI_G4_IO3, CAN1_RX 14 / 46 GD32F190xx I/O(2) Level Pin Type(1) QFN36 LQFP48 Pin Name LQFP64 Pins Functions description Default: PA12 PA12 45 33 24 I/O HVT Alternate: USART1_RTS, TM1_ETR, EVENTOUT, CMP2_OUT, TSI_G4_IO4, CAN1_TX PA13 46 34 25 I/O HVT PF6 47 35 26 I/O HVT PF7 48 36 27 I/O HVT PA14 49 37 28 I/O HVT Default: PA13/SWDAT Alternate: IR_OUT, SWDAT,SPI2_MISO, I2C1_SMBA Default: PF6 Alternate: I2C2_SCL(4), I2C1_SCL(3), SEG30 Default: PF7 Alternate: I2C2_SDA(4), I2C1_SDA(3), SEG31 Default: PA14/SWCLK Alternate: USART1_TX(3), USART2_TX(4), SWCLK, SPI2_MOSI Default: PA15 PA15 50 38 29 I/O HVT Alternate: SPI1_NSS , USART1_RX(3), USART2_RX(4), TM2_CH1_ETR, SPI2_NSS, EVENTOUT, I2S1_WS, SPI3_NSS, I2S3_WS, SEG17, I2C1_SMBA Default: PC10 PC10 51 - - I/O HVT PC11 52 - - I/O HVT PC12 53 - - I/O HVT PD2 54 - - I/O HVT PB3 55 39 30 I/O HVT Alternate: SPI1_SCK, TM2_CH2, EVENTOUT, I2S1_CK, Alternate: SPI3_SCK, I2S3_CK, COM4, SEG28 Default: PC11 Alternate: SPI3_MISO, I2S3_MCK, COM5, SEG29 Default: PC12 Alternate: SPI3_MOSI, I2S3_SD, COM6, SEG30 Default: PD2 Alternate: TM3_ETR, COM7, SEG31 Default: PB3 TSI_G5_IO1, SPI3_SCK, I2S3_CK, SEG7, I2C1_TXFRAME Default: PB4 PB4 56 40 31 I/O HVT Alternate: SPI1_MISO, TM3_CH1, EVENTOUT, I2S1_MCK, TSI_G5_IO2, SPI3_MISO, I2S3_MCK, SEG8, I2C3_SMBA Default: PB5 PB5 57 41 32 I/O HVT Alternate: SPI1_MOSI, I2C1_SMBA, TM16_BKIN, TM3_CH2, I2S1_SD, SPI3_MOSI, I2S3_SD, SEG9, I2C3_TXFRAME, CAN2_RX Default: PB6 PB6 58 42 33 I/O HVT Alternate: I2C1_SCL, USART1_TX, TM16_CH1N, TSI_G5_IO3, I2C3_SCL, CAN2_TX Default: PB7 PB7 59 43 34 I/O HVT Alternate: I2C1_SDA, USART1_RX, TM17_CH1N, TSI_G5_IO4, I2C3_SDA BOOT0 60 44 35 I Default: BOOT0 Default: PB8 PB8 61 45 - I/O HVT Alternate: I2C1_SCL, TM16_CH1, CEC, TSI_SYNC, SEG16, CAN1_RX 15 / 46 GD32F190xx I/O(2) Level Pin Type(1) QFN36 LQFP48 Pin Name LQFP64 Pins Functions description Default: PB9 - 62 46 VSS 63 47 36 P Default: VSS VDD 64 48 P Default: VDD 1 I/O HVT Alternate: I2C1_SDA, IR_OUT, TM17_CH1, EVENTOUT, COM3, CAN1_TX PB9 Notes: 1. Type: I = input, O = output, P = power. 2. I/O Level: HVT = High Voltage Tolerant. 3. This feature is available on GD32F190x4 devices only. 4. This feature is available on GD32F190x8 and GD32F190x6 devices only. 16 / 46 GD32F190xx Table 3. Port A alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 TSI_G1_IO1 I2C2_SCL AF5 AF6 USART1_CTS(1) TM2_CH1_ PA0 USART2_CTS(2) AF7 AF9 AF11 CMP1_O UT ETR USART1_RTS(1) PA1 EVENTOUT TM2_CH2 TSI_G1_IO2 I2C2_SDA TM2_CH3 TSI_G1_IO3 I2C2_SMBA SEG0 USART2_RTS(2) USART1_TX(1) PA2 TM15_CH1 CMP2_O SEG1 USART2_TX(2) UT USART1_RX(1) PA3 TM15_CH2 I2C2_TXFRA TM2_CH4 TSI_G1_IO4 SEG2 USART2_RX(2) SPI1_NSS ME USART1_CK(1) SPI3_NSS/ PA4 TSI_G2_IO1 I2S1_WS USART2_CK(2) SPI1_SCK I2S3_WS TM2_CH1_ CEC PA5 SPI2_NSS TM14_CH1 I2S1_CK TSI_G2_IO2 ETR SPI1_MISO PA6 CMP1_O TM3_CH1 TM1_BKIN TSI_G2_IO3 TM16_CH1 EVENTOUT SPI1_MOSI PA7 SEG3 UT I2S1_MCK CMP2_O TM3_CH2 TM1_CH1N TSI_G2_IO4 TM14_CH1 TM17_CH1 EVENTOUT SEG4 UT I2S1_SD I2C1_TXFR PA8 MCO USART1_CK TM1_CH1 EVENTOUT USART2_TX COM0 AME PA9 TM15_BKIN USART1_TX TM1_CH2 TSI_G4_IO1 I2C1_SCL SPI2_IO2 COM1 PA10 TM17_BKIN USART1_RX TM1_CH3 TSI_G4_IO2 I2C1_SDA SPI2_IO3 COM2 PA11 EVENTOUT USART1_CTS TM1_CH4 TSI_G4_IO3 CMP1_O CAN1_RX UT CMP2_O PA12 EVENTOUT USART1_RTS TM1_ETR TSI_G4_IO4 CAN1_TX UT PA13 SWDAT IR_OUT I2C1_SMBA SPI2_MISO USART1_TX(1) PA14 SWCLK SPI2_MOSI USART2_TX(2) SPI1_NSS USART1_RX(1) TM2_CH1_ I2S1_WS USART2_RX(2) SPI3_NSS EVENTOUT PA15 SPI2_NSS I2C1_SMBA ETR SEG17 I2S3_WS 1. This feature is available on GD32F190x4 devices only. 2. This feature is available on GD32F190x8 and GD32F190x6 devices only. 17 / 46 GD32F190xx Table 4. Port B alternate functions summary Pin Name AF0 AF1 AF2 PB0 EVENTOUT TM3_CH3 TM1_CH2N AF3 AF4 AF5 AF6 AF7 AF9 AF11 SPI3_NSS SEG5 TSI_G3_IO2 USART2_RX I2S3_WS PB1 TM14_CH1 TM3_CH4 TM1_CH3N PB2 TSI_G3_IO3 SPI2_SCK SEG6 TSI_G3_IO4 I2C1_TXFRA SPI3_SCK SPI1_SCK EVETOUT PB3 TM2_CH2 SEG7 TSI_G5_IO1 ME I2S1_CK SPI1_MISO SPI3_MISO TM3_CH1 PB4 EVENTOUT TSI_G5_IO2 I2C3_SMBA I2S1_MCK SEG8 I2S3_MCK I2C3_TXFRA SPI3_MOSI SPI1_MOSI TM3_CH2 PB5 I2S3_CK TM16_BKIN I2C1_SMBA CAN2_RX I2S1_SD ME PB6 USART1_TX I2C1_SCL TM16_CH1N TSI_G5_IO3 I2C3_SCL PB7 USART1_RX I2C1_SDA TM17_CH1N TSI_G5_IO4 I2C3_SDA SEG9 I2S3_SD CAN2_TX PB8 CEC I2C1_SCL TM16_CH1 TSI_SYNC CAN1_RX SEG16 PB9 IR_OUT I2C1_SDA TM17_CH1 EVENTOUT CAN1_TX PB10 CEC TM2_CH3 TSI_SYNC SPI2_IO2 SEG10 TM2_CH4 TSI_G6_IO1 SPI2_IO3 SEG11 EVENTOUT TM1_BKIN TSI_G6_IO2 TM1_CH1N TSI_G6_IO3 COM3 I2C1_SCL(1) I2C2_SCL(2) I2C1_SDA(1) PB11 EVENTOUT I2C2_SDA(2) SPI1_NSS(1) PB12 I2C2_SMBA CAN2_RX SEG12 SPI2_NSS(2) SPI1_SCK(1) PB13 I2C2_TXFRA SPI2_SCK(2) CAN2_TX SEG13 ME SPI1_MISO(1) PB14 TM15_CH1 TM1_CH2N TSI_G6_IO4 SEG14 TM15_CH2 TM1_CH3N TM15_CH1N SEG15 SPI2_MISO(2) SPI1_MOSI(1) PB15 SPI2_MOSI(2) 1. This feature is available on GD32F190x4 devices only. 2. This feature is available on GD32F190x8 and GD32F190x6 devices only. 18 / 46 GD32F190xx Table 5. Port C & D & F alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PC0 EVENTOUT I2C3_SCL SEG18 PC1 EVENTOUT I2C3_SDA SEG19 PC2 EVENTOUT I2C3_SMBA SEG20 PC3 EVENTOUT I2C3_TXFRAME SEG21 PC4 EVENTOUT SEG22 PC5 TSI_G3_IO1 SEG23 PC6 TIM3_CH1 I2C3_TXFRAME SEG24 PC7 TIM3_CH2 I2C3_SCL SEG25 PC8 TIM3_CH3 I2C3_SDA SEG26 PC9 TIM3_CH4 I2C3_SMBA MCO2 AF7 AF9 AF11 SEG27 SPI3_SCK COM4 I2S3_CK SEG28 SPI3_MISO COM5 I2S3_MCK SEG29 SPI3_MOSI COM6 I2S3_SD SEG30 PC10 PC11 PC12 COM7 PD2 TIM3_ETR SEG31 PF4 EVENTOUT SEG28 PF5 EVENTOUT SEG29 I2C1_SCL(1) SEG30 PF6 I2C2_SCL(2) I2C1_SDA(1) SEG31 PF7 I2C2_SDA(2) 1. This feature is available on GD32F190x4 devices only. 2. This feature is available on GD32F190x8 and GD32F190x6 devices only. 19 / 46 GD32F190xx 3 Functional description 3.1 ARM® Cortex®-M3 core The Cortex®-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.  32-bit ARM® Cortex®-M3 processor core  Up to 72 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M3:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 64 Kbytes of Flash memory  Up to 8 Kbytes of SRAM with hardware parity checking The ARM® Cortex®-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 64 Kbytes of inner Flash and 8 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Figure 5. GD32F190xx memory map shows the memory map of the GD32F190xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 20 / 46 GD32F190xx 3.3 Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.5 to 5.5 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB and two APB domains is 72 MHz. See Figure 9 for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 1.95V and down to 1.9V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.5 to 5.5 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VDDA range: 2.5 to 5.5 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 5.5 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default)  Boot from system memory  Boot from on-chip SRAM In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART1 in device mode. 21 / 46 GD32F190xx 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In Deep-sleep mode, all clocks in the 1.8V domain are off, and all of the high speed crystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 16 external lines, the RTC alarm and the LVD output,. When exiting the Deep-sleep mode, the HSI is selected as the system clock.  Standby mode In Standby mode, the whole 1.8V domain is power off, the LDO is shut down, and all of HSI, HSE and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge on WKUP pin. 3.6 Analog to digital converter (ADC)  12-bit SAR ADC engine with up to 2M SPS conversion rate  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit  Conversion range: VSSA to VDDA (3.0 to 5.5 V)  Temperature sensor A 12-bit 2M SPS multi-channel ADC are integrated in the device. It is a total of up to 16 multiplexed external channels with 2 internal channels for temperature sensor and voltage reference measurement. The conversion range is between 3.0 V < VDDA < 5.5 V. An on-chip 16-bit hardware oversample scheme improves performances while off-loading the related computational burden from the MCU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages. The ADC can be triggered from the events generated by the general-purpose timers (TMx) and the advanced-control timer (TM1) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected 22 / 46 GD32F190xx to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. 3.7 Digital to analog converter (DAC)  Two 12-bit DAC converter of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+. 3.8 DMA  7 channel DMA controller  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2Ss The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9 General-purpose inputs/outputs (GPIOs)  Up to 55 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 55 general purpose I/O pins (GPIO) in GD32F190xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 23 / 46 GD32F190xx 3.10 Timers and PWM generation  One 16-bit advanced-control timer (TM1), one 32-bit general-purpose timer (TM2), five 16-bit general-purpose timers (TM3, TM14 ~ TM17), and one 16-bit basic timer (TM6)  Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Independent watchdog and window watchdog) The advanced-control timer (TM1) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM) can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM14 ~ TM17 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TM6, is mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F190xx provides two watchdog peripherals, Independent watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in stop and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It 24 / 46 GD32F190xx features: 3.11  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.  Calendar with sub-seconds, seconds, minutes, hours, week day, date, year and month automatically correction  Alarm function with wake up from deep-sleep and standby mode capability  On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy. The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.12 Inter-integrated circuit (I2C)  Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode  Hardware support specifications of secure access and control module interface applied in validation for resident ID cards The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 25 / 46 GD32F190xx 3.13 Serial peripheral interface (SPI)  Up to three SPI interfaces with a frequency of up to 30 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking  Quad wire configuration available in master mode (SPI2) The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14 Universal synchronous asynchronous receiver transmitter (USART)  Up to two USARTs with operating frequency up to 9 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART1, USART2) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication. 3.15 Inter-IC sound (I2S)  Up to two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with SPI1 and SPI3  Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F190xx contain a I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI3. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error. 26 / 46 GD32F190xx 3.16 HDMI CEC  Hardware support Consumer Electronics Control (CEC) protocol (HDMI standard rev1.4) The CEC protocol provides high-level control functions between the audiovisual products linked with HDMI cables. GD32F190xx contain a HDMI-CEC controller which has an independent clock domain and can wake up the MCU from deep-sleep mode on data reception. 3.17 Touch sensing interface (TSI)  Supports up to 18 external electrodes by the sensing channels distributed over 6 analog I/O groups  Programmable charging frequency and I/O pins  Capability to wake up the MCU from power saving modes Capacitive sensing technology can be used for the detection of a finger (or any conductive object) presence near an electrode. The capacitive variation of the electrode introduced by the finger can be measured by charging and detecting the voltage across the sampling capacitor. GD32F190xx contain a hardware touch sensing interface (TSI) and only requires few external components to operate. The sensing channels are distributed over 6 analog I/O groups including: Group1 (PA0 ~ PA3), Group2 (PA4 ~ PA7), Group3 (PC5, PB0 ~ PB2), Group4 (PA9 ~ PA12), Group5 (PB3, PB4, PB6, PA7) and Group6 (PB11 ~ PB14), 3.18 Comparators (CMP)  Two fast rail-to-rail low-power comparators with software configurable  Programmable reference voltage (internal, external I/O or DAC output pin) Two Comparators (CMP) are implemented within the devices. Both comparators can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC. 3.19 Operational amplifiers (OP-AMP)  Rail-to-rail input and output voltage range  Low input bias current, offset voltage and low power mode GD32F190xx provides two operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement. 27 / 46 GD32F190xx 3.20 LCD controller (LCD)  Configurable frame frequency  Blinking of individual segments or all segments  Double buffer up to 8x32 bits registers for LCD_DATAx storage  The contrast can also be adjusted by configuring dead time  VLCD rails decoupling capability The LCD controller directly drives LCD displays by creating the AC segment and common voltage signals automatically. It can drive the monochrome passive liquid crystal display (LCD) which composed of a plurality of segments (pixels or complete symbols) that can be converted to visible or invisible. The LCD controller can support up to 32 segments and 8 commons. 3.21 Controller area network (CAN)  Two CAN2.0B interface with communication frequency up to 1 Mbit/s  Internal main PLL for USB CLK compliantly  A hardware CAN2.0B PHY integrated (CAN1) Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others. The integrated hardware CAN PHY can be enabled by register setting and this mode only used for CAN1. 3.22 Debug mode  Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.23 Package and operation temperature  LQFP64 (GD32F190Rx), LQFP48 (GD32F190Cx) and QFN36 (GD32F190Tx)  Operation temperature range: -40°C to +85°C (industrial level) 28 / 46 GD32F190xx 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Min Max Unit VDD External voltage range VSS - 0.3 VSS + 5.5 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 5.5 V VBAT External battery supply voltage VSS - 0.3 VSS + 5.5 V Input voltage on 5V tolerant pin VSS - 0.3 VSS + 7.5 V Input voltage on other I/O VSS - 0.3 5.5 V VIN IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Storage temperature range -55 +150 °C Maximum junction temperature — 125 °C TSTG TJ 4.2 Parameter Recommended DC characteristics Table 7. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.5 5.0 5.5 V VDDA Analog supply voltage Same as VDD 2.5 5.0 5.5 V VBAT Battery supply voltage — 2.0 — 5.5 V 29 / 46 GD32F190xx 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 8. Power consumption characteristics Symbol Parameter Conditions Min Typ — 59.23 — mA — 38.71 — mA -— 40.46 — mA — 26.72 — mA — 35.17 — mA — 13.00 — mA — 119.81 — μA — 105.35 — μA VDD=VDDA=5.0V, LSE off, LSI on, RTC on — 11.08 — μA VDD=VDDA=5.0V, LSE off, LSI on, RTC off — 10.56 — μA VDD=VDDA=5.0V, LSE off, LSI off, RTC off — 8.54 — μA — 2.30 — μA — 2.06 — μA — 1.56 — μA — 1.41 — μA — 1.32 — μA — 0.88 — μA — 0.75 — μA VDD=VDDA=5.0V, HSE=8MHz, System Max Unit clock=72 MHz, All peripherals enabled VDD=VDDA=5.0V, HSE=8MHz, System clock Supply current =72 MHz, All peripherals disabled (Run mode) VDD=VDDA=5.0V, HSE=8MHz, System clock =48 MHz, All peripherals enabled VDD=VDDA=5.0V, HSE=8MHz, System Clock =48 MHz, All peripherals disabled VDD=VDDA=5.0V, HSE=8MHz, CPU clock off, System clock=72MHz, All peripherals IDD Supply current enabled (Sleep mode) VDD=VDDA=5.0V, HSE=8MHz, CPU clock off, System clock=72MHz, All peripherals disabled VDD=VDDA=5.0V, Regulator in run mode, Supply current LSI on, RTC on, All GPIOs analog mode (Deep-Sleep VDD=VDDA=5.0V, Regulator in low power mode) mode, LSI on, RTC on, All GPIOs analog mode Supply current (Standby mode) VDD not available, VBAT=5.5 V, LSE on with external crystal, RTC on, Higher driving VDD not available, VBAT=5.0 V, LSE on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.3 V, LSE on with external crystal, RTC on, Higher driving IBAT Battery supply VDD not available, VBAT=2.5 V, LSE on with current external crystal, RTC on, Higher driving VDD not available, VBAT=5.0 V, LSE on with external crystal, RTC on, Lower driving VDD not available, VBAT=3.3 V, LSE on with external crystal, RTC on, Lower driving VDD not available, VBAT=2.5 V, LSE on with external crystal, RTC on, Lower driving 30 / 46 GD32F190xx 4.4 EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 9. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 5.0 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB Level/Class induce a functional disturbance through 100 pF on VDD and VSS pins 3B VDD = 5.0 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 10. EMI characteristics Symbol Parameter Tested Conditions frequency band Peak level 48M 0.1 to 2 MHz