GigaDevice Semiconductor Inc.
GD32F207xx
ARM® Cortex®-M3 32-bit MCU
Datasheet
GD32F207xx Datasheet
Table of Contents
Table of Contents ........................................................................................................... 1
List of Figures ................................................................................................................ 4
List of Tables .................................................................................................................. 5
1. General description ................................................................................................. 7
2. Device overview ....................................................................................................... 8
2.1.
Device information ...................................................................................................... 8
2.2.
Block diagram ............................................................................................................ 11
2.3.
Pinouts and pin assignment ..................................................................................... 12
2.4.
Memory map .............................................................................................................. 16
2.5.
Clock tree ................................................................................................................... 19
2.6.
Pin definitions ............................................................................................................ 20
2.6.1.
GD32F207Ix LQFP176 pin definitions ............................................................................... 20
2.6.2.
GD32F207Zx LQFP144 pin definitions .............................................................................. 30
2.6.3.
GD32F207Vx LQFP100 pin definitions ............................................................................. 39
2.6.4.
GD32F207Rx LQFP64 pin definitions ............................................................................... 46
3. Functional description .......................................................................................... 51
3.1.
ARM® Cortex®-M3 core .............................................................................................. 51
3.2.
On-chip memory ........................................................................................................ 51
3.3.
Clock, reset and supply management ...................................................................... 52
3.4.
Boot modes ................................................................................................................ 52
3.5.
Power saving modes ................................................................................................. 53
3.6.
Analog to digital converter (ADC) ............................................................................ 53
3.7.
Digital to analog converter (DAC) ............................................................................. 54
3.8.
DMA ............................................................................................................................ 54
3.9.
General-purpose inputs/outputs (GPIOs) ................................................................ 54
3.10.
Timers and PWM generation ................................................................................. 55
3.11.
Real time clock (RTC) and backup registers ........................................................ 56
3.12.
Inter-integrated circuit (I2C) .................................................................................. 56
3.13.
Serial peripheral interface (SPI) ............................................................................ 57
3.14.
Universal synchronous/asynchronous receiver transmitter (USART/UART) .... 57
1
GD32F207xx Datasheet
3.15.
Inter-IC sound (I2S) ................................................................................................ 57
3.16.
Universal serial bus full-speed interface (USBFS) ............................................... 58
3.17.
Controller area network (CAN) .............................................................................. 58
3.18.
Ethernet (ENET) ...................................................................................................... 58
3.19.
External memory controller (EXMC) ..................................................................... 59
3.20.
Secure digital input and output card interface (SDIO) ......................................... 59
3.21.
TFT LCD interface (TLI) .......................................................................................... 59
3.22.
Digital camera interface (DCI)................................................................................ 60
3.23.
Cryptographic acceleration Unit (CAU) ................................................................ 60
3.24.
Hash acceleration unit (HAU) ................................................................................ 60
3.25.
True Random number generator (TRNG) .............................................................. 61
3.26.
Debug mode ........................................................................................................... 61
3.27.
Package and operation temperature ..................................................................... 61
4. Electrical characteristics ....................................................................................... 62
4.1.
Absolute maximum ratings ....................................................................................... 62
4.2.
Recommended DC characteristics ........................................................................... 62
4.3.
Power consumption .................................................................................................. 64
4.4.
EMC characteristics .................................................................................................. 65
4.5.
Power supply supervisor characteristics ................................................................ 66
4.6.
Electrical sensitivity .................................................................................................. 66
4.7.
External clock characteristics .................................................................................. 67
4.8.
Internal clock characteristics ................................................................................... 69
4.9.
PLL characteristics.................................................................................................... 70
4.10.
Memory characteristics ......................................................................................... 70
4.11.
NRST pin characteristics ....................................................................................... 70
4.12.
GPIO characteristics .............................................................................................. 71
4.13.
ADC characteristics ............................................................................................... 73
4.14.
Temperature sensor characteristics ..................................................................... 74
4.15.
DAC characteristics ............................................................................................... 74
4.16.
I2C characteristics ................................................................................................. 75
4.17.
SPI characteristics ................................................................................................. 76
4.18.
I2S characteristics.................................................................................................. 78
2
GD32F207xx Datasheet
4.19.
USART characteristics ........................................................................................... 80
4.20.
SDIO characteristics .............................................................................................. 80
4.21.
CAN characteristics ............................................................................................... 80
4.22.
USBFS characteristics ........................................................................................... 81
4.23.
EXMC characteristics............................................................................................. 82
4.24.
TIMER characteristics ............................................................................................ 85
4.25.
DCI characteristics ................................................................................................. 86
4.26.
WDGT characteristics ............................................................................................ 86
4.27.
Parameter conditions............................................................................................. 87
5. Package information.............................................................................................. 88
5.1.
LQFP176 package outline dimensions..................................................................... 88
5.2.
LQFP144 package outline dimensions..................................................................... 90
5.3.
LQFP100 package outline dimensions..................................................................... 92
5.4.
LQFP64 package outline dimensions....................................................................... 94
5.5.
Thermal characteristics ............................................................................................ 96
6. Ordering information ............................................................................................. 98
7. Revision history ..................................................................................................... 99
3
GD32F207xx Datasheet
List of Figures
Figure 2-1. GD32F207xx block diagram ................................................................................................... 11
Figure 2-2. GD32F207Ix LQFP176 pinouts .............................................................................................. 12
Figure 2-3. GD32F207Zx LQFP144 pinouts ............................................................................................. 13
Figure 2-4. GD32F207Vx LQFP100 pinouts ............................................................................................. 14
Figure 2-5. GD32F207Rx LQFP64 pinouts .............................................................................................. 15
Figure 2-6. GD32F207xx clock tree .......................................................................................................... 19
Figure 4-1. Recommended power supply decoupling capacitors
(1)(2)
................................................. 63
Figure 4-2. I2C bus timing diagram.......................................................................................................... 76
Figure 4-3. SPI timing diagram - master mode ....................................................................................... 77
Figure 4-4. SPI timing diagram - slave mode .......................................................................................... 77
Figure 4-5. I2S timing diagram - master mode ....................................................................................... 79
Figure 4-6. I2S timing diagram - slave mode .......................................................................................... 79
Figure 4-7. USBFS timings: definition of data signal rise and fall time ............................................... 81
Figure 5-1. LQFP176 package outline ..................................................................................................... 88
Figure 5-2. LQFP176 recommended footprint ........................................................................................ 89
Figure 5-3. LQFP144 package outline ..................................................................................................... 90
Figure 5-4. LQFP144 recommended footprint ........................................................................................ 91
Figure 5-5. LQFP100 package outline ..................................................................................................... 92
Figure 5-6. LQFP100 recommended footprint ........................................................................................ 93
Figure 5-7. LQFP64 package outline ....................................................................................................... 94
Figure 5-8. LQFP64 recommended footprint .......................................................................................... 95
4
GD32F207xx Datasheet
List of Tables
Table 2-1. GD32F207xx devices features and peripheral list .................................................................. 8
Table 2-2. GD32F207xx memory map ...................................................................................................... 16
Table 2-3. GD32F207Ix LQFP176 pin definitions .................................................................................... 20
Table 2-4. GD32F207Zx LQFP144 pin definitions ................................................................................... 30
Table 2-5. GD32F207Vx LQFP100 pin definitions ................................................................................... 39
Table 2-6. GD32F207Rx LQFP64 pin definitions .................................................................................... 46
Table 4-1. Absolute maximum ratings (1)(4) .............................................................................................. 62
Table 4-2. DC operating conditions ......................................................................................................... 62
Table 4-3. Clock frequency (1) ................................................................................................................... 63
Table 4-4. Operating conditions at Power up/ Power down
Table 4-5. Start-up timings of Operating conditions
(1)(2)(3)
(1)
.............................................................. 63
.................................................................... 63
Table 4-6. Power saving mode wakeup timings characteristics (1)(2) .................................................... 64
Table 4-7. Power consumption characteristics ...................................................................................... 64
Table 4-8. EMS characteristics (1) ............................................................................................................. 65
Table 4-9. Power supply supervisor characteristics.............................................................................. 66
Table 4-10. ESD characteristics ............................................................................................................... 67
Table 4-11. Static latch-up characteristics .............................................................................................. 67
Table 4-12. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics . 67
Table 4-13. High speed external clock characteristics (HXTAL in bypass mode) .............................. 67
Table 4-14. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics .. 68
Table 4-15. Low speed external user clock characteristics (LXTAL in bypass mode) ....................... 68
Table 4-16. High speed internal clock (IRC8M) characteristics ............................................................ 69
Table 4-17. Low speed internal clock (IRC40K) characteristics ........................................................... 69
Table 4-18. PLL characteristics ................................................................................................................ 70
Table 4-19. Flash memory characteristics .............................................................................................. 70
Table 4-20. NRST pin characteristics ...................................................................................................... 70
Table 4-21. I/O port DC characteristics(1)(3) .............................................................................................. 71
Table 4-22. I/O port AC characteristics (1)(2)(4) .......................................................................................... 73
Table 4-23. ADC characteristics ............................................................................................................... 73
Table 4-24. ADC RAIN max for fADC = 28 MHz (1)(2) ................................................................................... 74
Table 4-25. Temperature sensor characteristics (1) ................................................................................ 74
Table 4-26. DAC characteristics ............................................................................................................... 74
Table 4-27. I2C characteristics (1)(2) .......................................................................................................... 75
Table 4-28. Standard SPI characteristics
Table 4-29. I2S characteristics
(1)(2)
(1)
............................................................................................ 76
.......................................................................................................... 78
Table 4-30. USART characteristics (1) ...................................................................................................... 80
Table 4-31. SDIO characteristics (1)(2) ....................................................................................................... 80
Table 4-32. USBFS start up time .............................................................................................................. 81
Table 4-33. USBFS DC electrical characteristics ................................................................................... 81
Table 4-34. USBFS full speed-electrical characteristics (1).................................................................... 81
5
GD32F207xx Datasheet
Table 4-35. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)(3) ........................ 82
Table 4-36. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)(3) ....................... 82
Table 4-37. Asynchronous multiplexed PSRAM/NOR read timings
Table 4-38. Asynchronous multiplexed PSRAM/NOR write timings
Table 4-39. Synchronous multiplexed PSRAM/NOR read timings
Table 4-40. Synchronous multiplexed PSRAM write timings
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
........................................... 83
........................................... 83
.............................................. 84
...................................................... 84
Table 4-41. Synchronous non-multiplexed PSRAM/NOR read timings (1)(2)(3) ...................................... 85
Table 4-42. Synchronous non-multiplexed PSRAM write timings (1)(2)(3) .............................................. 85
Table 4-43. TIMER characteristics (1) ....................................................................................................... 85
Table 4-44. DCI characteristics (1) ............................................................................................................ 86
Table 4-45. FWDGT min/max timeout period at 40 kHz (IRC40K) (1) ..................................................... 86
Table 4-46. WWDGT min-max timeout value at 60 MHz (fPCLK1) (1) ......................................................... 86
Table 5-1. LQFP176 package dimensions ............................................................................................... 88
Table 5-2. LQFP144 package dimensions ............................................................................................... 90
Table 5-3. LQFP100 package dimensions ............................................................................................... 92
Table 5-4. LQFP64 package dimensions ................................................................................................. 94
Table 5-5. Package thermal characteristics(1) ......................................................................................... 96
Table 6-1. Part ordering code for GD32F207xx devices ........................................................................ 98
Table 7-1. Revision history ....................................................................................................................... 99
6
GD32F207xx Datasheet
1.
General description
The GD32F207xx device belongs to the performance line of GD32 MCU Family. It is a new
32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best
cost-performance ratio in terms of processing capacity, reduced power consumption and
peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled
with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug
support.
The GD32F207xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating
at 120 MHz frequency with flash accesses zero wait states to obtain maximum efficiency. It
provides up to 3072 KB on-chip flash memory and 256 KB SRAM memory. An extensive
range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up
to three 12-bit 2 MSPS ADCs, two 12-bit DACs, up to ten 16-bit general timers, two 16-bit
basic timers plus two 16-bit PWM advanced timers, as well as standard and advanced
communication interfaces: up to three SPIs, three I2Cs, four USARTs and four UARTs, two
I2Ss, two CANs, a SDIO, a USBFS and an Ethernet. Additional peripherals as TFT-LCD
Interface (TLI), EXMC interface with SDRAM extension support, Digital camera interface
(DCI), Cryptographic acceleration unit (CAU), Hash acceleration unit (HAU), True random
number generator (TRNG) are included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization of power consumption, an especially important consideration in low power
applications.
The above features make GD32F207xx devices suitable for a wide range of interconnection
and advanced applications, especially in areas such as industrial control, consumer and
handheld equipment, embedded modules, human machine interface, security and alarm
systems, POS and electronic payment, automotive navigation and so on.
7
GD32F207xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32F207xx devices features and peripheral list
GD32F207xx
Flash
Part Number
RC
RE
RG
RK
VC
VE
VG
VK
Code area (KB)
256
512
384
384
256
512
384
384
Data area (KB)
0
0
640
2688
0
0
640
2688
Total (KB)
256
512
1024
3072
256
512
1024
3072
128
128
256
256
128
128
256
256
General timer(16-
10
10
10
10
10
10
10
10
bit)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
Advanced timer
2
2
2
2
2
2
2
2
(16-bit)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
SysTick
1
1
1
1
1
1
1
1
Timers
SRAM (KB)
Basic timer (16-
2
2
2
2
2
2
2
2
bit)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
Watchdog
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
USART
4
4
4
4
4
4
4
4
2
2
2
2
4
4
4
4
(3-4)
(3-4)
(3-4)
(3-4)
(3-4,6-7)
(3-4,6-7)
(3-4,6-7)
(3-4,6-7)
3
3
3
3
3
3
3
3
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
SDIO
1
1
1
1
1
1
1
1
CAN
2
2
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
1
1
ENET
1
1
1
1
1
1
1
1
TLI
0
0
0
0
1
1
1
1
DCI
1
1
1
1
1
1
1
1
CAU/HAU
1
1
1
1
1
1
1
1
GPIO
51
51
51
51
82
82
82
82
EXMC/SDRAM
0/0
0/0
0/0
0/0
1/0
1/0
1/0
1/0
UART
I2C
Connectivity
SPI/I2S
8
GD32F207xx Datasheet
GD32F207xx
Part Number
RC
RE
RG
RK
VC
VE
VG
VK
ADC (CHs)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
DAC
2
2
2
2
2
2
2
2
LQFP64
Package
LQFP100
Table 2-1. GD32F207xx devices features and peripheral list (continued)
GD32F207xx
Connectivity
Timers
Flash
Part Number
ZC
ZE
ZG
ZK
IE
IG
IK
Code area (KB)
256
512
384
384
512
384
384
Data area (KB)
0
0
640
2688
0
640
2688
Total (KB)
256
512
1024
3072
512
1024
3072
SRAM (KB)
128
128
256
256
128
256
256
General timer
10
10
10
10
10
10
10
(16-bit)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
Advanced timer
2
2
2
2
2
2
2
(16-bit)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
SysTick
1
1
1
1
1
1
1
Basic timer (16-
2
2
2
2
2
2
2
bit)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
Watchdog
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
USART
4
4
4
4
4
4
4
UART
4
4
4
4
4
4
4
I2C
3
3
3
3
3
3
3
SPI/I2S
3/2
3/2
3/2
3/2
3/2
3/2
3/2
SDIO
1
1
1
1
1
1
1
CAN
2
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
1
ENET
1
1
1
1
1
1
1
TLI
1
1
1
1
1
1
1
DCI
1
1
1
1
1
1
1
CAU/HAU
1
1
1
1
1
1
1
114
114
114
114
140
140
140
GPIO
9
GD32F207xx Datasheet
GD32F207xx
Part Number
ZC
ZE
ZG
ZK
IE
IG
IK
EXMC/SDRAM
1/1
1/1
1/1
1/1
1/1
1/1
1/1
ADC (CHs)
3(24)
3(24)
3(24)
3(24)
3(24)
3(24)
3(24)
DAC
2
2
2
2
2
2
2
Package
LQFP144
LQFP176
10
GD32F207xx Datasheet
2.2.
Block diagram
Figure 2-1. GD32F207xx block diagram
SW/JTAG
TPIU
ICode DCode System
ARM Cortex-M3
Processor
Fmax:120MHz
NVIC
POR/ PDR
Flash
Memory
PLL
F max : 120MHz
DBus
Slave
Slave
Master
Master
DMA1(7 chs)
Master
Slave
AHB Matrix
DMA0(7 chs)
ENET
Flash
Memory
Controller
IBus
Master
Slave
EXMC
SRAM0
SRAM1
SRAM2
CAU
Slave
LDO
1.2V
IRC
8MHz
HAU TRNG DCI
AHB2 Peripherals
HXTAL
3-25MHz
SDIO USBFS CRC RCU
AHB1 Peripherals
Slave
TLI
AHB to AP B
Brid ge2
AHB to AP B
Brid ge1
Master
LVD
Interrput request
WWDGT
USART0
Slave
SAR ADC
Slave
SPI0
FWDGT
ADC0~2
RTC
EXTI
DAC
GPIOA
CAN0
GPIOB
CAN1
Powered By V DDA
GPIOE
APB1: Fmax = 60MHz
GPIOD
APB2: Fmax = 120MHz
GPIOC
SPI1~2
TIMER1~3
TIMER4~6
GPIOF
TIMER
11~13
GPIOG
USART1~2
TIMER0
TIMER7
Powered By VDDA
UART3~4
UART6~7
TIMER8~10
I2C0
USART5
I2C1
GPIOH
I2C2
GPIOI
11
GD32F207xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32F207Ix LQFP176 pinouts
PI2
PI3
VSS
VDD
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
PD6
VDD_10
PD7
PG9
PG11
PG10
PG12
PG14
PG13
VSS_11
VDD_11
PB3
PG15
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PI4
PI5
PI6
PI7
PE2
1
176175174173172171170169168167166165 164163162161160159158157156155154153152 151150149148147146145144143142141140139138137136135134133
132
PE3
PE4
2
131
PI0
3
130
PH15
PE5
PE6
4
129
5
128
PH14
PH13
VBAT
6
127
VDD_2
PI1
PI8
7
126
VSS_2
PC13-TAMPER-RTC
PC14-OSC32IN
8
125
9
124
NC
PA13
PC15-OSC32OUT
10
123
PA12
PI9
11
122
PA11
PI10
12
121
PA10
PI11
13
120
PA9
VSS_5
14
119
PA8
VDD_5
15
118
PC9
PF0
16
117
PF1
17
116
PC8
PC7
PF2
18
115
PC6
PF3
19
114
VDD_9
PF4
20
113
VSS_9
PF5
21
112
PG8
VSS
22
111
PG7
110
PG6
109
PG5
108
PG4
107
PG3
27
106
PG2
PD15
VDD
23
PF6
24
PF7
25
PF8
26
PF9
GigaDevice GD32F207Ix
LQFP176
28
105
OSCIN
29
104
PD14
OSCOUT
30
103
VDD_8
NRST
31
102
VSS_8
PC0
32
101
PD13
PC1
33
100
PD12
PC2
34
99
PD11
PC3
35
98
PD10
VSSA
36
97
PD9
VREFVREF+
37
96
PD8
38
95
PB15
VDD
39
94
PB14
PA0_WKUP
40
93
PA1
41
92
PB13
PB12
PA2
42
91
VDD
PH2
43
90
VSS
PH3
44
89
PH12
PF10
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
PH11
PH10
PH9
PH8
VDD_1
PH7
VSS_1
PH6
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE8
PE9
PE7
PG1
PI5
PG0
PI4
VDD_6
PI3
VSS_6
PF12
PB2
PF11
PC5
PB1
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
PH5
PH4
12
GD32F207xx Datasheet
Figure 2-3. GD32F207Zx LQFP144 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109
PE2
1
108
PE3
PE4
2
107
VSS_2
3
106
NC
PE5
PE6
4
105
PA13
5
104
PA12
VBAT
6
103
PA11
PC13-TAMPER-RTC
PC14-OSC32IN
7
102
PA10
8
101
PA9
PC15-OSC32OUT
9
100
PA8
PF0
10
99
PC9
PF1
11
98
PC8
PF2
12
97
PC7
PF3
PF4
13
96
PC6
14
95
VDD_9
PF5
15
94
VSS_9
VSS_5
16
93
PG8
92
PG7
91
PG6
90
PG5
89
PG4
88
PG3
VDD_2
VDD_5
17
PF6
18
PF7
19
PF8
20
PF9
21
PF10
22
87
PG2
OSCIN
23
86
PD15
OSCOUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
82
PD13
PC2
28
81
PD12
PC3
VSSA
29
80
PD11
30
79
PD10
VREFVREF+
31
78
PD9
32
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
GigaDevice GD32F207Zx
LQFP144
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE8
PE9
PE7
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
13
GD32F207xx Datasheet
Figure 2-4. GD32F207Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32IN
7
70
69
PA10
8
68
PA9
PC15-OSC32OUT
9
67
PA8
VSS_5
10
66
PC9
VDD_5
11
65
PC8
64
PC7
63
PC6
14
62
PD15
OSCIN
12
GigaDevice GD32F207Vx
LQFP100
VDD_2
PA11
OSCOUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
14
GD32F207xx Datasheet
Figure 2-5. GD32F207Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32IN
3
46
PA13
PC15-OSC32OUT
PD0-OSCIN
4
45
PA12
5
44
PA11
PD1 OSCOUT
6
43
PA10
NRST
PC0
7
42
PA9
PC1
9
PC2
PC3
VSSA
GigaDevice GD32F207Rx
LQFP64
41
PA8
40
PC9
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PB14
PA1
15
34
PB13
16
33
PB12
PA2
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PB11
PB10
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
15
GD32F207xx Datasheet
2.4.
Memory map
Table 2-2. GD32F207xx memory map
Pre-defined
Regions
Bus
External
Device
AHB
External
RAM
AHB2
AHB1
Peripheral
APB2
Address
Peripherals
0xC000 0000 - 0xDFFF FFFF
EXMC - SDRAM
0xA000 1000 - 0xBFFF FFFF
Reserved
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
0x9000 0000 - 0x9FFF FFFF
EXMC - PC CARD
0x7000 0000 - 0x8FFF FFFF
EXMC - NAND
0x6000 0000 - 0x6FFF FFFF
EXMC - NOR/PSRAM/SRAM
0x5006 0C00 - 0x5FFF FFFF
Reserved
0x5006 0800 - 0x5006 0BFF
TRNG
0x 5006 0400 – 0x5006 07FF
HAU
0x 5006 0000 – 0x5006 03FF
CAU
0x5005 0400 - 0x5005 FFFF
Reserved
0x5005 0000 - 0x5005 03FF
DCI
0x5004 0000 - 0x5004 FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
USBFS
0x4002 A000 - 0x4FFF FFFF
Reserved
0x4002 8000 - 0x4002 9FFF
ENET
0x4002 3400 - 0x4002 7FFF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2400 - 0x4002 2FFF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1400 - 0x4002 1FFF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0800 - 0x4002 0FFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA0
0x4002 0000 - 0x4002 03FF
DMA1
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
SDIO
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
GPIOI
0x4001 7400 - 0x4001 77FF
GPIOH
0x4001 7000 - 0x4001 73FF
USART5
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
TLI
0x4001 5800 - 0x4001 67FF
Reserved
0x4001 5400 - 0x4001 57FF
TIMER10
0x4001 5000 - 0x4001 53FF
TIMER9
0x4001 4C00 - 0x4001 4FFF
TIMER8
16
GD32F207xx Datasheet
Pre-defined
Regions
Bus
APB1
Address
Peripherals
0x4001 4000 - 0x4001 4BFF
Reserved
0x4001 3C00 - 0x4001 3FFF
ADC2
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
TIMER7
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
0x4001 2000 - 0x4001 23FF
GPIOG
0x4001 1C00 - 0x4001 1FFF
GPIOF
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 C400 - 0x4000 FFFF
Reserved
0x4000 C000 - 0x4000 C3FF
I2C2
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
UART7
0x4000 7800 - 0x4000 7BFF
UART6
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
0x4000 5C00 - 0x4000 63FF
USB/CAN shared
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
17
GD32F207xx Datasheet
Pre-defined
Regions
SRAM
Code
Bus
AHB
AHB
Address
Peripherals
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
0x4000 1C00 - 0x4000 1FFF
TIMER12
0x4000 1800 - 0x4000 1BFF
TIMER11
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2004 0000 - 0x3FFF FFFF
Reserved
0x2002 0000 - 0x2003 FFFF
SRAM2(128KB)
0x2001 C000 - 0x2001 FFFF
SRAM1(16KB)
0x2000 0000 - 0x2001 BFFF
SRAM0(112KB)
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF B000 - 0x1FFF F7FF
System memory
0x0830 0000 - 0x1FFF AFFF
Reserved
0x0800 0000 - 0x082F FFFF
Main Flash(3072KB)
Aliased to Flash or system
0x0000 0000 - 0x07FF FFFF
memory according to BOOT
pins configuration
18
GD32F207xx Datasheet
2.5.
Clock tree
Figure 2-6. GD32F207xx clock tree
CK_HXTAL
PLLT prescaler
(PLLTPSC )
÷2,3...63
1 PLLT input clock
0
CK_IRC8M
PLLTSEL
VCO input clock ×49,50,
…,432
CK_VCO
PLLTR prescaler
(PLLTRPSC )
÷2,3...7
CK_PLLTR
TLI prescaler
(TLIPSC )
÷2,4,8,16
PLLTMF
(to FMC)
CK_USBFS(=48 MHz)
or CK_TRNG(MDy[1:0] bit value
(3)
Parameter
Conditions
Max Unit
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 50.2
GPIOx_CTL->MDy[1:0] = 10
（IO_Speed = 2 MHz）
GPIOx_CTL->MDy[1:0] = 01
（IO_Speed = 10 MHz）
TRise/TFall
2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 61.2
ns
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 71.6
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 22.4
TRise/TFall
2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 29
ns
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 33
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 3.2
GPIOx_CTL->MDy[1:0] = 11
（IO_Speed = 50 MHz）
(1)
(2)
(3)
(4)
4.13.
TRise/TFall
2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 3.8
ns
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 4.6
Based on characterization, not tested in production.
Unless otherwise specified, all test results given for TA = 25 °C.
The I/O speed is configured using the GPIOx_CTL->MDy[1:0] bits.
Only for reference, Depending on user’s design.
ADC characteristics
Table 4-23. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.6
3.3
3.6
V
VIN(1)
ADC input voltage range
—
0
—
VREF+
V
VREF+(2)
Positive Reference Voltage
—
2.6
—
VDDA
V
Negative Reference Voltage
—
—
VSSA
—
V
ADC clock
—
0.6
—
28
MHz
12-bit
0.04
—
2
10-bit
0.05
—
2.3
MSP
8-bit
0.06
—
2.8
S
6-bit
0.075
—
3.5
VREF-
(2)
fADC(1)
fS(1)
(1)
Analog input voltage
16 external; 3 internal
0
—
VDDA
V
(2)
External input impedance
See Equation 1
—
—
137.5
kΩ
—
—
—
0.45
kΩ
—
—
6.4
pF
VAIN
RAIN
RADC(2)
Input sampling switch
resistance
No pin/pad capacitance
CADC(2)
Input sampling capacitance
tCAL(2)
Calibration time
fADC = 28 MHz
—
3.035
—
μs
Sampling time
fADC = 28 MHz
0.05
—
8.55
μs
12-bit
—
14
—
Total conversion time (including
10-bit
—
12
—
sampling time)
8-bit
—
10
—
6-bit
—
8
—
—
—
—
1
(2)
ts
tCONV(2)
tSU(2)
(1)
Sampling rate
Startup time
included
1/ fADC
μs
Based on characterization, not tested in production.
73
GD32F207xx Datasheet
(2)
Guaranteed by design, not tested in production.
Equation 1: RAIN max formula
R AIN <
Ts
fADC ∗CADC ∗ln(2N+2 )
− R ADC
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-24. ADC RAIN max for fADC = 28 MHz (1)(2)
(1)
(2)
4.14.
Ts (cycles)
ts (us)
RAIN max (KΩ)
1.5
0.05
0.4
7.5
0.26
3.8
13.5
0.48
7.3
28.5
1.01
15.9
41.5
1.48
23.4
55.5
1.98
31.4
71.5
2.55
40.6
239.5
8.55
137.2
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Temperature sensor characteristics
Table 4-25. Temperature sensor characteristics (1)
Symbol
Parameter
Min
Typ
Max
Unit
TL
VSENSE linearity with temperature
—
±1.5
—
℃
Avg_Slope
Average slope
—
4.1
—
mV/℃
V25
Voltage at 25 °C
—
1.45
—
V
ADC sampling time when reading the temperature
—
17.1
—
μs
tS_temp
(1)
(2)
4.15.
(2)
Based on characterization, not tested in production.
Shortest sampling time can be determined in the application by multiple iterations.
DAC characteristics
Table 4-26. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.6
3.3
3.6
V
VREF+(2)
Positive Reference Voltage
—
2.6
—
VDDA
V
—
—
VSSA
—
V
Resistive load with buffer ON
5
—
—
kΩ
—
—
15
kΩ
VREF-(2)
Negative Reference
Voltage
RLOAD(2)
Resistive load
Ro(2)
Impedance output
CLOAD(2)
Capacitive load
Capacitive load with buffer ON
—
—
50
pF
DAC_OUT
Lower DAC_OUT voltage
Lower DAC_OUT voltage with
0.2
—
—
V
Impedance output with buffer
OFF
74
GD32F207xx Datasheet
min(2)
buffer ON
Lower DAC_OUT voltage with
buffer OFF
DAC_OUT
max (2)
Higher DAC_OUT voltage with
buffer ON
Higher DAC_OUT voltage
Higher DAC_OUT voltage with
buffer OFF
0.5
—
—
—
—
—
—
—
—
VDDA0.2
VDDA1LSB
mV
V
V
With no load, middle
code(0x800) on the input,
IDDA(1)
DAC current consumption
VREF+ = 3.6 V
in quiescent mode
With no load, worst
550
μA
code(0xF1C) on the input,
—
—
600
—
86
—
VREF+ = 3.6 V
With no load, middle
code(0x800) on the input,
IDDVREF+(1)
VREF+ = 3.6 V
DAC current consumption
in quiescent mode
μA
With no load, worst
code(0xF1C) on the input,
—
298
—
—
—
5
10
μs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
—
—
4
MS/s
No RLoad, CLOAD=50 pF
55
80
—
dB
VREF+ = 3.6 V
Twakeup
(2)
Update
rate(2)
PSRR(2)
(1)
(2)
4.16.
Wakeup from off state
Max frequency for a correct
DAC_OUT change from
code i to i±1LSB
Power supply rejection
ratio(to VDDA)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
I2C characteristics
Table 4-27. I2C characteristics (1)(2)
Symbol
Parameter
Conditions
tSCL(H)
SCL clock high time
tSCL(L)
Standard mode
Fast mode
Unit
Min
Max
Min
Max
—
4.0
—
0.6
—
μs
SCL clock low time
—
4.7
—
1.3
—
μs
tsu(SDA)
SDA setup time
—
2
—
0.8
th(SDA)
SDA data hold time
—
250
—
250
—
ns
tr(SDA/SCL)
SDA and SCL rise time
—
—
1000
20
300
ns
tf(SDA/SCL)
SDA and SCL fall time
—
4
300
4
300
ns
th(STA)
Start condition hold time
—
4.0
—
0.6
—
μs
—
4.7
—
0.6
—
μs
ts(STA)
Repeated Start condition setup
time
μs
75
GD32F207xx Datasheet
Symbol
Parameter
Conditions
ts(STO)
Stop condition setup time
Stop to Start condition time (bus
tbuff
free)
Standard mode
Fast mode
Unit
Min
Max
Min
Max
—
4.0
—
0.6
—
μs
—
4.7
—
1.3
—
μs
(1)
(2)
Guaranteed by design, not tested in production.
To ensure the standard mode I2C frequency, f PCLK1 must be at least 2 MHz. To ensure the fast mode I2C
frequency, fPCLK1 must be at least 4 MHz.
(3)
The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the
falling edge of SCL.
Figure 4-2. I2C bus timing diagram
tsu(STA)
SDA
70%
30%
tf(SDA)
tr(SDA)
tSCL(H)
th(STA)
SCL
tbuff
th(SDA)
tsu(SDA)
70%
30%
tSCL(L)
4.17.
tr(SCL)
tf(SCL)
tsu(STO)
SPI characteristics
Table 4-28. Standard SPI characteristics
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
30
MHz
tSCK(H)
SCK clock high time
—
14.67 16.67 18.67
ns
tSCK(L)
SCK clock low time
—
14.67 16.67 18.67
ns
SPI master mode
tV(MO)
Data output valid time
—
—
—
8
ns
tSU(MI)
Data input setup time
—
1
—
—
ns
tH(MI)
Data input hold time
—
0
—
—
ns
SPI slave mode
tSU(NSS)
NSS enable setup time
—
0
—
—
ns
tH(NSS)
NSS enable hold time
—
1
—
—
ns
tA(SO)
Data output access time
—
—
9
—
ns
tDIS(SO)
Data output disable time
—
—
10
—
ns
tV(SO)
Data output valid time
—
—
11
—
ns
tSU(SI)
Data input setup time
—
0
—
—
ns
tH(SI)
Data input hold time
—
2
—
—
ns
76
GD32F207xx Datasheet
(1)
Based on characterization, not tested in production.
Figure 4-3. SPI timing diagram - master mode
tSCK
SCK (CKPH=0 CKPL=0)
SCK (CKPH=0 CKPL=1)
SCK (CKPH=1 CKPL=0)
tSCK(H)
tSCK(L)
SCK (CKPH=1 CKPL=1)
tSU(MI)
MISO
D[0]
LF=1,FF16=0
D[7]
tH(MI)
D[0]
MOSI
D[7]
tH(MO)
tV(MO)
Figure 4-4. SPI timing diagram - slave mode
NSS
tSCK
tSU(NSS)
SCK (CKPH=0 CKPL=0)
tSCK(H)
SCK (CKPH=0 CKPL=1)
tSCK(L)
tH(NSS)
tH(SO)
tDIS(SO)
tV(SO)
tA(SO)
MISO
D[0]
D[7]
tSU(SI)
MOSI
D[0]
D[7]
tH(SI)
77
GD32F207xx Datasheet
4.18.
I2S characteristics
Table 4-29. I2S characteristics (1)(2)
Symbol
Parameter
fCK
Clock frequency
Conditions
Master mode (data: 16 bits,
Audio frequency = 96 kHz)
Slave mode
Min
Typ
Max
Unit
—
3.078
—
—
10
—
—
162
—
ns
—
163
—
ns
MHz
tH
Clock high time
tL
Clock low time
tV(WS)
WS valid time
Master mode
—
2
—
ns
tH(WS)
WS hold time
Master mode
—
2
—
ns
tSU(WS)
WS setup time
Slave mode
0
—
—
ns
tH(WS)
WS hold time
Slave mode
3
—
—
ns
Slave mode
—
50
—
%
Ducy(SCK)
I2S slave input clock duty
cycle
—
tSU(SD_MR)
Data input setup time
Master mode
1
—
—
ns
tsu(SD_SR)
Data input setup time
Slave mode
0
—
—
ns
Master receiver
0
—
—
ns
Slave receiver
1
—
—
ns
—
—
5
ns
6
—
—
ns
—
—
5
ns
0
—
—
ns
tH(SD_MR)
tH(SD_SR)
(1)
(2)
Data input hold time
tv(SD_ST)
Data output valid time
th(SD_ST)
Data output hold time
tv(SD_MT)
Data output valid time
th(SD_MT)
Data output hold time
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
78
GD32F207xx Datasheet
Figure 4-5. I2S timing diagram - master mode
tCK
CPOL=0
tL
CPOL=1
tV(WS)
tH
tH(WS)
WS output
th(SD_MT)
tv(SD_MT)
SD transmit
D[0]
SD receive
D[0]
tSU(SD_MR)
tH(SD_MR)
Figure 4-6. I2S timing diagram - slave mode
tCK
CPOL=0
tL
CPOL=1
tH
tH(WS)
WS input
tSU(WS)
SD transmit
SD receive
tv(SD_ST)
th(SD_ST)
D[0]
D[0]
tSU(SD_SR)
tH(SD_SR)
79
GD32F207xx Datasheet
4.19.
USART characteristics
Table 4-30. USART characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 120 MHz
—
—
60
MHz
tSCK(H)
SCK clock high time
fPCLKx = 120 MHz
8.3
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 120 MHz
8.3
—
—
ns
(1)
4.20.
Guaranteed by design, not tested in production.
SDIO characteristics
Table 4-31. SDIO characteristics (1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock frequency in data transfer mode
—
0
—
48
MHz
tW(CKL)
(3)
Clock low time
fpp = 48 MHz
9.5
10.5
—
ns
tW(CKH)
(3)
Clock high time
fpp = 48 MHz
9.3
10.3
—
ns
fPP(3)
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU(4)
Input setup time HS
fpp = 48 MHz
4
—
—
ns
tIH(4)
Input hold time HS
fpp = 48 MHz
3
—
—
ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV(3)
Output valid time HS
fpp = 48 MHz
—
—
13.8
ns
tOH(3)
Output hold time HS
fpp = 48 MHz
12
—
—
ns
CMD, D inputs (referenced to CK) in SD default mode
tISUD(4)
Input setup time SD
fpp = 24 MHz
3
—
—
ns
tIHD(4)
Input hold time SD
fpp = 24 MHz
3
—
—
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD(3)
Output valid default time SD
fpp = 24 MHz
—
2.4
2.8
ns
tOHD(3)
Output hold default time SD
fpp = 24 MHz
2
—
—
ns
(1)
(2)
(3)
(4)
4.21.
CLK timing is measured at 50% of VDD.
Capacitive load CL = 30 pF.
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CAN characteristics
Refer to Table 4-21. I/O port DC characteristics for more details on the input/output alternate
function characteristics (CAN TX and CAN RX).
80
GD32F207xx Datasheet
4.22.
USBFS characteristics
Table 4-32. USBFS start up time
Symbol
Parameter
Max
Unit
tSTARTUP(1)
USBFS startup time
1
μs
(1)
Guaranteed by design, not tested in production.
Table 4-33. USBFS DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
VDD
USBFS operating voltage
—
3
—
3.6
Input
VDI
Differential input sensitivity
—
0.2
—
—
levels(1)
VCM
Differential common mode range
Includes VDI range
0.8
—
2.5
VSE
Single ended receiver threshold
—
1.3
—
2.0
Output
VOL
Static output level low
RL of 1.0 kΩ to 3.6 V
—
0.06
0.3
levels (2)
VOH
Static output level high
RL of 15 kΩ to VSS
2.8
3.3
3.6
17
21
25
0.72
0.9
1.1
PA11, PA12(USBFS_DM/DP)
PB14, PB15(USBHS_ DM/DP)
RPD(2)
PA9(USBFS_VBUS)
PA9(USBFS_VBUS)
1.2
1.5
1.8
0.24
0.3
0.33
VIN = VSS
PB13(USBHS_VBUS)
(1)
(2)
V
kΩ
PA11, PA12(USBFS_DM/DP)
PB14, PB15(USBHS_ DM/DP)
V
VIN = VDD
PB13(USBHS_VBUS)
RPU(2)
Max Unit
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Table 4-34. USBFS full speed-electrical characteristics (1)
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tR
Rise time
CL = 50 pF
4
—
20
ns
tF
Fall time
CL = 50 pF
4
—
20
ns
tRFM
Rise/ fall time matching
tR / tF
90
—
110
%
vCRS
Output signal crossover voltage
—
1.3
—
2.0
V
Guaranteed by design, not tested in production.
Figure 4-7. USBFS timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
VCRS
VSS
tf
tr
81
GD32F207xx Datasheet
4.23.
EXMC characteristics
Table 4-35. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
40.5
42.5
ns
tV(NOE_NE)
EXMC_NEx low to EXMC_NOE low
0
—
ns
tw(NOE)
EXMC_NOE low time
40.5
42.5
ns
th(NE_NOE)
EXMC_NOE high to EXMC_NE high hold time
0
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tsu(DATA_NE)
Data to EXMC_NEx high setup time
32.2
—
ns
tsu(DATA_NOE)
Data to EXMC_NOEx high setup time
32.2
—
ns
th(DATA_NOE)
Data hold time after EXMC_NOE high
0
—
ns
th(DATA_NE)
Data hold time after EXMC_NEx high
0
—
ns
tv(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
(1)
(2)
(3)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
Table 4-36. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
23.9
25.9
ns
tV(NWE_NE)
EXMC_NEx low to EXMC_NWE low
7.3
—
ns
tw(NWE)
EXMC_NWE low time
7.3
9.3
ns
th(NE_NWE)
EXMC_NWE high to EXMC_NE high hold time
7.3
9.3
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tV(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
15.6
—
ns
th(AD_NADV)
EXMC_AD(address) valid hold time after
EXMC_NADV high
th(A_NWE)
Address hold time after EXMC_NWE high
7.3
—
ns
th(BL_NWE)
EXMC_BL hold time after EXMC_NWE high
7.3
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tv(DATA_NADV)
EXMC_NADV high to DATA valid
0
—
ns
th(DATA_NWE)
Data hold time after EXMC_NWE high
7.3
—
ns
(1)
(2)
(3)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime= 1, DataSetupTime = 1.
82
GD32F207xx Datasheet
Table 4-37. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
57.1
59.1
ns
tV(NOE_NE)
EXMC_NEx low to EXMC_NOE low
23.9
—
ns
tw(NOE)
EXMC_NOE low time
32.2
34.2
ns
th(NE_NOE)
EXMC_NOE high to EXMC_NE high hold time
0
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tv(A_NOE)
Address hold time after EXMC_NOE high
0
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
th(BL_NOE)
EXMC_BL hold time after EXMC_NOE high
0
—
ns
tsu(DATA_NE)
Data to EXMC_NEx high setup time
33.2
—
ns
tsu(DATA_NOE)
Data to EXMC_NOEx high setup time
33.2
—
ns
th(DATA_NOE)
Data hold time after EXMC_NOE high
0
—
ns
th(DATA_NE)
Data hold time after EXMC_NEx high
0
—
ns
tv(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
7.3
9.3
ns
Th(AD_NADV)
(1)
(2)
(3)
EXMC_AD(adress) valid hold time after
EXMC_NADV high
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
Table 4-38. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
40.5
42.5
ns
tV(NWE_NE)
EXMC_NEx low to EXMC_NWE low
7.3
—
ns
tw(NWE)
EXMC_NWE low time
23.9
25.9
ns
th(NE_NWE)
EXMC_NWE high to EXMC_NE high hold time
7.3
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tV(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
7.3
9.3
ns
7.3
—
ns
th(AD_NADV)
EXMC_AD(address) valid hold time after
EXMC_NADV high
th(A_NWE)
Address hold time after EXMC_NWE high
7.3
—
ns
th(BL_NWE)
EXMC_BL hold time after EXMC_NWE high
7.3
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tv(DATA_NADV)
EXMC_NADV high to DATA valid
7.3
—
ns
th(DATA_NWE)
Data hold time after EXMC_NWE high
7.3
—
ns
(1)
(2)
(3)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime =1.
83
GD32F207xx Datasheet
Table 4-39. Synchronous multiplexed PSRAM/NOR read timings
(1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NOEL)
EXMC_CLK low to EXMC_NOE low
0
—
ns
td(CLKH-NOEH)
EXMC_CLK high to EXMC_NOE high
15.6
—
ns
td(CLKL-ADV)
EXMC_CLK low to EXMC_AD valid
0
—
ns
td(CLKL-ADIV)
EXMC_CLK low to EXMC_AD invalid
0
—
ns
(1)
(2)
(3)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; Memory Type = PSRAM; WriteBurst =
Enable; CLKDivision = 3(EXMC_CLK is 4 divided by HCLK); Data Latency = 1.
Table 4-40. Synchronous multiplexed PSRAM write timings
(1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NWEL)
EXMC_CLK low to EXMC_NWE low
0
—
ns
td(CLKH-NWEH)
EXMC_CLK high to EXMC_NWE high
15.6
—
ns
td(CLKL-ADIV)
EXMC_CLK low to EXMC_AD invalid
0
—
ns
td(CLKL-DATA)
EXMC_A/D valid data after EXMC_CLK low
0
—
ns
th(CLKL-NBLH)
EXMC_CLK low to EXMC_NBL high
0
—
ns
(1)
(2)
(3)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst =
Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
84
GD32F207xx Datasheet
Table 4-41. Synchronous non-multiplexed PSRAM/NOR read timings (1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NOEL)
EXMC_CLK low to EXMC_NOE low
0
—
ns
td(CLKH-NOEH)
EXMC_CLK high to EXMC_NOE high
15.6
—
ns
(1)
(2)
(3)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: HCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst =
Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
Table 4-42. Synchronous non-multiplexed PSRAM write timings (1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
33.2
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
15.6
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
15.6
—
ns
td(CLKL-NWEL)
EXMC_CLK low to EXMC_NWE low
0
—
ns
td(CLKH-NWEH)
EXMC_CLK high to EXMC_NWE high
15.6
—
ns
td(CLKL-DATA)
EXMC_A/D valid data after EXMC_CLK low
0
—
ns
th(CLKL-NBLH)
EXMC_CLK low to EXMC_NBL high
0
—
ns
(1)
(2)
(3)
4.24.
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: HCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst =
Enable; CLKDivision = 3(EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
TIMER characteristics
Table 4-43. TIMER characteristics (1)
Symbol
Parameter
Conditions
Min
Max
Unit
tres
Timer resolution time
—
1
—
tTIMERxCLK
fTIMERxCLK = 120 MHz
8.4
—
ns
fEXT
Timer external clock frequency
—
0
fTIMERxCLK/2
MHz
fTIMERxCLK = 200 MHz
0
60
MHz
RES
Timer resolution
—
—
16
bit
tCOUNTER
16-bit counter clock period
—
1
65536
tTIMERxCLK
85
GD32F207xx Datasheet
fTIMERxCLK = 120 MHz 0.0084
when internal clock is selected
tMAX_COUNT
(1)
4.25.
Maximum possible count
—
—
fTIMERxCLK = 120 MHz
—
546
μs
65536x65536 tTIMERxCLK
35.7
s
Guaranteed by design, not tested in production.
DCI characteristics
Table 4-44. DCI characteristics (1)
Symbol
Parameter
Min
Max
Frequency ratio
DCI_PIXCLK /fHCLK
—
0.4
DCI_PIXCLK
Pixel clock input
—
48
MHz
DPixel
Pixel clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
2.5
—
ns
th(DATA)
Data output valid time
1
—
ns
tsu(HSYNC)
DCI_HS input setup time
2
—
ns
tsu(VSYNC)
DCI_VS input setup time
2
—
ns
th(HSYNC)
DCI_HS input hold time
0.5
—
ns
th(VSYNC)
DCI_VS input hold time
0.5
—
ns
(1)
4.26.
Unit
Guaranteed by design, not tested in production.
WDGT characteristics
Table 4-45. FWDGT min/max timeout period at 40 kHz (IRC40K) (1)
Prescaler divider
PSC[2:0] bits
1/4
(1)
Min timeout RLD[11:0] = Max timeout RLD[11:0]
0x000
= 0xFFF
000
0.025
409.525
1/8
001
0.025
819.025
1/16
010
0.025
1638.025
1/32
011
0.025
3276.025
1/64
100
0.025
6552.025
1/128
101
0.025
13104.025
1/256
110 or 111
0.025
26208.025
Unit
ms
Guaranteed by design, not tested in production.
Table 4-46. WWDGT min-max timeout value at 60 MHz (fPCLK1) (1)
Min timeout value
Prescaler divider
PSC[1:0]
1/1
00
68.2
1/2
01
136.4
1/4
10
272.8
1/8
11
545.6
(1)
CNT[6:0] = 0x40
Unit
Max timeout value
CNT[6:0] = 0x7F
Unit
4.3
μs
8.6
17.2
ms
34.4
Guaranteed by design, not tested in production.
86
GD32F207xx Datasheet
4.27.
Parameter conditions
Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 ℃.
87
GD32F207xx Datasheet
5.
Package information
5.1.
LQFP176 package outline dimensions
Figure 5-1. LQFP176 package outline
c
A2A
θ
F
A1
D
D1
132
89
88
133
E1
E
0.25
L
L1
DETAIL: F
176
45
1
44
b
e
Table 5-1. LQFP176 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
b
0.17
—
0.27
c
0.09
—
0.20
D
—
26.00
—
D1
—
24.00
—
E
—
26.00
—
E1
—
24.00
—
e
—
0.50
—
L
0.45
0.60
0.75
L1
—
1.00
—
θ
0°
3.5°
7°
(Original dimensions are in millimeters)
88
GD32F207xx Datasheet
Figure 5-2. LQFP176 recommended footprint
26.70
133
176
24.30
132
44
89
21.80
26.70
0.30
1
88
45
1.20
0.50
(Original dimensions are in millimeters)
89
GD32F207xx Datasheet
LQFP144 package outline dimensions
Figure 5-3. LQFP144 package outline
A3
c
A2A
F
θ
5.2.
A1
D
D1
108
73
109
72
0.25
L
L1
DETAIL: F
E1 E
b
b1
c1 c
37
144
BASE METAL
WITH PLATING
1
e
b
BB
SECTION B-B
36
Table 5-2. LQFP144 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
21.80
22.00
22.20
D1
19.90
20.00
20.10
E
21.80
22.00
22.20
E1
19.90
20.00
20.10
e
—
0.50
—
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
(Original dimensions are in millimeters)
90
GD32F207xx Datasheet
Figure 5-4. LQFP144 recommended footprint
22.70
109
144
20.30
108
36
73
72
37
17.80
22.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
91
GD32F207xx Datasheet
5.3.
LQFP100 package outline dimensions
Figure 5-5. LQFP100 package outline
A3
A2 A
c
θ
A1
F
eB
D
D1
51
75
0.25
50
76
L
L1
DETAIL: F
E1
E
b
b1
100
c1 c
26
BASE METAL
1
25
b
e
WITH PLATING
B B
SECTION B-B
Table 5-3. LQFP100 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
15.80
16.00
16.20
D1
13.90
14.00
14.10
E
15.80
16.00
16.20
E1
13.90
14.00
14.10
e
—
0.50
—
eB
15.05
—
15.35
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
(Original dimensions are in millimeters)
92
GD32F207xx Datasheet
Figure 5-6. LQFP100 recommended footprint
16.70
76
100
14.30
75
25
51
50
26
12.30
16.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
93
GD32F207xx Datasheet
5.4.
LQFP64 package outline dimensions
Figure 5-7. LQFP64 package outline
A3
A2 A
θ
c
A1
F
eB
D
D1
33
48
0.25
32
49
L
L1
DETAIL: F
E1
E
b
b1
c1 c
BASE METAL
64
17
WITH PLATING
1
e
b
SECTION B-B
16
B B
Table 5-4. LQFP64 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
11.80
12.00
12.20
D1
9.90
10.00
10.10
E
11.80
12.00
12.20
E1
9.90
10.00
10.10
e
—
0.50
—
eB
11.25
—
11.45
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
(Original dimensions are in millimeters)
94
GD32F207xx Datasheet
Figure 5-8. LQFP64 recommended footprint
12.70
64
49
10.30
48
16
33
17
32
7.80
12.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
95
GD32F207xx Datasheet
5.5.
Thermal characteristics
Thermal resistance is used to characterize the thermal performance of the package device,
which is represented by the Greek letter “θ”. For semiconductor devices, thermal resistance
represents the steady-state temperature rise of the chip junction due to the heat dissipated
on the chip surface.
θJA: Thermal resistance, junction-to-ambient.
θJB: Thermal resistance, junction-to-board.
θJC: Thermal resistance, junction-to-case.
ᴪJB: Thermal characterization parameter, junction-to-board.
ᴪJT: Thermal characterization parameter, junction-to-top center.
θJA =(TJ -TA )/PD
(5-1)
θJB =(TJ -TB )/PD
(5-2)
θJC =(TJ -TC )/PD
(5-3)
Where, TJ = Junction temperature.
TA = Ambient temperature
TB = Board temperature
TC = Case temperature which is monitoring on package surface
PD = Total power dissipation
θJA represents the resistance of the heat flows from the heating junction to ambient air. It is
an indicator of package heat dissipation capability. Lower θJA can be considerate as better
overall thermal performance. θJA is generally used to estimate junction temperature.
θJB is used to measure the heat flow resistance between the chip surface and the PCB board.
θJC represents the thermal resistance between the chip surface and the package top case.
θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat
dissipation methods outside the device package).
Table 5-5. Package thermal characteristics(1)
Symbol
θJA
θJB
Condition
Natural convection, 2S2P PCB
Cold plate, 2S2P PCB
Package
Value
LQFP176
—
LQFP144
48.76
LQFP100
57.42
LQFP64
61.80
LQFP176
—
LQFP144
35.00
LQFP100
31.68
Unit
°C/W
°C/W
96
GD32F207xx Datasheet
Symbol
θJC
ᴪJB
ᴪJT
(1)
Condition
Cold plate, 2S2P PCB
Natural convection, 2S2P PCB
Natural convection, 2S2P PCB
Package
Value
LQFP64
42.83
LQFP176
—
LQFP144
12.03
LQFP100
13.85
LQFP64
21.98
LQFP176
—
LQFP144
35.32
LQFP100
41.28
LQFP64
43.05
LQFP176
—
LQFP144
1.86
LQFP100
0.75
LQFP64
1.58
Unit
°C/W
°C/W
°C/W
Thermal characteristics are based on simulation, and meet JEDEC specification.
97
GD32F207xx Datasheet
6.
Ordering information
Table 6-1. Part ordering code for GD32F207xx devices
Ordering code
Flash (KB)
Package
Package type
GD32F207IKT6
3072
LQFP176
Green
GD32F207IGT6
1024
LQFP176
Green
GD32F207IET6
512
LQFP176
Green
GD32F207ZKT6
3072
LQFP144
Green
GD32F207ZGT6
1024
LQFP144
Green
GD32F207ZET6
512
LQFP144
Green
GD32F207ZCT6
256
LQFP144
Green
GD32F207VKT6
3072
LQFP100
Green
GD32F207VGT6
1024
LQFP100
Green
GD32F207VET6
512
LQFP100
Green
GD32F207VCT6
256
LQFP100
Green
GD32F207RKT6
3072
LQFP64
Green
GD32F207RGT6
1024
LQFP64
Green
GD32F207RET6
512
LQFP64
Green
GD32F207RCT6
256
LQFP64
Green
Temperature
operating range
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
98
GD32F207xx Datasheet
7.
Revision history
Table 7-1. Revision history
Revision
Description
Date
1.0
Initial Release
Jul. 10, 2015
2.0
Adapt To New Name Convention
Jan. 24, 2018
2.1
Change pin definitions
Dec. 7, 2018
2.2
Modify the clock tree
Nov. 30, 2019
No.
1.Modify the HXTAL frequency range of the clock tree to 4-32MHz。
2.3
2.The ADC2 mapping function corresponding to PF3, PF4 and PF5
Mar.13, 2020
pins is modified to multiplexing function.
2.4
1. Modify the Table 4 3. Power consumption characteristics. Add
test conditions and parameters in Deep-Sleep and Standby mode
Jun.1, 2021
1. Modified the description of zero wait in Code Flash, refer to
ARM® Cortex®-M3 core.
2.5
2. Update the pin names of EXMC_NL, EXMC_A16 and EXMC_A17
to EXMC_NL/EXMC_NADV, EXMC_A16/EXMC_CLE, and
Jul.18, 2022
EXMC_A17/EXMC_ALE, refer to Pin definitions.
3. Update the Electrical characteristics covering most chapter.
99
GD32F207xx Datasheet
Important Notice
This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any
product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and
treaties of the People’s Republic of China and other jurisdictions worldwide. The Company reserves all rights under such laws and
treaties and does not grant any license under its patents, copyrights, trademarks, or other intellectual property rights. The names and
brands of third party referred thereto (if any) are the property of their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product, including, but not
limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company does not assume any liability
arising out of the application or use of any Product described in this document. Any information provided in this document is provided
only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality
and safety of any application made of this information and any resulting product. Except for customized products which has been
expressly identified in the applicable agreement, the Products are designed, developed, and/or manufactured for ordinary business,
industrial, personal, and/or household applications only. The Products are not designed, intended, or authorized for use as components
in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, atomic energy control
instruments, combustion control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution
control or hazardous substances management, or other uses where the failure of the device or Product could cause personal injury,
death, property or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling
the Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and customers
shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage, or other liability arising
from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the Company as well as it’s suppliers
and/or distributors harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or
death, arising from or related to any Unintended Uses of the Products.
Information in this document is provided solely in connection with the Products. The Company reserves the right to make changes,
corrections, modifications or improvements to this document and Products and services described herein at any time, without notice.
© 2022 GigaDevice – All rights reserved
100
工商网监
湘ICP备2023018690号
