GigaDevice Semiconductor Inc.
GD32F403xx
ARM® Cortex®-M4 32-bit MCU
Datasheet
GD32F403xx Datasheet
Table of Contents
Table of Contents ........................................................................................................... 1
List of Figures ................................................................................................................ 4
List of Tables .................................................................................................................. 6
1. General description ................................................................................................. 8
2. Device overview ....................................................................................................... 9
2.1.
Device information ....................................................................................................................... 9
2.2.
Block diagram ............................................................................................................................. 12
2.3.
Pinouts and pin assignment ..................................................................................................... 13
2.4.
Memory map ............................................................................................................................... 16
2.5.
Clock tree .................................................................................................................................... 20
2.6.
Pin definitions ............................................................................................................................. 21
2.6.1.
2.6.2.
2.6.3.
2.6.4.
GD32F403Zx LQFP144 pin definitions.................................................................. 21
GD32F403Vx LQFP100 pin definitions ................................................................. 29
GD32F403Rx LQFP64 pin definitions ................................................................... 35
GD32F403Vx BGA100 pin definitions ................................................................... 39
3. Functional description .......................................................................................... 45
3.1.
ARM® Cortex®-M4 core............................................................................................................... 45
3.2.
On-chip memory ......................................................................................................................... 45
3.3.
Clock, reset and supply management ...................................................................................... 46
3.4.
Boot modes ................................................................................................................................. 46
3.5.
Power saving modes .................................................................................................................. 47
3.6.
Analog to digital converter (ADC)............................................................................................. 47
3.7.
Digital to analog converter (DAC) ............................................................................................. 48
3.8.
DMA ............................................................................................................................................. 48
3.9.
General-purpose inputs/outputs (GPIOs) ................................................................................ 48
3.10.
Timers and PWM generation ................................................................................................. 49
3.11.
Real time clock (RTC) ............................................................................................................. 50
3.12.
Inter-integrated circuit (I2C) .................................................................................................. 50
3.13.
Serial peripheral interface (SPI) ............................................................................................ 50
3.14.
Universal synchronous asynchronous receiver transmitter (USART) ............................. 51
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GD32F403xx Datasheet
3.15.
Inter-IC sound (I2S) ................................................................................................................ 51
3.16.
Universal serial bus on-the-go full-speed (USBFS) ............................................................ 51
3.17.
Controller area network (CAN) .............................................................................................. 52
3.18.
Secure digital input and output card interface (SDIO) ....................................................... 52
3.19.
External memory controller (EXMC) ..................................................................................... 52
3.20.
Debug mode ............................................................................................................................ 53
3.21.
Package and operation temperature .................................................................................... 53
4. Electrical characteristics ....................................................................................... 54
4.1.
Absolute maximum ratings ....................................................................................................... 54
4.2.
Operating conditions characteristics ....................................................................................... 54
4.3.
Power consumption ................................................................................................................... 56
4.4.
EMC characteristics ................................................................................................................... 63
4.5.
Power supply supervisor characteristics ................................................................................ 64
4.6.
Electrical sensitivity ................................................................................................................... 65
4.7.
External clock characteristics................................................................................................... 65
4.8.
Internal clock characteristics .................................................................................................... 67
4.9.
PLL characteristics .................................................................................................................... 69
4.10.
Memory characteristics ......................................................................................................... 70
4.11.
NRST pin characteristics ....................................................................................................... 71
4.12.
GPIO characteristics .............................................................................................................. 71
4.13.
ADC characteristics ............................................................................................................... 73
4.14.
Temperature sensor characteristics .................................................................................... 74
4.15.
DAC characteristics ............................................................................................................... 75
4.16.
I2C characteristics .................................................................................................................. 76
4.17.
SPI characteristics ................................................................................................................. 77
4.18.
I2S characteristics .................................................................................................................. 78
4.19.
USART characteristics ........................................................................................................... 78
4.20.
SDIO characteristics .............................................................................................................. 79
4.21.
CAN characteristics ............................................................................................................... 79
4.22.
USBFS characteristics ........................................................................................................... 79
4.23.
EXMC characteristics ............................................................................................................. 80
4.24.
TIMER characteristics ............................................................................................................ 84
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GD32F403xx Datasheet
4.25.
WDGT characteristics ............................................................................................................ 85
4.26.
Parameter conditions ............................................................................................................. 85
5. Package information.............................................................................................. 86
5.1.
LQFP144 package outline dimensions .................................................................................... 86
5.2.
LQFP100 package outline dimensions .................................................................................... 87
5.3.
BGA100 package outline dimensions ...................................................................................... 88
5.4.
LQFP64 package outline dimensions ...................................................................................... 89
6. Ordering information ............................................................................................. 91
7. Revision history ..................................................................................................... 92
3
GD32F403xx Datasheet
List of Figures
Figure 2-1. GD32F403xx block diagram ............................................................................................................. 12
Figure 2-2. GD32F403Zx LQFP144 pinouts ....................................................................................................... 13
Figure 2-3. GD32F403Vx LQFP100 pinouts ....................................................................................................... 14
Figure 2-4. GD32F403Rx LQFP64 pinouts ......................................................................................................... 15
Figure 2-5. GD32F403Vx BGA100 pinouts ........................................................................................................ 16
Figure 2-6. GD32F403xx clock tree ..................................................................................................................... 20
Figure 4-1. Recommended power supply decoupling capacitors (1) (2) ....................................................... 55
Figure 4-2. Typical supply current consumption in Run mode ................................................................... 61
Figure 4-3. Typical supply current consumption in Sleep mode ................................................................ 62
Figure 4-4. Recommended external NRST pin circuit .................................................................................... 71
Figure 4-5. I/O port AC characteristics definition ............................................................................................ 72
Figure 4-6. USBFS timings: definition of data signal rise and fall time ..................................................... 80
Figure 5-1. LQFP144 package outline ................................................................................................................ 86
Figure 5-2. LQFP100 package outline ................................................................................................................ 87
Figure 5-3. LQFP100 package outline ................................................................................................................ 88
Figure 5-4. LQFP64 package outline .................................................................................................................. 89
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GD32F403xx Datasheet
5
GD32F403xx Datasheet
List of Tables
Table 2-1. GD32F403xx devices features and peripheral list ......................................................................... 9
Table 2-2. GD32F403xx devices features and peripheral list (Cont.) ......................................................... 11
Table 2-3. GD32F403xx memory map ................................................................................................................. 16
Table 2-4. GD32F403Zx LQFP144 pin definitions ............................................................................................ 21
Table 2-5. GD32F403Vx LQFP100 pin definitions ............................................................................................ 29
Table 2-6. GD32F403Rx LQFP64 pin definitions.............................................................................................. 35
Table 2-7. GD32F403Vx BGA100 pin definitions ............................................................................................. 39
Table 4-1. Absolute maximum ratings(1) (4) ........................................................................................................ 54
Table 4-2. DC operating conditions .................................................................................................................... 54
Table 4-3. Clock frequency(1) ................................................................................................................................ 55
Table 4-4. Operating conditions at Power up / Power down (1) ..................................................................... 55
Table 4-5. Start-up timings of Operating conditions (1)(2)(3) ............................................................................. 55
Table 4-6. Power saving mode wakeup timings characteristics(1)(2) ........................................................... 55
Table 4-7. Power consumption characteristics (2)(3)(4)(5) .................................................................................. 56
Table 4-8. Peripheral current consumption characteristics(1) ...................................................................... 62
Table 4-9. EMS characteristics(1) ......................................................................................................................... 64
Table 4-10. Power supply supervisor characteristics .................................................................................... 64
Table 4-11. ESD characteristics(1) ........................................................................................................................ 65
Table 4-12. Static latch-up characteristics(1)..................................................................................................... 65
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics .. 65
Table 4-14. High speed external clock characteristics (HXTAL in bypass mode) .................................. 66
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ... 66
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode) .......................... 67
Table 4-17. High speed internal clock (IRC8M) characteristics ................................................................... 67
Table 4-18. Low speed internal clock (IRC40K) characteristics .................................................................. 68
Table 4-19. High speed internal clock (IRC48M) characteristics ................................................................. 68
Table 4-20. PLL characteristics............................................................................................................................ 69
Table 4-21. PLL1 characteristics ......................................................................................................................... 69
Table 4-22. PLL2 characteristics ......................................................................................................................... 70
Table 4-23. Flash memory characteristics ........................................................................................................ 70
Table 4-24. NRST pin characteristics ................................................................................................................. 71
Table 4-25. I/O port DC characteristics(1) (3) ....................................................................................................... 71
Table 4-26. I/O port AC characteristics(1)(2) ........................................................................................................ 72
Table 4-27. ADC characteristics .......................................................................................................................... 73
Table 4-28. ADC RAIN max for fADC = 40 MHz ......................................................................................................... 74
Table 4-29. ADC dynamic accuracy at fADC = 14 MHz(1) .................................................................................. 74
Table 4-30. ADC dynamic accuracy at fADC = 40 MHz(1) .................................................................................. 74
Table 4-31. ADC static accuracy at fADC = 14 MHz(1) ........................................................................................ 74
Table 4-32. Temperature sensor characteristics(1) .......................................................................................... 74
Table 4-33. DAC characteristics .......................................................................................................................... 75
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GD32F403xx Datasheet
Table 4-34. I2C characteristics(1)(2)....................................................................................................................... 76
Table 4-35. Standard SPI characteristics(1) ....................................................................................................... 77
Table 4-36. I2S characteristics(1) (2) ...................................................................................................................... 78
Table 4-37. USART characteristics(1) .................................................................................................................. 78
Table 4-38. SDIO characteristics(1) (2) .................................................................................................................. 79
Table 4-39. USBFS start up time .......................................................................................................................... 79
Table 4-40. USBFS DC electrical characteristics ............................................................................................ 80
Table 4-41. USBFS full speed-electrical characteristics(1) ............................................................................ 80
Table 4-42. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)(3)(4) ......................... 80
Table 4-43. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)(3)(4) ........................ 81
Table 4-44. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)(3)(4)............................................... 81
Table 4-45. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)(3)(4) .............................................. 82
Table 4-46. Synchronous multiplexed PSRAM/NOR read timings(1)(2)(3)(4) ................................................. 82
Table 4-47. Synchronous multiplexed PSRAM write timings(1)(2)(3)(4) .......................................................... 83
Table 4-48. Synchronous non-multiplexed PSRAM/NOR read timings(1)(2)(3)(4) ........................................ 83
Table 4-49. Synchronous non-multiplexed PSRAM write timings (1)(2)(3)(4) ................................................ 84
Table 4-50. TIMER characteristics(1).................................................................................................................... 84
Table 4-51. FWDGT min/max timeout period at 40 kHz (IRC40K) (1) ............................................................ 85
Table 4-52. WWDGT min-max timeout value at 84 MHz (fPCLK1) (1) ............................................................... 85
Table 5-1. LQFP144 package dimensions ......................................................................................................... 86
Table 5-2. LQFP100 package dimensions ......................................................................................................... 87
Table 5-3. BGA100 package dimensions ........................................................................................................... 88
Table 5-4. LQFP64 package dimensions ........................................................................................................... 89
Table 6-1. Part ordering code for GD32F403xx devices ................................................................................ 91
Table 7-1. Revision history.................................................................................................................................... 92
7
GD32F403xx Datasheet
1.
General description
The GD32F403xx device belongs to the performance line of GD32 MCU Family. It is a new
32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best
cost-performance ratio in terms of enhanced processing capacity, reduced power
consumption and peripheral set. The Cortex®-M4 core implements a full set of DSP
instructions to address digital signal control markets that demand an efficient, easy-to-use
blend of control and signal processing capabilities. It also provides a Memory Protection Unit
(MPU) and powerful trace technology for enhanced application security and advanced debug
support.
The GD32F403xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating
at 168 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It
provides up to 3072 KB on-chip Flash memory and 128 KB SRAM memory. An extensive
range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up
to three 12-bit 2.6M MSPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers,
two 16-bit PWM advanced-control timers, and two 16-bit basic timers, as well as standard
and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two
UARTs, two I2Ss, two CANs, a SDIO, and an USBFS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make GD32F403xx devices suitable for a wide range of interconnection
and advanced applications, especially in areas such as industrial control, consumer and
handheld equipment, embedded modules, human machine interface, security and alarm
systems, graphic display, automotive navigation, drone, IoT and so on.
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GD32F403xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32F403xx devices features and peripheral list
GD32F403xx
Part Number
RC
RE
RG
RI
RK
VC
VE
VG
VI
VK
256
256
256
256
256
256
256
256
256
256
0
256
768
1792
2816
0
256
768
1792
2816
256
512
1024
2048
3072
256
512
1024
2048
3072
SRAM (KB)
64
96
128
128
128
64
96
128
128
128
General
8
8
8
8
8
8
8
8
8
8
timer(16-bit)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
Advanced
2
2
2
2
2
2
2
2
2
2
timer(16-bit)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
Code area
Flash
(KB)
Data area
(KB)
Timers
Total (KB)
Basic
2
2
2
2
2
2
2
2
2
2
timer(16-bit)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
SysTick
1
1
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
USART
3
3
3
3
3
3
3
3
3
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
2
2
2
2
2
2
2
2
2
2
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
2
2
2
2
2
2
2
2
2
2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
SDIO
1
1
1
1
1
1
1
1
1
1
CAN
2
2
2
2
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
1
1
1
1
GPIO
51
51
51
51
51
80
80
80
80
80
EXMC
0
0
0
0
0
1
1
1
1
1
EXTI
16
16
16
16
16
16
16
16
16
16
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
UART
Connectivity
3
(0-2)
I2C
SPI/I2S
ADC Unit (CHs) 3(16)
9
GD32F403xx Datasheet
DAC
Package
2
2
2
LQFP64
2
2
2
2
2
2
2
LQFP100
10
GD32F403xx Datasheet
Table 2-2. GD32F403xx devices features and peripheral list (Cont.)
GD32F403xx
Part Number
VC
VE
VG
VI
VK
ZC
ZE
ZG
ZI
ZK
256
256
256
256
256
256
256
256
256
256
0
256
768
1792
2816
0
256
768
1792
2816
256
512
1024
2048
3072
256
512
1024
2048
3072
SRAM (KB)
64
96
128
128
128
64
96
128
128
128
General
8
8
8
8
8
8
8
8
8
8
timer(16-bit)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
(2-3,8-13)
Code area
Flash
(KB)
Data area
(KB)
Timers
Total (KB)
Advanced
2
2
2
2
2
2
2
2
2
2
timer(16-bit)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
(0,7)
Basic
2
2
2
2
2
2
2
2
2
2
timer(16-bit)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
SysTick
1
1
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
USART
3
3
3
3
3
3
3
3
3
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
2
2
2
2
2
2
2
2
2
2
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
(3-4)
2
2
2
2
2
2
2
2
2
2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
SDIO
1
1
1
1
1
1
1
1
1
1
CAN
2
2
2
2
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
1
1
1
1
GPIO
80
80
80
80
80
112
112
112
112
112
EXMC
1
1
1
1
1
1
1
1
1
1
EXTI
16
16
16
16
16
16
16
16
16
16
3(16)
3(16)
3(16)
3(16)
3(21)
3(21)
3(21)
3(21)
3(21)
2
2
2
2
2
2
2
2
2
UART
Connectivity
3
(0-2)
I2C
SPI/I2S
ADC Unit (CHs) 3(16)
DAC
Package
2
BGA100
LQFP144
11
GD32F403xx Datasheet
2.2.
Block diagram
Figure 2-1. GD32F403xx block diagram
SW/JTAG
TPIU
NVIC
ICode DCode System
ARM Cortex-M4
Processor
Fmax:168MHz
POR/ PDR
Flash
Memory
Controller
Ibus
Flash
Memory
PLL
F max : 168MHz
Dbus
FMC
Master
Master
Slave
EXMC
Slave
Slave
CRC
RCU
SDIO
LDO
1.2V
AHB Peripherals
Slave
AHB Matrix
GP DMA 12 chs
USBFS
SRAM
Controller
IRC
8MHz
SRAM
AHB to APB
Bridge2
HXTAL
3-25MHz
AHB to APB
Bridge 1
LVD
Interrput request
CAN0
USART0
Slave
12-bit
SAR ADC
Slave
SPI0
WWDGT
ADC0~2
TIMER2~3
EXTI
SPI1~2/
I2S1~2
GPIOA
USART1~2
GPIOB
I2C0
Powered By V DDA
GPIOE
APB1: Fmax = 84MHZ
GPIOD
APB2: Fmax = 168MHz
GPIOC
Powered By VDDA
I2C1
FWDGT
RTC
GPIOF
DAC
GPIOG
TIMER5~6
TIMER0
UART3~4
TIMER7
CAN1
TIMER8~10
TIMER
11~13
CTC
12
GD32F403xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32F403Zx LQFP144 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109
PE2
1
108
PE3
PE4
2
107
VSS_2
3
106
NC
PE5
PE6
4
105
PA13
5
104
PA12
VBAT
6
103
PA11
PC13-TAMPER-RTC
PC14-OSC32IN
7
102
PA10
8
101
PA9
PC15-OSC32OUT
9
100
PA8
PF0
10
99
PC9
PF1
11
98
PC8
PF2
12
97
PC7
PF3
PF4
13
96
PC6
14
95
VDD_9
PF5
15
94
VSS_9
VSS_5
16
93
PG8
92
PG7
91
PG6
90
PG5
89
PG4
88
PG3
VDD_2
VDD_5
17
PF6
18
PF7
19
PF8
20
PF9
21
PF10
22
87
PG2
OSCIN
23
86
PD15
OSCOUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
82
PD13
PC2
28
81
PD12
PC3
VSSA
29
80
PD11
30
79
PD10
VREFVREF+
31
78
PD9
32
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
GigaDevice GD32F403Zx
LQFP144
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE8
PE9
PE7
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
13
GD32F403xx Datasheet
Figure 2-3. GD32F403Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32IN
7
70
69
PA10
8
68
PA9
PC15-OSC32OUT
9
67
PA8
VSS_5
10
66
PC9
VDD_5
11
65
PC8
64
PC7
63
PC6
14
62
PD15
OSCIN
12
GigaDevice GD32F403Vx
LQFP100
VDD_2
PA11
OSCOUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
14
GD32F403xx Datasheet
Figure 2-4. GD32F403Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32IN
3
46
PA13
PC15-OSC32OUT
PD0-OSCIN
4
45
PA12
5
44
PA11
PD1 OSCOUT
6
43
PA10
7
42
PA9
41
PA8
NRST
PC0
GigaDevice GD32F403Rx
LQFP64
8
PC1
9
40
PC9
PC2
PC3
VSSA
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PB11
PB10
PB2
PB1
PB0
PC5
PA7
PC4
PA6
PA5
PA4
VDD_4
VSS_4
PA3
15
GD32F403xx Datasheet
Figure 2-5. GD32F403Vx BGA100 pinouts
2.4.
1
2
A
PE3
PE1
B
PE4
C
3
4
5
6
7
8
PB8 BOOT0
PD7
PD5
PB4
PB3
PA15 PA14
PE2
PB9
PB7
PB6
PD6
PD4
PD3
PD1
PC12 PC10 PA11
PC13
PE5
PE0
VDD
PB5
PD2
PD0
PC11
NC
PA10
D
PC14
PE6
VSS
PA9
PA8
PC9
E
PC15 VBAT
VSS
PC8
PC7
PC6
VSS
VSS
VDD
VDD
F
OSC
IN
VSS
G
OSC
OUT
VDD
H
PC0 NRST
9
10
GigaDevice GD32F403Vx
BGA100
11
12
PA13 PA12
VDD
PD15
PD14 PD13
PD12
PD11 PD10
PB15
PB14 PB13
J
VSSA
PC1
PC2
K
VREF-
PC3
PA2
PA5
PC4
L
VREF+
PA0
PA3
PA6
PC5
PB2
PE8
M
VDDA PA1
PA4
PA7
PB0
PB1
PE7
PD9
PB11
PE10 PE12 PB10
PE9
PD8
PB12
PE11 PE13 PE14 PE15
Memory map
Table 2-3. GD32F403xx memory map
Pre-defined
Regions
Bus
External
device
External
AHB3
RAM
Peripheral
AHB1
Address
Peripherals
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
0x9000 0000 - 0x9FFF FFFF
EXMC - PC CARD
0x7000 0000 - 0x8FFF FFFF
EXMC - NAND
0x6000 0000 - 0x6FFF FFFF
EXMC - NOR/PSRAM/SRAM
0x5000 0000 - 0x5003 FFFF
USBFS
0x4008 0000 - 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
Reserved
0x4002 BC00 - 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Reserved
0x4002 A000 - 0x4002 AFFF
Reserved
0x4002 8000 - 0x4002 9FFF
Reserved
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
Reserved
0x4002 6000 - 0x4002 63FF
Reserved
0x4002 5000 - 0x4002 5FFF
Reserved
16
GD32F403xx Datasheet
Pre-defined
Regions
Bus
APB2
Address
Peripherals
0x4002 4000 - 0x4002 4FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Reserved
0x4002 3800 - 0x4002 3BFF
Reserved
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
Reserved
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1C00 - 0x4002 1FFF
Reserved
0x4002 1800 - 0x4002 1BFF
Reserved
0x4002 1400 - 0x4002 17FF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA1
0x4002 0000 - 0x4002 03FF
DMA0
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
SDIO
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
Reserved
0x4001 7400 - 0x4001 77FF
Reserved
0x4001 7000 - 0x4001 73FF
Reserved
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
Reserved
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
Reserved
0x4001 5400 - 0x4001 57FF
TIMER10
0x4001 5000 - 0x4001 53FF
TIMER9
0x4001 4C00 - 0x4001 4FFF
TIMER8
0x4001 4800 - 0x4001 4BFF
Reserved
0x4001 4400 - 0x4001 47FF
Reserved
0x4001 4000 - 0x4001 43FF
Reserved
0x4001 3C00 - 0x4001 3FFF
ADC2
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
TIMER7
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
17
GD32F403xx Datasheet
Pre-defined
Regions
Bus
APB1
Address
Peripherals
0x4001 2000 - 0x4001 23FF
GPIOG
0x4001 1C00 - 0x4001 1FFF
GPIOF
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
CTC
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
0x4000 6000 - 0x4000 63FF
CAN SRAM 512 bytes
0x4000 5C00 - 0x4000 5FFF
Reserved
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
0x4000 1C00 - 0x4000 1FFF
TIMER12
0x4000 1800 - 0x4000 1BFF
TIMER11
18
GD32F403xx Datasheet
Pre-defined
Regions
SRAM
Bus
AHB
Address
Peripherals
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
Reserved
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
Reserved
0x2007 0000 - 0x3FFF FFFF
Reserved
0x2006 0000 - 0x2006 FFFF
Reserved
0x2003 0000 - 0x2005 FFFF
Reserved
0x2002 0000 - 0x2002 FFFF
Reserved
0x2001 C000 - 0x2001 FFFF
0x2001 8000 - 0x2001 BFFF
0x2000 5000 - 0x2001 7FFF
SRAM
0x2000 0000 - 0x2000 4FFF
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF F000 - 0x1FFF F7FF
0x1FFF C010 - 0x1FFF EFFF
0x1FFF C000 - 0x1FFF C00F
Boot loader
0x1FFF B000 - 0x1FFF BFFF
Code
AHB
0x1FFF 7A10 - 0x1FFF AFFF
Reserved
0x1FFF 7800 - 0x1FFF 7A0F
Reserved
0x1FFF 0000 - 0x1FFF 77FF
Reserved
0x1FFE C010 - 0x1FFE FFFF
Reserved
0x1FFE C000 - 0x1FFE C00F
Reserved
0x1001 0000 - 0x1FFE BFFF
Reserved
0x1000 0000 - 0x1000 FFFF
Reserved
0x083C 0000 - 0x0FFF FFFF
Reserved
0x0830 0000 - 0x083B FFFF
Reserved
0x0810 0000 - 0x082F FFFF
0x0802 0000 - 0x080F FFFF
Main Flash
0x0800 0000 - 0x0801 FFFF
0x0030 0000 - 0x07FF FFFF
0x0010 0000 - 0x002F FFFF
0x0002 0000 - 0x000F FFFF
0x0000 0000 - 0x0001 FFFF
Reserved
Aliased to Main Flash or Boot
loader
19
GD32F403xx Datasheet
2.5.
Clock tree
Figure 2-6. GD32F403xx clock tree
CTC
CK_IRC48M
CK_CTC
48 MHz
IRC48M
48 MHz
CK48MSEL
USBFS
Prescaler
1,1.5,2,2.5
3,3.5,4
1
SCS[1:0]
CK_IRC8M
8 MHz
IRC8M
0
1
PLLSEL
PREDV0
0
3-25 MHz
HXTAL
0
1
CK_USBFS
0
(to USBFS)
00
/2
PLLPRESEL
CK_IRC48M
1
1
×2,3,4
…,63
PLL
CK_PLL
PLLMF
/1,2,3…
15,16
10
AHB
Prescaler
÷1,2...512
CK_SYS
168 MHz max
CK_AHB
168 MHz max
CK_EXMC
EXMC enable
(by hardware)
(to EXMC)
HCLK
01
AHB enable
(to AHB bus,Cortex-M4,SRAM,DMA,FMC)
CK_CST
Clock
Monitor
÷8
(to Cortex-M4 SysTick)
FCLK
PREDV0SEL
EXT1 to
CK_OUT
(free running clock)
CK_HXTAL
APB1
Prescaler
÷1,2,4,8,16
CK_APB1
PCLK1
to APB1 peripherals
84 MHz max
Peripheral enable
×8,9,10…,
14,16,20
PLL1
TIMER2,3,5,6,11,
12,13 if(APB1
prescale =1)x1
else x 2
CK_PLL1
×8..14,16,
18..32,40
PLL2
PREDV1
0
CK_PLL2
x2
CK_I2S
1
APB2
Prescaler
÷1,2,4,8,16
11
CK_RTC
01
(to RTC)
10
RTCSRC[1:0]
40 KHz
IRC40K
CK_OUT0
00xx
0100
0101
0110
0111
1000
1001
1010
1011
TIMER0,7,8,9,10
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,6,8,12,1
6
CK_FWDGT
(to FWDGT)
CK_APB2
PCLK2
to APB2 peripherals
168 MHz max
Peripheral enable
I2S1/2SEL
PLL2MF
/128
to TIMER2,3,
5,6,11,12,13
PLL1MF
/1,2,3…
15,16
32.768 KHz
LXTAL
CK_TIMERx
TIMERx
enable
ADC
Prescaler
÷5,6,10,20
CK_TIMERx
TIMERx
enable
to
TIMER0,7,8,9,10
ADCPSC[3]
0
1
CK_ADCx to ADC0,1,2
40 MHz max
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
/2
CK_PLL
CK_PLL1
/2
CK_PLL2
EXT1
CK_PLL2
CKOUT0SEL[3:0]
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC8M: Internal 8M RC oscillators
IRC40K: Internal 40K RC oscillator
IRC48M: Internal 48M RC oscillators
20
GD32F403xx Datasheet
2.6.
Pin definitions
2.6.1.
GD32F403Zx LQFP144 pin definitions
Table 2-4. GD32F403Zx LQFP144 pin definitions
Pin
I/O
Type(1)
Level(2)
1
I/O
5VT
PE3
2
I/O
5VT
PE4
3
I/O
5VT
Pin Name
Pins
PE2
Functions description
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
PE5
4
I/O
5VT
Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0
Default: PE6
PE6
5
I/O
VBAT
6
P
7
I/O
8
I/O
9
I/O
5VT
Alternate:TRACED3, EXMC_A22
Remap: TIMER8_CH1
Default: VBAT
PC13TAMPER-
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
Default: PC14
Alternate: OSC32IN
PC15OSC32OU
Default: PC15
Alternate: OSC32OUT
T
Default: PF0
PF0
10
I/O
5VT
Alternate: EXMC_A0
Remap: CTC_SYNC
PF1
11
I/O
5VT
PF2
12
I/O
5VT
PF3
13
I/O
5VT
PF4
14
I/O
5VT
PF5
15
I/O
5VT
VSS_5
16
P
Default: PF1
Alternate: EXMC_A1
Default: PF2
Alternate: EXMC_A2
Default: PF3
Alternate: EXMC_A3
Default: PF4
Alternate: EXMC_A4
Default: PF5
Alternate: EXMC_A5
Default: VSS_5
21
GD32F403xx Datasheet
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VDD_5
17
P
PF6
18
I/O
Functions description
Default: VDD_5
Default: PF6
Alternate: ADC2_IN4, EXMC_NIORD
Remap: TIMER9_CH0
Default: PF7
PF7
19
I/O
Alternate: ADC2_IN5, EXMC_NREG
Remap: TIMER10_CH0
Default: PF8
PF8
20
I/O
Alternate: ADC2_IN6, EXMC_NIOWR
Remap: TIMER12_CH0
Default: PF9
PF9
21
I/O
Alternate: ADC2_IN7, EXMC_CD
Remap: TIMER13_CH0
Default: PF10
PF10
22
I/O
OSCIN
23
I
OSCOUT
24
O
NRST
25
I/O
PC0
26
I/O
PC1
27
I/O
PC2
28
I/O
PC3
29
I/O
VSSA
30
P
Default: VSSA
VREF-
31
P
Default: VREF-
VREF+
32
P
Default: VREF+
VDDA
33
P
Default: VDDA
PA0-WKUP
34
I/O
Alternate: ADC2_IN8, EXMC_INTR
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Default: PC1
Alternate: ADC012_IN11
Default: PC2
Alternate: ADC012_IN12
Default: PC3
Alternate: ADC012_IN13
Default: PA0
Alternate: WKUP, USART1_CTS, ADC012_IN0,
TIMER7_ETI
PA1
35
I/O
Default: PA1
Alternate: USART1_RTS, ADC012_IN1
Default: PA2
PA2
36
I/O
Alternate: USART1_TX, ADC012_IN2, TIMER8_CH0,
SPI0_IO2
PA3
37
I/O
Default: PA3
Alternate: USART1_RX, ADC012_IN3, TIMER8_CH1,
22
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
SPI0_IO3
VSS_4
38
P
Default: VSS_4
VDD_4
39
P
Default: VDD_4
Default: PA4
PA4
40
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
I/O
DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
41
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
42
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN, TIMER12_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
43
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
44
I/O
PC5
45
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
46
Alternate: ADC01_IN8, TIMER2_CH2,
I/O
TIMER7_CH1_ON
Remap: TIMER0_CH1_ON
Default: PB1
PB1
47
Alternate: ADC01_IN9, TIMER2_CH3,
I/O
TIMER7_CH2_ON
Remap: TIMER0_CH2_ON
Default: PB2, BOOT1
PB2
48
I/O
5VT
PF11
49
I/O
5VT
PF12
50
I/O
5VT
VSS_6
51
P
Default: VSS_6
VDD_6
52
P
Default: VDD_6
PF13
53
I/O
5VT
PF14
54
I/O
5VT
PF15
55
I/O
5VT
Default: PF11
Alternate: EXMC_NIOS16
Default: PF12
Alternate: EXMC_A6
Default: PF13
Alternate: EXMC_A7
Default: PF14
Alternate: EXMC_A8
Default: PF15
Alternate: EXMC_A9
23
GD32F403xx Datasheet
Pin
I/O
Type(1)
Level(2)
56
I/O
5VT
57
I/O
5VT
Pin Name
Pins
PG0
PG1
Functions description
Default: PG0
Alternate: EXMC_A10
Default: PG1
Alternate: EXMC_A11
Default: PE7
PE7
58
I/O
5VT
Alternate: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
59
I/O
5VT
Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
PE9
60
I/O
5VT
Alternate: EXMC_D6
Remap: TIMER0_CH0
VSS_7
61
P
Default: VSS_7
VDD_7
62
P
Default: VDD_7
PE10
63
I/O
Default: PE10
5VT
Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
64
I/O
5VT
Alternate: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
65
I/O
5VT
Alternate: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
66
I/O
5VT
Alternate: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
67
I/O
5VT
Alternate: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
68
I/O
5VT
Alternate: EXMC_D12
Remap: TIMER0_BRKIN
Default: PB10
PB10
69
I/O
5VT
PB11
70
I/O
5VT
VSS_1
71
P
Default: VSS_1
VDD_1
72
P
Default: VDD_1
PB12
73
I/O
Alternate: I2C1_SCL, USART2_TX
Default: PB11
Alternate: I2C1_SDA, USART2_RX
Default: PB12
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
24
GD32F403xx Datasheet
Pin Name
Pins
PB13
74
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PB13
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK, CAN1_TX
Default: PB14
PB14
75
I/O
5VT
Alternate: SPI1_MISO, USART2_RTS,
TIMER0_CH1_ON, TIMER11_CH0
Default: PB15
PB15
76
I/O
5VT
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1
Default: PD8
PD8
77
I/O
5VT
Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
78
I/O
5VT
Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
79
I/O
5VT
Alternate: EXMC_D15
Remap: USART2_CK
Default: PD11
PD11
80
I/O
5VT
Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
81
I/O
5VT
Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
82
I/O
5VT
Alternate: EXMC_A18
Remap: TIMER3_CH1
VSS_8
83
P
Default: VSS_8
VDD_8
84
P
Default: VDD_8
Default: PD14
PD14
85
I/O
5VT
Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
86
I/O
5VT
Alternate: EXMC_D1
Remap: TIMER3_CH3, CTC_SYNC
PG2
87
I/O
5VT
PG3
88
I/O
5VT
PG4
89
I/O
5VT
PG5
90
I/O
5VT
Default: PG2
Alternate: EXMC_A12
Default: PG3
Alternate: EXMC_A13
Default: PG4
Alternate: EXMC_A14
Default: PG5
Alternate: EXMC_A15
25
GD32F403xx Datasheet
Pin
I/O
Type(1)
Level(2)
91
I/O
5VT
PG7
92
I/O
5VT
PG8
93
I/O
5VT
VSS_9
94
P
Default: VSS_9
VDD_9
95
P
Default: VDD_9
PC6
96
I/O
Pin Name
Pins
PG6
Functions description
Default: PG6
Alternate: EXMC_INT1
Default: PG7
Alternate: EXMC_INT2
Default: PG8
Default: PC6
5VT
Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6
Remap: TIMER2_CH0
Default: PC7
PC7
97
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7
Remap: TIMER2_CH1
Default: PC8
PC8
98
I/O
5VT
Alternate: TIMER7_CH2, SDIO_D0
Remap: TIMER2_CH2
Default: PC9
PC9
99
I/O
5VT
Alternate: TIMER7_CH3, SDIO_D1
Remap: TIMER2_CH3
Default: PA8
PA8
100
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF,CTC_SYNC
PA9
101
I/O
5VT
PA10
102
I/O
5VT
Default: PA9
Alternate: USART0_TX, TIMER0_CH1,USBFS_VBUS
Default: PA10
Alternate: USART0_RX, TIMER0_CH2,USBFS_ID
Default: PA11
PA11
103
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
104
I/O
5VT
Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI,
USBFS_DP
5VT
Default: JTMS, SWDIO
PA13
105
I/O
NC
106
-
-
Remap: PA13
VSS_2
107
P
Default: VSS_2
VDD_2
108
P
Default: VDD_2
PA14
109
I/O
5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
110
I/O
5VT
Alternate: SPI2_NSS, I2S2_WS
Remap: PA15, SPI0_NSS
26
GD32F403xx Datasheet
Pin Name
Pins
PC10
111
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PC10
Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
112
I/O
5VT
Alternate: UART3_RX, SDIO_D3
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
113
I/O
5VT
Alternate: UART4_TX, SDIO_CK
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
114
I/O
5VT
Alternate: EXMC_D2
Remap: CAN0_RX, OSCIN
Default: PD1
PD1
115
I/O
5VT
Alternate: EXMC_D3
Remap: CAN0_TX, OSCOUT
PD2
116
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, SDIO_CMD, UART4_RX
Default: PD3
PD3
117
I/O
5VT
Alternate: EXMC_CLK
Remap: USART1_CTS
Default: PD4
PD4
118
I/O
5VT
Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
119
I/O
5VT
Alternate: EXMC_NWE
Remap: USART1_TX
VSS_10
120
P
Default: VSS_10
VDD_10
121
P
Default: VDD_10
PD6
122
I/O
Default: PD6
5VT
Alternate: EXMC_NWAIT
Remap: USART1_RX
Default: PD7
PD7
123
I/O
5VT
Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
PG9
124
I/O
5VT
PG10
125
I/O
5VT
PG11
126
I/O
5VT
PG12
127
I/O
5VT
PG13
128
I/O
5VT
Default: PG9
Alternate: EXMC_NE1, EXMC_NCE2
Default: PG10
Alternate: EXMC_NCE3_0, EXMC_NE2
Default: PG11
Alternate: EXMC_NCE3_1
Default: PG12
Alternate: EXMC_NE3
Default: PG13
27
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: EXMC_A24
5VT
Default: PG14
PG14
129
I/O
VSS_11
130
P
Default: VSS_11
VDD_11
131
P
Default: VDD_11
PG15
132
I/O
5VT
Alternate: EXMC_A25
Default: PG15
Default: JTDO
PB3
133
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
134
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
135
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
136
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX,SPI0_IO2
Default: PB7
PB7
137
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
BOOT0
138
Default: BOOT0
I
Default: PB8
PB8
139
I/O
5VT
Alternate: TIMER3_CH2, SDIO_D4, TIMER9_CH0
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
140
I/O
5VT
Alternate: TIMER3_CH3, SDIO_D5, TIMER10_CH0
Remap: I2C0_SDA, CAN0_TX
Default: PE0
PE0
141
I/O
5VT
PE1
142
I/O
5VT
VSS_3
143
P
Default: VSS_3
VDD_3
144
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
28
GD32F403xx Datasheet
2.6.2.
GD32F403Vx LQFP100 pin definitions
Table 2-5. GD32F403Vx LQFP100 pin definitions
Pin
I/O
Type(1)
Level(2)
1
I/O
5VT
PE3
2
I/O
5VT
PE4
3
I/O
5VT
PE5
4
I/O
5VT
Pin Name
Pins
PE2
Functions description
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0
Default: PE6
5VT
Alternate:TRACED3, EXMC_A22
PE6
5
I/O
VBAT
6
P
7
I/O
8
I/O
9
I/O
VSS_5
10
P
Default: VSS_5
VDD_5
11
P
Default: VDD_5
OSCIN
12
I
OSCOUT
13
O
NRST
14
I/O
PC0
15
I/O
PC1
16
I/O
PC2
17
I/O
PC3
18
I/O
VSSA
19
P
Default: VSSA
VREF-
20
P
Default: VREF-
Remap: TIMER8_CH1
PC13TAMPER-
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OU
T
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Default: PC1
Alternate: ADC012_IN11
Default: PC2
Alternate: ADC012_IN12
Default: PC3
Alternate: ADC012_IN13
29
GD32F403xx Datasheet
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
Functions description
VREF+
21
P
Default: VREF+
VDDA
22
P
Default: VDDA
PA0-WKUP
23
I/O
Default: PA0
Alternate: WKUP, USART1_CTS, ADC012_IN0,
TIMER7_ETI
PA1
24
Default: PA1
I/O
Alternate: USART1_RTS, ADC012_IN1
Default: PA2
PA2
25
Alternate: USART1_TX, ADC012_IN2, TIMER8_CH0,
I/O
SPI0_IO2
Default: PA3
PA3
26
Alternate: USART1_RX, ADC012_IN3, TIMER8_CH1,
I/O
SPI0_IO3
VSS_4
27
P
Default: VSS_4
VDD_4
28
P
Default: VDD_4
Default: PA4
PA4
29
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
I/O
DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
30
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
31
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN, TIMER12_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
32
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
33
I/O
PC5
34
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
35
Alternate: ADC01_IN8, TIMER2_CH2
I/O
TIMER7_CH1_ON
Remap: TIMER0_CH1_ON
Default: PB1
PB1
36
Alternate: ADC01_IN9, TIMER2_CH3,
I/O
TIMER7_CH2_ON
Remap: TIMER0_CH2_ON
PB2
37
I/O
5VT
Default: PB2, BOOT1
30
GD32F403xx Datasheet
Pin Name
Pins
PE7
38
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PE7
Alternate: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
39
I/O
5VT
Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
PE9
40
I/O
5VT
Alternate: EXMC_D6
Remap: TIMER0_CH0
Default: PE10
PE10
41
I/O
5VT
Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
42
I/O
5VT
Alternate: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
43
I/O
5VT
Alternate: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
44
I/O
5VT
Alternate: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
45
I/O
5VT
Alternate: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
46
I/O
5VT
Alternate: EXMC_D12
Remap: TIMER0_BRKIN
Default: PB10
PB10
47
I/O
5VT
PB11
48
I/O
5VT
VSS_1
49
P
Default: VSS_1
VDD_1
50
P
Default: VDD_1
PB12
51
I/O
Alternate: I2C1_SCL, USART2_TX
Default: PB11
Alternate: I2C1_SDA, USART2_RX
Default: PB12
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS,CAN1_RX
Default: PB13
PB13
52
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK,CAN1_TX
Default: PB14
PB14
53
I/O
5VT
Alternate: SPI1_MISO, USART2_RTS,
TIMER0_CH1_ON, TIMER11_CH0
PB15
54
I/O
5VT
Default: PB15
31
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1
Default: PD8
PD8
55
I/O
5VT
Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
56
I/O
5VT
Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
57
I/O
5VT
Alternate: EXMC_D15
Remap: USART2_CK
Default: PD11
PD11
58
I/O
5VT
Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
59
I/O
5VT
Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
60
I/O
5VT
Alternate: EXMC_A18
Remap: TIMER3_CH1
Default: PD14
PD14
61
I/O
5VT
Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
62
I/O
5VT
Alternate: EXMC_D1
Remap: TIMER3_CH3, CTC_SYNC
Default: PC6
PC6
63
I/O
5VT
Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6
Remap: TIMER2_CH0
Default: PC7
PC7
64
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7
Remap: TIMER2_CH1
Default: PC8
PC8
65
I/O
5VT
Alternate: TIMER7_CH2, SDIO_D0
Remap: TIMER2_CH2
Default: PC9
PC9
66
I/O
5VT
Alternate: TIMER7_CH3, SDIO_D1
Remap: TIMER2_CH3
Default: PA8
PA8
67
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF,CTC_SYNC
PA9
68
I/O
5VT
Default: PA9
Alternate: USART0_TX, TIMER0_CH1,USBFS_VBUS
32
GD32F403xx Datasheet
Pin Name
Pins
PA10
69
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
70
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
71
I/O
5VT
Alternate: USART0_RTS, USBFS_DP, CAN0_TX,
TIMER0_ETI
PA13
72
I/O
5VT
Default: JTMS, SWDIO
Remap: PA13
NC
73
-
-
VSS_2
74
P
Default: VSS_2
VDD_2
75
P
Default: VDD_2
PA14
76
I/O
5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
77
I/O
5VT
Alternate: SPI2_NSS, I2S2_WS
Remap: PA15, SPI0_NSS
Default: PC10
PC10
78
I/O
5VT
Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
79
I/O
5VT
Alternate: UART3_RX, SDIO_D3
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
80
I/O
5VT
Alternate: UART4_TX, SDIO_CK
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
81
I/O
5VT
Alternate: EXMC_D2
Remap: CAN0_RX, OSCIN
Default: PD1
PD1
82
I/O
5VT
Alternate: EXMC_D3
Remap: CAN0_TX, OSCOUT
PD2
83
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, SDIO_CMD, UART4_RX
Default: PD3
PD3
84
I/O
5VT
Alternate: EXMC_CLK
Remap: USART1_CTS
Default: PD4
PD4
85
I/O
5VT
Alternate: EXMC_NOE
Remap: USART1_RTS
PD5
86
I/O
5VT
Default: PD5
Alternate: EXMC_NWE
33
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Remap: USART1_TX
Default: PD6
PD6
87
I/O
5VT
Alternate: EXMC_NWAIT
Remap: USART1_RX
Default: PD7
PD7
88
I/O
5VT
Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
Default: JTDO
PB3
89
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
90
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
91
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
92
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, SPI0_IO2, CAN1_TX
Default: PB7
PB7
93
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
BOOT0
94
I
PB8
95
I/O
Default: BOOT0
Default: PB8
5VT
Alternate: TIMER3_CH2, SDIO_D4, TIMER9_CH0
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
96
I/O
5VT
Alternate: TIMER3_CH3, SDIO_D5, TIMER10_CH0
Remap: I2C0_SDA, CAN0_TX
Default: PE0
PE0
97
I/O
5VT
PE1
98
I/O
5VT
VSS_3
99
P
Default: VSS_3
VDD_3
100
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
34
GD32F403xx Datasheet
2.6.3.
GD32F403Rx LQFP64 pin definitions
Table 2-6. GD32F403Rx LQFP64 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
OSCIN
5
I
OSCOUT
6
O
NRST
7
I/O
PC0
8
I/O
PC1
9
I/O
PC2
10
I/O
PC3
11
I/O
VSSA
12
P
Default: VSSA
VDDA
13
P
Default: VDDA
PC13TAMPER-
Functions description
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OU
T
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0(3)
Default: OSCOUT
Remap: PD1(3)
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Default: PC1
Alternate: ADC012_IN11
Default: PC2
Alternate: ADC012_IN12
Default: PC3
Alternate: ADC012_IN13
Default: PA0
PA0-WKUP
14
I/O
Alternate: WKUP, USART1_CTS, ADC012_IN0,
TIMER7_ETI
PA1
15
I/O
PA2
16
I/O
Default: PA1
Alternate: USART1_RTS, ADC012_IN1
Default: PA2
Alternate: USART1_TX, ADC012_IN2, TIMER8_CH0,
SPI0_IO2
Default: PA3
Alternate: USART1_RX, ADC012_IN3, TIMER8_CH1,
PA3
17
I/O
VSS_4
18
P
Default: VSS_4
VDD_4
19
P
Default: VDD_4
PA4
20
I/O
Default: PA4
SPI0_IO3
35
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
21
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
22
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN, TIMER12_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
23
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
24
I/O
PC5
25
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
26
Alternate: ADC01_IN8, TIMER2_CH2,
I/O
TIMER7_CH1_ON
Remap: TIMER0_CH1_ON
Default: PB1
PB1
27
Alternate: ADC01_IN9, TIMER2_CH3,
I/O
TIMER7_CH2_ON
Remap: TIMER0_CH2_ON
Default: PB2, BOOT1
PB2
28
I/O
5VT
PB10
29
I/O
5VT
PB11
30
I/O
5VT
VSS_1
31
P
Default: VSS_1
VDD_1
32
P
Default: VDD_1
Default: PB10
Alternate: I2C1_SCL, USART2_TX
Default: PB11
Alternate: I2C1_SDA, USART2_RX
Default: PB12
PB12
33
I/O
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
Default: PB13
PB13
34
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK,CAN1_TX
Default: PB14
PB14
35
I/O
5VT
Alternate: SPI1_MISO, USART2_RTS,
TIMER0_CH1_ON, TIMER11_CH0
PB15
36
I/O
5VT
Default: PB15
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
36
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER11_CH1
Default: PC6
PC6
37
I/O
5VT
Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6
Remap: TIMER2_CH0
Default: PC7
PC7
38
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7
Remap: TIMER2_CH1
Default: PC8
PC8
39
I/O
5VT
Alternate: TIMER7_CH2, SDIO_D0
Remap: TIMER2_CH2
Default: PC9
PC9
40
I/O
5VT
Alternate: TIMER7_CH3, SDIO_D1
Remap: TIMER2_CH3
Default: PA8
PA8
41
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF, CTC_SYNC
Default: PA9
PA9
42
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1,
USBFS_VBUS
PA10
43
I/O
5VT
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
44
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
45
I/O
5VT
Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI,
USBFS_DP
5VT
Default: JTMS, SWDIO
PA13
46
I/O
VSS_2
47
P
Default: VSS_2
VDD_2
48
P
Default: VDD_2
PA14
49
I/O
5VT
PA15
50
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
Alternate: SPI2_NSS, I2S2_WS
Remap: PA15, SPI0_NSS
Default: PC10
PC10
51
I/O
5VT
Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
52
I/O
5VT
Alternate: UART3_RX, SDIO_D3
Remap: USART2_RX, SPI2_MISO
PC12
53
I/O
5VT
Default: PC12
37
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: UART4_TX, SDIO_CK
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
PD2
54
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, SDIO_CMD, UART4_RX
Default: JTDO
PB3
55
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
56
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
57
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
58
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, SPI0_IO2, CNA1_TX
Default: PB7
PB7
59
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1
Remap: USART0_RX, SPI0_IO3
BOOT0
60
Default: BOOT0
I
Default: PB8
PB8
61
I/O
5VT
Alternate: TIMER3_CH2, SDIO_D4, TIMER9_CH0
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
62
I/O
5VT
Alternate: TIMER3_CH3, SDIO_D5, TIMER10_CH0
Remap: I2C0_SDA, CAN0_TX
VSS_3
63
P
Default: VSS_3
VDD_3
64
P
Default: VDD_3
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
(3)PD0/PD1 cannot be used for EXTI in this package.
38
GD32F403xx Datasheet
2.6.4.
GD32F403Vx BGA100 pin definitions
Table 2-7. GD32F403Vx BGA100 pin definitions
Pin
I/O
Type(1)
Level(2)
B2
I/O
5VT
PE3
A1
I/O
5VT
PE4
B1
I/O
5VT
PE5
C2
I/O
5VT
Pin Name
Pins
PE2
Functions description
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0
Default: PE6
5VT
Alternate:TRACED3, EXMC_A22
PE6
D2
I/O
VBAT
E2
P
C1
I/O
D1
I/O
E1
I/O
VSS_5
F2
P
Default: VSS_5
VDD_5
G2
P
Default: VDD_5
OSCIN
F1
I
OSCOUT
G1
O
NRST
H2
I/O
PC0
H1
I/O
PC1
J2
I/O
PC2
J3
I/O
PC3
K2
I/O
VSSA
J1
P
Default: VSSA
VREF-
K1
P
Default: VREF-
Remap: TIMER8_CH1
PC13TAMPER-
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
RTC
PC14OSC32IN
PC15OSC32OU
T
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Default: PC1
Alternate: ADC012_IN11
Default: PC2
Alternate: ADC012_IN12
Default: PC3
Alternate: ADC012_IN13
39
GD32F403xx Datasheet
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
Functions description
VREF+
L1
P
Default: VREF+
VDDA
M1
P
Default: VDDA
PA0-WKUP
L2
I/O
Default: PA0
Alternate: WKUP, USART1_CTS, ADC012_IN0,
TIMER7_ETI
PA1
M2
Default: PA1
I/O
Alternate: USART1_RTS, ADC012_IN1
Default: PA2
PA2
K3
Alternate: USART1_TX, ADC012_IN2, TIMER8_CH0,
I/O
SPI0_IO2
Default: PA3
PA3
L3
Alternate: USART1_RX, ADC012_IN3, TIMER8_CH1,
I/O
SPI0_IO3
VSS_4
E3
P
Default: VSS_4
VDD_4
H3
P
Default: VDD_4
Default: PA4
PA4
M3
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
I/O
DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
K4
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
L4
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0,
I/O
TIMER7_BRKIN, TIMER12_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
M4
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
I/O
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
K5
I/O
PC5
L5
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
M5
Alternate: ADC01_IN8, TIMER2_CH2,
I/O
TIMER7_CH1_ON
Remap: TIMER0_CH1_ON
Default: PB1
PB1
M6
Alternate: ADC01_IN9, TIMER2_CH3,
I/O
TIMER7_CH2_ON
Remap: TIMER0_CH2_ON
PB2
L6
I/O
5VT
Default: PB2, BOOT1
40
GD32F403xx Datasheet
Pin Name
Pins
PE7
M7
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PE7
Alternate: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
L7
I/O
5VT
Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
PE9
M8
I/O
5VT
Alternate: EXMC_D6
Remap: TIMER0_CH0
Default: PE10
PE10
L8
I/O
5VT
Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
M9
I/O
5VT
Alternate: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
L9
I/O
5VT
Alternate: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
M10
I/O
5VT
Alternate: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
M11
I/O
5VT
Alternate: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
M12
I/O
5VT
Alternate: EXMC_D12
Remap: TIMER0_BRKIN
Default: PB10
PB10
L10
I/O
5VT
Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
Default: PB11
PB11
K9
I/O
5VT
Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
F12
P
Default: VSS_1
VDD_1
G12
P
Default: VDD_1
PB12
L12
I/O
Default: PB12
5VT
Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK,
TIMER0_BRKIN, I2S1_WS, CAN1_RX
Default: PB13
PB13
K12
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK, CAN1_TX
PB14
K11
I/O
5VT
Default: PB14
Alternate: SPI1_MISO, USART2_RTS,
41
GD32F403xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER0_CH1_ON, TIMER11_CH0
Default: PB15
PB15
K10
I/O
5VT
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
TIMER11_CH1
Default: PD8
PD8
L11
I/O
5VT
Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
K8
I/O
5VT
Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
J12
I/O
5VT
Alternate: EXMC_D15
Remap: USART2_CK
Default: PD11
PD11
J11
I/O
5VT
Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
J10
I/O
5VT
Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
H12
I/O
5VT
Alternate: EXMC_A18
Remap: TIMER3_CH1
Default: PD14
PD14
H11
I/O
5VT
Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
H10
I/O
5VT
Alternate: EXMC_D1
Remap: TIMER3_CH3, CTC_SYNC
Default: PC6
PC6
E12
I/O
5VT
Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6
Remap: TIMER2_CH0
Default: PC7
PC7
E11
I/O
5VT
Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7
Remap: TIMER2_CH1
Default: PC8
PC8
E10
I/O
5VT
Alternate: TIMER7_CH2, SDIO_D0
Remap: TIMER2_CH2
Default: PC9
PC9
D12
I/O
5VT
Alternate: TIMER7_CH3, SDIO_D1
Remap: TIMER2_CH3
Default: PA8
PA8
D11
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF, CTC_SYNC
42
GD32F403xx Datasheet
Pin
I/O
Type(1)
Level(2)
D10
I/O
5VT
C12
I/O
5VT
Pin Name
Pins
PA9
PA10
Functions description
Default: PA9
Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
B12
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
A12
I/O
5VT
Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI,
USBFS_DP
5VT
Default: JTMS, SWDIO
PA13
A11
I/O
NC
C11
-
-
Remap: PA13
VSS_2
F11
P
Default: VSS_2
VDD_2
G11
P
Default: VDD_2
PA14
A10
I/O
5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
A9
I/O
5VT
Alternate: SPI2_NSS, I2S2_WS
Remap: PA15, SPI0_NSS
Default: PC10
PC10
B11
I/O
5VT
Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
C10
I/O
5VT
Alternate: UART3_RX, SDIO_D3
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
B10
I/O
5VT
Alternate: UART4_TX, SDIO_CK
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
C9
I/O
5VT
Alternate: EXMC_D2
Remap: CAN0_RX, OSCIN
Default: PD1
PD1
B9
I/O
5VT
Alternate: EXMC_D3
Remap: CAN0_TX, OSCOUT
PD2
C8
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, SDIO_CMD, UART4_RX
Default: PD3
PD3
B8
I/O
5VT
Alternate: EXMC_CLK
Remap: USART1_CTS
Default: PD4
PD4
B7
I/O
5VT
Alternate: EXMC_NOE
Remap: USART1_RTS
43
GD32F403xx Datasheet
Pin Name
Pins
PD5
A6
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PD5
Alternate: EXMC_NWE
Remap: USART1_TX
Default: PD6
PD6
B6
I/O
5VT
Alternate: EXMC_NWAIT
Remap: USART1_RX
Default: PD7
PD7
A5
I/O
5VT
Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
Default: JTDO
PB3
A8
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
A7
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
C5
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
B5
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, SPI0_IO2, CAN1_TX
Default: PB7
PB7
B4
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
BOOT0
A4
I
PB8
A3
I/O
Default: BOOT0
Default: PB8
5VT
Alternate: TIMER3_CH2, SDIO_D4, TIMER9_CH0
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
B3
I/O
5VT
Alternate: TIMER3_CH3, SDIO_D5, TIMER10_CH0
Remap: I2C0_SDA, CAN0_TX
Default: PE0
PE0
C3
I/O
5VT
PE1
A2
I/O
5VT
VSS_3
D3
P
Default: VSS_3
VDD_3
C4
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
Notes:
(1)Type: I = input, O = output, P = power.
(2)I/O Level: 5VT = 5 V tolerant.
44
GD32F403xx Datasheet
3.
Functional description
3.1.
ARM® Cortex®-M4 core
The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP
instructions which allow efficient signal processing and complex algorithm execution. It brings
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital
signal control markets demand. The processor is highly configurable enabling a wide range
of implementations from those requiring floating point operations, memory protection and
powerful trace technology to cost sensitive devices requiring minimal area, while delivering
outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 168 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2.
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
Floating Point Unit (FPU)
On-chip memory
Up to 3072 Kbytes of Flash memory, including code Flash and data Flash
Up to 128 KB of SRAM
The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 3072 Kbytes of inner flash at most,
which includes code Flash that available for storing programs and data, and accessed (R/W)
at CPU clock speed with zero wait states. An extra data Flash is also included for storing data
45
GD32F403xx Datasheet
mainly. Table 2-3. GD32F403xx memory map shows the memory of the GD32F403xx
series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.
3.3.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include internal RC oscillator and external crystal oscillator, high speed and low speed two
types. Several prescalers allow the frequency configuration of the AHB and two APB domains.
The maximum frequency of the two AHB domains are 168 MHz The maximum frequency of
the two APB domains including APB1 is 84 MHz and APB2 is 168 MHz See Figure 2-6.
GD32F403xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are
always active, and ensures proper operation starting from/down to 2.6 V. The device remains
in reset mode when VDD is below a specified threshold. The embedded low voltage detector
(LVD) monitors the power supply, compares it to the voltage threshold and generates an
interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6)
and USBFS (PA9, PA11 and PA12) is also available for boot functions. It also can be used to
46
GD32F403xx Datasheet
transfer and update the Flash memory code, the data and the vector table sections. In default
condition, boot from bank0 of Flash memory is selected. It also supports to boot from bank1
of Flash memory by setting a bit in option bytes.
3.5.
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are sleep mode, deep-sleep mode and standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the deep-sleep mode including the 16 external lines, the RTC alarm, the
LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8M is
selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except
backup registers) are lost. There are four wakeup sources for the standby mode,
including the external reset from NRST pin, the RTC, the FWDGT reset, and the rising
edge on WKUP pin.
3.6.
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 2.6 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
Up to three 12-bit 2.6 MSPS multi-channel ADCs are integrated in the device. It has a total of
18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor
(VSENSE), and 1 channel for internal reference voltage (VREFINT). The input voltage range is
between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance
while off-loading the related computational burden from the CPU. An analog watchdog block
can be used to detect the channels, which are required to remain within a specific threshold
window. A configurable channel management block can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced use.
47
GD32F403xx Datasheet
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx)
and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature
sensor can be used to generate a voltage that varies linearly with temperature. It is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output voltage
in a digital value.
3.7.
Digital to analog converter (DAC)
Two 12-bit DACs with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller
The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC
channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel
operation, conversions could be done independently or simultaneously. The maximum output
value of the DAC is VREF+.
3.8.
DMA
7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9.
General-purpose inputs/outputs (GPIOs)
Up to 112 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 112 general purpose I/O pins (GPIO) in GD32F403xx, named PA0 ~ PA15
and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and
configuration registers to satisfy the requirements of specific applications. The external
interrupts on the GPIO pins of the device have related control and configuration registers in
the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative
functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can
be configured by software as output (push-pull or open-drain), as input (with or without pull48
GD32F403xx Datasheet
up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with
digital or analog alternate functions. All GPIOs are high-current capable except for analog
inputs.
3.10.
Timers and PWM generation
Two 16-bit advanced timer (TIMER0 & TIMER7), eight 16-bit general timers (TIMER2,
TIMER3, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed
on 6 channels. It has complementary PWM outputs with programmable dead-time generation.
It can also be used as a complete general timer. The 4 independent channels can be used
for input capture, output compare, PWM generation (edge-aligned or center-aligned counting
modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same
functions as the TIMERx timer. It can be synchronized with external signals or to interconnect
with other general timers together which have the same architecture and features.
The general timer, can be used for a variety of purposes including general time, input signal
pulse width measurement or output waveform generation such as a single pulse generation
or PWM output, up to 4 independent channels for input capture/output compare. TIMER2 &
TIMER3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~
TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer
also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 & TIMER6, are mainly used for DAC trigger generation.
They can also be used as a simple 16-bit time base.
The GD32F403xx have two watchdog peripherals, free watchdog timer and window watchdog
timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is
clocked from an independent 40 KHz internal RC and as it operates independently of the
main clock, it can operate in deep-sleep and standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for application
timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early wakeup interrupt capability and the counter can be frozen in
49
GD32F403xx Datasheet
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.11.
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC)
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wakeup event
The real time clock is an independent timer which provides a set of continuously running
counters which can be used with suitable software to provide a clock calendar function, and
provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit
programmable counter for long-term measurement using the compare register to generate an
alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
3.12.
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides several data transfer rates of up to 100 KHz in standard
mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus . The I2C module
also has an arbitration detect function to prevent the situation where more than one master
attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided
in I2C interface to perform packet error checking for I2C data.
3.13.
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
50
GD32F403xx Datasheet
Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking. Quad-SPI master mode is also supported in SPI0.
3.14.
Universal synchronous asynchronous receiver transmitter
(USART)
Up to three USARTs and two UARTs with operating frequency up to 10.5M Bits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface
The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data
exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232
standard communication. The USART/UART includes a programmable baud rate generator
which is capable of dividing the system clock to produce a dedicated clock for the USART
transmitter and receiver. The USART/UART also supports DMA function for high speed data
communication except UART4.
3.15.
Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32F403xx contain two I2S-bus interfaces that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and
SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported.
3.16.
Universal serial bus on-the-go full-speed (USBFS)
One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator support crystal-less operation
Internal main PLL for USB CLK compliantly
Internal USB OTG FS PHY support
51
GD32F403xx Datasheet
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction
formatting is performed by the hardware, including CRC generation and checking. It supports
both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and
Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For
full-speed or low-speed operation, no more external PHY chip is needed. It supports all the
four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol.
The required precise 48 MHz clock which can be generated from the internal main PLL (the
clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in
automatic trimming mode that allows crystal-less operation.
3.17.
Controller area network (CAN)
Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for CAN CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The
CAN protocol has been used extensively in industrial automation and automotive applications.
It can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. The CAN has three mailboxes for transmission and two FIFOs of three
message deep for reception. It also provides 28 scalable/configurable identifier filter banks
for selecting the incoming messages needed and discarding the others.
3.18.
Secure digital input and output card interface (SDIO)
Support SD2.0/SDIO2.0/MMC4.2 host interface
The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD
memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media
card system specification version 4.2 with DMA supported. In addition, this interface is also
compliant with CE-ATA digital protocol rev1.1.
3.19.
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
PC card
Provide ECC calculating hardware module for NAND Flash memory block
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
52
GD32F403xx Datasheet
execution from external memory except NAND Flash and PC card. The EXMC also can be
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
3.20.
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.21.
Package and operation temperature
LQFP144 (GD32F403Zx), LQFP100 (GD32F403Vx), LQFP64 (GD32F403Rx) and
BGA100 (GD32F403VxH)
Operation temperature range: -40°C to +85°C (industrial level)
53
GD32F403xx Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 4-1. Absolute maximum ratings(1) (4)
Symbol
VDD
Parameter
External voltage
range(2)
Min
Max
Unit
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VSS - 0.3
VDD + 3.6
V
Input voltage on other I/O
VSS - 0.3
3.6
V
|ΔVDDX|
Variations between different VDD power pins
—
50
mV
|VSSX −VSS|
Variations between different ground pins
—
50
mV
IIO
Maximum current for GPIO pins
—
±25
mA
TA
Operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
Input voltage on 5V tolerant
pin(3)
(1). Guaranteed by design, not tested in production.
(2). All main power and ground pins should be connected to an external power source within the allowable range.
(3). VIN maximum value cannot exceed 6.5 V.
(4). It is recommended that VDD and VDDA are powered by the same source. The maximum difference between
VDD and VDDA does not exceed 300 mV during power-up and operation.
4.2.
Operating conditions characteristics
Table 4-2. DC operating conditions
Min(1) Typ Max(1) Unit
Symbol
Parameter
Conditions
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
(1). Based on characterization, not tested in production.
54
GD32F403xx Datasheet
Figure 4-1. Recommended power supply decoupling capacitors(1) (2)
VBAT
100 nF
VSS
N * VDD
4.7 μF + N * 100 nF
VSS
VDDA
1 μF
VSSA
10 nF
VREF+
1 μF
VREF-
10 nF
(1). The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins
are not available and internally connected to VDDA and VSSA pins.
(2). All decoupling capacitors need to be as close as possible to the pins on the PCB board.
Table 4-3. Clock frequency(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
AHB clock frequency
—
—
168
MHz
fAPB1
APB1 clock frequency
—
—
84
MHz
fAPB2
APB2 clock frequency
—
—
168
MHz
Min
Max
Unit
0
∞
20
∞
(1). Guaranteed by design, not tested in production.
Table 4-4. Operating conditions at Power up / Power down(1)
Symbol
tVDD
Parameter
Conditions
VDD rise time rate
—
VDD fall time rate
μs/ V
(1). Guaranteed by design, not tested in production.
Table 4-5. Start-up timings of Operating conditions (1)(2)(3)
Symbol
Parameter
tstart-up
Start-up time
Conditions
Typ
Clock source from HXTAL
154
Clock source from IRC8M
154
Unit
ms
(1). Based on characterization, not tested in production.
(2). After power-up, the start-up time is the time between the rising edge of NRST high and the main function.
(3). PLL is off.
Table 4-6. Power saving mode wakeup timings characteristics(1)(2)
Symbol
Parameter
Typ
tSleep
Wakeup from Sleep mode
3.4
tDeep-sleep
Wakeup from Deep-sleep mode（LDO On）
5.8
Unit
μs
55
GD32F403xx Datasheet
Symbol
Parameter
Wakeup from Deep-sleep mode
（LDO in low power mode）
tStandby
Wakeup from Standby mode
Typ
Unit
5.8
154
ms
(1). Based on characterization, not tested in production.
(2). The wakeup time is measured from the wakeup event to the point at which the application code reads the first
instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz.
4.3.
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 4-7. Power consumption characteristics (2)(3)(4)(5)
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 168 MHz, All peripherals
—
59.9
—
mA
—
35.7
—
mA
—
43.4
—
mA
—
26.1
—
mA
—
39.3
—
mA
—
23.7
—
mA
—
33.2
—
mA
—
21.3
—
mA
—
26.9
—
mA
—
16.5
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 168 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
IDD+IDDA
Supply current
enabled
(Run mode)
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
disabled
56
GD32F403xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
—
18.7
—
mA
—
11.7
—
mA
—
14.6
—
mA
—
9.3
—
mA
—
10.4
—
mA
—
7.0
—
mA
—
7.7
—
mA
—
5.3
—
mA
—
4.9
—
mA
—
3.7
—
mA
—
1.5
—
mA
—
1.0
—
mA
—
0.9
—
mA
—
0.6
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System clock = 2 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, All peripherals
disabled
57
GD32F403xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 168 MHz, CPU clock off,
—
40.1
—
mA
—
14.0
—
mA
—
29.3
—
mA
—
10.6
—
mA
—
26.6
—
mA
—
9.7
—
mA
—
23.9
—
mA
—
8.9
—
mA
—
18.4
—
mA
—
7.2
—
mA
—
13.0
—
mA
—
5.5
—
mA
—
10.3
—
mA
—
4.7
—
mA
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 168 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
Supply current
peripherals enabled
(Sleep mode)
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals disabled
58
GD32F403xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
—
7.6
—
mA
—
3.8
—
mA
—
5.8
—
mA
—
3.3
—
mA
—
4.0
—
mA
—
2.7
—
mA
—
1.0
—
mA
—
0.5
—
mA
—
0.7
—
mA
—
0.4
—
mA
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, LDO in run mode,
IRC40K off, RTC off, All GPIOs analog
—
190.1 1100
μA
—
159.7 1100
μA
—
163.3 1100
μA
—
132.9 1100
μA
mode
VDD = VDDA = 3.3 V, LDO in low power
Supply current
(Deep-Sleep
mode)
mode, IRC40K off, RTC off, All GPIOs
analog mode
VDD = VDDA = 3.3 V, Main LDO in under
drive mode, IRC40K off, RTC off, All
GPIOs analog mode
VDD = VDDA = 3.3 V, Low Power LDO in
under drive mode, IRC40K off, RTC off, All
GPIOs analog mode
59
GD32F403xx Datasheet
Symbol
Parameter
Conditions
VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
Min Typ(1) Max
—
5.2
22
μA
—
5.0
22
μA
—
4.4
22
μA
—
1.7
—
μA
—
1.5
—
μA
—
1.3
—
μA
—
1.2
—
μA
—
1.4
—
μA
—
1.2
—
μA
—
1.1
—
μA
—
1.0
—
μA
—
1.1
—
μA
—
0.9
—
μA
—
0.8
—
μA
—
0.7
—
μA
RTC on
Supply current VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
(Standby mode)
RTC off
VDD = VDDA = 3.3 V, LXTAL off, IRC40K off,
Unit
RTC off
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
Battery supply
IBAT
current (Backup
mode)
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
60
GD32F403xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL Low
—
1.0
—
μA
—
0.9
—
μA
—
0.7
—
μA
—
0.6
—
μA
driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
(1). Based on characterization, not tested in production.
(2). Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value.
(3). When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed,
no PLL.
(4). When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed,
using PLL.
(5). When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional
power consumption should be considered.
Figure 4-2. Typical supply current consumption in Run mode
61
GD32F403xx Datasheet
Figure 4-3. Typical supply current consumption in Sleep mode
Table 4-8. Peripheral current consumption characteristics(1)
Peripherials(4)
APB1
Typical consumption at TA = 25 ℃
（TYP）
DAC(2)
1.2
PMU
2.16
BKP
2.9
CAN1
2.1
CAN0
2.13
I2C1
1.88
I2C0
1.86
UART4
1.89
UART3
1.9
USART2
1.87
USART1
1.87
SPI2
1.76
SPI1
1.76
WWDGT
1.68
TIMER13
2.16
TIMER12
2.16
TIMER11
2.2
TIMER6
1.7
TIMER5
1.7
Unit
mA
62
GD32F403xx Datasheet
Peripherials(4)
ADDAPB1
APB2
AHB
Typical consumption at TA = 25 ℃
（TYP）
TIMER3
3.36
TIMER2
3.36
CTC
1.69
TIMER10
3.48
TIMER9
3.45
TIMER8
3.47
ADC2(3)
0.81
USART0
3.34
TIMER7
4.04
SPI0
2.97
TIMER0
3.98
ADC1(3)
0.81
ADC0(3)
0.81
GPIOG
3.11
GPIOF
3.11
GPIOE
3.11
GPIOD
3.11
GPIOC
3.11
GPIOB
3.11
GPIOA
1.94
USBFS
5.3
SDIO
3.94
EXMC
3.93
CRC
2.87
DMA1
2.17
DMA0
2.42
Unit
(1). Based on characterization, not tested in production.
(2). DEN0 and DEN1 bits in the DAC_CTL register are set to 1, and the converted value set to 0x800.
(3). System clock = fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit is set to 1.
(4). If there is no other description, then HXTAL = 25 MHz, system clock = fHCLK = 168 MHz, fAPB1 = fHCLK/2, fAPB2 =
fHCLK.
4.4.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the Table 4-9. EMS characteristics(1), based on the EMS levels and classes
compliant with IEC 61000 series standard.
63
GD32F403xx Datasheet
Table 4-9. EMS characteristics(1)
Symbol
VESD
VFTB
Parameter
Conditions
Voltage applied to all device pins to
induce a functional disturbance
Level/Class
VDD = 3.3 V, TA = 25 °C
LQFP144, fHCLK = 168 MHz
3A
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VDD = 3.3 V, TA = 25 °C
induce a functional disturbance through
LQFP144, fHCLK = 168 MHz
100 pF on VDD and VSS pins
conforms to IEC 61000-4-4
4A
(1). Based on characterization, not tested in production.
4.5.
Power supply supervisor characteristics
Table 4-10. Power supply supervisor characteristics
Symbol
VLVD(1)
Parameter
Conditions
Min
Typ
Max
LVDT = 000(rising edge)
—
2.15
—
LVDT = 000(falling edge)
—
2.04
—
LVDT = 001(rising edge)
—
2.29
—
LVDT = 001(falling edge)
—
2.19
—
LVDT = 010(rising edge)
—
2.43
—
LVDT = 010(falling edge)
—
2.33
—
LVDT = 011(rising edge)
—
2.57
—
Low voltage
LVDT = 011(falling edge)
—
2.47
—
Detector level selection
LVDT = 100(rising edge)
—
2.71
—
LVDT = 100(falling edge)
—
2.60
—
LVDT = 101(rising edge)
—
2.85
—
LVDT = 101(falling edge)
—
2.74
—
LVDT = 110(rising edge)
—
2.99
—
LVDT = 110(falling edge)
—
2.89
—
LVDT = 111(rising edge)
—
3.13
—
LVDT = 111(falling edge)
—
3.03
—
—
—
100
—
mV
—
2.34
—
V
—
1.82
—
V
VLVDhyst(2)
LVD hystersis
VPOR(1)
Power on reset threshold
VPDR(1)
Power down reset
threshold
Unit
V
—
64
GD32F403xx Datasheet
Symbol
VPDRhyst
Parameter
Min
Typ
Max
Unit
PDR hysteresis
—
600
—
mV
Reset temporization
—
2
—
ms
(2)
tRSTTEMPO(2)
Conditions
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
4.6.
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up
(LU) test is based on the two measurement methods.
Table 4-11. ESD characteristics(1)
Symbol
VESD(HBM)
VESD(CDM)
Parameter
Conditions
Electrostatic discharge
TA = 25 °C;
voltage (human body model)
JESD22-A114
Electrostatic discharge
TA = 25 °C;
voltage (charge device model)
JESD22-C101
Min
Typ
Max2
Unit
—
—
4000
V
—
—
800
V
Min
Typ
Max2
Unit
—
—
±200
mA
—
—
5.4
V
(1). Based on characterization, not tested in production.
Table 4-12. Static latch-up characteristics(1)
Symbol
Parameter
Conditions
I-test
LU
TA = 25 °C; JESD78
Vsupply over voltage
(1). Based on characterization, not tested in production.
4.7.
External clock characteristics
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics
Symbol
fHXTAL
RF
(1)
(2)
Parameter
Conditions
Min
Typ
Max
Unit
Crystal or ceramic frequency
2.6 V ≤ VDD ≤ 3.6 V
4
8
32
MHz
Feedback resistor
VDD = 3.3 V
—
400
—
kΩ
—
—
20
30
pF
Recommended matching
CHXTAL
(2) (3)
capacitance on OSCIN and
OSCOUT
Ducy(HXTAL)(2)
Crystal or ceramic duty cycle
—
30
50
70
%
gm(2)
Oscillator transconductance
Startup
—
25
—
mA/V
—
1.26
—
mA
IDDHXTAL(1)
Crystal or ceramic operating
current
VDD = 3.3 V, fHCLK =
fIRC8M = 8 MHz
TA = 25 °C
65
GD32F403xx Datasheet
VDD = 3.3 V, fHCLK =
tSUHXTAL(1)
Crystal or ceramic startup time
fIRC8M = 8 MHz
—
—
1.8
ms
TA = 25 °C
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN
and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer.
For CS, it is PCB and MCU pin stray capacitance.
Table 4-14. High speed external clock characteristics (HXTAL in bypass mode)
Symbol
fHXTAL_ext(1)
Parameter
Conditions
External clock source or oscillator
2.6 V ≤ VDD ≤
frequency
3.6 V
OSCIN input pin high level
VHXTALH(2)
VHXTALL(2)
voltage
VDD = 3.3 V
OSCIN input pin low level voltage
Min
Typ
Max
Unit
1
—
50
MHz
0.7 VDD
—
VDD
V
VSS
—
0.3 VDD
V
tH/L(HXTAL)
(2)
OSCIN high or low time
—
5
—
—
ns
tR/F(HXTAL)
(2)
OSCIN rise or fall time
—
—
—
10
ns
CIN(2)
OSCIN input capacitance
—
—
5
—
pF
Ducy(HXTAL) (2)
Duty cycle
—
40
—
60
%
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic
characteristics
Symbol
fLXTAL(1)
Parameter
Crystal or ceramic
frequency
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
—
32.768
—
kHz
—
—
15
—
pF
—
30
—
70
%
—
4
—
—
6
—
Recommended matching
CLXTAL
(2) (3)
capacitance on OSC32IN
and OSC32OUT
Ducy(LXTAL)(2)
Crystal or ceramic duty
cycle
Lower driving
capability
Medium low driving
gm(2)
Oscillator transconductance
capability
Medium high driving
—
12
—
—
18
—
LXTALDRI[1:0] = 00
—
0.7
—
Crystal or ceramic operating
LXTALDRI[1:0] = 01
—
0.8
—
current
LXTALDRI[1:0] = 10
—
1.0
—
LXTALDRI[1:0] = 11
—
1.3
—
—
—
1.8
—
capability
Higher driving
capability
IDDLXTAL (1)
tSULXTAL
(1) (4)
μA/V
Crystal or ceramic startup
μA
s
66
GD32F403xx Datasheet
time
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN
and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic
manufacturer. For CS, it is PCB and MCU pin stray capacitance.
(4). tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator
stabilization flags is SET. This value varies significantly with the crystal manufacturer.
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode)
Symbol
Parameter
External clock source or
fLXTAL_ext(1)
oscillator frequency
VDD = 3.3 V
—
—
level voltage
OSC32IN input pin low
(2)
tH/L(LXTAL)
Min
OSC32IN input pin high
VLXTALH(2)
VLXTALL
Conditions
—
level voltage
(2)
tR/F(LXTAL) (2)
Unit
32.768 1000
kHz
—
VDD
VSS
—
0.3
—
VDD
V
VDD
OSC32IN high or low time
—
450
OSC32IN rise or fall time
—
—
—
50
—
—
5
—
pF
—
30
50
70
%
capacitance
Ducy(LXTAL) (2)
Max
—
OSC32IN input
CIN(2)
0.7
Typ
Duty cycle
ns
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
4.8.
Internal clock characteristics
Table 4-17. High speed internal clock (IRC8M) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = VDDA = 3.3 V
—
8
—
MHz
-2.5
—
+2.5
%
-1.8
—
+1.8
%
VDD = VDDA = 3.3 V, TA = 25 °C -1.0
—
+1.0
%
High Speed Internal
fIRC8M
Oscillator (IRC8M)
frequency
VDD = VDDA = 3.3 V,
IRC8M oscillator Frequency
accuracy, Factory-trimmed
ACCIRC8M
TA = -40 °C ~ +85 °C(1)
VDD = VDDA = 3.3 V,
TA = 0 °C ~ +85 °C(1)
IRC8M oscillator Frequency
—
—
0.5
—
%
DucyIRC8M(2) IRC8M oscillator duty cycle
VDD = VDDA = 3.3 V
45
50
55
%
IRC8M oscillator operating
VDD = VDDA = 3.3 V,
current
fHCLK = fHXTAL_PLL = 168 MHz
—
66
—
μA
IRC8M oscillator startup
VDD = VDDA = 3.3 V,
time
fHCLK = fHXTAL_PLL = 168 MHz
—
3.6
—
μs
accuracy, User trimming
step(1)
IDDAIRC8M(1)
tSUIRC8M(1)
67
GD32F403xx Datasheet
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
Table 4-18. Low speed internal clock (IRC40K) characteristics
Symbol
fIRC40K(1)
IDDAIRC40K(2)
tSUIRC40K(2)
Parameter
Conditions
Low Speed Internal oscillator
VDD = VDDA = 3.3 V,
(IRC40K) frequency
TA = -40 °C ~ +85 °C
IRC40K oscillator operating
current
IRC40K oscillator startup
time
Min
Typ
Max Unit
20
40
45
kHz
—
0.4
—
μA
—
96
—
μs
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 168 MHz,
TA = 25 °C
VDD = VDDA = 3.3 V, fHCLK =
fHXTAL_PLL = 168 MHz,
TA = 25 °C
(1). Guaranteed by design, not tested in production.
(2). Based on characterization, not tested in production.
Table 4-19. High speed internal clock (IRC48M) characteristics
Symbol
Parameter
Conditions
Min Typ
Max Unit
High Speed Internal
fIRC48M
—
48
—
MHz
-4.0
—
+5.0
%
-3.0
—
+3.0
%
-2.0
—
+2.0
%
—
—
0.12
—
%
VDD = VDDA = 3.3 V
45
50
55
%
—
356
—
μA
—
2.5
—
μs
Oscillator (IRC48M)
VDD = 3.3 V
frequency
VDD = VDDA = 3.3 V,
TA = -40°C ~ +85 °C(1)
IRC48M oscillator
Frequency accuracy,
Factory-trimmed
ACCIRC48M
VDD = VDDA = 3.3 V,
TA = 0 °C ~ +85 °C (1)
VDD = VDDA = 3.3 V,
TA = 25 °C
IRC48M oscillator
Frequency accuracy,
User trimming step(1)
DucyIRC48M(2)
IDDAIRC48M(1)
tSUIRC48M(1)
IRC48M oscillator duty
cycle
IRC48M oscillator
VDD = VDDA = 3.3 V,
operating current
fHCLK = fHXTAL_PLL = 168 MHz
IRC48M oscillator startup
VDD = VDDA = 3.3 V,
time
fHCLK = fHXTAL_PLL = 168 MHz
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
68
GD32F403xx Datasheet
4.9.
PLL characteristics
Table 4-20. PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLIN(1)
PLL input clock frequency
—
1
—
25
MHz
fPLLOUT
PLL output clock frequency
—
16
—
168
MHz
—
32
—
344
MHz
—
—
—
300
μs
VCO freq = 344 MHz
—
683
—
μA
—
35
—
fVCO
tLOCK(2)
IDDA(1)(3)
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
Cycle to cycle Jitter
ps
System clock
—
（peak to peak）
371
—
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). System clock = IRC8M = 8 MHz, PLL clock source = IRC8M/2 = 4 MHz, fPLLOUT = 168 MHz.
(4). Value given with main PLL running.
Table 4-21. PLL1 characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLIN(1)
PLL input clock frequency
—
1
—
25
MHz
fPLLOUT
PLL output clock frequency
—
16
—
168
MHz
—
32
—
200
MHz
—
—
—
300
μs
VCO freq = 200 MHz
—
520
—
μA
—
35
—
fVCO
tLOCK(2)
IDDA(1)(3)
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
Cycle to cycle Jitter
（peak to peak）
System clock
ps
—
371
—
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). System clock = IRC8M = 8 MHz, PLL1 clock source = IRC8M/2 = 4 MHz, fPLLOUT = 168 MHz.
(4). Value given with main PLL running.
69
GD32F403xx Datasheet
Table 4-22. PLL2 characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLIN(1)
PLL input clock frequency
—
1
—
25
MHz
fPLLOUT
PLL output clock frequency
—
16
—
168
MHz
—
32
—
200
MHz
—
—
—
300
μs
VCO freq = 200 MHz
—
520
—
μA
—
35
—
fVCO
tLOCK(2)
IDDA(1)(3)
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
System clock
Cycle to cycle Jitter
ps
—
（peak to peak）
371
—
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). System clock = IRC8M = 8 MHz, PLL2 clock source = IRC8M/2 = 4 MHz, fPLLOUT = 168 MHz.
(4). Value given with main PLL running.
4.10.
Memory characteristics
Table 4-23. Flash memory characteristics
Symbol
Parameter
Conditions
Min(1) Typ(1)
Max(2)
Number of guaranteed
PECYC
program /erase cycles
TA = -40 °C ~ +85 °C
100
—
—
before failure (Endurance)
Unit
kcycle
s
tRET
Data retention time
—
—
20
—
years
tPROG
Word programming time
TA = -40°C ~ +85 °C
—
37.5
86
μs
TA = -40°C ~ +85 °C
—
45
200/300(3)
ms
TA = -40°C ~ +85 °C
—
1
4.8/8.0(4)
s
TA = -40°C ~ +85 °C
—
4
19.2/32(5)
s
TA = -40°C ~ +85 °C
—
6
28.8/48(6)
s
s
s
tERASE
tMERASE(256K)
tMERASE(512K)
tMERASE(1MB)
Page erase time
Mass erase time
Mass erase time
Mass erase time
tMERASE(2MB)
Mass erase time
TA = -40°C ~ +85 °C
—
10
48/80(7)
tMERASE(3MB)
Mass erase time
TA = -40°C ~ +85 °C
—
14
67.2/112(8)
(1). Based on characterization, not tested in production.
(2). Guaranteed by design, not tested in production.
(3). Max value with 50K &
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