GigaDevice Semiconductor Inc.
GD32L233xx
Arm® Cortex®-M23 32-bit MCU
Datasheet
Revision 1.1
(Apr. 2022)
GD32L233xx Datasheet
Table of Contents
Table of Contents ..................................................................................................... 1
List of Figures .......................................................................................................... 4
List of Tables ............................................................................................................ 5
1. General description ........................................................................................... 7
2. Device overview ................................................................................................. 8
2.1.
Device information ................................................................................................ 8
2.2.
Block diagram ........................................................................................................ 9
2.3.
Pinouts and pin assignment ............................................................................... 10
2.4.
Memory map ........................................................................................................ 13
2.5.
Clock tree ............................................................................................................. 16
2.6.
Pin definitions ...................................................................................................... 17
2.6.1.
GD32L233Rx LQFP64 pin definitions ............................................................................ 17
2.6.2.
GD32L233Cx LQFP48 pin definitions ............................................................................ 23
2.6.3.
GD32L233Kx LQFP32 pin definitions ............................................................................ 27
2.6.4.
GD32L233Kx QFN32 pin definitions .............................................................................. 30
2.6.5.
GD32L233xx pin alternate functions .............................................................................. 33
3. Functional description..................................................................................... 36
3.1.
Arm® Cortex®-M23 core ....................................................................................... 36
3.2.
Embedded memory ............................................................................................. 36
3.3.
Clock, reset and supply management ................................................................ 37
3.4.
Boot modes.......................................................................................................... 37
3.5.
Power saving modes ........................................................................................... 38
3.6.
Clock trim controller (CTC) ................................................................................. 40
3.7.
General-purpose inputs/outputs (GPIOs) .......................................................... 40
3.8.
CRC calculation unit (CRC)................................................................................. 41
3.9.
True Random number generator (TRNG) ........................................................... 41
3.10.
Direct memory access controller (DMA)......................................................... 41
3.11.
DMA request multiplexer (DMAMUX) .............................................................. 42
3.12.
Analog to digital converter (ADC) ................................................................... 42
3.13.
Digital to analog converter (DAC) ................................................................... 43
3.14.
Real time clock (RTC) ...................................................................................... 43
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GD32L233xx Datasheet
4
3.15.
Timers and PWM generation ........................................................................... 43
3.16.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
44
3.17.
Universal asynchronous receiver transmitter (LPUART) .............................. 45
3.18.
Inter-integrated circuit (I2C) ............................................................................ 45
3.19.
Serial peripheral interface (SPI) ...................................................................... 46
3.20.
Inter-IC sound (I2S) .......................................................................................... 46
3.21.
Cryptographic acceleration Unit (CAU) .......................................................... 46
3.22.
Segment LCD controller (SLCD) ..................................................................... 47
3.23.
Comparators (CMP) ......................................................................................... 47
3.24.
Universal serial bus full-speed device interface (USBD) ............................... 47
3.25.
Debug mode ..................................................................................................... 48
3.26.
Package and operation temperature............................................................... 48
Electrical characteristics ................................................................................. 49
4.1
Absolute maximum ratings ................................................................................. 49
4.2
Operating conditions characteristics ................................................................. 49
4.3
Power consumption ............................................................................................ 51
4.4
EMC characteristics ............................................................................................ 58
4.5
Power supply supervisor characteristics .......................................................... 58
4.6
Electrical sensitivity ............................................................................................ 60
4.7
External clock characteristics ............................................................................ 60
4.8
Internal clock characteristics ............................................................................. 62
4.9
PLL characteristics ............................................................................................. 64
4.10
Memory characteristics ................................................................................... 64
4.11
NRST pin characteristics ................................................................................. 64
4.12
VREF buffer characteristics ............................................................................ 65
4.13
GPIO characteristics ........................................................................................ 66
4.14
ADC characteristics ......................................................................................... 68
4.15
DAC characteristics ......................................................................................... 70
4.16
Temperature sensor characteristics ............................................................... 71
4.17
Comparators characteristics ........................................................................... 71
4.18
TIMER characteristics ...................................................................................... 73
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GD32L233xx Datasheet
5
4.19
SLCD controller characteristics ...................................................................... 74
4.20
I2C characteristics ........................................................................................... 75
4.21
SPI characteristics ........................................................................................... 76
4.22
I2S characteristics ........................................................................................... 78
4.23
USART/LPUART characteristics ..................................................................... 80
4.24
USBD characteristics ....................................................................................... 80
4.25
WDGT characteristics ...................................................................................... 81
4.26
Parameter conditions....................................................................................... 82
Package information ........................................................................................ 83
5.1
LQFP64 package outline dimensions ................................................................ 83
5.2
LQFP48 package outline dimensions ................................................................ 85
5.3
LQFP32 package outline dimensions ................................................................ 87
5.4
QFN32 package outline dimensions .................................................................. 89
5.5
Thermal characteristics ...................................................................................... 91
6
Ordering information ....................................................................................... 93
7
Revision history ............................................................................................... 94
3
GD32L233xx Datasheet
List of Figures
Figure 2-1. GD32L233xx block diagram .............................................................................................. 9
Figure 2-2. GD32L233Rx LQFP64 pinouts ........................................................................................ 10
Figure 2-3. GD32L233Cx LQFP48 pinouts ........................................................................................ 11
Figure 2-4. GD32L233Kx LQFP32 pinouts ........................................................................................ 11
Figure 2-5. GD32L233Kx QFN32 pinouts .......................................................................................... 12
Figure 2-6. GD32L233xx clock tree ................................................................................................... 16
Figure 4-1. Recommended power supply decoupling capacitors(1) .............................................. 49
Figure 4-2. Typical supply current consumption in Run mode ...................................................... 56
Figure 4-3. Typical supply current consumption in Sleep mode ................................................... 57
Figure 4-4. Recommended external NRST pin circuit ..................................................................... 65
Figure 4-5. I/O port AC characteristics definition ............................................................................ 68
Figure 4-6. CMP hysteresis ................................................................................................................ 72
Figure 4-7. I2C bus timing diagram ................................................................................................... 75
Figure 4-8. SPI timing diagram - master mode ................................................................................ 76
Figure 4-9. SPI timing diagram - slave mode ................................................................................... 77
Figure 4-10. I2S timing diagram - master mode ............................................................................... 79
Figure 4-11. I2S timing diagram - slave mode .................................................................................. 79
Figure 4-12. USBD timings: definition of data signal rise and fall time ........................................ 80
Figure 5-1. LQFP64 package outline ................................................................................................. 83
Figure 5-2. LQFP64 recommended footprint .................................................................................... 84
Figure 5-3. LQFP48 package outline ................................................................................................. 85
Figure 5-4. LQFP48 recommended footprint .................................................................................... 86
Figure 5-5. LQFP32 package outline ................................................................................................. 87
Figure 5-6. LQFP32 recommended footprint .................................................................................... 88
Figure 5-7. QFN32 package outline ................................................................................................... 89
Figure 5-8. QFN32 recommended footprint ...................................................................................... 90
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GD32L233xx Datasheet
List of Tables
Table 2-1. GD32L233xx devices features and peripheral list ........................................................... 8
Table 2-2. GD32L233xx memory map ............................................................................................... 13
Table 2-3. GD32L233Rx LQFP64 pin definitions .............................................................................. 17
Table 2-4. GD32L233Cx LQFP48 pin definitions .............................................................................. 23
Table 2-5. GD32L233Kx LQFP32 pin definitions .............................................................................. 27
Table 2-6. GD32L233Kx QFN32 pin definitions ................................................................................ 30
Table 2-7. Port A alternate functions summary ............................................................................... 33
Table 2-8. Port B alternate functions summary ............................................................................... 33
Table 2-9. Port C alternate functions summary ............................................................................... 34
Table 2-10. Port D alternate functions summary ............................................................................. 34
Table 2-11. Port F alternate functions summary .............................................................................. 35
Table 4-1. Absolute maximum ratings(1)(4) ......................................................................................... 49
Table 4-2. DC operating conditions ................................................................................................... 49
Table 4-3. Clock frequency(1) .............................................................................................................. 50
Table 4-4. Operating conditions at Power up/ Power down(1) ......................................................... 50
Table 4-5. Start-up timings of Operating conditions (1) .................................................................... 50
Table 4-6. Power saving mode wakeup timings characteristics(1) (2) .............................................. 50
Table 4-7. Power consumption characteristics(2)(3) .......................................................................... 51
Table 4-8. EMS characteristics(1) ....................................................................................................... 58
Table 4-10. EMI characteristics(1) ....................................................................................................... 58
Table 4-9. Power supply supervisor characteristics(1) .................................................................... 58
Table 4-10. ESD characteristics(1) ...................................................................................................... 60
Table 4-11. Static latch-up characteristics(1) .................................................................................... 60
Table 4-12. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics ..................................................................................................................................... 60
Table 4-13. High speed external user clock characteristics (HXTAL in bypass mode) ............... 61
Table 4-14. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics
.............................................................................................................................................................. 61
Table 4-15. Low speed external user clock characteristics (LXTAL in bypass mode) ................ 62
Table 4-16. High speed internal clock (IRC16M) characteristics .................................................... 62
Table 4-17. Low speed internal clock (IRC32K) characteristics ..................................................... 63
Table 4-18. High speed internal clock (IRC48M) characteristics.................................................... 63
Table 4-19. PLL characteristics.......................................................................................................... 64
Table 4-20. Flash memory characteristics ........................................................................................ 64
Table 4-21. NRST pin characteristics ................................................................................................ 64
Table 4-22. VREF buffer characteristics ........................................................................................... 65
Table 4-23. I/O port DC characteristics(1)(3) ....................................................................................... 66
Table 4-24. I/O port AC characteristics(1) .......................................................................................... 67
Table 4-25. ADC characteristics......................................................................................................... 68
Table 4-26. ADC RAIN max for fADC = 16 MHz(1) ................................................................................... 69
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GD32L233xx Datasheet
Table 4-27. ADC dynamic accuracy at fADC = 16 MHz .................................................................... 69
(1)
Table 4-28. ADC static accuracy at fADC = 16 MHz(1) ......................................................................... 69
Table 4-29. ADC dynamic accuracy at fADC = 16 MHz(1) .................................................................... 69
Table 4-30. ADC static accuracy at fADC = 16 MHz(1) ......................................................................... 70
Table 4-31. ADC dynamic accuracy at fADC = 16 MHz(1) .................................................................... 70
Table 4-32. ADC static accuracy at fADC = 16 MHz(1) ......................................................................... 70
Table 4-33. DAC characteristics ........................................................................................................ 70
Table 4-34. Temperature sensor characteristics .............................................................................. 71
Table 4-35. CMP characteristics(1) ..................................................................................................... 71
Table 4-36. TIMER characteristics (1) ................................................................................................. 73
Table 4-37. SLCD controller characteristics(1) .................................................................................. 74
Table 4-38. I2C characteristics(1)(2)(3) .................................................................................................. 75
Table 4-39. Standard SPI characteristics(1) ....................................................................................... 76
Table 4-40. I2S characteristics(1) ........................................................................................................ 78
Table 4-41. USART/LPUART characteristics(1) ................................................................................. 80
Table 4-42. USBD startup time ........................................................................................................... 80
Table 4-43. USBD DC electrical characteristics ............................................................................... 80
Table 4-44. USBD full speed-electrical characteristics(1) ................................................................ 80
Table 4-45. FWDGT min/max timeout period at 32 kHz (IRC32K)(1) ................................................ 81
Table 4-46. WWDGT min-max timeout value at 32 MHz (fPCLK1)(1) ................................................... 82
Table 5-1. LQFP64 package dimensions .......................................................................................... 83
Table 5-2. LQFP48 package dimensions .......................................................................................... 85
Table 5-3. LQFP32 package dimensions ........................................................................................... 87
Table 5-4. QFN32 package dimensions ............................................................................................. 89
Table 6-1. Part ordering code for GD32L233xx devices .................................................................. 93
Table 7-1. Revision history................................................................................................................. 94
6
GD32L233xx Datasheet
1.
General description
The GD32L233xx device belongs to the value line of GD32 MCU family. It is a new 32bit general-purpose microcontroller based on the ARM® Cortex®-M23 core. The CortexM23 processor is an energy-efficient processor with a very low gate count. It is intended
to be used for microcontroller and deeply embedded applications that require an areaoptimized processor. The processor delivers high energy efficiency through a small but
powerful instruction set and extensively optimized design, providing high-end processing
hardware including a single-cycle multiplier and a 17-cycle divider.
The GD32L233xx device incorporates the ARM® Cortex®-M23 32-bit processor core
operating at up to 64 MHz frequency with Flash accesses 0~3 wait states to obtain
maximum efficiency. It provides up to 256 KB embedded Flash memory and up to 32 KB
SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two
APB buses. The devices offer one 12-bit ADC and two comparators, up to four general
16-bit timers, two basic timers, and a 32-bit low power timer, as well as standard and
advanced communication interfaces: up to two SPIs, three I2Cs, two USARTs, two
UARTs, an I2S, and an LPUART.
The device operates from a 1.71 to 3.63 V power supply and available in -40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32L233xx devices suitable for a wide range of
applications, especially in areas such as industrial control, motor drives, user interface,
power monitor and alarm systems, consumer and handheld equipment, gaming and GPS,
E-bike and so on.
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GD32L233xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32L233xx devices features and peripheral list
Part Number
Timers
KBT6
C8T6
CBT6 CCT6
R8T6
RBT6 RCT6
64
128
64
128
64
128
256
64
128
256
SRAM (KB)
16
24
16
24
16
24
32
16
24
32
General
3
3
3
3
3
4
4
3
4
4
timer(16-bit)
(1, 2, 8)
(1, 2, 8)
(1, 2, 8)
(1, 2, 8)
(1, 2, 8)
(1, 2, 8, 11)
(1, 2, 8, 11)
(1, 2, 8)
(1, 2, 8, 11)
(1, 2, 8, 11)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
timer(32-bit)
SysTick
Basic
2
2
2
2
2
2
2
2
2
2
timer(16-bit)
(5, 6)
(5, 6)
(5, 6)
(5, 6)
(5, 6)
(5, 6)
(5, 6)
(5, 6)
(5, 6)
(5, 6)
Watchdog
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
(3)
(3)
(3)
(3)
(3)
(3, 4)
(3, 4)
(3)
(3, 4)
(3, 4)
UART
Connectivity
K8Q6 KBQ6 K8T6
FLASH (KB)
Low power
USART
LPUART
I2C
2
2
2
2
2
2
2
2
2
2
(0, 1)
(0, 1)
(0, 1)
(0, 1)
(0, 1)
(0, 1)
(0, 1)
(0, 1)
(0, 1)
(0, 1)
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
3
3
3
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
(0-2)
(0-2)
(0-2)
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
1
1
1
1
1
1
1
1
1
1
29
29
27
27
43
43
43
59
59
59
1
1
1
1
1
1
1
1
1
1
10
10
10
10
10
10
10
16
16
16
4
4
4
4
4
4
4
4
4
4
DAC
1
1
1
1
1
1
1
1
1
1
CMP
2
2
2
2
2
2
2
2
2
2
SLCD
0
0
0
0
0
0
0
1
1
1
SPI/I2S
USBD
GPIO
Units
Channels
ADC
GD32L233xx
(External)
Channels
(Internal)
Package
QFN32
LQFP32
LQFP48
LQFP64
8
GD32L233xx Datasheet
2.2.
Block diagram
Figure 2-1. GD32L233xx block diagram
LDO
1.1/0.9V
TPIU
SW
AHB2: Fma x = 64MHz
SRAM
Controller
SRAM1(16K)
SBus
SRAM
Controller
SRAM2(16K)
Flash
Memory
Controller
256K
Flash
Memory
SBus
AHB Matrix
AHB BUS
ARM Cortex-M23
Processor
Fmax: 64MHz
GPIO Ports
A, B, C, D, F
SBus
SBus
NVIC
POR/PDR/
BOR
LVD
PLL
Fmax: 64MHz
HXTAL
4-32MHz
MBus
AHB1: Fma x = 64MHz
IRC16M
16MHz
GP DMA
7chs
AHB to
APB
Bridge 2
DMAMUX
C
R
C
C
A
U
AHB to
APB
Bridge 1
T
R
N
G
RST/CLK
Controller
IRC32K
32KHz
Powered by LDO (1.1/0.9V)
PMU
EXTI
FWDGT
12-bit
SAR ADC
IRC48M
48MHz
LXTAL
32.768KHz
Powered by V DD/VDDA
ADC
WWDGT
RTC
USART0
I2C0~2
SPI0
CMP0~1
APB1: Fmax = 32MHz
VREF
APB2: Fmax = 64MHz
SYS Config
USART1
UART3~4
LPUART
SPI1/I2S1
TIMER8
TIMER5~6
TIMER1~2
TIMER11
LPTIMER
DAC0
USBD
SLCD
CTC
9
GD32L233xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32L233Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
PB8
BOOT0-PD3
PB9
PD4
PD5
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
PD1
VBAT
2
47
PD0
PC13
3
46
PA13
PC14-OSC32IN
4
45
PA12
PC15-OSC32OUT
PF0-OSCIN
5
44
PA11
6
43
PA10
PF1-OSCOUT
7
42
PA9
NRST
8
41
PA8
PC0
9
40
PC9
PC1
10
39
PC8
PC2
11
38
PC7
PC3
12
37
PC6
VSS
13
36
PB15
VREF
14
35
PB14
VDD
15
34
PB13
PA0-WKUP0
16
33
PB12
PD6
GigaDevice GD32L233Rx
LQFP64
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PB11
PB10
BOOT1-PB2
PB1
PB0
PC5
PA7
PC4
PA6
PA5
PA4
PD9
PD8
PA3
PA2
PA1
10
GD32L233xx Datasheet
Figure 2-3. GD32L233Cx LQFP48 pinouts
PA15
PC10
PC11
PB3
PC12
PB4
PB5
PB6
PB7
BOOT0-PD3
PB8
PB9
48 47 46 45 44 43 42 41 40 39 38 37
VBAT
1
36
PA14
PC13
2
35
PA13
PC14-OSC32IN
3
34
PA12
PC15-OSC32OUT
PF0-OSCIN
4
33
PA11
5
32
PA10
PF1-OSCOUT
NRST
6
31
PA9
VSS
VREF
GigaDevice
GD32L233Cx
LQFP48
30
PA8
8
29
PC7
7
9
28
VDD
10
27
PC6
PB15
PA0-WKUP0
11
26
PB14
12
25
PB13
PA1
13 14 15 16 17 18 19 20 21 22 23 24
PB12
PB11
PB10
PB1
BOOT1-PB2
PB0
PA7
PA6
PA5
PA4
PA3
PA2
Figure 2-4. GD32L233Kx LQFP32 pinouts
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0-PD3
VSS
32 31 30 29 28 27 26 25
VDD
1
24
PA14
PF0-OSCIN
2
23
PA13
PF1-OSCOUT
3
PA12
NRST
VDDA
4
5
22
GigaDevice GD32L233Kx 21
LQFP32
20
PA0
6
19
PA9
PA1
PA2
7
18
PA8
17
VDD
8
PA11
PA10
9 10 11 12 13 14 15 16
BOOT1-PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
11
GD32L233xx Datasheet
Figure 2-5. GD32L233Kx QFN32 pinouts
5
PA0
7
PA1
8
PA15
PB3
NRST
VDD
PB4
PF0-OSCIN
PF1-OSCOUT
PB5
2
3
PB6
PC15-OSC32OUT
PB7
1
BOOT0-PD3
VBAT
PC14-OSC32IN
32 31 30 29 28 27 26 25
24
PA14
23
PA13
22
PA12
21
PA11
20
PA10
19
PA9
18
PA8
17
BOOT1-PB2
GigaDevice
GD32L233Kx
QFN32
4
6
VSS
9 10 11 12 13 14 15 16
PB1
PB0
PA7
PA6
PA5
PA4
PA3
PA2
12
GD32L233xx Datasheet
2.4.
Memory map
Table 2-2. GD32L233xx memory map
Pre-defined
ADDRESS
Peripherals
0xE000 0000 - 0xE00F FFFF
Cortex®-M23 internal peripherals
External Device
0xA000 0000 - 0xDFFF FFFF
Reserved
External RAM
0x60000000 - 0x9FFFFFFF
Reserved
0x5006 1000 - 0x5FFF FFFF
Reserved
0x5006 0C00 - 0x5006 0FFF
Reserved
0x5006 0800 - 0x5006 0BFF
TRNG
0x5006 0400 - 0x5006 07FF
Reserved
0x5006 0000 - 0x5006 03FF
CAU
0x5005 0400 - 0x5005 FFFF
Reserved
0x5005 0000 - 0x5005 03FF
Reserved
0x5004 0000 - 0x5004 FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
Reserved
0x4800 1800 - 0x4FFF FFFF
Reserved
0x4800 1400 - 0x4800 17FF
GPIOF
0x4800 1000 - 0x4800 13FF
Reserved
0x4800 0C00 - 0x4800 0FFF
GPIOD
0x4800 0800 - 0x4800 0BFF
GPIOC
0x4800 0400 - 0x4800 07FF
GPIOB
0x4800 0000 - 0x4800 03FF
GPIOA
0x4002 4400 - 0x47FF FFFF
Reserved
0x4002 4000 - 0x4002 43FF
Reserved
0x4002 3400 - 0x4002 3FFF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2400 - 0x4002 2FFF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1400 - 0x4002 1FFF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
DMAMUX
0x4002 0400 - 0x4002 07FF
Reserved
0x4002 0000 - 0x4002 03FF
DMA
0x4001 8000 - 0x4001 FFFF
Reserved
0x4001 7C00 - 0x4001 7FFF
CMP
0x4001 5C00 - 0x4001 7BFF
Reserved
0x4001 5800 - 0x4001 5BFF
DBG
0x4001 5000 - 0x4001 57FF
Reserved
0x4001 4C00 - 0x4001 4FFF
TIMER8
Regions
Bus
AHB1
AHB2
Peripherals
AHB1
APB2
13
GD32L233xx Datasheet
Pre-defined
Regions
Bus
APB1
ADDRESS
Peripherals
0x4001 3C00 - 0x4001 4BFF
Reserved
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
Reserved
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
Reserved
0x4001 2800 - 0x4001 2BFF
Reserved
0x4001 2400 - 0x4001 27FF
ADC
0x4001 0800 - 0x4001 23FF
Reserved
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
SYSCFG + VREF
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
CTC
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
I2C2
0x4000 9800 - 0x4000 BFFF
Reserved
0x4000 9400 - 0x4000 97FF
LPTIMER
0x4000 8400 - 0x4000 93FF
Reserved
0x4000 8000 - 0x4000 83FF
LPUART
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC0
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6400 - 0x4000 6FFF
Reserved
0x4000 6000 - 0x4000 63FF
USBD RAM (512 bytes)
0x4000 5C00 - 0x4000 5FFF
USBD
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
Reserved
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
Reserved
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
SLCD
0x4000 2000 - 0x4000 23FF
Reserved
14
GD32L233xx Datasheet
Pre-defined
Regions
Bus
ADDRESS
Peripherals
0x4000 1C00 - 0x4000 1FFF
Reserved
0x4000 1800 - 0x4000 1BFF
TIMER11
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0800 - 0x4000 0FFF
Reserved
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x4000 0000 - 0x4000 03FF
Reserved
0x2000 8000 - 0x3FFF FFFF
Reserved
0x2000 5000 - 0x2000 7FFF
SRAM
0x2000 4000 - 0x2000 4FFF
SRAM1(16KB)
0x2000 2000 - 0x2000 3FFF
0x2000 1000 - 0x2000 1FFF
SRAM0(16KB)
0x2000 0000 - 0x2000 0FFF
Code
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option bytes(16B)
0x1FFF D000- 0x1FFF F7FF
System memory(10KB)
0x1FFF 7200 - 0x1FFF CFFF
Reserved
0x1FFF 7000 - 0x1FFF 71FF
OTP(512B)
0x1000 0000 - 0x1FFF 6FFF
Reserved
0x0804 0000 - 0x0FFF FFFF
Reserved
0x0802 0000 - 0x0803 FFFF
0x0801 0000 - 0x0801 FFFF
Main Flash memory(256KB)
0x0800 0000 - 0x0800 FFFF
0x0001 0000 - 0x07FF FFFF
0x0000 0000 - 0x0000 FFFF
Reserved
Aliased to Flash or
system memory
15
GD32L233xx Datasheet
2.5.
Clock tree
Figure 2-6. GD32L233xx clock tree
IRC16M
divide
÷1,2,4,8,16
FMC
CK_I2S
CK_IRC1
6MDIV
CK_FMC
(to I2S)
FMC enable
(by hardware)
SCS[1:0]
(to FMC)
HCLK
CK_IRC16M
16 MHz
IRC16M
00
01
1x
AHB enable
00
÷1,2.
..16
X4,5，
,127
PLL
PREDV[3:0]
PLLMF
[6:0]
CK_PLL
CK_SYS
64 MHz max
10
AHB
Prescaler
÷1,2,4,...512
(to AHB bus,Cortex-M23,SRAM,DMA)
CK_CST
CK_AHB
÷8
64 MHz max
(to Cortex-M23 SysTick)
FCLK
01
PLLSEL[
1:0]
4-32 MHz
HXTAL
(free running clock)
TIMER1,2,5,6,11
if(APB1 prescaler = 1)
÷1
else
÷[APB1 prescaler/2]
11
Clock
Monitor
CK_HXTAL
CK_CTC
(to CTC)
APB1
Prescaler
÷1,2,4,8,16
CK_TIMERx
TIMERx
enable
to TIMER1,2,5,6,11
CK_APB1
PCLK1
32 MHz max
to APB1 peripherals
Peripheral enable
IRC48MHz
0
CK_USBD/CK_TRNG
CK_PLL
1
CK_IRC16M
DIV
CK_SYS
(to USBD/TRNG)
1x
CK_I2Cx
01
to I2C0,1,2
00
/32
USBSEL
11
I2CxSEL[1:0]
32.768 KHz
LXTAL
CK_RTC/CK_SLCD
01
(to RTC/SLCD)
10
RTCSRC[1:0]
32 KHz
IRC32K
CK_FWDGT
(to FWDGT)
TIMER8
if(APB2 prescaler = 1)
÷1
else
÷[APB2 prescaler/2]
APB2
Prescaler
÷1,2,4,8,16
CK_TIMER8
TIMER8
enable
to TIMER8
CK_APB2
PCLK2
64 MHz max
to APB2 peripherals
Peripheral enable
CKOUTSEL[2:0]
CK_IRC16MDIV
CK_OUT
÷1,2,4...128
CKOUTDIV[2:0]
CK_IRC16M
DIV
CK_LXTAL
11
10
CK_SYS
01
CK_APB1
00
CK_USART1SE
L/CK_LPUART
to USART1/LPUART
USART1SEL/LPUS
ARTSEL[1:0]
CK_IRC48M
CK_IRC32K
CK_ LXTAL
CK_SYS
CK_IRC16M
CK_HXTAL
/1,2
CK_PLL
001
010
011
100
101
110
111
CK_IRC16M
DIV
CK_LXTAL
11
CK_IRC32K
01
CK_APB2
00
10
CK_LPTIMER
11
CK_LXTAL
10
CK_ SYS
01
CK_USART0
to USART0
00
USART0SEL[1:0]
CK_IRC16M
ADC
Prescaler
÷2,4 ,6,8
10,12,14,16
0
CK_ ADC to ADC
1
16 MHz max
ADCSEL
to LPTIMER
LPTIMERSEL[1:0]
ADC
Prescaler
÷3,5,7,9
11,13,15,17
Note:
The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The
frequency of TIMERs clock is equal to CK_APBx (APB prescaler is 1), twice the
CK_APBx (APB prescaler is not 1).
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC16M: Internal 16M RC oscillator
IRC48M: Internal 48M RC oscillator
IRC32K: Internal 32K RC oscillator
16
GD32L233xx Datasheet
2.6.
Pin definitions
2.6.1.
GD32L233Rx LQFP64 pin definitions
Table 2-3. GD32L233Rx LQFP64 pin definitions
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Default: PD6
PD6
1
I/O
5VT
Alternate: USART1_RX, EVENTOUT, SPI0_MOSI, L
PTIMER_IN1
Additional: VSLCD
VBAT
2
P
Default: VBAT
Default: PC13
PC13
3
I/O
Alternate: EVENTOUT
Additional: RTC_TAMP0, RTC_OUT, RTC_TS, WK
UP1
PC14-OSC32
IN
PC15-OSC32
OUT
Default: PC14
4
I/O
Alternate: EVENTOUT
Additional: OSC32IN
Default: PC15
5
I/O
Alternate: EVENTOUT
Additional: OSC32OUT
Default: OSCIN
PF0-OSCIN
6
I/O
Alternate: EVENTOUT, SPI1_NSS, I2S1_WS
Additional: PF0
PF1-OSCOU
T
NRST
Default: OSCOUT
7
I/O
Alternate: EVENTOUT, SPI1_SCK, I2S1_CK
Additional: PF1
8
I/O
Default: NRST
Default: PC0
PC0
9
I/O
Alternate: SEG18, I2C2_SCL, LPUART_RX, LPTIM
ER_IN0, EVENTOUT
Additional: ADC_IN10
Default: PC1
PC1
10
I/O
Alternate: SEG19, I2C2_SDA, LPUART_TX, LPTIM
ER_OUT, EVENTOUT
Additional: ADC_IN11
Default: PC2
PC2
11
I/O
Alternate: SPI1_MISO, I2S1_MCK, SEG20, EVENT
OUT, LPTIMER_IN1
Additional: ADC_IN12
PC3
12
I/O
Default: PC3
Alternate: SPI1_MOSI, I2S1_SD, SEG21, LPTIMER
17
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
_ETI0, EVENTOUT
Additional: ADC_IN13
VSS
13
P
Default: VSS
VREF
14
P
Default: VREF
VDD
15
P
Default: VDD
Default: PA0
Alternate: USART1_CTS, TIMER1_CH0_ETI, CMP0
PA0
16
_OUT, EVENTOUT, UART3_TX
I/O
Additional: WKUP0, ADC_IN0, RTC_TAMP1, CMP0
_IM4
Default: PA1
PA1
17
Alternate: USART1_RTS, TIMER1_CH1, I2C0_SMB
I/O
A, SPI0_SCK, SEG0, EVENTOUT, UART3_RX
Additional: ADC_IN1, CMP0_IP
Default: PA2
Alternate: USART1_TX, TIMER8_CH0, TIMER1_CH
PA2
18
2, SPI0_IO2, CMP1_OUT, LPUART_TX, SEG1, EV
I/O
ENTOUT
Additional: ADC_IN2, CMP1_IM4, RTC_TAMP2, WK
UP2
Default: PA3
PA3
19
Alternate: USART1_RX, TIMER8_CH1, TIMER1_CH
I/O
3, SPI0_IO3, LPUART_RX, SEG2, EVENTOUT
Additional: ADC_IN3, CMP1_IP0
Default: PD8
PD8
20
I/O
5VT
Alternate: LPTIMER_ETI0, LPUART_TX, EVENTOU
T, SEG30
Default: PD9
PD9
21
I/O
5VT
Alternate: LPTIMER_IN0, LPUART_RX, EVENTOU
T, SEG31
Default: PA4
PA4
22
I/O
Alternate: SPI0_NSS, USART1_CK, SPI1_NSS, I2S
1_WS, LPTIMER_OUT, EVENTOUT
Additional: ADC_IN4, DAC_OUT
Default: PA5
PA5
23
I/O
Alternate: SPI0_SCK, TIMER1_CH0_ETI, LPTIMER_
ETI0, EVENTOUT
Additional: ADC_IN5
Default: PA6
PA6
24
I/O
Alternate: SPI0_MISO, TIMER2_CH0, LPTIMER_IN
0, CMP0_OUT, LPUART_CTS, SEG3, EVENTOUT
Additional: ADC_IN6
PA7
25
I/O
Default: PA7
18
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Alternate: SPI0_MOSI, TIMER2_CH1, LPTIMER_ETI
0, I2C2_SCL, CMP1_OUT, SEG4, EVENTOUT
Additional: ADC_IN7
Default: PC4
PC4
26
Alternate: LPUART_TX, USART0_TX, TIMER1_CH0
I/O
_ETI, SEG22, EVENTOUT
Additional: ADC_IN14
Default: PC5
PC5
27
Alternate: LPUART_RX, USART0_RX, TIMER1_CH
I/O
1, SEG23, EVENTOUT
Additional: ADC_IN15
Default: PB0
PB0
28
Alternate: TIMER2_CH2, LPTIMER_OUT, SPI0_NS
I/O
S, CMP0_OUT, SEG5, EVENTOUT
Additional: ADC_IN8, VREF_OUT
Default: PB1
PB1
29
Alternate: TIMER2_CH3, LPUART_RTS, LPTIMER_I
I/O
N0, SEG6, EVENTOUT
Additional: ADC_IN9, VREF_OUT
Default: BOOT1
BOOT1-PB2
30
I/O
5VT
Alternate: LPTIMER_OUT, EVENTOUT, RTC_OUT
Additional: PB2, WKUP3
Default: PB10
PB10
31
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, LPUART_TX, I2C1_
SCL, LPUART_RX, TIMER1_CH2, CMP0_OUT, SE
G10, EVENTOUT
Default: PB11
PB11
32
I/O
5VT
Alternate: LPUART_RX, I2C1_SDA, LPUART_TX, T
IMER1_CH3, CMP1_OUT, SEG11, EVENTOUT
Default: PB12
PB12
33
I/O
5VT
Alternate: SPI1_NSS, I2S1_WS, I2C1_SMBA, LPUA
RT_RTS, SEG12, EVENTOUT
Default: PB13
PB13
34
I/O
5VT
Alternate: CK_OUT, SPI1_SCK, I2S1_CK, LPUART
_CTS, I2C1_SCL, SEG13, EVENTOUT
Default: PB14
PB14
35
I/O
5VT
Alternate: SPI1_MISO, LPUART_RTS, I2C1_SDA, T
IMER11_CH0(3), SEG14, EVENTOUT, RTC_OUT
Default: PB15
PB15
36
I/O
5VT
Alternate: SPI1_MOSI, I2S1_SD, TIMER11_CH1(3),
SEG15, EVENTOUT
Additional: RTC_REFIN
PC6
37
I/O
5VT
Default: PC6
19
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Alternate: I2S1_MCK, TIMER2_CH0, SEG24, EVEN
TOUT
Additional: WKUP4
PC7
38
I/O
5VT
Default: PC7
Alternate: TIMER2_CH1, SEG25, EVENTOUT
Default: PC8
PC8
39
I/O
5VT
Alternate: TIMER2_CH2, I2C2_SDA, SEG26, EVEN
TOUT
Default: PC9
PC9
40
I/O
5VT
Alternate: TIMER2_CH3, I2C2_SCL, SEG27, EVEN
TOUT
Default: PA8
PA8
41
I/O
5VT
Alternate: USART0_CK, CK_OUT, LPTIMER_OUT, I
2C2_SMBA, COM0, EVENTOUT, CTC_SYNC
Additional: VCORE
Default: PA9
PA9
42
I/O
5VT
Alternate: CK_OUT, USART0_TX, I2C0_SCL, COM
1, EVENTOUT, LPTIMER_IN1
Default: PA10
PA10
43
I/O
5VT
Alternate: USART0_RX, I2C0_SDA, COM2, EVENT
OUT
Default: PA11
PA11
44
I/O
5VT
Alternate: CMP0_OUT, USART0_CTS, SPI0_MISO,
EVENTOUT
Additional: USBDM
Default: PA12
PA12
45
I/O
5VT
Alternate: CMP1_OUT, USART0_RTS, SPI0_MOSI,
EVENTOUT
Additional: USBDP
Default: SWDIO
PA13
46
I/O
5VT
Alternate: LPUART_RX, I2C0_SCL, USART0_TX, S
PI0_IO2, SPI0_NSS, EVENTOUT
Additional: PA13
Default: PD0
PD0
47
I/O
5VT
Alternate: SPI1_NSS, I2S1_WS, LPTIMER_OUT, U
SART1_CK, EVENTOUT, CTC_SYNC
Default: PD1
PD1
48
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, SPI1_MISO, USAR
T1_CTS, EVENTOUT
Default: SWCLK
PA14
49
I/O
5VT
Alternate: LPUART_TX, USART1_TX, I2C0_SDA, U
SART0_RX, SPI0_IO3, SPI1_NSS, I2S1_WS, EVEN
TOUT
20
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Additional: PA14
Default: PA15
PA15
50
I/O
5VT
Alternate: SPI1_NSS, I2S1_WS, TIMER1_CH0_ETI,
SPI0_NSS, USART1_RX, SEG17, EVENTOUT
Default: PC10
PC10
51
I/O
5VT
Alternate: UART3_TX, LPUART_TX, SPI1_SCK, I2S
1_CK, SEG28, COM4, EVENTOUT
Default: PC11
PC11
52
I/O
5VT
Alternate: UART3_RX, LPUART_RX, SPI1_MISO, S
EG29, COM5, EVENTOUT
Default: PC12
PC12
53
I/O
5VT
Alternate: UART4_TX(3), SPI1_MOSI, I2S1_SD, SE
G30, COM6, EVENTOUT
Default: PD2
PD2
54
I/O
5VT
Alternate: LPUART_RTS, TIMER2_ETI, UART4_RX
(3),
SEG31, COM7, EVENTOUT
Default: PB3
Alternate:UART4_TX(3), SPI1_SCK, I2S1_CK, TIME
PB3
55
I/O
5VT
R1_CH1, SPI0_SCK, USART0_RTS, SEG7, EVENT
OUT, LPTIMER_IN1
Additional: CMP1_IM6
Default: PB4
PB4
56
I/O
5VT
Alternate: UART4_RX(3), SPI1_MISO, TIMER2_CH0,
SPI0_MISO, USART0_CTS, SEG8, EVENTOUT
Additional: CMP1_IP1
Default: PB5
Alternate: LPTIMER_IN0, I2C0_SMBA, SPI1_MOSI,
PB5
57
I2S1_SD, TIMER2_CH1, SPI0_MOSI, USART0_CK,
I/O
CMP1_OUT, SEG9, EVENTOUT
Additional: CMP1_IP2
Default: PB6
PB6
58
I/O
5VT
Alternate: LPTIMER_ETI0, I2C1_SCL, I2C0_SCL, U
SART0_TX, SPI0_IO2, EVENTOUT
Additional: CMP1_IP3
Default: PB7
PB7
59
I/O
5VT
Alternate: I2C1_SDA, I2C0_SDA, USART0_RX, SPI
0_IO3, EVENTOUT
Additional: CMP1_IP4
Default: BOOT0
BOOT0-PD3
60
I/O
PB8
61
I/O
Alternate: USART1_CTS, SPI1_MISO, I2S1_MCK
Additional: PD3
5VT
Default: PB8
21
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Alternate: I2C1_SCL, I2C0_SCL, CMP0_OUT, SEG
16, EVENTOUT
Default: PB9
PB9
62
I/O
5VT
Alternate: I2C1_SDA, SPI1_NSS, I2S1_WS, I2C0_S
DA, CMP1_OUT, COM3, EVENTOUT
Default: PD4
PD4
63
I/O
5VT
Alternate: SPI1_MOSI, I2S1_SD, USART1_RTS, EV
ENTOUT, SEG28
Default: PD5
PD5
64
I/O
5VT
Alternate: USART1_TX, EVENTOUT, SPI0_MISO, S
EG29
Note:
(1) Type: I = input, O = output, A = analog, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32L233RB/C devices only.
22
GD32L233xx Datasheet
2.6.2.
GD32L233Cx LQFP48 pin definitions
Table 2-4. GD32L233Cx LQFP48 pin definitions
Pin Name
Pins
VBAT
1
Pin Typ I/O Lev
e(1)
P
Functions description
el(2)
Default: VBAT
Default: PC13
PC13
2
I/O
Alternate: EVENTOUT
Additional: RTC_TAMP0, RTC_OUT, RTC_TS, WK
UP1
PC14-OSC32
IN
PC15-OSC32
OUT
Default: PC14
3
I/O
Alternate: EVENTOUT
Additional: OSC32IN
Default: PC15
4
I/O
Alternate: EVENTOUT
Additional: OSC32OUT
Default: OSCIN
PF0-OSCIN
5
I/O
Alternate: EVENTOUT, SPI1_NSS, I2S1_WS
Additional: PF0
PF1-OSCOU
T
Default: OSCOUT
6
I/O
Alternate: EVENTOUT, SPI1_SCK, I2S1_CK
Additional: PF1
Default: NRST
NRST
7
I/O
VSS
8
P
Default: VSS
VREF
9
P
Default: VREF
VDD
10
P
Default: VDD
Default: PA0
Alternate: USART1_CTS, TIMER1_CH0_ETI, CMP0
PA0
11
I/O
_OUT, EVENTOUT, UART3_TX
Additional: WKUP0, ADC_IN0, RTC_TAMP1, CMP0
_IM4
Default: PA1
PA1
12
I/O
Alternate: USART1_RTS, TIMER1_CH1, I2C0_SMB
A, SPI0_SCK, EVENTOUT, UART3_RX
Additional: ADC_IN1, CMP0_IP
Default: PA2
Alternate: USART1_TX, TIMER8_CH0, TIMER1_CH
PA2
13
I/O
2, SPI0_IO2, CMP1_OUT, LPUART_TX, EVENTOU
T
Additional: ADC_IN2, CMP1_IM4, RTC_TAMP2, WK
UP2
Default: PA3
PA3
14
I/O
Alternate: USART1_RX, TIMER8_CH1, TIMER1_CH
3, SPI0_IO3, LPUART_RX, EVENTOUT
23
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Additional: ADC_IN3, CMP1_IP0
Default: PA4
PA4
15
Alternate: SPI0_NSS, USART1_CK, SPI1_NSS, I2S
I/O
1_WS, LPTIMER_OUT, EVENTOUT
Additional: ADC_IN4, DAC_OUT
Default: PA5
PA5
16
Alternate: SPI0_SCK, TIMER1_CH0_ETI, LPTIMER_
I/O
ETI0, EVENTOUT
Additional: ADC_IN5
Default: PA6
PA6
17
Alternate: SPI0_MISO, TIMER2_CH0, LPTIMER_IN
I/O
0, CMP0_OUT, LPUART_CTS, EVENTOUT
Additional: ADC_IN6
Default: PA7
PA7
18
Alternate: SPI0_MOSI, TIMER2_CH1, LPTIMER_ETI
I/O
0, CMP1_OUT, EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
19
Alternate: TIMER2_CH2, LPTIMER_OUT, SPI0_NS
I/O
S, CMP0_OUT, EVENTOUT
Additional: ADC_IN8, VREF_OUT
Default: PB1
PB1
20
Alternate: TIMER2_CH3, LPUART_RTS, LPTIMER_I
I/O
N0, EVENTOUT
Additional: ADC_IN9, VREF_OUT
Default: BOOT1
BOOT1-PB2
21
I/O
5VT
Alternate: LPTIMER_OUT, EVENTOUT, RTC_OUT
Additional: PB2, WKUP3
Default: PB10
PB10
22
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, LPUART_TX, I2C1_
SCL, LPUART_RX, TIMER1_CH2, CMP0_OUT, EV
ENTOUT
Default: PB11
PB11
23
I/O
5VT
Alternate: LPUART_RX, I2C1_SDA, LPUART_TX, T
IMER1_CH3, CMP1_OUT, EVENTOUT
Default: PB12
PB12
24
I/O
5VT
Alternate: SPI1_NSS, I2S1_WS, I2C1_SMBA, LPUA
RT_RTS, EVENTOUT
Default: PB13
PB13
25
I/O
5VT
Alternate: CK_OUT, SPI1_SCK, I2S1_CK, LPUART
_CTS, I2C1_SCL, EVENTOUT
PB14
26
I/O
5VT
Default: PB14
Alternate: SPI1_MISO, LPUART_RTS, I2C1_SDA, T
24
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
IMER11_CH0(3), EVENTOUT, RTC_OUT
Default: PB15
PB15
27
I/O
5VT
Alternate: SPI1_MOSI, I2S1_SD, TIMER11_CH1(3),
EVENTOUT
Additional: RTC_REFIN
Default: PC6
PC6
28
I/O
5VT
Alternate: I2S1_MCK, TIMER2_CH0, EVENTOUT
Additional: WKUP4
PC7
29
I/O
5VT
Default: PC7
Alternate: TIMER2_CH1, EVENTOUT
Default: PA8
PA8
30
I/O
5VT
Alternate: USART0_CK, CK_OUT, LPTIMER_OUT,
EVENTOUT, CTC_SYNC
Additional: VCORE
Default: PA9
PA9
31
I/O
5VT
Alternate: CK_OUT, USART0_TX, I2C0_SCL, EVEN
TOUT, LPTIMER_IN1
PA10
32
I/O
5VT
Default: PA10
Alternate: USART0_RX, I2C0_SDA, EVENTOUT
Default: PA11
PA11
33
I/O
5VT
Alternate: CMP0_OUT, USART0_CTS, SPI0_MISO,
EVENTOUT
Additional: USBDM
Default: PA12
PA12
34
I/O
5VT
Alternate: CMP1_OUT, USART0_RTS, SPI0_MOSI,
EVENTOUT
Additional: USBDP
Default: SWDIO
PA13
35
I/O
5VT
Alternate: LPUART_RX, I2C0_SCL, USART0_TX, S
PI0_IO2, SPI0_NSS, EVENTOUT
Additional: PA13
Default: SWCLK
Alternate: LPUART_TX, USART1_TX, I2C0_SDA, U
PA14
36
I/O
5VT
SART0_RX, SPI0_IO3, SPI1_NSS, I2S1_WS, EVEN
TOUT
Additional: PA14
Default: PA15
PA15
37
I/O
5VT
Alternate: SPI1_NSS, I2S1_WS, TIMER1_CH0_ETI,
SPI0_NSS, USART1_RX, EVENTOUT
Default: PC10
PC10
38
I/O
5VT
Alternate: UART3_TX, LPUART_TX, SPI1_SCK, I2S
1_CK, EVENTOUT
PC11
39
I/O
5VT
Default: PC11
25
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Alternate: UART3_RX, LPUART_RX, SPI1_MISO, E
VENTOUT
Default: PC12
PC12
40
I/O
5VT
Alternate: UART4_TX(3), SPI1_MOSI, I2S1_SD, EVE
NTOUT
Default: PB3
Alternate:UART4_TX(3), SPI1_SCK, I2S1_CK, TIME
PB3
41
I/O
5VT
R1_CH1, SPI0_SCK, USART0_RTS, EVENTOUT, L
PTIMER_IN1
Additional: CMP1_IM6
Default: PB4
PB4
42
I/O
5VT
Alternate: UART4_RX(3), SPI1_MISO, TIMER2_CH0,
SPI0_MISO, USART0_CTS, EVENTOUT
Additional: CMP1_IP1
Default: PB5
Alternate: LPTIMER_IN0, I2C0_SMBA, SPI1_MOSI,
PB5
43
I2S1_SD, TIMER2_CH1, SPI0_MOSI, USART0_CK,
I/O
CMP1_OUT, EVENTOUT
Additional: CMP1_IP2
Default: PB6
PB6
44
I/O
5VT
Alternate: LPTIMER_ETI0, I2C1_SCL, I2C0_SCL, U
SART0_TX, SPI0_IO2, EVENTOUT
Additional: CMP1_IP3
Default: PB7
PB7
45
I/O
5VT
Alternate: I2C1_SDA, I2C0_SDA, USART0_RX, SPI
0_IO3, EVENTOUT
Additional: CMP1_IP4
Default: BOOT0
BOOT0-PD3
46
Alternate: USART1_CTS, SPI1_MISO, I2S1_MCK
I/O
Additional: PD3
Default: PB8
PB8
47
I/O
5VT
Alternate: I2C1_SCL, I2C0_SCL, CMP0_OUT, EVE
NTOUT
Default: PB9
PB9
48
I/O
5VT
Alternate: I2C1_SDA, SPI1_NSS, I2S1_WS, I2C0_S
DA, CMP1_OUT, EVENTOUT
Note:
(1) Type: I = input, O = output, A = analog, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32L233CB/C devices only.
26
GD32L233xx Datasheet
2.6.3.
GD32L233Kx LQFP32 pin definitions
Table 2-5. GD32L233Kx LQFP32 pin definitions
Pin Typ I/O Lev
Pin Name
Pins
VDD
1
P
PF0-OSCIN
2
I/O
e(1)
Functions description
el(2)
Default: VDD
Default: OSCIN
Alternate: EVENTOUT, SPI1_NSS, I2S1_WS
Additional: PF0
PF1-OSCOU
T
Default: OSCOUT
3
I/O
Alternate: EVENTOUT, SPI1_SCK, I2S1_CK
Additional: PF1
NRST
4
I/O
Default: NRST
VDDA
5
P
Default: VDDA
Default: PA0
Alternate: USART1_CTS, TIMER1_CH0_ETI, CMP0
PA0
6
I/O
_OUT, EVENTOUT, UART3_TX
Additional: WKUP0, ADC_IN0, RTC_TAMP1, CMP0
_IM4
Default: PA1
PA1
7
I/O
Alternate: USART1_RTS, TIMER1_CH1, I2C0_SMB
A, SPI0_SCK, EVENTOUT, UART3_RX
Additional: ADC_IN1, CMP0_IP
Default: PA2
Alternate: USART1_TX, TIMER8_CH0, TIMER1_CH
PA2
8
I/O
2, SPI0_IO2, CMP1_OUT, LPUART_TX, EVENTOU
T
Additional: ADC_IN2, CMP1_IM4, RTC_TAMP2, WK
UP2
Default: PA3
PA3
9
I/O
Alternate: USART1_RX, TIMER8_CH1, TIMER1_CH
3, SPI0_IO3, LPUART_RX, EVENTOUT
Additional: ADC_IN3, CMP1_IP0
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, USART1_CK, SPI1_NSS, I2S
1_WS, LPTIMER_OUT, EVENTOUT
Additional: ADC_IN4, DAC_OUT
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, TIMER1_CH0_ETI, LPTIMER_
ETI0, EVENTOUT
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, TIMER2_CH0, LPTIMER_IN
0, CMP0_OUT, LPUART_CTS, EVENTOUT
27
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Additional: ADC_IN6
Default: PA7
PA7
13
Alternate: SPI0_MOSI, TIMER2_CH1, LPTIMER_ETI
I/O
0, CMP1_OUT, EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
14
Alternate: TIMER2_CH2, LPTIMER_OUT, SPI0_NS
I/O
S, CMP0_OUT, EVENTOUT
Additional: ADC_IN8, VREF_OUT
Default: PB1
PB1
15
Alternate: TIMER2_CH3, LPUART_RTS, LPTIMER_I
I/O
N0, EVENTOUT
Additional: ADC_IN9, VREF_OUT
Default: BOOT1
BOOT1-PB2
16
I/O
5VT
Alternate: LPTIMER_OUT, EVENTOUT, RTC_OUT
Additional: PB2, WKUP3
VDD
17
Default: VDD
P
Default: PA8
PA8
18
I/O
5VT
Alternate: USART0_CK, CK_OUT, LPTIMER_OUT,
EVENTOUT, CTC_SYNC
Additional: VCORE
Default: PA9
PA9
19
I/O
5VT
Alternate: CK_OUT, USART0_TX, I2C0_SCL, EVEN
TOUT, LPTIMER_IN1
PA10
20
I/O
5VT
Default: PA10
Alternate: USART0_RX, I2C0_SDA, EVENTOUT
Default: PA11
PA11
21
I/O
5VT
Alternate: CMP0_OUT, USART0_CTS, SPI0_MISO,
EVENTOUT
Additional: USBDM
Default: PA12
PA12
22
I/O
5VT
Alternate: CMP1_OUT, USART0_RTS, SPI0_MOSI,
EVENTOUT
Additional: USBDP
Default: SWDIO
PA13
23
I/O
5VT
Alternate: LPUART_RX, I2C0_SCL, USART0_TX, S
PI0_IO2, SPI0_NSS, EVENTOUT
Additional: PA13
Default: SWCLK
Alternate: LPUART_TX, USART1_TX, I2C0_SDA, U
PA14
24
I/O
5VT
SART0_RX, SPI0_IO3, SPI1_NSS, I2S1_WS, EVEN
TOUT
Additional: PA14
28
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Default: PA15
PA15
25
I/O
5VT
Alternate: SPI1_NSS, I2S1_WS, TIMER1_CH0_ETI,
SPI0_NSS, USART1_RX, EVENTOUT
Default: PB3
PB3
26
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, TIMER1_CH1, SPI0
_SCK, USART0_RTS, EVENTOUT, LPTIMER_IN1
Additional: CMP1_IM6
Default: PB4
PB4
27
I/O
5VT
Alternate: SPI1_MISO, TIMER2_CH0, SPI0_MISO,
USART0_CTS, EVENTOUT
Additional: CMP1_IP1
Default: PB5
Alternate: LPTIMER_IN0, I2C0_SMBA, SPI1_MOSI,
PB5
28
I2S1_SD, TIMER2_CH1, SPI0_MOSI, USART0_CK,
I/O
CMP1_OUT, EVENTOUT
Additional: CMP1_IP2
Default: PB6
PB6
29
I/O
5VT
Alternate: LPTIMER_ETI0, I2C1_SCL, I2C0_SCL, U
SART0_TX, SPI0_IO2, EVENTOUT
Additional: CMP1_IP3
Default: PB7
PB7
30
I/O
5VT
Alternate: I2C1_SDA, I2C0_SDA, USART0_RX, SPI
0_IO3, EVENTOUT
Additional: CMP1_IP4
Default: BOOT0
BOOT0-PD3
31
I/O
Alternate: USART1_CTS, SPI1_MISO, I2S1_MCK
Additional: PD3
VSS
32
P
Default: VSS
Note:
(1) Type: I = input, O = output, A = analog, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
29
GD32L233xx Datasheet
2.6.4.
GD32L233Kx QFN32 pin definitions
Table 2-6. GD32L233Kx QFN32 pin definitions
Pin Name
PC14-OSC32
IN
PC15-OSC32
OUT
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Default: PC14
1
I/O
Alternate: EVENTOUT
Additional: OSC32IN
Default: PC15
2
I/O
Alternate: EVENTOUT
Additional: OSC32OUT
Default: OSCIN
PF0-OSCIN
3
I/O
Alternate: EVENTOUT, SPI1_NSS, I2S1_WS
Additional: PF0
PF1-OSCOU
T
Default: OSCOUT
4
I/O
Alternate: EVENTOUT, SPI1_SCK, I2S1_CK
Additional: PF1
NRST
5
I/O
VDD
6
P
Default: NRST
Default: VDD
Default: PA0
Alternate: USART1_CTS, TIMER1_CH0_ETI, CMP0
PA0
7
I/O
_OUT, EVENTOUT, UART3_TX
Additional: WKUP0, ADC_IN0, RTC_TAMP1, CMP0
_IM4
Default: PA1
PA1
8
I/O
Alternate: USART1_RTS, TIMER1_CH1, I2C0_SMB
A, SPI0_SCK, EVENTOUT, UART3_RX
Additional: ADC_IN1, CMP0_IP
Default: PA2
Alternate: USART1_TX, TIMER8_CH0, TIMER1_CH
PA2
9
I/O
2, SPI0_IO2, CMP1_OUT, LPUART_TX, EVENTOU
T
Additional: ADC_IN2, CMP1_IM4, RTC_TAMP2, WK
UP2
Default: PA3
PA3
10
I/O
Alternate: USART1_RX, TIMER8_CH1, TIMER1_CH
3, SPI0_IO3, LPUART_RX, EVENTOUT
Additional: ADC_IN3, CMP1_IP0
Default: PA4
PA4
11
I/O
Alternate: SPI0_NSS, USART1_CK, SPI1_NSS, I2S
1_WS, LPTIMER_OUT, EVENTOUT
Additional: ADC_IN4, DAC_OUT
PA5
12
I/O
Default: PA5
Alternate: SPI0_SCK, TIMER1_CH0_ETI, LPTIMER_
30
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
ETI0, EVENTOUT
Additional: ADC_IN5
Default: PA6
PA6
13
Alternate: SPI0_MISO, TIMER2_CH0, LPTIMER_IN
I/O
0, CMP0_OUT, LPUART_CTS, EVENTOUT
Additional: ADC_IN6
Default: PA7
PA7
14
Alternate: SPI0_MOSI, TIMER2_CH1, LPTIMER_ETI
I/O
0, CMP1_OUT, EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
15
Alternate: TIMER2_CH2, LPTIMER_OUT, SPI0_NS
I/O
S, CMP0_OUT, EVENTOUT
Additional: ADC_IN8, VREF_OUT
Default: PB1
PB1
16
Alternate: TIMER2_CH3, LPUART_RTS, LPTIMER_I
I/O
N0, EVENTOUT
Additional: ADC_IN9, VREF_OUT
Default: BOOT1
BOOT1-PB2
17
I/O
5VT
Alternate: LPTIMER_OUT, EVENTOUT, RTC_OUT
Additional: PB2, WKUP3
Default: PA8
PA8
18
I/O
5VT
Alternate: USART0_CK, CK_OUT, LPTIMER_OUT,
EVENTOUT, CTC_SYNC
Additional: VCORE
Default: PA9
PA9
19
I/O
5VT
Alternate: CK_OUT, USART0_TX, I2C0_SCL, EVEN
TOUT, LPTIMER_IN1
PA10
20
I/O
5VT
Default: PA10
Alternate: USART0_RX, I2C0_SDA, EVENTOUT
Default: PA11
PA11
21
I/O
5VT
Alternate: CMP0_OUT, USART0_CTS, SPI0_MISO,
EVENTOUT
Additional: USBDM
Default: PA12
PA12
22
I/O
5VT
Alternate: CMP1_OUT, USART0_RTS, SPI0_MOSI,
EVENTOUT
Additional: USBDP
Default: SWDIO
PA13
23
I/O
5VT
Alternate: LPUART_RX, I2C0_SCL, USART0_TX, S
PI0_IO2, SPI0_NSS, EVENTOUT
Additional: PA13
PA14
24
I/O
5VT
Default: SWCLK
31
GD32L233xx Datasheet
Pin Name
Pins
Pin Typ I/O Lev
e(1)
Functions description
el(2)
Alternate: LPUART_TX, USART1_TX, I2C0_SDA, U
SART0_RX, SPI0_IO3, SPI1_NSS, I2S1_WS, EVEN
TOUT
Additional: PA14
Default: PA15
PA15
25
I/O
5VT
Alternate: SPI1_NSS, I2S1_WS, TIMER1_CH0_ETI,
SPI0_NSS, USART1_RX, EVENTOUT
Default: PB3
PB3
26
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, TIMER1_CH1, SPI0
_SCK, USART0_RTS, EVENTOUT, LPTIMER_IN1
Additional: CMP1_IM6
Default: PB4
PB4
27
I/O
5VT
Alternate: SPI1_MISO, TIMER2_CH0, SPI0_MISO,
USART0_CTS, EVENTOUT
Additional: CMP1_IP1
Default: PB5
Alternate: LPTIMER_IN0, I2C0_SMBA, SPI1_MOSI,
PB5
28
I2S1_SD, TIMER2_CH1, SPI0_MOSI, USART0_CK,
I/O
CMP1_OUT, EVENTOUT
Additional: CMP1_IP2
Default: PB6
PB6
29
I/O
5VT
Alternate: LPTIMER_ETI0, I2C1_SCL, I2C0_SCL, U
SART0_TX, SPI0_IO2, EVENTOUT
Additional: CMP1_IP3
Default: PB7
PB7
30
I/O
5VT
Alternate: I2C1_SDA, I2C0_SDA, USART0_RX, SPI
0_IO3, EVENTOUT
Additional: CMP1_IP4
Default: BOOT0
BOOT0-PD3
31
I/O
Alternate: USART1_CTS, SPI1_MISO, I2S1_MCK
Additional: PD3
VBAT
32
P
Default: VBAT
Note:
(1) Type: I = input, O = output, A = analog, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
32
GD32L233xx Datasheet
GD32L233xx pin alternate functions
2.6.5.
Table 2-7. Port A alternate functions summary
Pin Name
AF0
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
CK_OUT
PA9
CK_OUT
PA10
PA11
PA12
PA13
SWDIO
PA14
SWCLK
PA15
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
TIMER1_
CMP0_O USART1 UART3_ EVENTO
CH0_ETI
UT
_CTS
TX
UT
TIMER1_
I2C0_SM SPI0_SC
USART1 UART3_ EVENTO
(2)
SEG0
CH1
BA
K
_RTS
RX
UT
TIMER1_ TIMER8_
CMP1_O USART1 LPUART EVENTO
(2)
SEG1
SPI0_IO2
CH2
CH0
UT
1_TX
_TX
UT
TIMER1_ TIMER8_
USART1
LPUART
EVENTO
SEG2(2)
SPI0_IO3
CH3
CH1
_RX
_RX
UT
SPI1_NS
LPTIMER
SPI0_NS
USART1
EVENTO
S/I2S1_
_OUT
S
_CK
UT
WS
TIMER1_ LPTIMER
SPI0_SC
EVENTO
CH0_ETI _ETI0
K
UT
TIMER2_ LPTIMER
SPI0_MI CMP0_O
LPUART EVENTO
(2)
SEG3
CH0
_IN0
SO
UT
_CTS
UT
TIMER2_ LPTIMER
I2C2_SC
SPI0_MO
CMP1_O
EVENTO
SEG4(2)
CH1
_ETI0
L(2)
SI
UT
UT
LPTIMER
I2C2_SM
USART0 CTC_SY EVENTO
COM0(2)
_OUT
BA(2)
_CK
NC
UT
LPTIMER
I2C0_SC
USART0
EVENTO
(2)
COM1
_IN1
L
_TX
UT
I2C0_SD
USART0
EVENTO
(2)
COM2
A
_RX
UT
SPI0_MI CMP0_O USART0
EVENTO
SO
UT
_CTS
UT
SPI0_MO CMP1_O USART0
EVENTO
SI
UT
_RTS
UT
LPUART
I2C0_SC
SPI0_NS USART0
EVENTO
SPI0_IO2
_RX
L
S
_TX
UT
SPI1_NS
LPUART
I2C0_SD
USART0 USART1 EVENTO
SPI0_IO3 S/I2S1_
_TX
A
_RX
_TX
UT
WS
SPI1_NS
TIMER1_
SPI0_NS
USART1
EVENTO
SEG17(2)
S/I2S1_
CH0_ETI
S
_RX
UT
WS
Table 2-8. Port B alternate functions summary
Pin Name
PB0
PB1
PB2
AF0
AF1
AF2
AF3
TIMER2_ LPTIMER
SEG5(2)
CH2
_OUT
TIMER2_ LPTIMER
SEG6(2)
CH3
_IN0
RTC_OU
LPTIMER
T
_OUT
PB3
TIMER1_ LPTIMER
SEG7(2)
CH1
_IN1
PB4
TIMER2_
CH0
PB5
TIMER2_ LPTIMER
SEG9(2)
CH1
_IN0
PB6
LPTIMER
_ETI0
SEG8(2)
PB7
PB8
SEG16(2)
PB9
COM3(2)
AF4
AF5
AF6
SPI0_NS CMP0_O
S
UT
AF7
AF8
AF9
EVENTO
UT
LPUART EVENTO
_RTS
UT
EVENTO
UT
SPI1_SC
SPI0_SC
USART0 UART4_ EVENTO
K/I2S1_C
K
_RTS
TX(1)
UT
K
SPI0_MI SPI1_MI USART0 UART4_ EVENTO
SO
SO
_CTS
RX(1)
UT
SPI1_MO
I2C0_SM SPI0_MO
USART0 CMP1_O EVENTO
SI/I2S1_
BA
SI
_CK
UT
UT
SD
I2C0_SC
USART0 I2C1_SC EVENTO
SPI0_IO2
L
_TX
L
UT
I2C0_SD
USART0 I2C1_SD EVENTO
SPI0_IO3
A
_RX
A
UT
I2C0_SC
CMP0_O
I2C1_SC EVENTO
L
UT
L
UT
I2C0_SD SPI1_NS CMP1_O
I2C1_SD EVENTO
A
S/I2S1_
UT
A
UT
33
GD32L233xx Datasheet
Pin Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
WS
PB10
TIMER1_
CH2
SEG10(2)
PB11
TIMER1_
CH3
SEG11(2)
SEG12(2)
PB12
PB13
CK_OUT
SEG13(2)
PB14
RTC_OU
T
TIMER11
SEG14(2)
_CH0(1)
TIMER11
SEG15(2)
_CH1(1)
PB15
SPI1_SC
I2C1_SC
CMP0_O LPUART
K/I2S1_C
L
UT
_TX
K
I2C1_SD
CMP1_O LPUART
A
UT
_RX
SPI1_NS
I2C1_SM
S/I2S1_
BA
WS
SPI1_SC
I2C1_SC
K/I2S1_C
L
K
I2C1_SD
SPI1_MI
A
SO
SPI1_MO
SI/I2S1_
SD
LPUART EVENTO
_RX
UT
LPUART EVENTO
_TX
UT
LPUART EVENTO
_RTS
UT
LPUART EVENTO
_CTS
UT
LPUART EVENTO
_RTS
UT
EVENTO
UT
Table 2-9. Port C alternate functions summary
Pin Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
LPTIMER
I2C2_SC
SEG18(2)
_IN0
L(2)
LPTIMER
I2C2_SD
(2)
SEG19
_OUT
A(2)
LPTIMER
SPI1_MI I2S1_MC
(2)
SEG20
_IN1
SO
K
SPI1_MO
LPTIMER
SEG21(2)
SI/I2S1_
_ETI0
SD
PC0
PC1
PC2
PC3
TIMER1_
CH0_ETI
TIMER1_
CH1
TIMER2_
CH0
TIMER2_
CH1
TIMER2_
CH2
TIMER2_
CH3
PC4
PC5
PC6
PC7
PC8
PC9
SEG23(2)
I2S1_MC
K
SEG25(2)
SEG26(2)
SEG27(2)
PC10
SEG28(2)
/COM4(2)
PC11
SEG29(2)
/COM5(2)
PC12
SEG30(2)
/COM6(2)
AF9
EVENTO
UT
USART0 LPUART EVENTO
_TX
_TX
UT
USART0 LPUART EVENTO
_RX
_RX
UT
EVENTO
UT
EVENTO
UT
EVENTO
UT
EVENTO
UT
SEG22(2)
SEG24(2)
AF8
LPUART EVENTO
_RX
UT
LPUART EVENTO
_TX
UT
EVENTO
UT
I2C2_SD
A(2)
I2C2_SC
L(2)
SPI1_SC
K/I2S1_C
K
SPI1_MI
SO
SPI1_MO
SI/I2S1_
SD
UART3_T LPUART EVENTO
X
_TX
UT
UART3_ LPUART EVENTO
RX
_RX
UT
UART4_T
X(1)
EVENTO
UT
EVENTO
UT
EVENTO
UT
EVENTO
UT
PC13
PC14
PC15
Table 2-10. Port D alternate functions summary
Pin Name
PD0
PD1
AF0
AF1
AF2
LPTIMER
_OUT
AF3
AF4
AF5
AF6
AF7
AF8
AF9
SPI1_NS
USART1 CTC_SY EVENTO
S/I2S1_
_CK
NC
UT
WS
SPI1_MI SPI1_SC USART1
EVENTO
SO
K/I2S1_C _CTS
UT
34
GD32L233xx Datasheet
Pin Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
K
SEG31(2)
/COM7(2)
TIMER2_
ETI
PD2
UART4_ LPUART EVENTO
RX(1)
_RTS
UT
SPI1_MI I2S1_MC USART1
SO
K
_CTS
SPI1_MO
USART1
EVENTO
SI/I2S1_
_RTS
UT
SD
SPI0_MI
USART1
EVENTO
SO
_TX
UT
SPI0_MO
USART1
EVENTO
SI
_RX
UT
LPUART EVENTO
_TX
UT
LPUART EVENTO
_RX
UT
PD3
PD4
SEG28(2)
PD5
SEG29(2)
LPTIMER
_IN1
LPTIMER
SEG30(2)
_ETI0
LPTIMER
SEG31(2)
_IN0
PD6
PD8
PD9
Table 2-11. Port F alternate functions summary
Pin Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
SPI1_NS
S/I2S1_
WS
SPI1_SC
K/I2S1_C
K
PF0
PF1
AF9
EVENTO
UT
EVENTO
UT
Note:
(1) Functions are available on GD32L233RC/RB/CC/CB devices only.
(2) Functions are available on GD32L233Rx devices only.
35
GD32L233xx Datasheet
3.
Functional description
3.1.
Arm® Cortex®-M23 core
The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It
is intended to be used for microcontroller and deeply embedded applications that require
an area-optimized processor. The processor is highly configurable enabling a wide range
of implementations from those requiring memory protection and powerful trace
technology to cost sensitive devices requiring minimal area, while delivering outstanding
computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M23 processor core
Up to 64 MHz operation frequency.
Single-cycle multiplication and hardware divider.
Ultra-low power, energy-efficient operation.
Excellent code density.
Integrated Nested Vectored Interrupt Controller (NVIC).
24-bit SysTick timer.
The Cortex®-M23 processor is based on the ARMv8-M architecture and supports both
Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also
provided by Cortex®-M23:
Internal Bus Matrix connected with AHB master, Serial Wire Debug Port and Singlecycle IO port.
3.2.
Nested Vectored Interrupt Controller (NVIC).
Breakpoint Unit(BPU).
Data Watchpoint and Trace (DWT).
Serial Wire Debug Port.
Embedded memory
Up to 256 Kbytes of Flash memory.
Up to 32 Kbytes of SRAM with hardware parity checking.
256 Kbytes of inner Flash memory, and 32 Kbytes of inner SRAM at most is available for
storing programs and data, and Flash is accessed (read) at CPU clock speed with 0~3
wait states. Table 2-2. GD32L233xx memory map shows the memory map of the
GD32L233xx series of devices, including code, SRAM, peripheral, and other pre-defined
regions.
36
GD32L233xx Datasheet
3.3.
Clock, reset and supply management
Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator.
Internal 48 MHz factory-trimmed RC.
Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator.
Integrated system clock PLL.
1.71 to 3.63 V application supply and I/Os.
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low
voltage detector (LVD).
The Clock Control Unit (CCTL) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low
speed two types. Several prescalers allow the frequency configuration of the AHB and
two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 64
MHz/64 MHz/32 MHz. See Figure 2-6. GD32L233xx clock tree for details on the clock
tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the
processor core and peripheral IP components. Power-on reset (POR) and power-down
reset (PDR) are always active, and ensures proper operation starting from 1.60 V and
down to 1.56V. The device remains in reset mode when VDD is below a specified threshold.
The embedded low voltage detector (LVD) monitors the power supply, compares it to the
voltage threshold and generates an interrupt as a warning message for leading the MCU
into security.
Power supply schemes:
VDD range: 1.71 to 3.63 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSS is 0 V.
VDDA range: 1.71 to 3.63 V, external analog power supplies for ADC, reset blocks,
RCs and PLL.
VBAK range: 1.71 to 3.63 V, power supply for RTC unit, LXTAL oscillator, BPOR, and
two pads, including PC13 to PC15 when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default).
Boot from system memory.
Boot from on-chip SRAM.
In default condition, boot from main Flash memory is selected. The boot loader is located
in the internal boot ROM memory (system memory). It is used to reprogram the Flash
37
GD32L233xx Datasheet
memory by using USART0 (PA9 and PA10) or USART1 (PA2 and PA3) or USBD (PA11
and PA12).
3.5.
Power saving modes
The MCU supports ten kinds of power saving modes to achieve even lower power
consumption. They are Run, Run1, Run2, Sleep, Sleep1, Sleep2, Deep-sleep, Deepsleep 1, Deep-sleep 2 and Standby mode. These operating modes reduce the power
consumption and allow the application to achieve the best balance between the CPU
operating time, speed and power consumption.
Run mode
After system reset/ power reset or wakeup from standby mode, the MCU enters Run
mode. And the NPLDO (normal power LDO) works in 1.1V mode.
Run1 mode
When in Run mode, the NPLDO should be selected as 0.9V by configuring the
LDOVS bits in PMU_CTL0. In this mode, the system clock frequency should not
exceed 16MHz.
Run2 mode
When in Run mode or Run1 mode, the NPLDO can be selected as 0.9V by
configuring the LDOVS bits in PMU_CTL0. The LDNP in PMU_CTL0 register should
be configured to select the low-dirver mode. In this mode, the system clock
frequency should not exceed 2MHz.
Sleep mode
The Sleep mode is corresponding to the SLEEPING mode of the Cortex®-M23. In
Sleep mode, only clock of Cortex®-M23 is off. To enter the Sleep mode, it is only
necessary to clear the SLEEPDEEP bit in the Cortex®-M23 System Control Register,
and execute a WFI or WFE instruction. If the Sleep mode is entered by executing a
WFI instruction, any interrupt can wake up the system. If it is entered by executing
a WFE instruction, any wakeup event can wake up the system (If SEVONPEND is
1, any interrupt can wake up the system, refer to Cortex®-M33 Technical Reference
Manual). The mode offers the lowest wakeup time as no time is wasted in interrupt
entry or exit.
Sleep1 mode
The Sleep1 mode is corresponding to the SLEEPING mode of the Cortex ®-M23
When in Run1 mode. The NPLDO should be selected as 0.9V by configuring the
LDOVS bits in PMU_CTL0.
Sleep2 mode
The Sleep2 mode is corresponding to the SLEEPING mode of the Cortex ®-M23
When in Run2 mode. The NPLDO should be selected as 0.9V by configuring the
LDOVS bits in PMU_CTL0. The LDNP in PMU_CTL0 should be configured to select
the low-dirver mode.
Deep-sleep mode
The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex ®-M23. In
38
GD32L233xx Datasheet
Deep-sleep mode, all clocks in the 1.1V domain are off, and all of IRC16M, IRC48M,
HXTAL and PLLs are disabled. The contents of SRAM and registers are preserved.
The NPLDO can operate normally or in low driver mode depending on the LDNPDSP
bit in the PMU_CTL0 register. Before entering the Deep-sleep mode, it is necessary
to set the SLEEPDEEP bit in the Cortex®-M23 System Control Register, and set
LPMOD bits to “00” in the PMU_CTL0 register. Then, the device enters the Deepsleep mode after a WFI or WFE instruction is executed. If the Deep-sleep mode is
entered by executing a WFI instruction, any interrupt from EXTI lines can wake up
the system. If it is entered by executing a WFE instruction, any wakeup event from
EXTI lines can wake up the system (If SEVONPEND is 1, any interrupt from EXTI
lines can wake up the system, refer to Cortex®-M23 Technical Reference Manual).
When exiting the Deep-sleep mode, the IRC16M is selected as the system clock.
Notice that an additional wakeup delay will be incurred if the LDO operates in low
driver mode.
Deep-sleep 1 mode
The Deep-sleep 1 mode is based on the SLEEPDEEP mode of the Cortex®-M23. In
Deep-sleep 1 mode, all clocks in the 1.1V domain are off, and all of IRC16M,
IRC48M, HXTAL and PLLs are disabled. The LPLDO (low power LDO) can operate
normally instead of NPLDO. Before entering the Deep-sleep 1 mode, it is necessary
to set the SLEEPDEEP bit in the Cortex®-M23 System Control Register, set LPMOD
bits to “01” in the PMU_CTL0 register. Then, the device enters the Deep-sleep 1
mode after a WFI or WFE instruction is executed. If the Deep-sleep 1 mode is
entered by executing a WFI instruction, any interrupt from EXTI lines can wake up
the system. If it is entered by executing a WFE instruction, any wakeup event from
EXTI lines can wake up the system (If SEVONPEND is 1, any interrupt from EXTI
lines can wake up the system, refer to Cortex®-M23 Technical Reference Manual).
When exiting the Deep-sleep 1 mode, the IRC16M is selected as the system clock.
Waking up from Deep-sleep 1 mode needs an additional delay to wakeup NPLDO.
Deep-sleep 2 mode
The Deep-sleep 2 mode is based on the SLEEPDEEP mode of the Cortex®-M23. In
Deep-sleep 2 mode, all clocks in the 1.1V domain are off, and all of IRC16M,
IRC48M,
HXTAL
and
PLLs
COREOFF0/SRAM1/COREOFF1
are
domain
disabled.
is
cut
off.
The
power
of
The
contents
of
COREOFF0/SRAM1/COREOFF1 domain are lost. The LPLDO can operate
normally instead of NPLDO. Before entering the Deep-sleep 2 mode, it is necessary
to set the SLEEPDEEP bit in the Cortex®-M23 System Control Register, set LPMOD
bits to “10” in the PMU_CTL0 register. Then, the device enters the Deep-sleep 2
mode after a WFI or WFE instruction is executed. If the Deep-sleep 2 mode is
entered by executing a WFI instruction, any interrupt from EXTI lines can wake up
the system. If it is entered by executing a WFE instruction, any wakeup event from
EXTI lines can wake up the system (If SEVONPEND is 1, any interrupt from EXTI
lines can wake up the system, refer to Cortex®-M23 Technical Reference Manual).
When exiting the Deep-sleep 2 mode, the IRC16M is selected as the system clock.
Waking up from Deep-sleep 2 mode needs an additional delay to wakeup NPLDO.
39
GD32L233xx Datasheet
Standby mode
The Standby mode is based on the SLEEPDEEP mode of the Cortex ®-M23, too. In
Standby mode, the whole 1.1V domain is power off, the NPLDO/LPLDO is shut down,
and all of IRC16M, IRC48M, HXTAL and PLLs are disabled. Before entering the
Standby mode, it is necessary to set the SLEEPDEEP bit in the Cortex ®-M23 System
Control Register, and set the LPMOD bits to “11” in the PMU_CTL0 register, and
clear WUF bit in the PMU_CS register. Then, the device enters the Standby mode
after a WFI or WFE instruction is executed, and the STBF status flag in the PMU_CS
register indicates that the MCU has been in Standby mode. There are four wakeup
sources for the Standby mode, including the external reset from NRST pin, the RTC
alarm/time stamp/tamper/auto wakeup events, the FWDGT reset, and the rising
edge on WKUP pins. The Standby mode achieves the lowest power consumption,
but spends longest time to wake up. Besides, the contents of SRAM and registers
in 1.1V power domain are lost in Standby mode. When exiting from the Standby
mode, a power-on reset occurs and the Cortex®-M23 will execute instruction code
from the 0x00000000 address.
3.6.
Clock trim controller (CTC)
Three external reference signal source: GPIO, LXTAL clock, USBD_SOF.
Provide software reference sync pulse.
Automatically trimmed by hardware without any software action.
16 bits trim counter with reference signal source capture and reload.
8 bits clock trim base value to frequency evaluation and automatically trim.
The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M)
automatically by hardware. If using IRC48M clock to USBD, the IRC48M must be 48 MHz
with 500ppm. The internal oscillator without such a high degree of accuracy needs to be
trimmed. The CTC unit trim the frequency of the IRC48M based on an external accurate
reference signal source. It can automatically adjust the trim value to provide a precise
IRC48M clock.
3.7.
General-purpose inputs/outputs (GPIOs)
Up to 59 fast GPIOs, all mappable on 16 external interrupt lines.
Analog input/output configurable.
Alternate function input/output configurable.
There are up to 59 general purpose I/O pins (GPIO) in GD32L233xx, named PA0 ~ PA15,
PB0 ~ PB15, PC0 ~ PC15, PD0~PD6, PD8~PD9, PF0~ PF1 to implement logic
input/output functions. Each GPIO port has related control and configuration registers to
satisfy the requirements of specific applications. The external interrupts on the GPIO pins
of the device have related control and configuration registers in the Interrupt/Event
40
GD32L233xx Datasheet
Controller Unit (EXTI).The GPIO ports are pin-shared with other alternative functions
(AFs) to obtain maximum flexibility on the package pins.
Each of the GPIO pins can be configured by software as output (push-pull or open-drain),
input, peripheral alternate function or analog mode. Most of the GPIO pins are shared
with digital or analog alternate functions.
3.8.
CRC calculation unit (CRC)
Supports 7/8/16/32 bit data input.
For 7(8)/16/32 bit input data length, the calculation cycles are 1/2/4 AHB clock cycles.
Free 8-bit register is unrelated to calculation and can be used for any other goals by
any other peripheral devices.
User configurable polynomial value and size.
A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital
networks and storage devices to detect accidental changes to raw data. This CRC
calculation unit can be used to calculate 7/8/16/32 bit CRC code within user configurable
polynomial.
3.9.
True Random number generator (TRNG)
About 40 periods of TRNG_CLK are needed between two consecutive random
numbers.
Disable TRNG module will reduce the chip power consumption.
32-bit random value seed is generated from analog noise, so the random number is
a true random number.
The true random number generator (TRNG) module can generate a 32-bit random value
by using continuous analog noise.
3.10.
Direct memory access controller (DMA)
7 channels for DMA controller.
DMA request from DMAMAX: peripherals (Timers, ADC, DAC, SPIs, I2S, I2Cs,
USARTs, CAU and LPUART) and request generator.
The flexible general-purpose DMA controllers provide a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby
increasing system performance by off-loading the MCU from copying large amounts of
data and avoiding frequent interrupts to serve peripherals needing more data or having
available data. Three types of access method are supported: peripheral to memory,
memory to peripheral, memory to memory.
41
GD32L233xx Datasheet
Each channel is connected to flexible hardware DMA requests. The priorities of DMA
channel requests are determined by software configuration and hardware channel
number. Transfer size of source and destination are independent and configurable.
3.11.
DMA request multiplexer (DMAMUX)
7 channels for DMAMUX request multiplexer.
4 channels for DMAMUX request generator.
Support 21 trigger inputs and 21 synchronization inputs.
DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request
multiplexer is used for routing a DMA request line between the peripherals / generated
DMA request (from the DMAMUX request generator) and the DMA controller. Each
DMAMUX request multiplexer channel selects a unique DMA request line,
unconditionally or synchronously with events from its DMAMUX synchronization inputs.
The DMA request is pending until it is served by the DMA controller which generates a
DMA acknowledge signal (the DMA request signal is de-asserted).
3.12.
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 1.07 MSPS.
Hardware oversampling ratio adjustable from 2x to 256x improves resolution to 16bit.
Input voltage range: VSS/VSSA to VDD/VDDA.
Temperature sensor.
A 12-bit multi-channel ADC is integrated in the device. It has a total of 20 multiplexed
channels: up to 16 external channels, 1 channel for internal temperature sensor (VSENSE),
1 channel for internal reference voltage (VREFINT), 1 channel for external battery power
supply (VBAT), and 1 channel for LCD voltage (VSLCD). The input voltage range is between
VSS/VSSA and VDD/VDDA. An on-chip hardware oversampling scheme improves
performance while off-loading the related computational burden from the CPU. The
analog watchdog allows the application to detect whether the input voltage goes outside
the user-defined higher or lower thresholds. A configurable channel management block
can be used to perform conversions in single, continuous, scan or discontinuous mode
to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers
(TIMERx, x=1, 2) and the general level 1 timers (TIMERx, x=8, 11) with internal
connection. The temperature sensor can be used to generate a voltage that varies
linearly with temperature. It is internally connected to the ADC_IN16 input channel which
is used to convert the sensor output voltage in a digital value.
To ensure a high accuracy on ADC, the independent power supply V DDA is implemented
42
GD32L233xx Datasheet
to achieve better performance of analog circuits. VDDA can be externally connected to VDD
through the external filtering circuit that avoids noise on VDDA.
3.13.
Digital to analog converter (DAC)
One12-bit DAC with one output channel.
8-bit or 12-bit mode in conjunction with the DMA controller.
Support references from internal 2.5 V precision reference or external VREF pin.
The 12-bit buffered DAC is used to generate variable analog outputs. The DAC channels
can be triggered by the timer or EXTI with DMA support. The maximum output value of
the DAC is VREF.
3.14.
Real time clock (RTC)
Independent binary-coded decimal (BCD) format timer/counter with five 32-bit
backup registers.
Calendar with sub-second, second, minute, hour, week day, day, month and year
automatically correction.
Alarm function with wake up from deep-sleep and standby mode capability.
On-the-fly correction for synchronization with master clock. Digital calibration with
0.95 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running
counters in backup registers to provide a real calendar function, and provides an alarm
interrupt or an expected interrupt. It is not reset by a system or power reset, or when the
device wakes up from standby mode. In the RTC unit, there are two prescalers used for
implementing the calendar and other functions. One prescaler is a 7-bit asynchronous
prescaler and the other is a 15-bit synchronous prescaler.
3.15.
Timers and PWM generation
Up to four 16-bit general timers (TIMER1, TIMER2, TIMER8, TIMER11), two 16-bit
basic timer (TIMER5, TIMER6), and one 32-bit low power timer (LPTIMER).
Up to 4 independent channels of PWM, output compare or input capture for each
general timer and external trigger input.
Encoder interface controller with two inputs using quadrature decoder.
Two 24-bit SysTick timers down counter.
2 watchdog timers (free watchdog timer and window watchdog timer).
The LPTIMER is a 32-bit timer and it is able to keep running in all power modes except
for Standby mode with its diversity of clock sources. The LPTIMER provides one PWM
out and also supports an encoder interface with two inputs using quadrature decoder.
43
GD32L233xx Datasheet
The general timer can be used for a variety of purposes including general time, input
signal pulse width measurement or output waveform generation such as a single pulse
generation or PWM output, up to 4 independent channels for input capture/output
compare. TIMER1 and TIMER2 are based on a 16-bit auto-reload up/down/centeraligned counter and a 16-bit prescaler. TIMER8 and TIMER11 is based on a 16-bit autoreload up counter and a 16-bit prescaler. The general timer also supports an encoder
interface with two inputs using quadrature decoder.
The basic timer TIMER5 and TIMER6, are mainly used as a simple 16-bit time base.
The GD32L233xx have two watchdog peripherals, free watchdog timer and window
watchdog timer. They offer a combination of high safety level, flexibility of use and timing
accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-stage
prescaler. It is clocked from an independent 32 KHz internal RC and as it operates
independently of the main clock, it can operate in deep-sleep and standby modes. It can
be used either as a watchdog to reset the device when a problem occurs, or as a freerunning timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked
from the main clock. It has an early wakeup interrupt capability and the counter can be
frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.16.
A 24-bit down counter.
Auto reload capability.
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source.
Universal synchronous/asynchronous receiver transmitter
(USART/UART)
Up to two USARTs and two UARTs with operating frequency up to 8 MBits/s.
Supports both asynchronous and clocked synchronous serial communication modes.
IrDA SIR encoder and decoder support.
LIN break generation and detection.
ISO 7816-3 compliant smart card interface.
Dual clock domain.
Wake up from Deep-sleep mode.
The USART (USART0, USART1) and UART (UART3, UART4) are used to translate data
between parallel and serial interfaces, provides a flexible full duplex data exchange using
44
GD32L233xx Datasheet
synchronous or asynchronous transfer. It is also commonly used for RS-232 standard
communication. The USART/UART includes a programmable baud rate generator which
is capable of dividing the system clock to produce a dedicated clock for the USART/UART
transmitter and receiver. The USART/UART also supports DMA function for high speed
data communication.
3.17.
Universal asynchronous receiver transmitter (LPUART)
Maximum speed up to 21 MBits/s.
Supports asynchronous serial communication modes.
Supports hardware modem operations (CTS/RTS) and RS485 drive.
Dual clock domain.
Wake up from Deep-sleep mode.
The Low-power universal Asynchronous Receiver/Transmitter (LPUART) provides a
flexible serial data exchange interface with a limited power consumption. LPUART can
perform asynchronous serial communication even with low power consumption. Data
frames can be transferred in full duplex or half duplex mode, asynchronously through this
interface. A programmable baud rate generator divides the clock to produces a dedicated
wide range baudrate clock for the LPUART transmitter and receiver.
3.18.
Inter-integrated circuit (I2C)
Support both master and slave mode with a frequency up to 1 MHz (Fast mode plus).
Provide arbitration function, optional PEC (packet error checking) generation and
checking.
Supports 7-bit and 10-bit addressing mode and general call addressing mode.
Multiple 7-bit slave addresses (2 address, 1 with configurable mask).
SMBus 3.0 and PMBus 1.3 compatible.
Wakeup from Deep-sleep / Deep-sleep1 / Deep-sleep2 mode on I2C address match
(only in I2C2).
Wakeup from Deep-sleep1 / Deep-sleep2 mode on I2C address match (in I2C0 and
I2C1).
The I2C interface is an internal circuit allowing communication with an external I2C
interface which is an industry standard two line serial interface used for connection to
external hardware. These two serial lines are known as a serial data line (SDA) and a
serial clock line (SCL). The I2C module provides different data transfer rates: up to 100
KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode
plus. The I2C module also has an arbitration detect function to prevent the situation where
more than one master attempts to transmit data to the I2C bus at the same time. A CRC8 calculator is also provided in I2C interface to perform packet error checking for I2C data.
45
GD32L233xx Datasheet
3.19.
Serial peripheral interface (SPI)
Up to two SPI interfaces with a frequency of up to 16 MHz.
Support both master and slave mode.
Hardware CRC calculation and transmit automatic CRC error checking.
Separate transmit and receive 32-bit FIFO with DMA capability (only in SPI0).
Data frame size can be 4 to 16 bits (only in SPI0).
Quad-SPI configuration available in master mode (only in SPI0).
The SPI interface uses 4 pins, among which are the serial data input and output lines
(MISO & MOSI), the clock line (SCK) and the slave select line (NSS). All SPIs can be
served by the DMA controller. The SPI interface may be used for a variety of purposes,
including simplex synchronous transfers on two lines with a possible bidirectional data
line or reliable communication using CRC checking. Quad-SPI master mode is also
supported in SPI0.
3.20.
Inter-IC sound (I2S)
Sampling frequency from 8 KHz to 192 KHz.
Support either master or slave mode.
The Inter-IC sound (I2S) bus provides a standard communication interface for digital
audio applications by 4-wire serial lines. GD32L233xx contain an I2S-bus interface that
can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with
SPI1. The audio sampling frequency from 8 KHz to 192 KHz is supported.
3.21.
Cryptographic acceleration Unit (CAU)
Supports DES, TDES or AES (128, 192, or 256) algorithms.
DES/TDES supports Electronic codebook (ECB) or Cipher block chaining (CBC)
mode.
AES supports 128bits-key, 192bits-key or 256 bits-key.
AES supports Electronic codebook (ECB), Cipher block chaining (CBC) mode,
Counter mode (CTR) mode, Galois/counter mode (GCM), Galois message
authentication code mode (GMAC), Counter with CBC-MAC (CCM), Cipher
Feedback mode (CFB) and Output Feedback mode (OFB).
DMA transfer for incoming and outgoing data is supported.
The Cryptographic Acceleration Unit supports acceleration of DES, TDES or AES (128,
192, or 256) algorithms. The DES/TDES supports Electronic codebook (ECB) or Cipher
block chaining (CBC) mode. The AES supports Electronic codebook (ECB), Cipher block
chaining (CBC) mode, Counter mode (CTR) mode, Galois/counter mode (GCM), Galois
message authentication code mode (GMAC), Counter with CBC-MAC (CCM), Cipher
46
GD32L233xx Datasheet
Feedback mode (CFB) and Output Feedback mode (OFB).
3.22.
Segment LCD controller (SLCD)
Configurable frame frequency.
Blinking of individual segments or all segments.
Supports Static, 1/2, 1/3, 1/4, 1/6 and 1/8 duty.
Supports 1/2, 1/3 and 1/4 bias.
Double buffer up to 8x32 bits registers to store SLCD_DATAx.
The contrast can also be adjusted by configuring dead time.
Optional voltage output driver for enhance SLCD driving capability.
The SLCD controller directly drives LCD displays by creating the AC segment and
common voltage signals automatically. It can drive the monochrome passive liquid crystal
display (LCD) which composed of a plurality of segments (pixels or complete symbols)
that can be converted to visible or invisible. The SLCD controller can support up to 32
segments and 8 commons.
3.23.
Comparators (CMP)
Two fast rail-to-rail low-power comparators with software configurable.
Programmable reference voltage (internal or external I/O).
Two Comparators (CMP) is implemented within the device. It can wake up from deepsleep mode to generate interrupts and breaks for the timers and also can be combined
as a window comparator. The internal voltage reference is also connected to ADC_IN17
input channel of the ADC.
3.24.
Universal serial bus full-speed device interface (USBD)
USB 2.0 full-speed device controller.
Support USB 2.0 Link Power Management.
Dedicated 512-byte SRAM used for data packet buffer.
Support embedded pull-up on the DP line.
Integrated USB PHY.
The Universal Serial Bus full-speed device interface (USBD) module contains a fullspeed internal USB PHY and no more external PHY chip is needed. USBD supports all
the four types of transfer (control, bulk, interrupt and isochronous) defined in USB 2.0
protocol. USBD supports 8 USB bidirectional endpoints that can be individually
configured.
47
GD32L233xx Datasheet
3.25.
Debug mode
Serial wire debug port (SW-DP).
Debug capabilities can be accessed by a debug tool via Serial Wire (SW - Debug Port).
3.26.
Package and operation temperature
LQFP64 (GD32L233RxT6), LQFP48 (GD32L233CxT6), LQFP32 (GD32L233KxT6)
and QFN32 (GD32L233KxQ6).
Operation temperature range: -40°C to +85°C (industrial level)
48
GD32L233xx Datasheet
4
Electrical characteristics
4.1
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without
permanently damaging the device. Note that the device is not guaranteed to operate
properly at the maximum ratings. Exposure to the absolute maximum rating conditions
for extended periods may affect device reliability.
Table 4-1. Absolute maximum ratings(1)(4)
Symbol
Parameter
Min
Max
Unit
VDD
External voltage range(2)
VSS - 0.3
VSS + 3.63
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.63
V
Input voltage on 5V tolerant pin(3)
VSS - 0.3
VDD + 3.63
V
Input voltage on other I/O
VSS - 0.3
3.63
V
|ΔVDDx|
Variations between different VDD power pins
—
50
mV
|VSSX −VSS|
Variations between different ground pins
—
50
mV
IIO
Maximum current for GPIO pins
—
±25
mA
TA
Operating temperature range
-40
+85
°C
Power dissipation at TA = 85°C of LQFP64
—
733
Power dissipation at TA = 85°C of LQFP48
—
574
Power dissipation at TA = 85°C of LQFP32
—
724
Power dissipation at TA = 85°C of QFN32
—
940
TSTG
Storage temperature range
-65
+150
°C
TJ
Maximum junction temperature
—
+125
°C
VIN
PD
(1)
(2)
(3)
(4)
4.2
mW
Guaranteed by design, not tested in production.
All main power and ground pins should be connected to an external power source within the allowable
range.
VIN maximum value cannot exceed 5.5 V.
It is recommended that VDD and VDDA are powered by the same source. The maximum difference between
VDD and VDDA does not exceed 300 mV during power-up and operation.
Operating conditions characteristics
Table 4-2. DC operating conditions
Min(1) Typ Max(1) Unit
Symbol
Parameter
Conditions
VDD
Supply voltage
—
1.71
3.3
3.63
V
VDDA
Analog supply voltage
—
1.71
3.3
3.63
V
VBAT
Battery supply voltage
—
1.71
3.3
3.63
V
(1)
Based on characterization, not tested in production.
Figure 4-1. Recommended power supply decoupling capacitors(1)
49
GD32L233xx Datasheet
VBAT
100 nF
VDD
4.7 μF + 100 nF
VDDA
1 μF 10 nF
VREF
1 μF
(1)
10 nF
VSS
All decoupling capacitors need to be as close as possible to the pins on the PCB board.
Table 4-3. Clock frequency(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK1
AHB1 clock frequency
—
0
64
MHz
fHCLK2
AHB2 clock frequency
—
0
64
MHz
fAPB1
APB1 clock frequency
—
0
32
MHz
fAPB2
APB2 clock frequency
—
0
64
MHz
Min
Max
Unit
0
∞
50
∞
(1)
Guaranteed by design, not tested in production.
Table 4-4. Operating conditions at Power up/ Power down(1)
Symbol
tVDD
(1)
Parameter
Conditions
VDD rise time rate
—
VDD fall time rate
us/v
Guaranteed by design, not tested in production.
Table 4-5. Start-up timings of Operating conditions (1)
Symbol
Parameter
tstart-up
Start-up time
(1)
(2)
(3)
Conditions
Typ
Unit
Clock source from HXTAL
1.24
ms
Clock source from IRC16M
16.6
us
Based on characterization, not tested in production.
After power-up, the start-up time is the time between the rising edge of NRST high and the first I/O
instruction conversion in SystemInit function.
PLL is off.
Table 4-6. Power saving mode wakeup timings characteristics(1) (2)
Symbol
tSleep
Parameter
Typ
Wakeup from Sleep mode
1.29
Wakeup from Sleep 1 mode (NPLDO=0.9V)
1.30
Wakeup from Sleep 2 mode (NPLDO=0.9V and
1.32
Unit
us
50
GD32L233xx Datasheet
Symbol
Parameter
Typ
Unit
NPLDO in Low-driver mode)
tDeep-sleep
Wakeup from Deep-sleep mode (NPLDO in normal driver mode)
9.95
Wakeup from Deep-sleep mode (NPLDO in low driver mode)
9.93
Wakeup from Deep-sleep 1 mode
13.74
Wakeup from Deep-sleep 2 mode
15.50
Wakeup from Standby mode
20.92
tStandby
(1)
(2)
4.3
Based on characterization, not tested in production.
The wakeup time is measured from the wakeup event to the point at which the application code reads
the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC16M = System clock = 16MHz.
Power consumption
The power measurements specified in the tables represent that code with data executing
from on-chip Flash with the following specifications.
Table 4-7. Power consumption characteristics(2)(3)
Symbol
Parameter
Typ(1) Max Unit
Conditions
Min
VDD = 3.3 V, HXTAL = 8 MHz, System clock
—
9.38
—
—
4.39
—
-—
7.23
-—
—
3.46
—
—
5.06
—
-—
2.2
-—
—
4.47
—
—
2.54
—
-—
3.24
-—
—
1.92
—
—
1.98
—
-—
1.29
-—
—
1.36
—
= 64 MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 64 MHz, All peripherals disabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 48 MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 48 MHz, All peripherals disabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 36 MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 36 MHz, All peripherals disabled
IDD+IDDA
Supply current VDD = 3.3 V, HXTAL = 8 MHz, System clock
(Run mode)
mA
= 24 MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 24 MHz, All peripherals disabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 16 MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 16 MHz, All peripherals disabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 8 MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 8 MHz, All peripherals disabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 4 MHz, All peripherals enabled
51
GD32L233xx Datasheet
Symbol
Parameter
Typ(1) Max Unit
Conditions
Min
VDD = 3.3 V, HXTAL = 8 MHz, System clock
—
0.96
—
-—
1.04
-—
—
0.81
—
—
0.9
—
—
0.75
—
—
1.91
—
—
0.77
—
-—
1.29
-—
—
0.69
—
—
0.8
—
-—
0.47
-—
—
0.56
—
= 4 MHz, All peripherals disabled
VDD = 3.3 V, HXTAL = 8 MHz, System clock
= 2 MHz, All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 2 MHz, All peripherals
disabled
VDD = 3.3 V, HXTAL = 4 MHz, System clock
= 1 MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 4 MHz, System clock
= 1 MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 16
MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 16
MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 8
MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 8
MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 4
Supply current
MHz, All peripherals enabled
(Run 1 mode)
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 4
MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 2
MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 2
mA
—
0.36
—
—
0.43
—
-—
0.3
-—
—
0.45
—
—
0.25
—
-—
0.35
-—
—
0.22
—
—
7.73
—
MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 1
MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, HCLK = 1
MHz, All peripherals disabled
VDD = 3.3 V, HXTAL = 16 MHz, HCLK = 2
MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 16 MHz, HCLK = 2
Supply current
MHz, All peripherals disabled
(Run 2 mode)
VDD = 3.3 V, HXTAL = 16 MHz, HCLK = 1
MHz, All peripherals enabled
VDD = 3.3 V, HXTAL = 16 MHz, HCLK = 1
MHz, All peripherals disabled
Supply current
(Sleep mode)
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 64 MHz, All peripherals
mA
enabled
52
GD32L233xx Datasheet
Symbol
Parameter
Conditions
Min
Typ(1) Max Unit
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 64 MHz, All peripherals
—
2.33
—
-—
5.99
-—
—
1.92
—
—
4.68
—
-—
1.6
-—
—
3.38
—
—
1.29
—
-—
2.51
-—
—
1.09
—
—
1.62
—
-—
0.86
-—
—
1.18
—
—
0.75
—
—
0.94
—
disabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 48 MHz, All peripherals
enabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 48 MHz, All peripherals
disabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 36 MHz, All peripherals
enabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 36 MHz, All peripherals
disabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 24 MHz, All peripherals
enabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 24 MHz, All peripherals
disabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 16 MHz, All peripherals
enabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 16 MHz, All peripherals
disabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 8 MHz, All peripherals
enabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 8 MHz, All peripherals
disabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 4 MHz, All peripherals
enabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 4 MHz, All peripherals
disabled
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 2 MHz, All peripherals
enabled
53
GD32L233xx Datasheet
Symbol
Parameter
Conditions
Min
Typ(1) Max Unit
VDD = 3.3 V, HXTAL = 8 MHz, CPU clock
off, System clock = 2 MHz, All peripherals
—
0.7
—
-—
0.86
-—
—
0.7
—
—
1.74
—
-—
0.52
-—
—
1.03
—
—
0.38
—
—
0.67
—
-—
0.31
-—
—
0.49
—
—
0.28
—
-—
0.4
-—
—
0.26
—
—
0.43
—
—
0.22
—
disabled
VDD = 3.3 V, HXTAL = 4 MHz, CPU clock
off, System clock = 1 MHz, All peripherals
enabled
VDD = 3.3 V, HXTAL = 4 MHz, CPU clock
off, System clock = 1 MHz, All peripherals
disabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 16 MHz, All peripherals
enabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 16 MHz, All peripherals
disabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 8 MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 8 MHz, All peripherals disabled
Supply current VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
(Sleep 1 mode) off, HCLK = 4 MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 4 MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 2 MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 2 MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 1 MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 1 MHz, All peripherals disabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 2 MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
Supply current off, HCLK = 2 MHz, All peripherals disabled
(Sleep 2 mode) VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
mA
—
0.34
—
—
0.21
—
—
40.09
—
off, HCLK = 1 MHz, All peripherals enabled
VDD = 3.3 V, IRC16M = 16 MHz, CPU clock
off, HCLK = 1 MHz, All peripherals disabled
Supply current
VDD = 3.3 V, NPLDO in Low driver mode,
(Deep-sleep
IRC40K off, RTC off, All GPIOs analog
mode)
mode
μA
54
GD32L233xx Datasheet
Symbol
Parameter
Conditions
Supply current
VDD = 3.3 V, NPLDO off, LPLDO on,
(Deep-sleep 1
IRC40K off, RTC off, All GPIOs analog
mode)
mode
Supply current
(Deep-sleep 2
mode)
Supply current
(Standby mode)
Min
Typ(1) Max Unit
—
3.144
—
—
1.702
—
VDD = 3.3 V, LXTAL off, IRC32K off, RTC off
—
0.442
—
μA
VDD off, VBAT = 3.6V, LXTAL on with
—
1.22
—
μA
—
1.09
—
μA
—
0.93
—
μA
—
0.79
—
μA
—
1.09
—
μA
—
0.97
—
μA
—
0.8
—
μA
—
0.66
—
μA
—
0.92
—
μA
—
0.79
—
μA
—
0.63
—
μA
—
0.49
—
μA
—
0.87
—
μA
—
0.74
—
μA
VDD = 3.3 V, NPLDO off, LPLDO on,
COREOFF0/SRAM1/COREOFF1 off,
IRC40K off, RTC off, All GPIOs analog
mode
external crystal, RTC on, Higher driving
VDD off, VBAT = 3.3V, LXTAL on with
external crystal, RTC on, Higher driving
VDD off, VBAT = 2.6V, LXTAL on with
external crystal, RTC on, Higher driving
VDD off, VBAT = 1.71V, LXTAL on with
external crystal, RTC on, Higher driving
VDD off, VBAT = 3.6V, LXTAL on with
external crystal, RTC on, Medium High
driving
VDD off, VBAT = 3.3V, LXTAL on with
external crystal, RTC on, Medium High
driving
VDD off, VBAT = 2.6V, LXTAL on with
external crystal, RTC on, Medium High
ILXTAL+RTC
LXTAL+RTC
current
driving
VDD off, VBAT = 1.71V, LXTAL on with
external crystal, RTC on, Medium High
driving
VDD off, VBAT = 3.6V, LXTAL on with
external crystal, RTC on, Medium Low
driving
VDD off, VBAT = 3.3V, LXTAL on with
external crystal, RTC on, Medium Low
driving
VDD off, VBAT = 2.6V, LXTAL on with
external crystal, RTC on, Medium Low
driving
VDD off, VBAT = 1.71V, LXTAL on with
external crystal, RTC on, Medium Low
driving
VDD off, VBAT = 3.6V, LXTAL on with
external crystal, RTC on, Low driving
VDD off, VBAT = 3.3V, LXTAL on with
55
GD32L233xx Datasheet
Symbol
Parameter
Conditions
Min
Typ(1) Max Unit
external crystal, RTC on, Low driving
VDD off, VBAT = 2.6V, LXTAL on with
—
0.57
—
μA
—
0.43
—
μA
external crystal, RTC on, Low driving
VDD off, VBAT = 1.71V, LXTAL on with
external crystal, RTC on, Low driving
(1)
(2)
(3)
Based on characterization, not tested in production.
When analog peripheral blocks such as ADCs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional
power consumption should be considered.
The system clock 36MHZ (inclusive) to 64MHZ (inclusive) adopts FMC_WAIT_STATE_1, the system
clock 24MHZ (inclusive) to 1MHZ (inclusive) adopts FMC_WAIT_STATE_0.
Figure 4-2. Typical supply current consumption in Run mode
10
9.38
9
8
7.23
IDD+IDDA(mA)
7
6
5
All peripherals enabled
4
All peripherals disabled
5.06
4.47
4.39
3.24
3
3.46
1.98
2
1
0
1
2.54
1.36
0.9
1.04
0.75
0.81
0.96
2
4
1.92
2.2
1.29
8
16
24
36
48
64
System clock(MHz)
56
GD32L233xx Datasheet
Figure 4-3. Typical supply current consumption in Sleep mode
9
7.73
8
7
IDD+IDDA(mA)
5.99
6
4.68
5
All peripherals enabled
4
3.38
All peripherals disabled
3
2.51
1.62
2
0.86 0.94
1
0.7
0
1
2.33
1.18
0.7
0.75
0.86
2
4
8
1.09
16
1.29
24
1.6
36
1.92
48
64
System clock(MHz)
57
GD32L233xx Datasheet
4.4
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result
is given in Table 4-8. EMS characteristics, based on the EMS levels and classes
compliant with IEC 61000 series standard.
Table 4-8. EMS characteristics(1)
Symbol
VESD
VFTB
(1)
Parameter
Voltage applied to all device pins to
induce a functional disturbance
Conditions
Level/Class
VDD = 3.3 V, LQFP64,
fHCLK = 64 MHz
3A
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VDD = 3.3 V, LQFP64,
induce a functional disturbance through
fHCLK = 64 MHz
100 pF on VDD and VSS pins
conforms to IEC 61000-4-4
4A
Based on characterization, not tested in production.
EMI (Electromagnetic Interference) emission test result is given in the Table 4-9. EMI
characteristics(1), The electromagnetic field emitted by the device are monitored while
an application, executing EEMBC code, is running. The test is compliant with SAE J17523:2017 standard which specifies the test board and the pin loading.
Table 4-9. EMI characteristics(1)
Max vs.
Symbol
Parameter
Conditions
VDD = 3.6 V, TA = +25 °C,
SEMI
Peak level
LQFP64,
4.5
frequency band
[fHXTAL/fHCLK] Unit
8/64 MHz
0.15 MHz to 30 MHz
-11.89
fHCLK = 64 MHz, 30 MHz to 130 MHz
-1.54
conforms to SAE J17523:2017
(1)
Tested
130 MHz to 1 GHz
dBμV
3.05
Based on characterization, not tested in production.
Power supply supervisor characteristics
Table 4-10. Power supply supervisor characteristics(1)
58
GD32L233xx Datasheet
Symbol
VLVD(1)
VLVDhyst(2)
VBOR0
VBOR1
VBOR2
VBOR3
VBOR4
VPOR(1)
VPDR(1)
Parameter
Conditions
Min
Typ
Max
Unit
LVDT[2:0] = 000, rising edge
—
2.15
—
V
LVDT[2:0] = 000, falling edge
—
2.05
—
V
LVDT[2:0] = 001, rising edge
—
2.30
—
V
LVDT[2:0] = 001, falling edge
—
2.20
—
V
LVDT[2:0] = 010, rising edge
—
2.45
—
V
LVDT[2:0] = 010, falling edge
—
2.35
—
V
Low Voltage Detector
LVDT[2:0] = 011, rising edge
—
2.60
—
V
Threshold
LVDT[2:0] = 011, falling edge
—
2.50
—
V
LVDT[2:0] = 100, rising edge
—
2.75
—
V
LVDT[2:0] = 100, falling edge
—
2.65
—
V
LVDT[2:0] = 101, rising edge
—
2.90
—
V
LVDT[2:0] = 101, falling edge
—
2.80
—
V
LVDT[2:0] = 110, rising edge
—
3.00
—
V
LVDT[2:0] = 110, falling edge
—
2.90
—
V
LVD hysteresis
—
—
100
—
mV
Brown-out reset
rising edge
—
1.60
—
threshold 0
falling edge
—
1.56
—
Brown-out reset
rising edge
—
2.10
—
threshold 1
falling edge
—
2.00
—
Brown-out reset
rising edge
—
2.30
—
threshold 2
falling edge
—
2.20
—
Brown-out reset
rising edge
—
2.60
—
threshold 3
falling edge
—
2.50
—
Brown-out reset
rising edge
—
2.90
—
threshold 4
falling edge
—
2.80
—
1.56
1.60
1.63
V
1.52
1.56
1.59
V
Power on reset
threshold
Power down reset
threshold
—
V
V
V
V
V
VPDRhyst(2)
PDR hysteresis
—
40
—
mV
tRSTTEMPO(2)
Reset temporization
—
550
—
us
(1)
(2)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
59
GD32L233xx Datasheet
4.6
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical
sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample.
Static latch-up (LU) test is based on the two measurement methods.
Table 4-11. ESD characteristics(1)
Symbol
VESD(HBM)
VESD(CDM)
(1)
Parameter
Electrostatic discharge
voltage (human body model)
Electrostatic discharge
voltage (charge device model)
Conditions
Min
Typ
Max
Unit
JS-001-2017
—
—
2000
V
JS-002-2018
—
—
500
V
Conditions
Min
Typ
Max
Unit
—
—
±200
mA
—
—
5.4
V
Based on characterization, not tested in production.
Table 4-12. Static latch-up characteristics(1)
Symbol
Parameter
I-test
LU
JESD78
Vsupply over voltage
(1)
4.7
Based on characterization, not tested in production.
External clock characteristics
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics
Symbol
fHXTAL
RF
(1)
(2)
Parameter
Conditions
Min
Typ
Max
Unit
Crystal or ceramic frequency
VDD = 3.3 V
4
8
48
MHz
Feedback resistor
VDD = 3.3 V
—
400
—
kΩ
—
—
20
30
pF
Recommended matching
CHXTAL
(2) (3)
capacitance on OSCIN and
OSCOUT
Ducy(HXTAL)(2)
Crystal or ceramic duty cycle
—
30
50
70
%
gm(2)
Oscillator transconductance
Startup
—
20
—
mA/V
VDD = 3.3 V
—
0.32
—
mA
VDD = 3.3 V
—
1.27
—
ms
IDD(HXTAL) (1)
tSUHXTAL(1)
(1)
(2)
(3)
Crystal or ceramic operating
current
Crystal or ceramic startup time
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on
OSCIN and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or
ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance.
60
GD32L233xx Datasheet
Table 4-14. High speed external user clock characteristics (HXTAL in bypass mode)
Symbol
Parameter
External clock source or oscillator
fHXTAL_ext(1)
frequency
VHXTALH(2)
OSCIN input pin high level voltage
(2)
OSCIN input pin low level voltage
VHXTALL
tH/L(HXTAL) (2)
tR/F(HXTAL)
(2)
CIN(2)
Ducy(HXTAL)
(1)
(2)
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
1
8
50
MHz
0.7 VDD —
VDD
VDD = 3.3 V
VSS
—
0.3 VDD
V
OSCIN high or low time
—
5
—
—
OSCIN rise or fall time
—
—
—
10
OSCIN input capacitance
—
—
5
—
pF
Duty cycle
—
30
50
70
%
(2)
ns
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic
characteristics
Symbol
fLXTAL
(1)
Parameter
Conditions
Min
Typ
Max
Unit
Crystal or ceramic frequency
VDD = 3.3 V
—
32.768
—
kHz
—
—
10
—
pF
—
30
—
70
%
—
3.6
—
—
4.8
—
Recommended matching
CLXTAL
(2)(3)
capacitance on OSC32IN
and OSC32OUT
Ducy(LXTAL)(2) Crystal or ceramic duty cycle
Lower driving
capability
Medium low driving
gm(2)
Oscillator transconductance
capability
Medium high driving
capability
Higher driving
capability
Lower driving
capability
Medium low driving
IDDLXTAL
(1)
Crystal or ceramic operating
capability
current
Medium high driving
capability
Higher driving
capability
tSULXTAL(1)(4)
(1)
(2)
(3)
(4)
Crystal or ceramic startup
time
VDD = 3.3 V
μA/V
—
8.4
—
—
10.8
—
—
332
—
—
392
—
nA
—
562
—
—
692
—
—
0.32
—
s
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on
OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or
ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance.
tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz
oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer.
61
GD32L233xx Datasheet
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode)
Symbol
Parameter
fLXTAL_ext(1)
voltage
(2)
CIN(2)
Ducy(LXTAL)
4.8
Max
Unit
VDD = 3.3 V
—
32.768
1000
kHz
0.7 VDD
—
VDD
voltage
tH/L(LXTAL) (2)
(1)
(2)
Typ
VDD = 3.3 V
OSC32IN input pin low level
(2)
tR/F(LXTAL)
oscillator frequency
Min
OSC32IN input pin high level
VLXTALH(2)
VLXTALL
External clock source or
Conditions
V
VSS
—
0.3 VDD
OSC32IN high or low time
—
250
—
—
OSC32IN rise or fall time
—
—
—
50
OSC32IN input capacitance
—
—
5
—
pF
Duty cycle
—
30
50
70
%
(2)
ns
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Internal clock characteristics
Table 4-17. High speed internal clock (IRC16M) characteristics
Symbol
Parameter
Conditions
Min
Typ
VDD = VDDA = 3.3 V
—
16
Max Unit
High Speed Internal
fIRC16M
Oscillator (IRC16M)
—
MHz
—
%
frequency
ACCIRC16M
IRC16M oscillator
VDD = VDDA = 3.3 V,
Frequency accuracy,
TA = -40 °C ~ +85 °C
Factory-trimmed
VDD = VDDA = 3.3 V
-1.0
—
+1.0
%
—
—
0.3(1)
—
%
IRC16M oscillator duty cycle
VDD = VDDA = 3.3 V
45
50
55
%
IRC16M oscillator operating
VDD = VDDA = 3.3 V,
current
fIRC8M = 16 MHz
—
110
—
μA
IRC16M oscillator startup
VDD = VDDA = 3.3 V,
time
fIRC8M = 16 MHz
—
0.75
—
μs
trimming
IDDIRC16M(1)
tSUIRC16M(1)
(1)
(2)
-1.5 to
1.5(1)
IRC16M oscillator
Frequency accuracy, User
DIRC16M(2)
—
step(1)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
62
GD32L233xx Datasheet
Table 4-18. Low speed internal clock (IRC32K) characteristics
Symbol
fIRC32K
IDDAIRC32K(2)
tSUIRC32K(2)
(1)
(2)
Parameter
Low Speed Internal oscillator
(IRC32K) frequency
IRC32K oscillator operating
current
IRC32K oscillator startup
time
Conditions
Min
VDD = VDDA = 3.3 V,
TA = -40~85
Typ
Max
Unit
31.7 to
°C(2)
32.3
kHz
VDD = VDDA = 3.3 V
30
35
VDD = VDDA = 3.3 V
—
160
—
nA
VDD = VDDA = 3.3 V
—
40
—
μs
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Table 4-19. High speed internal clock (IRC48M) characteristics
Symbol
Parameter
Conditions
Min
Typ
VDD = VDDA = 3.3 V
—
48
Max Unit
High Speed Internal
fIRC48M
Oscillator (IRC48M)
—
MHz
frequency
ACCIRC48M
IRC48M oscillator
VDD = VDDA = 3.3 V,
Frequency accuracy,
TA = -40 °C ~ +85 °C
Factory-trimmed
VDD = VDDA = 3.3 V
— -3.3 to -0.25(1) —
%
-2.0
—
+2.0
%
—
—
0.12
—
%
IRC48M oscillator duty cycle
VDD = VDDA = 3.3 V
45
50
55
%
IRC48M oscillator operating
VDD = VDDA = 3.3 V,
current
fIRC28M = 48 MHz
—
327
—
μA
IRC48M oscillator startup
VDD = VDDA = 3.3 V,
time
fIRC28M = 48 MHz
—
1.8
—
μs
IRC48M oscillator
Frequency accuracy, User
trimming step
DIRC48M(2)
IDDAIRC48M(1)
tSUIRC48M(1)
(1)
(2)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
63
GD32L233xx Datasheet
4.9
PLL characteristics
Table 4-20. PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
2
—
16
MHz
—
16
—
64
MHz
—
—
—
64
MHz
—
—
—
200
μs
VCO freq = 64 MHz
—
400
—
μA
—
120
—
PLL input clock
fPLLIN(1)
frequency
PLL output clock
fPLLOUT(2)
frequency
PLL VCO output clock
fVCO(2)
frequency
tLOCK(2)
PLL lock time
Current consumption
IDD(1)
on VDD
Cycle to cycle Jitter
JitterPLL(3)
（rms）
System clock
Cycle to cycle Jitter
ps
—
（peak to peak）
(1)
(2)
(3)
4.10
—
900
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Value given with main PLL running.
Memory characteristics
Table 4-21. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TA = -40 °C ~ +85 °C
10
—
—
kcycles
Number of guaranteed
PECYC(1)
program /erase cycles
before failure (Endurance)
tRET(1)
Data retention time
10k cycles at TA = 85 °C
10
—
—
years
tPROG(2)
Word programming time
TA = -40 °C ~ + 85 °C
—
37.5
—
μs
tERASE(2)
Page erase time
TA = -40 °C ~ + 85 °C
—
11
—
ms
tMERASE(2)
Mass erase time
TA = -40 °C ~ + 85°C
—
12
—
ms
(1)
(2)
4.11
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
NRST pin characteristics
Table 4-22. NRST pin characteristics
64
GD32L233xx Datasheet
Symbol
VIL(NRST)
(1)
VIH(NRST)
(1)
Vhyst(1)
Rpu
(1)
(2)
(2)
Parameter
Conditions
NRST Input low level voltage
1.71 V ≤ VDD = VDDA
NRST Input high level voltage
≤ 3.63 V
Schmidt trigger Voltage hysteresis
Min
Typ
Max
-0.5
—
0.35 VDD
0.65 VDD
—
VDD + 0.5
—
400
—
mV
—
40
—
kΩ
—
Pull-up equivalent resistor
Unit
V
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Figure 4-4. Recommended external NRST pin circuit
VDD
VDD
External reset circuit
RPU
10 kΩ
NRST
K
100 nF
GND
4.12
VREF buffer characteristics
Table 4-23. VREF buffer characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Analog Supply Voltage
—
2.7
3.3
3.63
V
Output Reference
VDDA = 3.3 V
2.49
2.50
2.51
All VDDA, All Temp(2)
2.47
2.50
2.53
Power Supply
DC (IO = 0)
—
57
—
Rejection
DC (IO = 200 μA )
—
57
—
TSU(1)
Setup Time
CL = 1 μF + 10 nF
—
—
200
μs
ILOAD_R(1)
Load Regulation
ILOAD from 0 to 200 μA
—
5
—
μV/μA
CLOAD(1)
Load Capacitor
—
—
1
—
μF
TRIM(1)
Trim Step
—
—
3
—
mV
VREF
PSRR(1)
Voltage
V
dB
(1). Guaranteed by design, not tested in production.
(2). Based on characterization, not tested in production.
65
GD32L233xx Datasheet
4.13
GPIO characteristics
Table 4-24. I/O port DC characteristics(1)(3)
Symbol
Parameter
Conditions
Standard IO Low level 1.71 V ≤ VDD = VDDA ≤ 3.63
VIL
VIH
VOL
(IO_speed=50MHz)
Max
—
—
0.3 VDD
—
—
0.3 VDD
V
5V-tolerant IO Low
1.71 V ≤ VDD = VDDA ≤ 3.63
level input voltage
V
Standard IO High
1.71 V ≤ VDD = VDDA ≤ 3.63
level input voltage
V
5 V-tolerant IO High
1.71 V ≤ VDD = VDDA ≤ 3.63
level input voltage
V
Low level output
VDD = 1.71 V
—
0.26
—
voltage for an IO Pin
VDD = 3.3 V
—
0.13
—
(IIO = +8 mA)
VDD = 3.6 V
—
0.13
—
(IIO = +10 mA)
VDD = 1.71 V
—
0.20
—
Low level output
VDD = 3.3 V
—
0.33
—
VDD = 3.6 V
—
0.32
—
High level output
VDD = 1.71V
—
1.46
—
voltage for an IO Pin
VDD = 3.3 V
—
3.15
—
(IIO = +8 mA)
VDD = 3.6 V
—
3.45
—
(IIO = +10 mA)
VDD = 1.71 V
—
1.38
—
High level output
VDD = 3.3 V
—
2.91
—
(IIO = +20 mA)
VDD = 3.6 V
—
3.22
—
(IIO = +4 mA)
VDD = 1.71 V
—
0.31
—
Low level output
VDD = 3.3 V
—
0.36
—
(IIO = +8 mA)
VDD = 3.6 V
—
0.35
—
Low level output
VDD = 1.71 V
—
—
—
voltage for an IO Pin
VDD = 3.3 V
—
0.73
—
(IIO = +15 mA)
VDD = 3.6 V
—
0.70
—
(IIO = +4 mA)
VDD = 1.71 V
—
1.33
—
High level output
VDD = 3.3 V
—
2.87
—
VDD = 3.6 V
—
3.19
—
High level output
VDD = 1.71 V
—
—
—
voltage for an IO Pin
VDD = 3.3 V
—
2.42
—
(IIO = +15 mA)
VDD = 3.6 V
—
2.78
—
(IIO = +1 mA)
VDD = 1.71 V
—
0.32
—
(IIO = +20 mA)
(IO_speed=50MHz)
Typ
input voltage
voltage for an IO Pin
VOH
Min
Unit
V
0.7 VDD —
—
0.7 VDD —
—
V
V
voltage for an IO Pin
VOL
(IO_speed=10MHz)
VOH
(IO_speed=10MHz)
VOL
voltage for an IO Pin
V
voltage for an IO Pin
(IIO = +8 mA)
V
V
66
GD32L233xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(IO_speed=2MHz)
Low level output
VDD = 3.3 V
—
0.55
—
(IIO = +4 mA)
VDD = 3.6 V
—
0.53
—
(IIO = +1 mA)
VDD = 1.71 V
—
1.32
—
VOH
High level output
VDD = 3.3 V
—
2.65
—
(IO_speed=2MHz)
voltage for an IO Pin
VDD = 3.6 V
—
2.99
—
—
—
40
—
kΩ
—
—
40
—
kΩ
voltage for an IO Pin
(IIO = +4 mA)
RPU(2)
RPD(2)
(1)
(2)
(3)
Internal pull-up
resistor
Internal pull-down
resistor
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which
can only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz
when they are in output mode(maximum load: 30 pF).
Table 4-25. I/O port AC characteristics(1)
GPIOx_OSPD[1:0] bit value(2)
Parameter
Conditions
1.71 ≤ VDD ≤ 3.63 V,
CL = 10 pF
GPIOx_OSPD->OSPDy[1:0] = X0
Maximum
（IO_Speed = 2 MHz）
frequency
1.71 ≤ VDD ≤ 3.63 V,
CL = 30 pF
1.71≤ VDD ≤ 3.63 V, CL = 50 pF
1.71 ≤ VDD ≤ 3.63 V,
CL = 10 pF
GPIOx_OSPD->OSPDy[1:0] = 01
Maximum
1.71 ≤ VDD ≤ 3.63 V,
（IO_Speed = 10 MHz）
frequency
CL = 30 pF
1.71 ≤ VDD ≤ 3.63 V,
CL = 50 pF
1.71 ≤ VDD ≤ 3.63 V,
CL = 10 pF
GPIOx_OSPD->OSPDy[1:0] = 11
Maximum
1.71 ≤ VDD ≤ 3.63 V,
（IO_Speed = 50 MHz）
frequency
CL = 30 pF
1.71 ≤ VDD ≤ 3.63 V,
CL = 50 pF
(1)
(2)
Max
Unit
6
5
MHz
4
17
14
MHz
12
81
72
MHz
60
Based on characterization, not tested in production.
The I/O speed is configured using the GPIOx_OSPD->OSPDy [1:0] bits. Refer to the GD32L233 user
manual which is selected to set the GPIO port output speed.
67
GD32L233xx Datasheet
Figure 4-5. I/O port AC characteristics definition
90
%
EXTERNAL
OUTPUT
ON 50pF
90
%
50
10 %
%
tr(IO)ou
t
50
%
10
%
tf(IO)out
T
If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved .
The duty cycle is （45%-55%）when loaded by 50 pF
4.14
ADC characteristics
Table 4-26. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
1.8
3.3
3.6
V
VIN(1)
ADC input voltage range
—
0
—
VDDA
V
fADC(1)
ADC clock
—
0.125
—
16
MHz
12-bit
0.008
—
1.067
10-bit
0.009
—
1.23
MSP
8-bit
0.011
—
1.45
S
6-bit
0.013
—
1.78
Analog input voltage
16 external; 4 internal
0
—
VDDA
V
External input impedance
See Equation 1
—
—
513.6
kΩ
—
—
—
0.5
kΩ
—
—
3
pF
fS(1)
VAIN1)
RAIN
(2)
RADC(2)
Sampling rate
Input sampling switch
resistance
No pin/pad capacitance
CADC(2)
Input sampling capacitance
tCAL(2)
Calibration time
fADC = 16 MHz
—
13.4
—
μs
Sampling time
fADC = 16 MHz
0.156
—
14.97
μs
12-bit
—
15
—
10-bit
—
13
—
1/
8-bit
—
11
—
fADC
6-bit
—
9
—
fS = 1M
—
133
—
fS = 0.5M
—
77
—
fS = 10k
—
17.5
—
fS = 1M
—
14.7
—
fS = 0.5M
—
7.6
—
fS = 10k
—
0.4
—
—
—
5
—
ts
(2)
Total conversion
tCONV(2)
time(including sampling
time)
IDDA(ADC)
IDDV(ADC)
tSU(2)
ADC consumption from
VDDA
ADC consumption from
VREFP
Startup time
included
uA
uA
us
68
GD32L233xx Datasheet
(1)
(2)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Equation 1: RAIN max formula R AIN <
Ts
fADC ∗CADC ∗ln(2N+2 )
− R ADC
The formula above (Equation 1) is used to determine the maximum external impedance allowed
for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-27. ADC RAIN max for fADC = 16 MHz(1)
(1)
Ts(cycles)
ts(μs)
RAINmax (kΩ)
2.5
0.16
4.8
7.5
0.47
15.6
13.5
0.85
28.4
28.5
1.79
60.6
41.5
2.60
88.5
55.5
3.47
118.6
71.5
4.47
153.0
239.5
14.97
513.6
Based on characterization, not tested in production.
Table 4-28. ADC dynamic accuracy at fADC = 16 MHz(1)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC = 16 MHz
10.8
11.2
—
bits
SNDR
Signal-to-noise and distortion ratio
VDDA = VREF+ = 3.3 V
66.7
69.1
—
Signal-to-noise ratio
Input Frequency = 20
66.9
69.3
—
Total harmonic distortion
kHz
—
-82
-78
Typ
Max
—
—
±0.6
±1
±0.8
±1.5
SNR
THD
(1)
dB
Based on characterization, not tested in production.
Table 4-29. ADC static accuracy at fADC = 16 MHz(1)
Symbol
Parameter
Offset
Offset error
DNL
Differential linearity error
INL
Integral linearity error
(1)
Test conditions
fADC = 16 MHz
VDDA = VREF+ = 3.3 V
Unit
LSB
Based on characterization, not tested in production.
Table 4-30. ADC dynamic accuracy at fADC = 16 MHz(1)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC = 16 MHz
10.7
11.2
—
bits
66.2
69.1
—
66.4
69.3
—
—
-82
-78
SNDR
SNR
Signal-to-noise and distortion ratio VDDA = 3.3V VREF+ = 2.5
V
Signal-to-noise ratio
Input Frequency = 20
THD
(1)
Total harmonic distortion
kHz
dB
Based on characterization, not tested in production.
69
GD32L233xx Datasheet
Table 4-31. ADC static accuracy at fADC = 16 MHz(1)
Symbol
Parameter
Offset
Offset error
DNL
Differential linearity error
INL
Integral linearity error
(1)
Test conditions
fADC = 16 MHz,
VDDA = 3.3V VREF+ = 2.5 V
Typ
Max
—
—
±0.6
±1
±0.8
±1.5
Unit
LSB
Based on characterization, not tested in production.
Table 4-32. ADC dynamic accuracy at fADC = 16 MHz(1)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC = 16 MHz,
10.5
10.8
—
bits
SNDR
Signal-to-noise and distortion ratio
VDDA = VREF+ = 1.8 V
64.9
66.7
—
SNR
Signal-to-noise ratio
Input Frequency = 20
65.1
66.9
—
THD
Total harmonic distortion
kHz
—
-71
-68
Typ
Max
—
—
±0.8
±1
±1
±1.5
(1)
dB
Based on characterization, not tested in production.
Table 4-33. ADC static accuracy at fADC = 16 MHz(1)
Symbol
Parameter
Offset
Offset error
DNL
Differential linearity error
INL
Integral linearity error
(1)
4.15
Test conditions
fADC = 16 MHz,
VDDA = VREF+ = 1.8 V
Unit
LSB
Based on characterization, not tested in production.
DAC characteristics
Table 4-34. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
1.71
3.3
3.63
V
VREF+(2)
Positive Reference Voltage
—
1.71
—
VDDA
V
—
—
VSSA
—
V
Resistive load with buffer ON
5
—
—
kΩ
—
—
15
kΩ
—
—
50
pF
0.2
—
—
V
0.5
—
—
mV
—
—
—
—
—
400
VREF-(2)
Negative Reference
Voltage
RLOAD(2)
Resistive load
Ro(2)
Impedance output
CLOAD(2)
Capacitive load
Impedance output with buffer
OFF
Capacitive load with buffer ON
Lower DAC_OUT voltage with
DAC_OUT
min(2)
Lower DAC_OUT voltage
buffer ON
Lower DAC_OUT voltage with
buffer OFF
DAC_OUT
max (2)
Higher DAC_OUT voltage with
buffer ON
Higher DAC_OUT voltage
Higher DAC_OUT voltage with
buffer OFF
IDDA(1)
DAC current consumption
With no load, middle
in quiescent mode
code(0x800) on the input,
VDDA-
V
0.2
VDDA-
V
1LSB
—
μA
70
GD32L233xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
114
—
μA
10-bit configuration
—
—
±0.5
12-bit configuration
—
—
±2
10-bit configuration
—
—
±1
12-bit configuration
—
—
±4
VREFP = 3.3 V
With no load, middle
IDDVREF+(1)
DAC current consumption
in quiescent mode
code(0x800) on the input,
VREFP = 3.3 V
DNL(1)
Differential non linearity
INL(1)
Integral non linearity
Offset(1)
Offset error
DAC in 12-bit mode
—
—
±12
LSB
GE(1)
Gain error
DAC in 12-bit mode
—
±0.5
—
%
Settling time
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
—
0.5
—
μs
Wakeup from off state
—
—
5
—
μs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
—
—
4
MS/s
No RLoad, CLOAD=50 pF
—
-80
—
dB
Tsetting
(1)
Twakeup
(2)
Update
rate(2)
PSRR(2)
(1)
(2)
4.16
LSB
LSB
Max frequency for a correct
DAC_OUT change from
code i to i±1LSB
Power supply rejection
ratio(to VDDA)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Temperature sensor characteristics
Table 4-35. Temperature sensor characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOFF
Uncalibrated Offset
TA = 30°C
—
1022.8
—
mV
Uncalibrated Offset Error
TA = 30°C
—
2
—
mV
M
Slope
—
—
3.3
—
mV/°C
EM(1)
Slope Error
—
—
30
—
μV/°C
LIN(3)
Linearity
—
-0.4 to1.2
—
°C
tON
Turn-on Time
—
—
—
μs
-3.5
—
4.7
°C
EOFF
(1)
Temp Sensor Error Using
ETOT(2)(3)
Typical Slope and
Factory-Calibrated Offset
(1)
(2)
(3)
4.17
TA = -40 °C to
85 °C
—
TA = -40 °C to
85 °C
Represents one standard deviation from the mean.
The factory-calibrated offset value is stored in the read-only area of flash in locations 0x1FFFF7F8.
Based on characterization, not tested in production.
Comparators characteristics
Table 4-36. CMP characteristics(1)
71
GD32L233xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VDDA
Operating voltage
—
1.71
3.3
3.63
V
VIN
Input voltage range
—
0
—
VDDA
V
VBG
Scaler input voltage
—
—
0.8
—
V
VSC
Scaler offset voltage
—
—
±5
—
mV
Scaler static consumption
BEN=0 (bridge disable)
—
200
—
nA
from VDDA
BEN=1 (bridge enable)
—
0.8
—
μA
Scaler startup time
—
—
100
—
μs
Propagation delay for 200
Ultra low power mode
—
3.63
—
μs
mV step with 100 mV
Medium power mode
—
0.18
—
μs
overdrive
High speed power mode
—
55
—
ns
Ultra low power mode
—
0.5
—
Medium power mode
—
4.7
—
High speed power mode
—
47
—
—
—
±5
—
No Hysteresis
—
0
—
Low Hysteresis
—
8
—
Medium Hysteresis
—
16
—
High Hysteresis
—
32
—
IDDA(SCALER)
tSTART_SCALER
tD
IDD
Voffset
Vhyst
(1)
Current consumption
Offset error
Hysteresis Voltage
μA
mV
mV
Based on characterization, not tested in production.
Figure 4-6. CMP hysteresis
72
GD32L233xx Datasheet
4.18
TIMER characteristics
Table 4-37. TIMER characteristics (1)
Symbol
Parameter
tres
Timer resolution time
fEXT
RES
Conditions
Min
Max
Unit
—
1
—
tTIMERxCLK
fTIMERxCLK = 64 MHz
15.6
—
ns
Timer external clock
—
0
fTIMERxCLK/2
MHz
frequency
fTIMERxCLK = 64 MHz
0
32
MHz
Timer resolution
—
—
16
bit
—
1
65536
tTIMERxCLK
fTIMERxCLK = 64 MHz
0.0156
1024
μs
—
—
fTIMERxCLK = 64 MHz
—
16-bit counter clock period
tCOUNTER
when internal clock is
selected
tMAX_COUNT
(1)
Maximum possible count
65536 × 65536 tTIMERxCLK
67.11
s
Guaranteed by design, not tested in production.
73
GD32L233xx Datasheet
4.19
SLCD controller characteristics
Table 4-38. SLCD controller characteristics(1)
Symbol
Parameter
Conditions
Typ
Max
VSLCD
SLCD external voltage
—
—
3.63
VSLCD0
SLCD internal reference voltage 0
—
2.65
—
VSLCD1
SLCD internal reference voltage 1
—
2.80
—
VSLCD2
SLCD internal reference voltage 2
—
2.92
—
VSLCD3
SLCD internal reference voltage 3
—
3.08
—
VSLCD4
SLCD internal reference voltage 4
—
3.23
—
VSLCD5
SLCD internal reference voltage 5
—
3.37
—
VSLCD6
SLCD internal reference voltage 6
—
3.52
—
VSLCD7
SLCD internal reference voltage 7
—
3.67
—
0.2
—
2
Buffer OFF (VODEN=0 is
Cext
VSLCD external
SLCD_CTL register)
capacitance
Buffer ON (VODEN=1 is
SLCD_CTL register)
Supply current from VDD Buffer OFF (VODEN=0 is
ISLCD(2)
at VDD = 2.2 V
SLCD_CTL register)
Supply current from VDD Buffer OFF (VODEN=0 is
at VDD = 3.0 V
SLCD_CTL register)
Buffer OFF (VODEN = 0,
PULSE = 0)
Buffer ON (VODEN = 1, 1/2
IVSLCD
Supply current from
VSLCD (VSLCD = 3.0 V)
Bias)
Buffer ON (VODEN = 1, 1/3
Bias)
Buffer ON (VODEN = 1, 1/4
Bias)
RHN
RLN
(1)
(2)
Min
Total High Resistor value for Low drive resistive
network
Total Low Resistor value for High drive resistive
network
Unit
V
uF
1
—
2
—
3.2
—
uA
—
2.4
—
—
0.5
—
—
0.65
—
uA
—
0.8
—
—
0.95
—
—
—
—
MΩ
—
—
—
kΩ
V44
Segment/Common highest level voltage
—
VSLCD
—
V34
Segment/Common 3/4 level voltage
—
3/4VSLCD
—
V23
Segment/Common 2/3 level voltage
—
2/3VSLCD
—
V12
Segment/Common 1/2 level voltage
—
1/2VSLCD
—
V13
Segment/Common 1/3 level voltage
—
1/3VSLCD
—
V14
Segment/Common 1/4 level voltage
—
1/4VSLCD
—
V0
Segment/Common lowest level voltage
—
0
—
V
Guaranteed by design, not tested in production.
SLCD enabled with 3V internal step-up active,1/8 duty,1/4 bias, division ratio= 64, all pixels active, no
SLCD connected.
74
GD32L233xx Datasheet
4.20
I2C characteristics
Table 4-39. I2C characteristics(1)(2)(3)
Symbol
Parameter
Conditi
ons
Standard
mode
Fast mode
Fast mode
plus
Unit
Min
Max
Min
Max
Min
Max
tSCL(H)
SCL clock high time
—
4.0
—
0.6
—
0.2
—
μs
tSCL(L)
SCL clock low time
—
4.7
—
1.3
—
0.5
—
μs
tsu(SDA)
SDA setup time
250
—
—
50
—
ns
th(SDA)
SDA data hold time
0(3)
3450
0
900
0
450
ns
—
—
1000
—
300
—
120
ns
—
—
300
—
300
—
120
ns
—
4.0
—
0.6
—
0.26
—
μs
—
4.7
—
0.6
—
0.26
—
μs
—
4.0
—
0.6
—
0.26
—
μs
—
4.7
—
1.3
—
0.5
—
μs
—
—
SDA and SCL rise
tr(SDA/SCL)
time
SDA and SCL fall
tf(SDA/SCL)
time
Start condition hold
th(STA)
time
100
Repeated Start
condition
ts(STA)
setup time
Stop condition setup
ts(STO)
time
Stop to Start
condition time (bus
tbuff
free)
(1)
(2)
(3)
Guaranteed by design, not tested in production.
To ensure the standard mode I2C frequency, fPCLK1 must be at least 2 MHz. To ensure the fast mode I2C
frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode plus I2C frequency, f PCLK1 must be at
least a multiple of 10 MHz.
The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of
the falling edge of SCL.
Figure 4-7. I2C bus timing diagram
tsu(STA)
SDA
70%
30%
tf(SDA)
tr(SDA)
tSCL(H)
th(STA)
SCL
tbuff
th(SDA)
tsu(SDA)
70%
30%
tSCL(L)
tr(SCL)
tf(SCL)
tsu(STO)
75
GD32L233xx Datasheet
4.21
SPI characteristics
Table 4-40. Standard SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
16
MHz
tsck(H)
SCK clock high time
—
20
—
ns
tsck (L)
SCK clock low time
—
20
—
ns
Master mode, fPCLKx = 64 MHz,
presc = 4
Master mode, fPCLKx = 64 MHz,
presc = 4
SPI master mode
tV(MO)
Data output valid time
—
—
—
10
ns
tSU(MI)
Data input setup time
—
1
—
—
ns
tH(MI)
Data input hold time
—
0
—
—
ns
SPI slave mode
(1)
tSU(NSS)
NSS enable setup time
—
0
—
—
ns
tH(NSS)
NSS enable hold time
—
1
—
—
ns
tA(SO)
Data output access time
—
—
8
—
ns
tDIS(SO)
Data output disable time
—
—
9
—
ns
tV(SO)
Data output valid time
—
—
9
—
ns
tSU(SI)
Data input setup time
—
0
—
—
ns
tH(SI)
Data input hold time
—
1
—
—
ns
Based on characterization, not tested in production.
Figure 4-8. SPI timing diagram - master mode
tSCK
SCK (CKPH=0 CKPL=0)
SCK (CKPH=0 CKPL=1)
SCK (CKPH=1 CKPL=0)
tSCK(H)
tSCK(L)
SCK (CKPH=1 CKPL=1)
tSU(MI)
MISO
D[0]
LF=1,FF16=0
D[7]
tH(MI)
MOSI
D[0]
D[7]
tV(MO)
tH(MO)
76
GD32L233xx Datasheet
Figure 4-9. SPI timing diagram - slave mode
NSS
tSCK
tSU(NSS)
SCK (CKPH=0 CKPL=0)
tSCK(H)
SCK (CKPH=0 CKPL=1)
tSCK(L)
tH(NSS)
tH(SO)
tDIS(SO)
tV(SO)
tA(SO)
MISO
D[0]
D[7]
tSU(SI)
MOSI
D[0]
D[7]
tH(SI)
77
GD32L233xx Datasheet
4.22
I2S characteristics
Table 4-41. I2S characteristics(1)
Symbol
Parameter
Conditions
Master mode (data: 16 bits,
fCK
Clock frequency
Audio frequency = 96 kHz)
Slave mode
Min
Typ
Max
Unit
—
6.25
—
—
—
12.5
—
80
—
ns
—
80
—
ns
MHz
tH
Clock high time
tL
Clock low time
tV(WS)
WS valid time
Master mode
—
3
—
ns
tH(WS)
WS hold time
Master mode
—
3
—
ns
tSU(WS)
WS setup time
Slave mode
0
—
—
ns
tH(WS)
WS hold time
Slave mode
3
—
—
ns
Slave mode
—
50
—
%
Ducy(sck)
—
I2S slave input clock duty
cycle
tSU(SD_MR)
Data input setup time
Master mode
1
—
—
ns
tSU(SD_SR)
Data input setup time
Slave mode
0
—
—
ns
Master receiver
0
—
—
ns
Slave receiver
1
—
—
ns
—
—
10
ns
3
—
—
ns
—
—
10
ns
0
—
—
ns
tH(SD_MR)
tH(SD_SR)
Data input hold time
tV(SD_ST)
Data output valid time
tH(SD_ST)
Data output hold time
tV(SD_MT)
Data output valid time
tH(SD_MT)
Data output hold time
(1)
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
Based on characterization, not tested in production.
78
GD32L233xx Datasheet
Figure 4-10. I2S timing diagram - master mode
tCK
CPOL=0
tL
CPOL=1
tV(WS)
tH
tH(WS)
WS output
tH(SD_MT)
tV(SD_MT)
SD transmit
D[0]
SD receive
D[0]
tSU(SD_MR)
tH(SD_MR)
Figure 4-11. I2S timing diagram - slave mode
tCK
CPOL=0
tL
CPOL=1
tH
tH(WS)
WS input
tSU(WS)
SD transmit
SD receive
tV(SD_ST)
tH(SD_ST)
D[0]
D[0]
tSU(SD_SR)
tH(SD_SR)
79
GD32L233xx Datasheet
4.23
USART/LPUART characteristics
Table 4-42. USART/LPUART characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 64 MHz
—
—
32
MHz
tSCK(H)
SCK clock high time
fPCLKx = 64 MHz
15.625
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 64 MHz
15.625
—
—
ns
(1)
4.24
Guaranteed by design, not tested in production.
USBD characteristics
Table 4-43. USBD startup time
Symbol
Parameter
Max
Unit
tSTARTUP(1)
USBD startup time
1
μs
(1) Guaranteed by design, not tested in production.
Table 4-44. USBD DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
VDD
USBD operating voltage
—
3.0
—
3.63
Input
VDI
Differential input sensitivity
—
0.2
—
—
levels(1)
VCM
Differential common mode range
Includes VDI range
0.8
—
2.5
VSE
Single ended receiver threshold
—
0.8
—
2.0
VOL
Static output level low
RL of 1.0 kΩ to 3.63 V
—
—
0.3
levels (2) VOH
Static output level high
RL of 15 kΩ to VSS
2.8
3.3
3.63
RPU(2)
USBDP
VIN = VSS
1.2
1.5
1.8
Output
Max Unit
V
V
KΩ
(1) Guaranteed by design, not tested in production.
(2) Based on characterization, not tested in production.
Table 4-45. USBD full speed-electrical characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tR
Rise time
CL = 50 pF
4
5
20
ns
tF
Fall time
CL = 50 pF
4
5
20
ns
tRFM
Rise/ fall time matching
tR / tF
90
—
111
%
vCRS
Output signal crossover voltage
—
1.09
—
2.0
V
(1) Guaranteed by design, not tested in production.
Figure 4-12. USBD timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
VCRS
VSS
tf
tr
80
GD32L233xx Datasheet
4.25
WDGT characteristics
Table 4-46. FWDGT min/max timeout period at 32 kHz (IRC32K)(1)
Prescaler divider
PSC[2:0] bits
1/4
(1)
Min timeout RLD[11:0]= Max timeout RLD[11:0]=
0x000
0xFFF
000
0.03125
511.90625
1/8
001
0.03125
1023.78125
1/16
010
0.03125
2047.53125
1/32
011
0.03125
4095.03125
1/64
100
0.03125
8190.03125
1/128
101
0.03125
16380.03125
1/256
110 or 111
0.03125
32760.03125
Unit
ms
Guaranteed by design, not tested in production.
81
GD32L233xx Datasheet
Table 4-47. WWDGT min-max timeout value at 32 MHz (fPCLK1)(1)
Prescaler
divider
(1)
4.26
PSC[3:0]
Min timeout value
CNT[6:0] = 0x40
Unit
Max timeout value
CNT[6:0] = 0x7F
1/1
0000
128
1/2
0001
256
1/4
0010
512
32.768
1/8
0011
1.024
65.536
1/16
0100
2.048
131.072
1/32
0101
4.096
262.144
1/64
0110
8.192
524.288
1/128
0111
16.384
1048.576
1/256
1000
32.768
1/512
1001
65.536
4194.304
1/1024
1010
131.072
8388.608
1/2048
1011
262.144
16777.216
1/4096
1100
524.288
33554.432
1/8192
1101
1048.576
67108.864
1/1
1110
128
1/1
1111
128
Unit
8.192
μs
ms
μs
16.384
2097.152
ms
4.096
4.096
Guaranteed by design, not tested in production.
Parameter conditions
Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 ℃.
82
GD32L233xx Datasheet
5
Package information
5.1
LQFP64 package outline dimensions
Figure 5-1. LQFP64 package outline
A3
A2 A
θ
c
A1
F
eB
D
D1
33
48
0.25
32
37
L
L1
DETAIL: F
E1
E
b
b1
c1 c
BASE METAL
64
17
WITH PLATING
1
e
b
SECTION B-B
16
B B
Table 5-1. LQFP64 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
11.80
12.00
12.20
D1
9.90
10.00
10.10
E
11.80
12.00
12.20
E1
9.90
10.00
10.10
e
—
0.50
—
eB
11.25
—
11.45
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
83
GD32L233xx Datasheet
(Original dimensions are in millimeters)
Figure 5-2. LQFP64 recommended footprint
12.70
64
49
10.30
48
16
33
17
32
7.80
12.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
84
GD32L233xx Datasheet
LQFP48 package outline dimensions
Figure 5-3. LQFP48 package outline
A3
A2 A
θ
A1
c
5.2
F
eB
D
D1
36
0.25
25
L
24
37
L1
DETAIL: F
E1 E
b
b1
13
48
c1c
BASE METAL
WITH PLATING
1
12
b
e
SECTION B-B
BB
Table 5-2. LQFP48 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
7.10
e
—
0.50
—
eB
8.10
—
8.25
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
(Original dimensions are in millimeters)
85
GD32L233xx Datasheet
Figure 5-4. LQFP48 recommended footprint
9.70
37
48
7.30
36
12
25
24
13
5.80
9.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
86
GD32L233xx Datasheet
5.3
LQFP32 package outline dimensions
Figure 5-5. LQFP32 package outline
A3
A2 A
c
θ
A1
F
eB
D
D1
L
24
0.25
17
L1
DETAIL: F
16
25
E1
b
E
b1
c1 c
9
32
BASE METAL
8
1
WITH PLATING
B B
b
e
SECTION B-B
Table 5-3. LQFP32 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.33
—
0.41
b1
0.32
0.35
0.38
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
7.10
e
—
0.80
—
eB
8.10
—
8.25
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
(Original dimensions are in millimeters)
87
GD32L233xx Datasheet
Figure 5-6. LQFP32 recommended footprint
9.70
25
32
7.30
24
8
17
9
16
6.05
9.70
0.45
1
1.20
0.80
(Original dimensions are in millimeters)
88
GD32L233xx Datasheet
QFN32 package outline dimensions
Figure 5-7. QFN32 package outline
D
b1
32
L
32
1
h
1
2
h
2
K
E2
E
Ne
D2
b
e
Nd
TOP VIEW
EXPOSED THERMAL
PAD ZONE
A
BOTTOM VIEW
A1
c
5.4
SIDE VIEW
Table 5-4. QFN32 package dimensions
Symbol
Min
Typ
Max
A
0.70
0.75
0.80
A1
0
0.02
0.05
b
0.15
0.20
0.25
b1
—
0.14
—
c
—
0.20
—
D
3.90
4.00
4.10
D2
2.60
2.70
2.80
E
3.90
4.00
4.10
E2
2.60
2.70
2.80
e
—
0.40
—
h
0.25
0.30
0.35
K
—
0.30
—
L
0.30
0.35
0.40
Nd
—
2.80
—
Ne
—
2.80
—
(Original dimensions are in millimeters)
89
GD32L233xx Datasheet
Figure 5-8. QFN32 recommended footprint
4.70
25
32
3.20
R 0.125
1
3.05
4.70
2.65
0.25
24
2.65
8
16
9
17
0.75
0.40
(Original dimensions are in millimeters)
90
GD32L233xx Datasheet
5.5
Thermal characteristics
Thermal resistance is used to characterize the thermal performance of the package
device, which is represented by the Greek letter “θ”. For semiconductor devices, thermal
resistance represents the steady-state temperature rise of the chip junction due to the
heat dissipated on the chip surface.
θJA: Thermal resistance, junction-to-ambient.
θJB: Thermal resistance, junction-to-board.
θJC: Thermal resistance, junction-to-case.
ᴪJB: Thermal characterization parameter, junction-to-board.
ᴪJT: Thermal characterization parameter, junction-to-top center.
θJA =(TJ -TA )/PD
(5-1)
θJB =(TJ -TB )/PD
(5-2)
θJC =(TJ -TC )/PD
(5-3)
Where, TJ = Junction temperature.
TA = Ambient temperature
TB = Board temperature
TC = Case temperature which is monitoring on package surface
PD = Total power dissipation
θJA represents the resistance of the heat flows from the heating junction to ambient air. It
is an indicator of package heat dissipation capability. Lower θJA can be considerate as
better overall thermal performance. θJA is generally used to estimate junction temperature.
θJB is used to measure the heat flow resistance between the chip surface and the PCB
board.
θJC represents the thermal resistance between the chip surface and the package top case.
θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other
heat dissipation methods outside the device package).
Table 5-6. Package thermal characteristics(1)
Symbol
θJA
θJB
Condition
Natural convection, 2S2P PCB
Cold plate, 2S2P PCB
Package
Value
LQFP64
54.57
LQFP48
69.64
LQFP32
55.26
QFN32
42.57
LQFP64
35.08
LQFP48
43.16
Unit
°C/W
°C/W
91
GD32L233xx Datasheet
Symbol
θJC
ᴪJB
ᴪJT
(1)
Condition
Cold plate, 2S2P PCB
Natural convection, 2S2P PCB
Natural convection, 2S2P PCB
Package
Value
LQFP32
26.24
QFN32
19.21
LQFP64
18.11
LQFP48
25.36
LQFP32
25.23
QFN32
19.10
LQFP64
35.41
LQFP48
47.75
LQFP32
32.03
QFN32
19.18
LQFP64
1.10
LQFP48
2.45
LQFP32
2.06
QFN32
0.62
Unit
°C/W
°C/W
°C/W
Thermal characteristics are based on simulation, and meet JEDEC specification.
92
GD32L233xx Datasheet
6
Ordering information
Table 6-1. Part ordering code for GD32L233xx devices
Ordering code
Flash (KB)
Package
Package type
GD32L233RCT6
256
LQFP64
Green
GD32L233RBT6
128
LQFP64
Green
GD32L233R8T6
64
LQFP64
Green
GD32L233CCT6
256
LQFP48
Green
GD32L233CBT6
128
LQFP48
Green
GD32L233C8T6
64
LQFP48
Green
GD32L233KBT6
128
LQFP32
Green
GD32L233K8T6
64
LQFP32
Green
GD32L233KBQ6
128
QFN32
Green
GD32L233K8Q6
64
QFN32
Green
Temperature
operating range
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
93
GD32L233xx Datasheet
7
Revision history
Table 7-1. Revision history
Revision No.
Description
Date
1.0
Initial Release
Oct.19, 2021
1. Modify description in Debug mode.
2. Modify description in Embedded memory.
3. Add EMI parameter in Table 4-9. EMI characteristics(1).
1.1
4. Modify table 4-17 and table 4-19
Apr.13 2022
5. Modify power consumption value in Table 4-7. Power
consumption characteristics(2)(3)
6. Update QFN32 recommended footprint figure.
94
GD32L233xx Datasheet
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