GD32E103R8T6

GigaDevice Semiconductor Inc. GD32E103xx Arm® Cortex®-M4 32-bit MCU Datasheet GD32E103xx Datasheet Table of Contents Table of Contents ........................................................................................................... 1 List of Figures ................................................................................................................ 4 List of Tables .................................................................................................................. 5 1. General description ................................................................................................. 7 2. Device overview ....................................................................................................... 8 2.1. Device information ...................................................................................................... 8 2.2. Block diagram .............................................................................................................. 9 2.3. Pinouts and pin assignment ..................................................................................... 10 2.4. Memory map .............................................................................................................. 12 2.5. Clock tree ................................................................................................................... 16 2.6. Pin definitions ............................................................................................................ 16 2.6.1. GD32E103Vx LQFP100 pin definitions ................................................................................ 17 2.6.2. GD32E103Rx LQFP64 pin definitions .................................................................................. 23 2.6.3. GD32E103Cx LQFP48 pin definitions .................................................................................. 27 2.6.4. GD32E103Tx QFN36 pin definitions .................................................................................... 30 3. Functional description .......................................................................................... 33 3.1. Arm® Cortex®-M4 core ............................................................................................... 33 3.2. On-chip memory ........................................................................................................ 33 3.3. Clock, reset and supply management ...................................................................... 34 3.4. Boot modes ................................................................................................................ 34 3.5. Power saving modes ................................................................................................. 35 3.6. Analog to digital converter (ADC) ............................................................................ 35 3.7. Digital to analog converter (DAC) ............................................................................. 36 3.8. DMA ............................................................................................................................ 36 3.9. General-purpose inputs/outputs (GPIOs) ................................................................ 36 3.10. Timers and PWM generation ................................................................................. 37 3.11. Real time clock (RTC) ............................................................................................ 38 3.12. Inter-integrated circuit (I2C) .................................................................................. 38 3.13. Serial peripheral interface (SPI) ............................................................................ 38 3.14. Universal synchronous asynchronous receiver transmitter (USART) ............... 39 1 GD32E103xx Datasheet 3.15. Inter-IC sound (I2S) ................................................................................................ 39 3.16. Universal serial bus full-speed interface (USBFS) ............................................... 39 3.17. External memory controller (EXMC) ..................................................................... 40 3.18. Debug mode ........................................................................................................... 40 3.19. Package and operation temperature ..................................................................... 40 4. Electrical characteristics ....................................................................................... 41 4.1. Absolute maximum ratings ....................................................................................... 41 4.2. Operating conditions characteristics ....................................................................... 41 4.3. Power consumption .................................................................................................. 43 4.4. EMC characteristics .................................................................................................. 50 4.5. Power supply supervisor characteristics ................................................................ 50 4.6. Electrical sensitivity .................................................................................................. 51 4.7. External clock characteristics .................................................................................. 53 4.8. Internal clock characteristics ................................................................................... 55 4.9. PLL characteristics.................................................................................................... 56 4.10. Memory characteristics ......................................................................................... 57 4.11. NRST pin characteristics ....................................................................................... 57 4.12. GPIO characteristics .............................................................................................. 58 4.13. ADC characteristics ............................................................................................... 60 4.14. Temperature sensor characteristics ..................................................................... 61 4.15. DAC characteristics ............................................................................................... 61 4.16. I2C characteristics ................................................................................................. 63 4.17. SPI characteristics ................................................................................................. 64 4.18. I2S characteristics.................................................................................................. 65 4.19. USART characteristics ........................................................................................... 67 4.20. USBFS characteristics ........................................................................................... 67 4.21. EXMC characteristics............................................................................................. 68 4.22. TIMER characteristics ............................................................................................ 72 4.23. WDGT characteristics ............................................................................................ 72 4.24. Parameter conditions............................................................................................. 73 5. Package information.............................................................................................. 74 5.1. LQFP100 package outline dimensions..................................................................... 74 2 GD32E103xx Datasheet 5.2. LQFP64 package outline dimensions....................................................................... 76 5.3. LQFP48 package outline dimensions....................................................................... 78 5.4. QFN36 package outline dimensions ........................................................................ 80 5.5. Thermal characteristics ............................................................................................ 82 6. Ordering information ............................................................................................. 84 7. Revision history ..................................................................................................... 85 3 GD32E103xx Datasheet List of Figures Figure 2-1.GD32E103xx block diagram ..................................................................................................... 9 Figure 2-2. GD32E103Vx LQFP100 pinouts ............................................................................................ 10 Figure 2-3. GD32E103Rx LQFP64 pinouts ............................................................................................... 11 Figure 2-4. GD32E103Cx LQFP48 pinouts ............................................................................................... 11 Figure 2-5. GD32E103Tx QFN36 pinouts ................................................................................................. 12 Figure 2-6. GD32E103xx clock tree .......................................................................................................... 16 Figure 4-1. Recommended power supply decoupling capacitors (1)(2) .................................................. 41 Figure 4-2. Typical supply current consumption in Run mode ............................................................ 48 Figure 4-3. Typical supply current consumption in Sleep mode .......................................................... 48 Figure 4-4. Recommended external NRST pin circuit............................................................................ 58 Figure 4-5. I/O port AC characteristics definition................................................................................... 59 Figure 4-6. I2C bus timing diagram.......................................................................................................... 64 Figure 4-7. SPI timing diagram - master mode ....................................................................................... 65 Figure 4-8. SPI timing diagram - slave mode .......................................................................................... 65 Figure 4-9. I2S timing diagram - master mode ....................................................................................... 66 Figure 4-10. I2S timing diagram - slave mode ........................................................................................ 67 Figure 4-11. USBFS timings: definition of data signal rise and fall time ............................................. 68 Figure 5-1. LQFP100 package outline ..................................................................................................... 74 Figure 5-2. LQFP100 recommended footprint ........................................................................................ 75 Figure 5-3. LQFP64 package outline ....................................................................................................... 76 Figure 5-4. LQFP64 recommended footprint .......................................................................................... 77 Figure 5-5. LQFP48 package outline ....................................................................................................... 78 Figure 5-6. LQFP48 recommended footprint .......................................................................................... 79 Figure 5-7. QFN36 package outline ......................................................................................................... 80 Figure 5-8. QFN36 recommended footprint ............................................................................................ 81 4 GD32E103xx Datasheet List of Tables Table 2-1. GD32E103xx devices features and peripheral list .................................................................. 8 Table 2-2. GD32E103xx memory map ...................................................................................................... 12 Table 2-3. GD32E103Vx LQFP100 pin definitions ................................................................................... 17 Table 2-4. GD32E103Rx LQFP64 pin definitions .................................................................................... 23 Table 2-5. GD32E103Cx LQFP48 pin definitions .................................................................................... 27 Table 2-6. GD32E103Tx LQFP36 pin definitions ..................................................................................... 30 Table 4-1. Absolute maximum ratings(1)(4) ............................................................................................... 41 Table 4-2. DC operating conditions ......................................................................................................... 41 Table 4-3. Clock frequency(1) .................................................................................................................... 42 Table 4-4. Operating conditions at Power up/ Power down(1) ............................................................... 42 Table 4-5. Start-up timings of Operating conditions (1)(2)(3) ..................................................................... 42 Table 4-6. Power saving mode wakeup timings characteristics(1)(2) ..................................................... 42 Table 4-7. Power consumption characteristics(2)(3)(4)(5) .......................................................................... 43 Table 4-8. Peripheral current consumption characteristics(1) ............................................................... 48 Table 4-9. EMS characteristics(1) .............................................................................................................. 50 Table 4-10. EMI characteristics(1) ............................................................................................................. 50 Table 4-11. Power supply supervisor characteristics............................................................................ 50 Table 4-12. ESD characteristics(1) ............................................................................................................ 51 Table 4-13. Static latch-up characteristics(1) ........................................................................................... 53 Table 4-14. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics . 53 Table 4-15. High speed external clock characteristics (HXTAL in bypass mode) .............................. 53 Table 4-16. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics .. 54 Table 4-17.Low speed external user clock characteristics (LXTAL in bypass mode)........................ 54 Table 4-18. High speed internal clock (IRC8M) characteristics ............................................................ 55 Table 4-19. Low speed internal clock (IRC40K) characteristics ........................................................... 55 Table 4-20. High speed internal clock (IRC48M) characteristics .......................................................... 56 Table 4-21. PLL characteristics ................................................................................................................ 56 Table 4-22. PLL1/2 characteristics ........................................................................................................... 56 Table 4-23. Flash memory characteristics .............................................................................................. 57 Table 4-24. NRST pin characteristics ...................................................................................................... 57 Table 4-25. I/O port DC characteristics(1)(3) .............................................................................................. 58 Table 4-26. I/O port AC characteristics(1)(2) .............................................................................................. 59 Table 4-27. ADC characteristics ............................................................................................................... 60 Table 4-28. ADC RAIN max for fADC = 42 MHz ............................................................................................ 60 Table 4-29. ADC dynamic accuracy at fADC = 14 MHz(1) .......................................................................... 61 Table 4-30. ADC dynamic accuracy at fADC = 42 MHz(1) .......................................................................... 61 Table 4-31. ADC static accuracy at fADC = 42 MHz(1) ............................................................................... 61 Table 4-32. Temperature sensor characteristics(1) ................................................................................. 61 Table 4-33. DAC characteristics ............................................................................................................... 61 Table 4-34. I2C characteristics(1)(2) ........................................................................................................... 63 5 GD32E103xx Datasheet Table 4-35. Standard SPI characteristics Table 4-36. I2S characteristics (1)(2) (1) ............................................................................................. 64 ........................................................................................................... 65 Table 4-37. USART characteristics(1) ....................................................................................................... 67 Table 4-38. USBFS start up time .............................................................................................................. 67 Table 4-39. USBFS DC electrical characteristics ................................................................................... 67 Table 4-40. USBFS electrical characteristics(1) ....................................................................................... 68 Table 4-41. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)(3) ......................... 68 Table 4-42. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)(3) ........................ 69 Table 4-43. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)(3) ............................................ 69 Table 4-44. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)(3)............................................ 70 Table 4-45. Synchronous multiplexed PSRAM/NOR read timings(1)(2)(3)............................................... 70 Table 4-46. Synchronous multiplexed PSRAM write timings(1)(2)(3) ....................................................... 70 Table 4-47. Synchronous non-multiplexed PSRAM/NOR read timings(1)(2)(3) ....................................... 71 Table 4-48. Synchronous non-multiplexed PSRAM write timings(1)(2)(3) ............................................... 71 Table 4-49. TIMER characteristics(1) ........................................................................................................ 72 Table 4-50. FWDGT min/max timeout period at 40 kHz (IRC40K)(1) ...................................................... 72 Table 4-51. WWDGT min-max timeout value at 60 MHz (fPCLK1)(1).......................................................... 72 Table 5-1. LQFP100 package dimensions ............................................................................................... 74 Table 5-2. LQFP64 package dimensions ................................................................................................. 76 Table 5-3. LQFP48 package dimensions ................................................................................................. 78 Table 5-4. QFN36 package dimensions ................................................................................................... 80 Table 5-5. Package thermal characteristics(1) ......................................................................................... 82 Table 6-1. Part ordering code for GD32E103xx devices ........................................................................ 84 Table 7-1. Revision history ....................................................................................................................... 85 6 GD32E103xx Datasheet 1. General description The GD32E103xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the Arm® Cortex®-M4 RISC core with best costperformance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides powerful trace technology for enhanced application security and advanced debug support. The GD32E103xx device incorporates the Arm® Cortex®-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and 32 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit 3 MSPS ADCs, two 12-bit DACs, up to ten general 16-bit timers, two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two I2Ss and an USBFS. The device operates from 1.71 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make GD32E103xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, motor drives, consumer and handheld equipment, human machine interface, security and alarm systems, POS, automotive navigation, IoT and so on. 7 GD32E103xx Datasheet 2. Device overview 2.1. Device information Table 2-1. GD32E103xx devices features and peripheral list GD32E103xx Timers Part Number T8 TB C8 CB R8 RB V8 VB Flash (KB) 64 128 64 128 64 128 64 128 SRAM (KB) 20 32 20 32 20 32 20 32 General timer(16- 4 4 10 10 10 10 10 10 bit) (1-4) (1-4) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) Advanced 1 1 1 1 2 2 2 2 timer(16-bit) (0) (0) (0) (0) (0,7) (0,7) (0,7) (0,7) SysTick 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) Watchdog 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 Basic timer(16-bit) Connectivity USART UART 2 3 3 3 3 3 3 (0-1) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) 0 0 0 0 2 2 2 2 (3-4) (3-4) (3-4) (3-4) 1 1 2 2 2 2 2 2 (0) (0) (0-1) (0-1) (0-1) (0-1) (0-1) (0-1) 1/0 1/0 3/2 3/2 3/2 3/2 3/2 3/2 (0/-) (0/-) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) 1 1 1 1 1 1 1 1 GPIO 26 26 37 37 51 51 80 80 EXMC 0 0 0 0 0 0 1 1 EXTI 16 16 16 16 16 16 16 16 Units 2 2 2 2 2 2 2 2 Channels 10 10 10 10 16 16 16 16 2 2 2 2 2 2 2 2 I2C SPI/I2S USBFS ADC 2 (0-1) DAC Package QFN36 LQFP48 LQFP64 LQFP100 8 GD32E103xx Datasheet 2.2. Block diagram Figure 2-1.GD32E103xx block diagram SW/JTAG TPIU NVIC ICode DCode System ARM Cortex-M4 Processor Fmax:120MHz POR/ PDR Flash Memory Controller Ibus Flash Memory PLL F max : 120MHz Dbus FMC Master Master Slave Slave EXMC CRC LDO 1.2V RCU AHB Peripherals Slave AHB Matrix DMA 12 chs USBFS SRAM Controller AHB to APB Bridge2 IRC 8MHz SRAM HXTAL 4-32MHz AHB to APB Bridge1 Slave LVD Interrput request Powered By VDDA USART0 Slave 12-bit SAR ADC Slave SPI0 WWDGT ADC0~1 TIMER1~3 EXTI SPI1~2 GPIOA USART1~2 GPIOB I2C0 Powered By V DDA GPIOE APB1: Fmax = 60MHZ GPIOD APB2: Fmax = 120MHz GPIOC I2C1 FWDGT RTC DAC TIMER4~6 TIMER0 UART3~4 TIMER7 TIMER 11~13 TIMER8~10 CTC 9 GD32E103xx Datasheet 2.3. Pinouts and pin assignment Figure 2-2. GD32E103Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS_2 3 73 NC PE5 PE6 4 72 PA13 5 71 PA12 VBAT 6 PC13-TAMPER-RTC PC14-OSC32IN 7 70 69 PA10 8 68 PA9 PC15-OSC32OUT 9 67 PA8 VSS_5 10 66 PC9 VDD_5 11 65 PC8 64 PC7 63 PC6 14 62 PD15 OSCIN 12 GigaDevice GD32E103Vx LQFP100 VDD_2 PA11 OSCOUT NRST PC0 13 15 61 PD14 PC1 16 60 PD13 PC2 PC3 17 59 PD12 18 58 PD11 VSSA 19 57 PD10 VREFVREF+ 20 56 PD9 21 55 PD8 VDDA 22 54 PB15 PA0-WKUP 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS_1 VDD_1 PB11 PB10 PE15 PE14 PE13 PE11 PE12 PE10 PE9 PE8 PE7 PB2 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VDD_4 PA3 VSS_4 10 GD32E103xx Datasheet Figure 2-3. GD32E103Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PD2 PC12 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 VDD_2 PC13-TAMPER-RTC 2 47 VSS_2 PC14-OSC32IN 3 46 PA13 PC15-OSC32OUT PD0-OSCIN 4 45 PA12 5 44 PA11 PD1-OSCOUT 6 43 PA10 NRST PC0 7 42 PA9 PC1 9 PC2 PC3 VSSA GigaDevice GD32E103Rx LQFP64 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0-WKUP 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB3 VSS_1 PB4 VDD_1 PB2 PB11 PB1 PB10 PB0 PB5 PC5 PC4 PA7 PA6 PA5 PA4 VDD_4 PA3 VSS_4 Figure 2-4. GD32E103Cx LQFP48 pinouts PA14 PA15 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 48 47 46 45 44 43 42 41 40 39 38 37 VBAT 1 36 VDD_2 PC13-TAMPER-RTC 2 35 VSS_2 PC14-OSC32IN 3 34 PA13 PC15-OSC32OUT PD0-OSCIN 4 33 PA12 5 32 PA11 PD1-OSCOUT NRST VSSA 6 31 PA10 30 PA9 8 29 VDDA 9 28 PA8 PB15 PA0-WKUP 10 27 PB14 PA1 PA2 11 26 PB13 25 PB12 GigaDevice GD32E103Cx LQFP48 7 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS_1 VDD_1 PB11 PB10 PB2 PB1 PA7 PB0 PA6 PA5 PA4 PA3 11 GD32E103xx Datasheet Figure 2-5. GD32E103Tx QFN36 pinouts 36 35 34 33 32 31 30 29 28 1 27 2 26 VDD_2 3 25 PA13 24 5 GigaDevice GD32E103Tx 23 QFN36 6 22 7 21 PA12 4 8 20 9 19 10 11 12 13 14 15 16 17 18 VSS_2 PA11 PA10 PA9 PA8 VDD_1 VSS_1 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 2.4. PA14 PA2 PA15 PA1 PB3 PB4 PA0-WKUP PB5 VDDA PB6 PD0-OSCIN PD1-OSCOUT NRST VSSA PB7 BOOT0 VSS_3 VDD_3 Memory map Table 2-2. GD32E103xx memory map Pre-defined regions Bus External device External RAM AHB3 Address Peripherals 0xA000 0000 - 0xA000 0FFF EXMC - SWREG 0x9000 0000 - 0x9FFF FFFF Reserved 0x7000 0000 - 0x8FFF FFFF Reserved 0x6000 0000 - 0x63FF FFFF Peripheral AHB1 EXMC NOR/PSRAM/SRAM 0x5000 0000 - 0x5003 FFFF USBFS 0x4008 0000 - 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF Reserved 0x4002 BC00 - 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF Reserved 0x4002 6000 - 0x4002 63FF Reserved 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Reserved 12 GD32E103xx Datasheet Pre-defined regions Bus APB2 Address Peripherals 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF Reserved 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1C00 - 0x4002 1FFF Reserved 0x4002 1800 - 0x4002 1BFF Reserved 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF RCU 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 0x4001 8000 - 0x4001 83FF Reserved 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF Reserved 0x4001 6C00 - 0x4001 6FFF Reserved 0x4001 6800 - 0x4001 6BFF Reserved 0x4001 5C00 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF Reserved 0x4001 5400 - 0x4001 57FF TIMER10 0x4001 5000 - 0x4001 53FF TIMER9 0x4001 4C00 - 0x4001 4FFF TIMER8 0x4001 4800 - 0x4001 4BFF Reserved 0x4001 4400 - 0x4001 47FF Reserved 0x4001 4000 - 0x4001 43FF Reserved 0x4001 3C00 - 0x4001 3FFF Reserved 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF TIMER7 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF TIMER0 0x4001 2800 - 0x4001 2BFF ADC1 0x4001 2400 - 0x4001 27FF ADC0 0x4001 2000 - 0x4001 23FF Reserved 13 GD32E103xx Datasheet Pre-defined regions Bus APB1 Address Peripherals 0x4001 1C00 - 0x4001 1FFF Reserved 0x4001 1800 - 0x4001 1BFF GPIOE 0x4001 1400 - 0x4001 17FF GPIOD 0x4001 1000 - 0x4001 13FF GPIOC 0x4001 0C00 - 0x4001 0FFF GPIOB 0x4001 0800 - 0x4001 0BFF GPIOA 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF CTC 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PMU 0x4000 6C00 - 0x4000 6FFF BKP 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF Reserved 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF Reserved 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF UART3 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1C00 - 0x4000 1FFF TIMER12 0x4000 1800 - 0x4000 1BFF TIMER11 14 GD32E103xx Datasheet Pre-defined regions SRAM Bus AHB Address Peripherals 0x4000 1400 - 0x4000 17FF TIMER6 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF Reserved 0x2003 0000 - 0x2005 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2001 C000 - 0x2001 FFFF 0x2001 8000 - 0x2001 BFFF 0x2000 5000 - 0x2001 7FFF SRAM 0x2000 0000 - 0x2000 4FFF 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF F000 - 0x1FFF F7FF 0x1FFF C010 - 0x1FFF EFFF 0x1FFF C000 - 0x1FFF C00F Boot loader 0x1FFF B000 - 0x1FFF BFFF Code AHB 0x1FFF 7A10 - 0x1FFF AFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 0000 - 0x1FFF 77FF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Reserved 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF Reserved 0x083C 0000 - 0x0FFF FFFF Reserved 0x0830 0000 - 0x083B FFFF Reserved 0x0810 0000 - 0x082F FFFF 0x0802 0000 - 0x080F FFFF Main Flash 0x0800 0000 - 0x0801 FFFF 0x0030 0000 - 0x07FF FFFF Reserved 0x0010 0000 - 0x002F FFFF 0x0002 0000 - 0x000F FFFF Aliased to Main Flash or Boot loader 0x0000 0000 - 0x0001 FFFF 15 GD32E103xx Datasheet 2.5. Clock tree Figure 2-6. GD32E103xx clock tree CTC CK_IRC48M CK_CTC 48 MHz IRC48M 48 MHz CK48MSEL USBFS Prescaler 1,1.5,2,2.5 3,3.5,4 1 SCS[1:0] CK_IRC8M 8 MHz IRC8M 0 1 ×2,3,4 …,31 PLL CK_PLL PLLPRESEL 1 4-32 MHz HXTAL 0 PLLSEL PREDV0 0 1 CK_USBFS 0 (to USBFS) 00 /2 CK_IRC48M 1 PLLMF /1,2,3… 15,16 AHB Prescaler ÷1,2...512 CK_SYS 120 MHz max 10 CK_AHB 120 MHz max CK_EXMC EXMC enable (by hardware) (to EXMC) HCLK 01 AHB enable (to AHB bus,Cortex-M4,SRAM,DMA,FMC) CK_CST Clock Monitor ÷8 (to Cortex-M4 SysTick) FCLK PREDV0SEL (free running clock) CK_HXTAL APB1 Prescaler ÷1,2,4,8,16 CK_APB1 PCLK1 to APB1 peripherals 60 MHz max Peripheral enable ×8,9,10…, 14,16,20 PLL1 TIMER1,2,3,4,5,6, 11,12,13 if(APB1 prescale =1)x1 else x 2 CK_PLL1 ×8,9,10…, 14,16,20 PLL2 PREDV1 0 CK_PLL2 x2 CK_I2S 1 APB2 Prescaler ÷1,2,4,8,16 CK_RTC 01 (to RTC) 10 RTCSRC[1:0] 40 KHz IRC40K CK_OUT0 TIMER0,7,8,9,10 if(APB2 prescale =1)x1 else x 2 ADC Prescaler ÷2,4,6,8,12,1 6 CK_FWDGT (to FWDGT) 00xx 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 CK_APB2 PCLK2 to APB2 peripherals 120 MHz max Peripheral enable I2S1/2SEL PLL2MF 11 32.768 KHz LXTAL to TIMER1,2,3,4, 5,6,11,12,13 PLL1MF /1,2,3… 15,16 /128 CK_TIMERx TIMERx enable ADC Prescaler ÷3,5,7,9 CK_TIMERx TIMERx enable to TIMER0,7,8,9,10 ADCPSC[3] 0 1 CK_ADCx to ADC0,1 40 MHz max NO CLK CK_SYS CK_IRC8M CK_HXTAL /2 CK_PLL CK_PLL1 /2 CK_PLL2 CK_HXTAL CK_PLL2 CK_IRC48M /8 CK_IRC48M CKOUT0SEL[3:0] Legend: HXTAL: 4 to 32 MHz High Speed crystal oscillator LXTAL: 32,768 Hz Low Speed crystal oscillator IRC8M: Internal 8 MHz RC oscillator IRC40K: Internal 40 KHz RC oscillator IRC48M: Internal 48 MHz RC oscillator 2.6. Pin definitions Notes: For GD32E103Rx LQFP64, GD32E103Cx LQFP48 and GD32E103Tx QFN36, VREF- and VREF+ are internally connected to VSSA and VDDA respectively. 16 GD32E103xx Datasheet 2.6.1. GD32E103Vx LQFP100 pin definitions Table 2-3. GD32E103Vx LQFP100 pin definitions Pin Name Pins Pin I/O Type(1) Level(2) PE2 1 I/O 5VT PE3 2 I/O 5VT PE4 3 I/O 5VT Functions description Default: PE2 Alternate: EXMC_A23 Default: PE3 Alternate: EXMC_A19 Default: PE4 Alternate: EXMC_A20 Default: PE5 PE5 4 I/O 5VT Alternate: EXMC_A21 Remap: TIMER8_CH0 Default: PE6 PE6 5 I/O 5VT Alternate: EXMC_A22 Remap: TIMER8_CH1 VBAT 6 P - 7 I/O - 8 I/O - 9 I/O - VSS_5 10 P - Default: VSS_5 VDD_5 11 P - Default: VDD_5 OSCIN 12 I - OSCOUT 13 O - NRST 14 I/O - PC0 15 I/O - PC1 16 I/O - PC2 17 I/O - PC3 18 I/O - VSSA 19 P - Default: VSSA VREF- 20 P - Default: VREF- PC13TAMPERRTC PC14OSC32IN PC15OSC32OU T Default: VBAT Default: PC13 Alternate: RTC_TAMPER Default: PC14 Alternate: OSC32IN Default: PC15 Alternate: OSC32OUT Default: OSCIN Remap: PD0 Default: OSCOUT Remap:PD1 Default: NRST Default: PC0 Alternate: ADC01_IN10 Default: PC1 Alternate: ADC01_IN11 Default: PC2 Alternate: ADC01_IN12 Default: PC3 Alternate: ADC01_IN13 17 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description VREF+ 21 P - Default: VREF+ VDDA 22 P - Default: VDDA Default: PA0 PA0-WKUP 23 I/O - Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI Default: PA1 PA1 24 I/O - Alternate: USART1_RTS/USART1_DE, ADC01_IN1, TIMER4_CH1, TIMER1_CH1 Default: PA2 PA2 25 I/O - Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2, TIMER8_CH0, TIMER1_CH2, SPI0_IO2 Default: PA3 PA3 26 I/O - Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3, TIMER1_CH3, TIMER8_CH1, SPI0_IO3 VSS_4 27 P - Default: VSS_4 VDD_4 28 P - Default: VDD_4 Default: PA4 PA4 29 I/O - Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4 Remap: SPI2_NSS, I2S2_WS PA5 30 I/O - Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 31 I/O - Alternate: SPI0_MISO, TIMER7_BRKIN, ADC01_IN6, TIMER2_CH0, TIMER12_CH0 Remap: TIMER0_BRKIN Default: PA7 PA7 32 I/O - Alternate: SPI0_MOSI, TIMER7_CH0_ON, ADC01_IN7, TIMER2_CH1, TIMER13_CH0 Remap: TIMER0_CH0_ON PC4 33 I/O - PC5 34 I/O - Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 PB0 35 I/O - Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON Remap: TIMER0_CH1_ON Default: PB1 PB1 36 I/O - Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON Remap: TIMER0_CH2_ON PB2 37 I/O 5VT Default: PB2, BOOT1 18 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PE7 PE7 38 I/O 5VT Alternate: EXMC_D4 Remap: TIMER0_ETI Default: PE8 PE8 39 I/O 5VT Alternate: EXMC_D5 Remap: TIMER0_CH0_ON Default: PE9 PE9 40 I/O 5VT Alternate: EXMC_D6 Remap: TIMER0_CH0 Default: PE10 PE10 41 I/O 5VT Alternate: EXMC_D7 Remap: TIMER0_CH1_ON Default: PE11 PE11 42 I/O 5VT Alternate: EXMC_D8 Remap: TIMER0_CH1 Default: PE12 PE12 43 I/O 5VT Alternate: EXMC_D9 Remap: TIMER0_CH2_ON Default: PE13 PE13 44 I/O 5VT Alternate: EXMC_D10 Remap: TIMER0_CH2 Default: PE14 PE14 45 I/O 5VT Alternate: EXMC_D11 Remap: TIMER0_CH3 Default: PE15 PE15 46 I/O 5VT Alternate: EXMC_D12 Remap: TIMER0_BRKIN Default: PB10 PB10 47 I/O 5VT Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 Default: PB11 PB11 48 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 VSS_1 49 P - Default: VSS_1 VDD_1 50 P - Default: VDD_1 Default: PB12 PB12 51 I/O 5VT Alternate: SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN Default: PB13 PB13 52 I/O 5VT Alternate: SPI1_SCK, I2S1_CK, USART2_CTS, TIMER0_CH0_ON, I2C1_TXFRAME 19 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PB14 PB14 53 I/O 5VT Alternate: SPI1_MISO, USART2_RTS/USART2_DE, TIMER0_CH1_ON, TIMER11_CH0 Default: PB15 PB15 54 I/O 5VT Alternate: SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON, TIMER11_CH1 Default: PD8 PD8 55 I/O 5VT Alternate: EXMC_D13 Remap: USART2_TX Default: PD9 PD9 56 I/O 5VT Alternate: EXMC_D14 Remap: USART2_RX Default: PD10 PD10 57 I/O 5VT Alternate: EXMC_D15 Remap: USART2_CK Default: PD11 PD11 58 I/O 5VT Alternate: EXMC_A16/EXMC_CLE Remap: USART2_CTS Default: PD12 PD12 59 I/O 5VT Alternate: EXMC_A17/EXMC_ALE Remap: TIMER3_CH0, USART2_RTS/USART2_DE Default: PD13 PD13 60 I/O 5VT Alternate: EXMC_A18 Remap: TIMER3_CH1 Default: PD14 PD14 61 I/O 5VT Alternate: EXMC_D0 Remap: TIMER3_CH2 Default: PD15 PD15 62 I/O 5VT Alternate: EXMC_D1 Remap: TIMER3_CH3, CTC_SYNC Default: PC6 PC6 63 I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0 Default: PC7 PC7 64 I/O 5VT Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1 Default: PC8 PC8 65 I/O 5VT Alternate: TIMER7_CH2 Remap: TIMER2_CH2 20 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PC9 PC9 66 I/O 5VT Alternate: TIMER7_CH3 Remap: TIMER2_CH3 Default: PA8 PA8 67 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF, CTC_SYNC PA9 68 I/O 5VT PA10 69 I/O 5VT PA11 70 I/O 5VT Default: PA9 Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS Default: PA10 Alternate: USART0_RX, TIMER0_CH2, USBFS_ID, V1REF Default: PA11 Alternate: USART0_CTS, USBFS_DM, TIMER0_CH3 Default: PA12 PA12 71 I/O 5VT Alternate: USART0_RTS/USART0_DE, USBFS_DP, TIMER0_ETI Default: JTMS, SWDIO PA13 72 I/O 5VT NC 73 - - - VSS_2 74 P - Default: VSS_2 VDD_2 75 P - Default: VDD_2 PA14 76 I/O 5VT Remap: PA13 Default: JTCK, SWCLK Remap:PA14 Default: JTDI PA15 77 I/O 5VT Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: PC10 PC10 78 I/O 5VT Alternate: UART3_TX Remap: USART2_TX, SPI2_SCK, I2S2_CK Default: PC11 PC11 79 I/O 5VT Alternate: UART3_RX Remap: USART2_RX, SPI2_MISO Default: PC12 PC12 80 I/O 5VT Alternate: UART4_TX Remap: USART2_CK, SPI2_MOSI, I2S2_SD Default: PD0 PD0 81 I/O 5VT Alternate: EXMC_D2 Remap: OSCIN Default: PD1 PD1 82 I/O 5VT Alternate: EXMC_D3 Remap: OSCOUT 21 GD32E103xx Datasheet Pin Name Pins PD2 83 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PD2 Alternate: TIMER2_ETI, UART4_RX Default: PD3 PD3 84 I/O 5VT Alternate: EXMC_CLK Remap: USART1_CTS Default: PD4 PD4 85 I/O 5VT Alternate: EXMC_NOE Remap: USART1_RTS/USART1_DE Default: PD5 PD5 86 I/O 5VT Alternate: EXMC_NWE Remap: USART1_TX Default: PD6 PD6 87 I/O 5VT Alternate: EXMC_NWAIT Remap: USART1_RX Default: PD7 PD7 88 I/O 5VT Alternate: EXMC_NE0 Remap: USART1_CK Default: JTDO PB3 89 I/O 5VT Alternate: SPI2_SCK, I2S2_CK Remap: TIMER1_CH1, PB3, SPI0_SCK Default: NJTRST PB4 90 I/O 5VT Alternate: SPI2_MISO, I2C0_TXFRAME Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 91 I/O - Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 92 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, SPI0_IO2 Default: PB7 PB7 93 I/O 5VT Alternate: I2C0_SDA, TIMER3_CH1, EXMC_NL(NADV) Remap: USART0_RX, SPI0_IO3 BOOT0 94 I - Default: BOOT0 Default: PB8 PB8 95 I/O 5VT Alternate: TIMER3_CH2, TIMER9_CH0 Remap: I2C0_SCL Default: PB9 PB9 96 I/O 5VT Alternate: TIMER3_CH3, TIMER10_CH0 Remap: I2C0_SDA PE0 97 I/O 5VT Default:PE0 Alternate: TIMER3_ETI, EXMC_NBL0 22 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PE1 PE1 98 I/O 5VT VSS_3 99 P - Default: VSS_3 VDD_3 100 P - Default: VDD_3 Alternate: EXMC_NBL1 Notes: 2.6.2. 1. Type: I= input, O = output, P = power. 2. I/O Level: 5VT = 5V tolerant. 3. Functions are available in GD32E103xx devices. GD32E103Rx LQFP64 pin definitions Table 2-4. GD32E103Rx LQFP64 pin definitions Pin I/O Type(1) Level(2) 1 P - 2 I/O - 3 I/O - 4 I/O - 5 I - 6 O - NRST 7 I/O - PC0 8 I/O - PC1 9 I/O - PC2 10 I/O - PC3 11 I/O - VSSA 12 P - Default: VSSA VDDA 13 P - Default: VDDA Pin Name Pins VBAT PC13TAMPERRTC PC14OSC32IN PC15OSC32OUT PD0-OSCIN PD1OSCOUT Functions description Default: VBAT Default: PC13 Alternate: RTC_TAMPER Default: PC14 Alternate:OSC32IN Default: PC15 Alternate:OSC32OUT Default: OSCIN Remap: PD0(3) Default: OSCOUT Remap: PD1(3) Default: NRST Default: PC0 Alternate: ADC01_IN10 Default: PC1 Alternate: ADC01_IN11 Default: PC2 Alternate: ADC01_IN12 Default: PC3 Alternate: ADC01_IN13 Default: PA0 PA0-WKUP 14 I/O - Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI PA1 15 I/O - Default: PA1 23 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: USART1_RTS/USART1_DE, ADC01_IN1, TIMER4_CH1, TIMER1_CH1 Default: PA2 PA2 16 I/O - Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2, TIMER8_CH0, TIMER1_CH2, SPI0_IO2 Default: PA3 PA3 17 I/O - Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3, TIMER1_CH3, TIMER8_CH1, SPI0_IO3 VSS_4 18 P - Default: VSS_4 VDD_4 19 P - Default: VDD_4 Default: PA4 PA4 20 I/O - Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4 Remap: SPI2_NSS, I2S2_WS PA5 21 I/O - Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 22 I/O - Alternate: SPI0_MISO, TIMER7_BRKIN, ADC01_IN6, TIMER2_CH0, TIMER12_CH0 Remap: TIMER0_BRKIN Default: PA7 PA7 23 I/O - Alternate: SPI0_MOSI, TIMER7_CH0_ON, ADC01_IN7, TIMER2_CH1, TIMER13_CH0 Remap: TIMER0_CH0_ON PC4 24 I/O - PC5 25 I/O - Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 PB0 26 I/O - Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON Remap: TIMER0_CH1_ON Default: PB1 PB1 27 I/O - Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON Remap: TIMER0_CH2_ON PB2 28 I/O 5VT Default: PB2, BOOT1 Default: PB10 PB10 29 I/O 5VT Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 Default: PB11 PB11 30 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 24 GD32E103xx Datasheet Pin I/O Type(1) Level(2) 31 P - Default: VSS_1 32 P - Default: VDD_1 Pin Name Pins VSS_1 VDD_1 Functions description Default: PB12 PB12 33 I/O 5VT Alternate: SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN Default: PB13 PB13 34 I/O 5VT Alternate: SPI1_SCK, I2S1_CK, USART2_CTS, TIMER0_CH0_ON, I2C1_TXFRAME Default: PB14 PB14 35 I/O 5VT Alternate: SPI1_MISO, USART2_RTS/USART2_DE, TIMER0_CH1_ON, TIMER11_CH0 Default: PB15 PB15 36 I/O 5VT Alternate: SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON, TIMER11_CH1 Default: PC6 PC6 37 I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0 Default: PC7 PC7 38 I/O 5VT Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1 Default: PC8 PC8 39 I/O 5VT Alternate: TIMER7_CH2 Remap: TIMER2_CH2 Default: PC9 PC9 40 I/O 5VT Alternate: TIMER7_CH3 Remap: TIMER2_CH3 Default: PA8 PA8 41 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF, CTC_SYNC PA9 42 I/O 5VT PA10 43 I/O 5VT PA11 44 I/O 5VT Default: PA9 Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS Default: PA10 Alternate: USART0_RX, TIMER0_CH2, USBFS_ID, V1REF Default: PA11 Alternate: USART0_CTS, USBFS_DM, TIMER0_CH3 Default: PA12 PA12 45 I/O 5VT Alternate: USART0_RTS/USART0_DE, USBFS_DP, TIMER0_ETI PA13 46 I/O 5VT VSS_2 47 P - Default: JTMS, SWDIO Remap: PA13 Default: VSS_2 25 GD32E103xx Datasheet Pin I/O Type(1) Level(2) 48 P - 49 I/O 5VT Pin Name Pins VDD_2 PA14 Functions description Default: VDD_2 Default: JTCK, SWCLK Remap:PA14 Default: JTDI PA15 50 I/O 5VT Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, TIMER1_ETI, PA15, SPI0_NSS Default: PC10 PC10 51 I/O 5VT Alternate: UART3_TX Remap: USART2_TX, SPI2_SCK, I2S2_CK Default: PC11 PC11 52 I/O 5VT Alternate: UART3_RX Remap: USART2_RX, SPI2_MISO Default: PC12 PC12 53 I/O 5VT Alternate: UART4_TX Remap: USART2_CK, SPI2_MOSI, I2S2_SD PD2 54 I/O 5VT Default: PD2 Alternate: TIMER2_ETI, UART4_RX Default: JTDO PB3 55 I/O 5VT Alternate: SPI2_SCK, I2S2_CK Remap: TIMER1_CH1, PB3, SPI0_SCK Default: NJTRST PB4 56 I/O 5VT Alternate: SPI2_MISO, I2C0_TXFRAME Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 57 I/O - Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 58 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, SPI0_IO2 Default: PB7 PB7 59 I/O 5VT Alternate: I2C0_SDA, TIMER3_CH1 Remap: USART0_RX, SPI0_IO3 BOOT0 60 I - Default: BOOT0 Default: PB8 PB8 61 I/O 5VT Alternate: TIMER3_CH2, TIMER9_CH0 Remap: I2C0_SCL Default: PB9 PB9 62 I/O 5VT Alternate: TIMER3_CH3, TIMER10_CH0 Remap: I2C0_SDA VSS_3 63 P - Default: VSS_3 26 GD32E103xx Datasheet Pin Name Pins VDD_3 64 Pin I/O Type(1) Level(2) P - Functions description Default: VDD_3 Notes: 2.6.3. 1. Type: I= input, O = output, P = power. 2. I/O Level: 5VT = 5V tolerant. 3. PD0/PD1 cannot be used for EXTI in this package. GD32E103Cx LQFP48 pin definitions Table 2-5. GD32E103Cx LQFP48 pin definitions Pin I/O Type(1) Level(2) 1 P - 2 I/O - 3 I/O - 4 I/O - PD0-OSCIN 5 I - PD1-OSCOUT 6 O - NRST 7 I/O - Default: NRST VSSA 8 P - Default: VSSA VDDA 9 P - Default: VDDA Pin Name Pins VBAT PC13TAMPERRTC PC14OSC32IN PC15OSC32OUT Functions description Default: VBAT Default: PC13 Alternate: RTC_TAMPER Default: PC14 Alternate:OSC32IN Default: PC15 Alternate:OSC32OUT Default: OSCIN Remap: PD0(3) Default: OSCOUT Remap: PD1(3) Default: PA0 PA0-WKUP 10 I/O - Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0 Default: PA1 PA1 11 I/O - Alternate: USART1_RTS/USART1_DE, ADC01_IN1, TIMER4_CH1, TIMER1_CH1 Default: PA2 PA2 12 I/O - Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2, TIMER8_CH0, TIMER1_CH2, SPI0_IO2 Default: PA3 PA3 13 I/O - Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3, TIMER1_CH3, TIMER8_CH1, SPI0_IO3 Default: PA4 PA4 14 I/O - Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4 27 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Remap: SPI2_NSS, I2S2_WS PA5 15 I/O - Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 16 I/O - Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER12_CH0 Remap: TIMER0_BRKIN Default: PA7 PA7 17 I/O - Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER13_CH0 Remap: TIMER0_CH0_ON Default: PB0 PB0 18 I/O - Alternate: ADC01_IN8, TIMER2_CH2 Remap: TIMER0_CH1_ON Default: PB1 PB1 19 I/O - Alternate: ADC01_IN9, TIMER2_CH3 Remap: TIMER0_CH2_ON PB2 20 I/O 5VT Default: PB2, BOOT1 Default: PB10 PB10 21 I/O 5VT Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 Default: PB11 PB11 22 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 VSS_1 23 P - Default: VSS_1 VDD_1 24 P - Default: VDD_1 PB12 25 I/O 5VT Default: PB12 Alternate: SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN Default: PB13 PB13 26 I/O 5VT Alternate: SPI1_SCK, I2S1_CK, USART2_CTS, TIMER0_CH0_ON, I2C1_TXFRAME Default: PB14 PB14 27 I/O 5VT Alternate: SPI1_MISO, USART2_RTS/USART2_DE, TIMER0_CH1_ON, TIMER11_CH0 Default: PB15 PB15 28 I/O 5VT Alternate: SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON, TIMER11_CH1 Default: PA8 PA8 29 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF, CTC_SYNC 28 GD32E103xx Datasheet Pin Name Pins PA9 30 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PA9 Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS Default: PA10 PA10 31 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, USBFS_ID, V1REF PA11 32 I/O 5VT Default: PA11 Alternate: USART0_CTS, USBFS_DM, TIMER0_CH3 Default: PA12 PA12 33 I/O 5VT Alternate: USART0_RTS/USART0_DE, USBFS_DP, TIMER0_ETI Default: JTMS, SWDIO PA13 34 I/O 5VT VSS_2 35 P - Default: VSS_2 VDD_2 36 P - Default: VDD_2 PA14 37 I/O 5VT Remap: PA13 Default: JTCK, SWCLK Remap:PA14 Default: JTDI PA15 38 I/O 5VT Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, TIMER1_ETI, PA15, SPI0_NSS Default: JTDO PB3 39 I/O 5VT Alternate: SPI2_SCK, I2S2_CK Remap: TIMER1_CH1, PB3, SPI0_SCK Default: NJTRST PB4 40 I/O 5VT Alternate: SPI2_MISO, I2C0_TXFRAME Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 41 I/O - Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 42 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, SPI0_IO2 Default: PB7 PB7 43 I/O 5VT Alternate: I2C0_SDA, TIMER3_CH1 Remap: USART0_RX, SPI0_IO3 BOOT0 44 I - Default: BOOT0 Default: PB8 PB8 45 I/O 5VT Alternate: TIMER3_CH2, TIMER9_CH0 Remap: I2C0_SCL PB9 46 I/O 5VT Default: PB9 Alternate: TIMER3_CH3, TIMER10_CH0 29 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Remap: I2C0_SDA VSS_3 47 P - Default: VSS_3 VDD_3 48 P - Default: VDD_3 Notes: 2.6.4. 1. Type: I= input, O = output, P = power. 2. I/O Level: 5VT = 5V tolerant. 3. PD0/PD1 cannot be used for EXTI in this package. GD32E103Tx QFN36 pin definitions Table 2-6. GD32E103Tx LQFP36 pin definitions Pin I/O Type(1) Level(2) 2 I - PD1-OSCOUT 3 O - NRST 4 I/O - Default: NRST VSSA 5 P - Default: VSSA VDDA 6 P - Default: VDDA Pin Name Pins PD0-OSCIN Functions description Default: OSCIN Remap: PD0(3) Default: OSCOUT Remap: PD1(3) Default: PA0 PA0-WKUP 7 I/O - Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0 Default: PA1 PA1 8 I/O - Alternate: USART1_RTS/USART1_DE, ADC01_IN1, TIMER4_CH1, TIMER1_CH1 Default: PA2 PA2 9 I/O - Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2, TIMER1_CH2, SPI0_IO2 Default: PA3 PA3 10 I/O - Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3, TIMER1_CH3, SPI0_IO3 Default: PA4 PA4 11 I/O - Alternate: SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4 PA5 12 I/O - Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 13 I/O - Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0 Remap: TIMER0_BRKIN PA7 14 I/O - Default: PA7 30 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1 Remap: TIMER0_CH0_ON Default: PB0 PB0 15 I/O - Alternate: ADC01_IN8, TIMER2_CH2 Remap: TIMER0_CH1_ON Default: PB1 PB1 16 I/O - Alternate: ADC01_IN9, TIMER2_CH3 Remap: TIMER0_CH2_ON PB2 17 I/O 5VT Default: PB2, BOOT1 VSS_1 18 P - Default: VSS_1 VDD_1 19 P - Default: VDD_1 Default: PA8 PA8 20 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF, CTC_SYNC Default: PA9 PA9 21 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS Default: PA10 PA10 22 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, USBFS_ID, V1REF Default: PA11 PA11 23 I/O 5VT Alternate: USART0_CTS, USBFS_DM, TIMER0_CH3 Default: PA12 PA12 24 I/O 5VT Alternate: USART0_RTS/USART0_DE, USBFS_DP, TIMER0_ETI Default: JTMS, SWDIO PA13 25 I/O 5VT VSS_2 26 P - Default: VSS_2 VDD_2 27 P - Default: VDD_2 PA14 28 I/O 5VT Remap: PA13 Default: JTCK, SWCLK Remap:PA14 Default: JTDI PA15 29 I/O 5VT Remap: TIMER1_CH0, TIMER1_ETI, TIMER1_ETI, PA15, SPI0_NSS PB3 30 I/O 5VT Default: JTDO Remap: TIMER1_CH1, PB3, SPI0_SCK Default: NJTRST PB4 31 I/O 5VT Alternate: I2C0_TXFRAME Remap: TIMER2_CH0, PB4, SPI0_MISO PB5 32 I/O - Default: PB5 31 GD32E103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: I2C0_SMBA Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 33 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, SPI0_IO2 Default: PB7 PB7 34 I/O 5VT Alternate: I2C0_SDA, TIMER3_CH1 Remap: USART0_RX, SPI0_IO3 BOOT0 35 I - Default: BOOT0 VSS_3 36 P - Default: VSS_3 VDD_3 1 P - Default: VDD_3 Notes: 1. Type: I= input, O = output, P = power. 2. I/O Level: 5VT = 5V tolerant. 3. PD0/PD1 cannot be used for EXTI in this package. 32 GD32E103xx Datasheet 3. Functional description 3.1. Arm® Cortex®-M4 core The Arm® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit Arm® Cortex®-M4 processor core Up to 120 MHz operation frequency Single-cycle multiplication and hardware divider Floating Point Unit (FPU) Integrated DSP instructions Integrated Nested Vectored Interrupt Controller (NVIC) 24-bit SysTick timer The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4: Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) Nested Vectored Interrupt Controller (NVIC) Flash Patch and Breakpoint (FPB) Data Watchpoint and Trace (DWT) Instrument Trace Macrocell (ITM) Serial Wire JTAG Debug Port (SWJ-DP) Trace Port Interface Unit (TPIU) 3.2. On-chip memory Up to 128 Kbytes of Flash memory Up to 32 KB of SRAM The Arm® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash at most is available for storing programs and data. Table 2-2. GD32E103xx memory map shows the memory of the GD32E103xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions. 33 GD32E103xx Datasheet 3.3. Clock, reset and supply management Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator Internal 48 MHz RC oscillator Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator 1.71 to 3.6 V application supply and I/Os Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 120MHz. The maximum frequency of the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz. See Figure 2-6. GD32E103xx clock tree for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 1.66V/down to 1.62V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes: VDD range: 1.71 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VDDA range: 1.71 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT range: 1.71 to 3.6 V, power supply for RTC, external clock 32.768 KHz oscillator and backup registers (through power switch) when VDD is not present. 3.4. Boot modes At startup, boot pins are used to select one of three boot options: Boot from main flash memory (default) Boot from system memory Boot from on-chip SRAM In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10). 34 GD32E103xx Datasheet 3.5. Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption. Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system. Deep-sleep mode In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, IRC48M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock. Standby mode In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, IRC48M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin. 3.6. Analog to digital converter (ADC) 12-bit SAR ADC's conversion rate is up to 3 MSPS 12-bit, 10-bit, 8-bit or 6-bit configurable resolution Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit Input voltage range: VREF- to VREF+ Temperature sensor Up to two 12-bit 3 MSPS multi-channel ADCs are integrated in the device. It has a total of 18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT, VREFINT = 1.2V). The input voltage range is from VREF- to VREF+. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general level 0 timers (TIMERx, x=1, 2, 3) and the advanced timers (TIMER0 and TIMER7) with internal connection. The 35 GD32E103xx Datasheet temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 3.7. Digital to analog converter (DAC) 12-bit DAC with independent output channels 8-bit or 12-bit mode in conjunction with the DMA controller The 12-bit buffered DAC is used to generate variable analog outputs. The DAC channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+. 3.8. DMA 7 channel DMA0 controller and 5 channel DMA1 controller Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory. Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9. General-purpose inputs/outputs (GPIOs) Up to 80 fast GPIOs, all mappable on 16 external interrupt lines Analog input/output configurable Alternate function input/output configurable There are up to 80 general purpose I/O pins (GPIO) in GD32E103xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15 and PE0 ~ PE15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 36 GD32E103xx Datasheet 3.10. Timers and PWM generation Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~ TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6) Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input 16-bit, motor control PWM advanced timer with programmable dead-time generation for output match Encoder interface controller with two inputs using quadrature decoder 24-bit SysTick timer down counter 2 watchdog timers (free watchdog timer and window watchdog timer) The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge-aligned or center-aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features. The general timer, can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 ~ TIMER4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~ TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TIMER5 &TIMER6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32E103xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 37 GD32E103xx Datasheet A 24-bit down counter Auto reload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source 3.11. Real time clock (RTC) 32-bit up-counter with a programmable 20-bit prescaler Alarm function Interrupt and wake-up event The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator. 3.12. Inter-integrated circuit (I2C) Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus) Provide arbitration function, optional PEC (packet error checking) generation and checking Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides several data transfer rates: up to 100 KHz of standard mode, up to 400 KHz of the fast mode and up to 1 MHz of the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 3.13. Serial peripheral interface (SPI) Up to three SPI interfaces with a frequency of up to 30 MHz Support both master and slave mode Hardware CRC calculation and transmit automatic CRC error checking Quad-SPI configuration available in master mode (only in SPI0) SPI TI mode and NSS pulse mode supported 38 GD32E103xx Datasheet The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14. Universal synchronous asynchronous receiver transmitter (USART) Up to three USARTs and two UARTs with operating frequency up to 7.5MBits/s Supports both asynchronous and clocked synchronous serial communication modes IrDA SIR encoder and decoder support LIN break generation and detection USARTs support ISO 7816-3 compliant smart card interface The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication except UART4. 3.15. Inter-IC sound (I2S) Two I2S bus interfaces with sampling frequency from 8 KHz to 192 KHz Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32E103xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported. 3.16. Universal serial bus full-speed interface (USBFS) One full-speed USB Interface with frequency up to 12 Mbit/s Internal 48 MHz oscillator support crystal-less operation Internal main PLL for USB CLK compliantly The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports 39 GD32E103xx Datasheet device modes. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystalless operation. 3.17. External memory controller (EXMC) Supported external memory: SRAM, PSRAM, ROM and NOR-Flash Up to 16-bit data bus Support to interface with Motorola 6800 and Intel 8080 type LCD directly External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity. 3.18. Debug mode Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.19. Package and operation temperature LQFP100 (GD32E103Vx), LQFP64 (GD32E103Rx) and LQFP48 (GD32E103Cx) QFN36 (GD32E103Tx) Operation temperature range: -40°C to +85°C (industrial level) 40 GD32E103xx Datasheet 4. Electrical characteristics 4.1. Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute maximum ratings(1)(4) Symbol Parameter Min Max Unit VDD External voltage range(2) VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V VSS - 0.3 VDD + 3.6 V Input voltage on other I/O VSS - 0.3 3.6 V |ΔVDDX| Variations between different VDD power pins — 50 mV |VSSX −VSS| Variations between different ground pins — 50 mV IIO Maximum current for GPIO pins — ±25 mA TA Operating temperature range -40 +85 °C Power dissipation at TA = 85°C of LQFP100 — 813 Power dissipation at TA = 85°C of LQFP64 — 733 Power dissipation at TA = 85°C of LQFP48 — 574 Power dissipation at TA = 85°C of QFN36 — 1086 TSTG Storage temperature range -65 +150 °C TJ Maximum junction temperature — 125 °C VIN PD (1) (2) (3) (4) 4.2. Input voltage on 5V tolerant pin (3) mW Guaranteed by design, not tested in production. All main power and ground pins should be connected to an external power source within the allowable range. VIN maximum value cannot exceed 5.5 V. It is recommended that VDD and VDDA are powered by the same source. The maximum difference between V DD and VDDA does not exceed 300 mV during power-up and operation. Operating conditions characteristics Table 4-2. DC operating conditions Symbol Parameter Conditions VDD Supply voltage — VDDA VBAT (1) Analog supply voltage ADC not used Analog supply voltage ADC used Battery supply voltage — — Min(1) Typ Max(1) Unit 1.71 3.3 3.6 1.71 3.3 3.6 2.4 3.3 3.6 1.71 — 3.6 V V V Guaranteed by design, not tested in production. Figure 4-1. Recommended power supply decoupling capacitors(1)(2) 41 GD32E103xx Datasheet VBAT 100 nF VSS N * VDD 4.7 μF + N * 100 nF VSS VDDA 1 μF VSSA 10 nF VREF+ 1 μF (1) (2) VREF- 10 nF The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins are not available and internally connected to VDDA and VSSA pins. All decoupling capacitors need to be as close as possible to the pins on the PCB board. Table 4-3. Clock frequency(1) Symbol Parameter Conditions Min Max Unit fHCLK AHB clock frequency — — 120 MHz fAPB1 APB1 clock frequency — — 60 MHz fAPB2 APB2 clock frequency — — 120 MHz Min Max Unit 0 ∞ 20 ∞ (1) Guaranteed by design, not tested in production. Table 4-4. Operating conditions at Power up/ Power down(1) Symbol tVDD (1) Parameter Conditions VDD rise time rate — VDD fall time rate μs/V Guaranteed by design, not tested in production. Table 4-5. Start-up timings of Operating conditions (1)(2)(3) (1) (2) (3) Symbol Parameter tstart-up Start-up time Conditions Typ Clock source from HXTAL 468 Clock source from IRC8M 86.8 Unit μs Based on characterization, not tested in production. After power-up, the start-up time is the time between the rising edge of NRST high and the first I/O instruction conversion in SystemInit function. PLL is off. Table 4-6. Power saving mode wakeup timings characteristics(1)(2) Symbol Parameter Typ tSleep Wakeup from Sleep mode 4.3 tDeep-sleep Wakeup from Deep-sleep mode（LDO On） 18.0 Unit μs 42 GD32E103xx Datasheet Symbol Parameter Wakeup from Deep-sleep mode（LDO in low power mode） tStandby (1) (2) 4.3. Wakeup from Standby mode Typ Unit 18.0 82.0 Based on characterization, not tested in production. The wakeup time is measured from the wakeup event to the point at which the application code reads the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz. Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 4-7. Power consumption characteristics(2)(3)(4)(5) Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock=120 MHz, All peripherals — 28.1 — mA — 16.0 — mA — 24.6 — mA — 14.7 — mA — 22.3 — mA — 13.6 — mA — 17.2 — mA — 10.8 — mA — 12.3 — mA — 8.1 — mA enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 120 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 96 MHz, All peripherals IDD+IDDA Supply current enabled (Run mode) VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 96 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 72 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 72 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 48 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 48 MHz, All peripherals disabled 43 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 36 MHz, All peripherals — 9.8 — mA — 6.7 — mA — 7.4 — mA — 5.3 — mA — 5.7 — mA — 4.4 — mA — 4.1 — mA — 3.4 — mA — 1.3 — mA — 1.0 — mA — 0.9 — mA — 0.7 — mA — 20.5 — mA — 6.9 — mA enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 36 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 24 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 24 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, System clock = 4 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, System clock = 4 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, System clock = 2 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, System Clock = 2 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 120 MHz, CPU clock off, All Supply current peripherals enabled (Sleep mode) VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 120 MHz, CPU clock off, All peripherals disabled 44 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 108 MHz, CPU clock off, All — 18.6 — mA — 6.4 — mA — 16.5 — mA — 5.8 — mA — 13 — mA — 5 — mA — 9.5 — mA — 4.1 — mA — 7.7 — mA — 3.7 — mA — 5.9 — mA — 3.3 — mA — 4.8 — mA — 3 — mA peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 108 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 96 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 96 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 72 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 72 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 48 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 48 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 36 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 36 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 24 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 24 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 16 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 16 MHz, CPU clock off, All peripherals disabled 45 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 8 MHz, CPU clock off, All — 3.6 — mA — 2.7 — mA — 1.1 — mA — 0.6 — mA — 0.8 — mA — 0.6 — mA — 41.8 550 μA — 31.8 550 μA — 2.1 11 μA — 2.0 11 μA — 1.5 11 μA — 1.6 — μA — 1.4 — μA — 1.3 — μA — 1.2 — μA peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 8 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, System Clock = 4 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, System Clock = 4 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, System Clock = 2 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, System Clock = 2 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, LDO in normal power Supply current (Deep-Sleep mode) mode, IRC40K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LDO in low power mode, IRC40K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, RTC on Supply current (Standby mode) VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, RTC off VDD = VDDA = 3.3 V, LXTAL off, IRC40K off, RTC off VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL High driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on Battery supply IBAT current (Backup mode) with external crystal, RTC on, LXTAL High driving VDD off, VDDA off, VBAT = 2.5 V, LXTAL on with external crystal, RTC on, LXTAL High driving VDD off, VDDA off, VBAT = 1.71 V, LXTAL on with external crystal, RTC on, LXTAL High driving 46 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL — 1.3 — μA — 1.1 — μA — 1.0 — μA — 0.9 — μA — 1.0 — μA — 0.9 — μA — 0.7 — μA — 0.6 — μA — 0.9 — μA — 0.8 — μA — 0.6 — μA — 0.5 — μA Medium High driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on, LXTAL Medium High driving VDD off, VDDA off, VBAT = 2.5 V, LXTAL on with external crystal, RTC on, LXTAL Medium High driving VDD off, VDDA off, VBAT = 1.71 V, LXTAL on with external crystal, RTC on, LXTAL Medium High driving VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL Medium Low driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on, LXTAL Medium Low driving VDD off, VDDA off, VBAT = 2.5 V, LXTAL on with external crystal, RTC on, LXTAL Medium Low driving VDD off, VDDA off, VBAT = 1.71 V, LXTAL on with external crystal, RTC on, LXTAL Medium Low driving VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL Low driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on, LXTAL Low driving VDD off, VDDA off, VBAT = 2.5 V, LXTAL on with external crystal, RTC on, LXTAL Low driving VDD off, VDDA off, VBAT = 1.71 V, LXTAL on with external crystal, RTC on, LXTAL Low driving (1) (2) (3) (4) (5) Based on characterization, not tested in production. Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value. When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed, no PLL. When System Clock is greater than 8 MHz, a crystal 25 MHz is used, and the HXTAL bypass function is closed, using PLL. When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additionalpower consumption should be considered. 47 GD32E103xx Datasheet Figure 4-2. Typical supply current consumption in Run mode Figure 4-3. Typical supply current consumption in Sleep mode Table 4-8. Peripheral current consumption characteristics(1) Peripherials(4) APB1 DAC(2) Typical consumption at 25 ℃（TYP） Unit 0.44 mA 48 GD32E103xx Datasheet Peripherials(4) ADDAPB1 APB2 AHB Typical consumption at 25 ℃（TYP） PMU 0.18 BKPI 0.38 I2C1 0.77 I2C0 0.77 UART4 0.78 UART3 0.78 USART2 0.78 USART1 0.78 SPI2 0.72 SPI1 0.78 WWDGT 0.03 TIMER13 0.32 TIMER12 0.3 TIMER11 0.31 TIMER6 0.05 TIMER5 0.04 TIMER4 0.38 TIMER3 0.37 TIMER2 0.36 TIMER1 0.37 CTC 0.68 TIMER10 0.56 TIMER9 0.58 TIMER8 0.6 USART0 0.52 TIMER7 0.87 SPI0 0.09 TIMER0 0.65 ADC1(3) 1.36 ADC0(3) 1.35 GPIOE 0.18 GPIOD 0.19 GPIOC 0.2 GPIOB 0.18 GPIOA 0.19 GPIOF 0.04 USBFS 1.48 EXMC 0.29 CRC 0.03 DMA1 0.31 DMA0 0.39 Unit 49 GD32E103xx Datasheet (1) (2) (3) (4) 4.4. Based on characterization, not tested in production. DEN0 and DEN1 bits in the DAC_CTL register are set to 1, and the converted value set to 0x800. System clock = fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADCON bit is set to 1. If there is no other description, then HXTAL = 25 MHz, system clock = fHCLK = 120 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK. EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the Table 4-9. EMS characteristics(1), based on the EMS levels and classes compliant with IEC 61000 series standard. Table 4-9. EMS characteristics(1) Symbol VESD VFTB (1) Parameter Conditions Voltage applied to all device pins to induce a functional disturbance Level/Class VDD = 3.3 V, TA = 25 °C, LQFP100, fHCLK = 120 MHz 3A conforms to IEC 61000-4-2 Fast transient voltage burst applied to VDD= 3.3 V, TA = 25 °C, induce a functional disturbance through LQFP100, fHCLK = 120 MHz 100 pF on VDD and VSS pins conforms to IEC 61000-4-4 4A Based on characterization, not tested in production. EMI (Electromagnetic Interference) emission test result is given in the Table 4-10. EMI characteristics(1), The electromagnetic field emitted by the device are monitored while an application, executing EEMBC code, is running. The test is compliant with SAE J1752-3:2017 standard which specifies the test board and the pin loading. Table 4-10. EMI characteristics(1) Max vs. Symbol Parameter Tested Conditions frequency band VDD = 3.6 V, TA = +20 °C, SEMI Peak level LQFP100, fHCLK = 120 MHz, conforms to SAE J1752-3:2017 (1) 4.5. [fHXTAL/fHCLK] Unit 8/120 MHz 0.15 MHz to 30 MHz -2.86 30 MHz to 130 MHz 2.13 130 MHz to 1 GHz 5.03 dBμV Based on characterization, not tested in production. Power supply supervisor characteristics Table 4-11. Power supply supervisor characteristics Symbol VLVD(1) Parameter Conditions Min Typ Max Low voltage LVDT = 000(rising edge) — 2.07 — Detector Threshold LVDT = 000(falling edge) — 1.97 — Unit V 50 GD32E103xx Datasheet Symbol VLVDhyst(2) LVD hystersis VPOR(1) Power on reset threshold VPDR(1) 4.6. Parameter Conditions Min Typ Max LVDT = 001(rising edge) — 2.2 — LVDT = 001(falling edge) — 2.1 — LVDT = 010(rising edge) — 2.34 — LVDT = 010(falling edge) — 2.24 — LVDT = 011(rising edge) — 2.47 — LVDT = 011(falling edge) — 2.37 — LVDT = 100(rising edge) — 2.61 — LVDT = 100(falling edge) — 2.51 — LVDT = 101(rising edge) — 2.74 — LVDT = 101(falling edge) — 2.64 — LVDT = 110(rising edge) — 2.88 — LVDT = 110(falling edge) — 2.78 — LVDT = 111(rising edge) — 3.01 — LVDT = 111(falling edge) — 2.91 — — — 100 — mV — 1.67 — V — 1.62 — V Power down reset threshold — Unit VPDRhyst(2) PDR hysteresis — 40 — mV tRSTTEMPO(2) Reset temporization — 2 — ms (1) Based on characterization, not tested in production. (2) Guaranteed by design, not tested in production. Electrical sensitivity The device is strained in order to determine its performance in terms of electrical sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up (LU) test is based on the two measurement methods. Table 4-12. ESD characteristics(1) Symbol VESD(HBM) Parameter Conditions Electrostatic discharge TA = 25 °C; voltage (human body model) JS-001-2014 Min Typ Max Unit — — 5000 V 51 GD32E103xx Datasheet VESD(CDM) (1) Electrostatic discharge TA = 25 °C; voltage (charge device model) JS-002-2014 — — 800 V Based on characterization, not tested in production. 52 GD32E103xx Datasheet Table 4-13. Static latch-up characteristics Symbol (1) Parameter Conditions Min Typ Max Unit — — ±200 mA — — 5.4 V I-test LU TA = 25 °C; JESD78 Vsupply over voltage (1) 4.7. Based on characterization, not tested in production. External clock characteristics Table 4-14. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics Symbol fHXTAL RF (1) (2) Parameter Conditions Min Typ Max Unit Crystal or ceramic frequency 1.71 ≤ VDD ≤ 3.6 V 4 8 32 MHz Feedback resistor VDD = 3.3 V — 400 — kΩ — — 20 30 pF Crystal or ceramic duty cycle — 30 50 70 % Oscillator transconductance Startup — 25 — mA/V VDD = 3.3 V — 1.1 — mA VDD = 3.3 V — 1.8 — ms Recommended matching CHXTAL (2) (3) capacitance on OSCIN and OSCOUT Ducy(HXTAL) (2) gm(2) IDD(HXTAL) (1) tSUHXTAL(1) (1) (2) (3) Crystal or ceramic operating current Crystal or ceramic startup time Based on characterization, not tested in production. Guaranteed by design, not tested in production. CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. Table 4-15. High speed external clock characteristics (HXTAL in bypass mode) Symbol Parameter fHXTAL_ext(1) VHXTALH(2) VHXTALL External clock source or oscillator frequency OSCIN input pin high level voltage (2) OSCIN input pin low level voltage Conditions Min Typ Max Unit VDD = 3.3 V 1 — 50 MHz 0.7 VDD — VDD V VSS — 0.3 VDD V VDD = 3.3 V tH/L(HXTAL) (2) OSCIN high or low time — 5 — — ns tR/F(HXTAL) (2) OSCIN rise or fall time — — — 10 ns OSCIN input capacitance — — 5 — pF Duty cycle — 40 — 60 % CIN(2) Ducy(HXTAL) (1) (2) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. 53 GD32E103xx Datasheet Table 4-16. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics Symbol fLXTAL(1) Parameter Conditions Min Typ VDD = 3.3 V — 32.768 — kHz — — 10 — pF — 30 — 70 % Lower driving capability — 4 — — 6 — Crystal or ceramic frequency Max Unit Recommended matching CLXTAL(2) (3) capacitance on OSC32IN and OSC32OUT Ducy(LXTAL) (2) Crystal or ceramic duty cycle Medium low driving gm(2) Oscillator capability transconductance Medium high driving — 12 — Higher driving capability — 18 — Lower driving capability — 0.7 — — 0.8 — capability Medium low driving IDDLXTAL (1) Crystal or ceramic capability operating current Medium high driving (1) (2) (3) (4) μA — 1.1 — Higher driving capability — 1.4 — — — 1.8 — capability tSULXTAL(1) (4) μA/V Crystal or ceramic startup time s Based on characterization, not tested in production. Guaranteed by design, not tested in production. CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer. Table 4-17.Low speed external user clock characteristics (LXTAL in bypass mode) Symbol Conditions Min Typ Max Unit VDD = 3.3 V — 32.768 1000 kHz — 0.7 VDD — VDD — VSS — 0.3 VDD OSC32IN high or low time — 450 — — tR/F(LXTAL) (2) OSC32IN rise or fall time — — — 50 CIN(2) OSC32IN input capacitance — — 5 — pF Ducy(LXTAL) (2) Duty cycle — 30 50 70 % fLXTAL_ext(1) VLXTALH(2) VLXTALL(2) tH/L(LXTAL) (2) Parameter External clock source or oscillator frequency OSC32IN input pin high level voltage OSC32IN input pin low level voltage (1) Based on characterization, not tested in production. (2) Guaranteed by design, not tested in production. V ns 54 GD32E103xx Datasheet 4.8. Internal clock characteristics Table 4-18. High speed internal clock (IRC8M) characteristics Symbol fIRC8M Parameter Conditions High Speed Internal VDD = VDDA = 3.3 V Min Typ Max Unit MH — 8 — -2.5 — +2.5 % -1.8 — +1.8 % VDD = VDDA = 3.3 V, TA = 25 °C -1.0 — +1.0 % — — 0.3 — % DucyIRC8M(2) IRC8M oscillator duty cycle VDD = VDDA = 3.3 V 45 50 55 % IRC8M oscillator operating VDD = VDDA = 3.3 V, current fIRC8M = 8 MHz — 110 — μA — 2 — μs Oscillator (IRC8M) frequency VDD = VDDA = 3.3 V, IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M TA = -40 °C ~ +85 °C(1) VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C(1) z IRC8M oscillator Frequency accuracy, User trimming step(1) IDDAIRC8M(1) tSUIRC8M(1) (1) (2) VDD = VDDA = 3.3 V, IRC8M oscillator startup time fIRC8M = 8 MHz Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-19. Low speed internal clock (IRC40K) characteristics Symbol fIRC40K(1) IDDAIRC40K(2) tSUIRC40K(2) (1) (2) Parameter Conditions Low Speed Internal oscillator VDD = VDDA = 3.3 V, (IRC40K) frequency TA = -40 °C ~ +85 °C IRC40K oscillator operating current IRC40K oscillator startup time Min Typ Max Unit 28 40 60 kHz VDD = VDDA = 3.3 V — 0.42 — μA VDD = VDDA = 3.3 V — — μs 110 Guaranteed by design, not tested in production. Based on characterization, not tested in production. 55 GD32E103xx Datasheet Table 4-20. High speed internal clock (IRC48M) characteristics Symbol Parameter Conditions Min Typ Max Unit High Speed Internal fIRC48M Oscillator (IRC48M) VDD = VDDA = 3.3 V — 48 — MHz -4.0 — 5.0 % -3.0 — 3.0 % VDD = VDDA = 3.3 V, TA = 25 °C -2.0 — 2.0 % — — 0.1 — % DucyIRC48M(2) IRC48M oscillator duty cycle VDD = VDDA = 3.3 V 45 50 55 % IRC48M oscillator operating VDD = VDDA = 3.3 V, current fIRC48M = 48 MHz — 270 — μA IRC48M oscillator startup VDD = VDDA = 3.3 V, time fIRC48M = 48 MHz — 2.5 — μs frequency VDD = VDDA = 3.3 V, IRC48M oscillator Frequency TA = -40 °C ~ +85 °C(1) VDD = VDDA = 3.3 V, accuracy, Factory-trimmed ACCIRC48M TA = 0 °C ~ +85 °C(1) IRC48M oscillator Frequency accuracy, User trimming step(1) IDDIRC48M(1) tSUIRC48M(1) (1) (2) 4.9. Based on characterization, not tested in production. Guaranteed by design, not tested in production. PLL characteristics Table 4-21. PLL characteristics Symbol fPLLIN (1) fPLLOUT (2) Parameter Conditions Min Typ Max Unit PLL input clock frequency — 1 8 25 MHz PLL output clock frequency — 16 — 120 MHz fVCO(2) VCO output frequency — 32 — 240 MHz tLOCK(2) PLL lock time — — — 300 μs VCO freq = 240 MHz — 350 — μA — 46 — IDDA(1) Current consumption on VDDA Cycle to cycle Jitter JitterPLL(1)(3) （rms） Cycle to cycle Jitter System clock （peak to peak） (1) (2) (3) ps — 463 — Based on characterization, not tested in production. Guaranteed by design, not tested in production. Value given with main PLL running. Table 4-22. PLL1/2 characteristics Symbol fPLLIN (1) fPLLOUT (2) fVCO(2) Parameter Conditions Min Typ Max Unit PLL input clock frequency — 1 8 25 MHz PLL output clock frequency — 16 — 120 MHz VCO output frequency — 32 — 240 MHz 56 GD32E103xx Datasheet tLOCK(2) IDDA(1) PLL lock time Current consumption on VDDA — — — 300 μs VCO freq = 240 MHz — 320 — μA — 46 — Cycle to cycle Jitter JitterPLL(1)(3) （rms） System clock Cycle to cycle Jitter ps — （peak to peak） (1) (2) (3) 4.10. — 463 Based on characterization, not tested in production. Guaranteed by design, not tested in production. Value given with main PLL running. Memory characteristics Table 4-23. Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit TA = -40 °C ~ +85 °C 100 — — kcycles 10k cycles at TA = 85 °C 10 — — years Number of guaranteed PECYC(1) program /erase cycles before failure(Endurance) tRET (1) tPROG Data retention time Word(3) TA = -40 °C ~ +85 °C 37 — 44 μs tERASE(2) Page erase time TA = -40 °C ~ +85 °C 3.2 — 4 ms tMERASE(2) Mass erase time TA = -40 °C ~ +85 °C 8 — 10 ms Min Typ -0.5 — (1) (2) (3) 4.11. (2) programming time Based on characterization, not tested in production. Guaranteed by design, not tested in production. Word is 32 bits or 64 bits depend on PGW bit in FMC_WS register. NRST pin characteristics Table 4-24. NRST pin characteristics Symbol Parameter VIL(NRST)(1) NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage Vhyst(1) Schmidt trigger Voltage hysteresis Rpu (1) (2) (2) Conditions 1.8 V ≤ VDD = VDDA Pull-up equivalent resistor ≤ 3.6 V — 0.7 VDD — Max 0.3 VDD VDD + 0.45 Unit V — 460 — mV — 40 — kΩ Based on characterization, not tested in production. Guaranteed by design, not tested in production. 57 GD32E103xx Datasheet Figure 4-4. Recommended external NRST pin circuit VDD VDD External reset circuit RPU 10 kΩ NRST K 100 nF GND 4.12. GPIO characteristics Table 4-25. I/O port DC characteristics(1)(3) Symbol Parameter Standard IO Low level input voltage VIL 5V-tolerant IO Low level input voltage Standard IO High level input voltage VIH VOL VOH VOH 1.8 V ≤ VDD = VDDA ≤ 3.6 V 1.8 V ≤ VDD = VDDA ≤ 3.6 V Min Typ Max Unit — — 0.3 VDD V — — 0.3 VDD V — — V — — V 1.8 V ≤ VDD = VDDA ≤ 3.6 0.7 V VDD 1.8 V ≤ VDD = VDDA ≤ 3.6 0.7 V VDD VDD = 1.8 V — — 0.32 Low level output voltage VDD = 2.5 V — — 0.24 (IIO = +8 mA) VDD = 3.3 V — — 0.11 VDD = 3.6 V — — 0.11 VDD = 1.8 V — — 0.53 Low level output voltage VDD = 2.5 V — — 0.60 (IIO = +20 mA) VDD = 3.3 V — — 0.28 VDD = 3.6 V — — 0.27 VDD = 1.8 V 1.49 — — High level output voltage VDD = 2.5 V 2.27 — — (IIO = +8 mA) VDD = 3.3 V 3.14 — — VDD = 3.6 V 3.45 — — VDD = 1.8 V 1.25 — — VDD = 2.5 V 1.89 — — VDD = 3.3 V 2.91 — — 5V-tolerant IO High level input voltage VOL Conditions High level output voltage (IIO = +20 mA) V V V V 58 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ Max VDD = 3.6 V 3.23 — — Unit RPU(2) Internal pull-up resistor — — 40 — kΩ RPD(2) Internal pull-down resistor — — 40 — kΩ (1) (2) (3) Based on characterization, not tested in production. Guaranteed by design, not tested in production. All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which can only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz when they are in output mode(maximum load: 30 pF). Table 4-26. I/O port AC characteristics(1)(2) GPIOx_MDy[1:0] bit value(3) Parameter GPIOx_CTL->MDy[1:0] = 10 （IO_Speed = 2 MHz） GPIOx_CTL->MDy[1:0] = 01 GPIOx_CTL->MDy[1:0] = 11 9 Maximum frequency(4) 1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF 6 1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF 4 1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF 50 1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF 25 1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF 15 1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF 60 1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF 30 1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF 20 1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF 70 1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF 50 1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF 30 Maximum （IO_Speed = 50 MHz） frequency(4) frequency(4) GPIOx_CTL->MDy[1:0] = 11 and GPIOx_SPDy = 1 Maximum frequency(4) （IO_Speed = MAX） (1) (2) (3) (4) Max Unit 1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF Maximum （IO_Speed = 10 MHz） Conditions MHz MHz MHz MHz Based on characterization, not tested in production. Unless otherwise specified, all test results given for TA = 25 ℃. The I/O speed is configured using the GPIOx_CTL -> MDy[1:0] bits. Refer to the GD32E103xx user manual which is selected to set the GPIO port output speed. The maximum frequency is defined in Figure 4-5. I/O port AC characteristics definition Figure 4-5. I/O port AC characteristics definition 90% EXTERNAL OUTPU T ON 50pF 90% 50% 50% 10% tr(IO)out 10% tf(IO)out T If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved . The duty cycle is （45%-55%）when loaded by 50 pF 59 GD32E103xx Datasheet 4.13. ADC characteristics Table 4-27. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 2.4 3.3 3.6 V VIN(1) ADC input voltage range — 0 — VREF+ V fADC(1) ADC clock — 0.1 — 42 MHz 12-bit 0.007 — 3 10-bit 0.008 — 3.5 8-bit 0.01 — 4.2 6-bit 0.011 — 5.25 Analog input voltage 16 external; 2 internal 0 — VDDA V Positive Reference Voltage — 1.8 — VDDA V — — VSSA — V See Equation 1 — — 24 kΩ — — — 0.2 kΩ — — 5.5 pF fS(1) (1) VAIN VREF+(2) VREF-(2) RAIN(2) RADC(2) Sampling rate Negative Reference Voltage External input impedance Input sampling switch resistance No pin/pad capacitance CADC(2) Input sampling capacitance tCAL(2) Calibration time fADC = 42 MHz — 3.12 — μs Sampling time fADC = 42 MHz 0.036 — 5.7 μs 12-bit — 14 — 10-bit — 12 — 8-bit — 10 — 6-bit — 8 — — — — 1 (2) ts included Total conversion tCONV(2) time(including sampling time) tSU(2) (1) (2) MSPS Startup time 1/ fADC μs Based on characterization, not tested in production. Guaranteed by design, not tested in production. Equation 1: RAIN max formula R AIN < Ts fADC ∗CADC ∗ln(2N+2 ) − R ADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 4-28. ADC RAIN max for fADC = 42 MHz Ts(cycles) ts(us) RAINmax (kΩ) 1.5 0.04 0.47 7.5 0.18 3.15 13.5 0.32 5.82 28.5 0.68 12.55 41.5 0.99 18.35 55.5 1.32 24.55 71.5 1.70 NA 60 GD32E103xx Datasheet Ts(cycles) ts(us) RAINmax (kΩ) 239.5 5.70 NA Table 4-29. ADC dynamic accuracy at fADC = 14 MHz(1) Symbol Parameter Test conditions Min Typ Max Unit ENOB Effective number of bits fADC = 14 MHz — 10.3 — bits SNDR Signal-to-noise and distortion ratio VDDA = VREF+ = 3.3 V — 63.8 — SNR Signal-to-noise ratio Input Frequency = 20 — 64.5 — — -67.5 — THD (1) kHz Total harmonic distortion Temperature = 25 ℃ dB Based on characterization, not tested in production. Table 4-30. ADC dynamic accuracy at fADC = 42 MHz(1) Symbol Parameter Test conditions Min Typ ENOB Effective number of bits fADC = 42 MHz — 10.3 — SNDR Signal-to-noise and distortion ratio VDDA = VREF+ = 3.3 V — 63.8 — SNR Signal-to-noise ratio Input Frequency = 20 kHz — 64.5 — THD Total harmonic distortion Temperature = 25 ℃ — -67.5 — (1) Max Unit bits dB Based on characterization, not tested in production. Table 4-31. ADC static accuracy at fADC = 42 MHz(1) Symbol Parameter Offset Offset error DNL Differential linearity error INL Integral linearity error (1) 4.14. Test conditions Typ Max ±1 — ±1 — ±3 — fADC = 42 MHz VDDA = VREF+ = 3.3 V Unit LSB Based on characterization, not tested in production. Temperature sensor characteristics Table 4-32. Temperature sensor characteristics(1) Symbol Parameter Min Typ Max Unit TL VSENSE linearity with temperature — ±1.5 — ℃ Avg_Slope Average slope — 4.3 — mV/℃ V25 Voltage at 25 °C — 1.47 — V Startup time — — — μs ADC sampling time when reading the temperature — 17.1 — μs tSTART tS_temp (1) (2) 4.15. (2) Based on characterization, not tested in production. Shortest sampling time can be determined in the application by multiple iterations. DAC characteristics Table 4-33. DAC characteristics 61 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 1.71 3.3 3.6 V VREF+(1) Reference supply voltage — 1.8 — VDDA V — — VSSA — V 5 — — kΩ — — 15 kΩ — — 50 pF — 0.2 — — V — — — — — 0.5 — — — — 380 — μA — 460 — μA — 120 — μA — 320 — μA DAC in 12-bit mode — — ±3 LSB VREF-(1) RLOAD(2) Ro(2) CLOAD(2) Negative Reference Voltage Load resistance Impedance output with buffer OFF Load capacitance DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF DAC_OUT Higher DAC_OUT voltage max(2) with buffer OFF Resistive load with buffer ON — No pin/pad capacitance included VDDA0.2 — VDDA1LSB V mV V With no load, middle code(0x800) on the input, VREF+ IDDA(1) DAC current consumption = 3.6 V in quiescent mode With no load, worst code(0xF1C) on the input, VREF+ = 3.6 V With no load, middle code(0x800) on the input, VREF+ IDDVREF+(1) DAC current consumption = 3.6 V in quiescent mode With no load, worst code(0xF1C) on the input, VREF+ = 3.6 V DNL(1) Differential non-linearity error INL(1) Integral non-linearity DAC in 12-bit mode — — ±4 LSB Offset(1) Offset error DAC in 12-bit mode — — ±12 LSB GE(1) Tsetting Gain error DAC in 12-bit mode — — ±0.5 % (1) Settling time CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ — 0.3 1 μs (2) Wakeup from off state — — 5 10 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ — — 4 MS/s — 55 80 — dB Twakeup Update rate(2) PSRR(2) Max frequency for a correct DAC_OUT change from code i to i±1LSBs Power supply rejection ratio 62 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ Max Unit (to VDDA) (1) (2) 4.16. Based on characterization, not tested in production. Guaranteed by design, not tested in production. I2C characteristics Table 4-34. I2C characteristics(1)(2) Symbol Parameter Conditio ns Standard mode Fast mode Fast mode plus Unit Min Max Min Max Min Max tSCL(H) SCL clock high time — 4.0 — 0.6 — 0.2 — μs tSCL(L) SCL clock low time — 4.7 — 1.3 — 0.5 — μs tsu(SDA) SDA setup time 250 — 100 — 50 — ns th(SDA) SDA data hold time 0(3) 3450 0 900 0 450 ns — — 1000 — 300 — 120 ns — — 300 — 300 — 120 ns — 4.0 — 0.6 — 0.26 — μs — 4.7 — 0.6 — 0.26 — μs — 4.0 — 0.6 — 0.26 — μs — 4.7 — 1.3 — 0.5 — μs tr(SDA/SCL) tf(SDA/SCL) th(STA) SDA and SCL rise time SDA and SCL fall time Start condition hold time — — Repeated Start ts(STA) condition setup time ts(STO) Stop condition setup time Stop to Start tbuff condition time (bus free) (1) (2) (3) Guaranteed by design, not tested in production To ensure the standard mode I2C frequency, f PCLK1 must be at least 2 MHz. To ensure the fast mode I2C frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode plus I2C frequency, f PCLK1 must be at least a multiple of 10 MHz The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the falling edge of SCL. 63 GD32E103xx Datasheet Figure 4-6. I2C bus timing diagram tsu(STA) SDA 70% 30% tf(SDA) tr(SDA) tSCL(H) th(STA) SCL tbuff th(SDA) tsu(SDA) 70% 30% tSCL(L) 4.17. tr(SCL) tf(SCL) tsu(STO) SPI characteristics Table 4-35. Standard SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency — — — 30 MHz tSCK(H) SCK clock high time tSCK(L) SCK clock low time Master mode, fPCLKx = 120 MHz, presc = 8 Master mode, fPCLKx = 120 MHz, presc = 8 31.83 33.33 34.83 ns 31.83 33.33 34.83 ns SPI master mode tV(MO) Data output valid time — — 7 — ns tH(MO) Data output hold time — — 4 — ns tSU(MI) Data input setup time — 1 — — ns tH(MI) Data input hold time — 0 — — ns SPI slave mode (1) tSU(NSS) NSS enable setup time — 0 — — ns tH(NSS) NSS enable hold time — 1 — — ns tA(SO) Data output access time — — 9 — ns tDIS(SO) Data output disable time — — 8 — ns tV(SO) Data output valid time — — 10 — ns tH(SO) Data output hold time — — 10 — ns tSU(SI) Data input setup time — 0 — — ns tH(SI) Data input hold time — 2 — — ns Based on characterization, not tested in production. 64 GD32E103xx Datasheet Figure 4-7. SPI timing diagram - master mode tSCK SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) tSCK(H) SCK (CKPH=1 CKPL=1) tSCK(L) tSU(MI) D[0] MISO D[7] tH(MI) LF=1,FF16=0 D[0] MOSI D[7] tV(MO) Figure 4-8. SPI timing diagram - slave mode NSS tSCK SCK (CKPH=0 CKPL=0) tH(NSS) tSCK(L) tSCK(H) tsuNSS SCK (CKPH=0 CKPL=1) tDIS(SO) tA(SO) tV(SO) MISO D[7] D[0] MOSI D[7] D[0] tHSI tSU(SI) 4.18. I2S characteristics Table 4-36. I2S characteristics(1)(2) Symbol Parameter fCK Clock frequency Conditions Master mode (data: 16 bits, Audio frequency = 96 kHz) Min Typ Max Unit — 3.078 — MHz 65 GD32E103xx Datasheet Slave mode — 10 — — 162 — ns — 163 — ns tH Clock high time tL Clock low time tV(WS) WS valid time Master mode — 2 — ns tH(WS) WS hold time Master mode — 2 — ns tSU(WS) WS setup time Slave mode 0 — — ns tH(WS) WS hold time Slave mode 3 — — ns Slave mode — 50 — % DuCy(SCK) — I2S slave input clock duty cycle tSU(SD_MR) Data input setup time Master mode 0 — — ns tsu(SD_SR) Data input setup time Slave mode 0 — — ns Master receiver 1 — — ns Slave receiver 3 — — ns — 12 — ns — 10 — ns — 10 — ns — 7 — ns tH(SD_MR) Data input hold time tH(SD_SR) (1) (2) tv(SD_ST) Data output valid time th(SD_ST) Data output hold time tv(SD_MT) Data output valid time th(SD_MT) Data output hold time Slave transmitter (after enable edge) Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) Guaranteed by design, not tested in production. Based on characterization, not tested in production. Figure 4-9. I2S timing diagram - master mode tCK CPOL=0 tL CPOL=1 tV(WS) tH tH(WS) WS output tv(SD_MT) SD transmit SD receive th(SD_MT) D[0] D[0] tSU(SD_MR) tH(SD_MR) 66 GD32E103xx Datasheet Figure 4-10. I2S timing diagram - slave mode tCK CPOL=0 tL CPOL=1 tH tH(WS) WS input tSU(WS) th(SD_ST) tv(SD_ST) SD transmit D[0] SD receive D[0] tSU(SD_SR) tH(SD_SR) 4.19. USART characteristics Table 4-37. USART characteristics(1) (1) 4.20. Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency fPCLKx = 120 MHz — — 60 MHz tSCK(H) SCK clock high time fPCLKx = 120 MHz 7.5 — — ns tSCK(L) SCK clock low time fPCLKx = 120 MHz 7.5 — — ns Guaranteed by design, not tested in production. USBFS characteristics Table 4-38. USBFS start up time Symbol (1) tSTARTUP (1) Parameter Max Unit USBFS startup time 1 μs Guaranteed by design, not tested in production. Table 4-39. USBFS DC electrical characteristics 67 GD32E103xx Datasheet Symbol Parameter Conditions Min Typ VDD USBFS operating voltage — 3 — 3.6 VDI Differential input sensitivity — 0.2 — — Includes VDI range 0.8 — 2.5 Single ended receiver threshold — 1.3 — 2.0 Output VOL Static output level low RL of 1.0 kΩ to 3.6 V — 0.064 0.3 levels (2) Static output level high RL of 15 kΩ to VSS 2.8 3.3 3.6 17 20.574 24 0.65 — 2.0 1.5 1.585 2.1 0.25 0.326 0.55 Input levels(1) VCM Differential common mode range VSE VOH PA11, PA12(USB_DM/DP) RPD(2) PA9(USB_VBUS) PA11, PA12(USB_DM/DP) RPU(2) (1) (2) VIN = VDD VIN = VSS PA9(USB_VBUS) Max Unit V V kΩ Guaranteed by design, not tested in production. Based on characterization, not tested in production. Table 4-40. USBFS electrical characteristics(1) (1) Symbol Parameter Conditions Min Typ Max Unit tR Rise time CL = 50 pF 4 — 20 ns tF Fall time CL = 50 pF 4 — 20 ns tRFM Rise/fall time matching tR/tF 90 — 110 % VCRS Output signal crossover voltage — 1.3 — 2.0 V Guaranteed by design, not tested in production. Figure 4-11. USBFS timings: definition of data signal rise and fall time Crossover points Differential data lines VCRS VSS tf 4.21. tr EXMC characteristics Table 4-41. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)(3) Symbol Parameter Min Max Unit tw(NE) EXMC_NE low time 40.5 42.5 ns tV(NOE_NE) EXMC_NEx low to EXMC_NOE low 0 — ns tw(NOE) EXMC_NOE low time 40.5 42.5 ns th(NE_NOE) EXMC_NOE high to EXMC_NE high hold time 0 — ns tv(A_NE) EXMC_NEx low to EXMC_A valid 0 — ns tv(BL_NE) EXMC_NEx low to EXMC_BL valid 0 — ns tsu(DATA_NE) Data to EXMC_NEx high setup time 32.2 — ns 68 GD32E103xx Datasheet tsu(DATA_NOE) Data to EXMC_NOEx high setup time 32.2 — ns th(DATA_NOE) Data hold time after EXMC_NOE high 0 — ns th(DATA_NE) Data hold time after EXMC_NEx high 0 — ns tv(NADV_NE) EXMC_NEx low to EXMC_NADV low 0 — ns tw(NADV) EXMC_NADV low time 7.3 9.3 ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1. Table 4-42. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)(3) Symbol Parameter Min Max Unit tw(NE) EXMC_NE low time 23.9 25.9 ns tV(NWE_NE) EXMC_NEx low to EXMC_NWE low 7.3 — ns tw(NWE) EXMC_NWE low time 7.3 9.3 ns th(NE_NWE) EXMC_NWE high to EXMC_NE high hold time 7.3 9.3 ns tv(A_NE) EXMC_NEx low to EXMC_A valid 0 — ns tV(NADV_NE) EXMC_NEx low to EXMC_NADV low 0 — ns tw(NADV) EXMC_NADV low time 7.3 9.3 ns 15.6 — ns th(AD_NADV) EXMC_AD(address) valid hold time after EXMC_NADV high th(A_NWE) Address hold time after EXMC_NWE high 7.3 — ns th(BL_NWE) EXMC_BL hold time after EXMC_NWE high 7.3 — ns tv(BL_NE) EXMC_NEx low to EXMC_BL valid 0 — ns tv(DATA_NADV) EXMC_NADV high to DATA valid 0 — ns th(DATA_NWE) Data hold time after EXMC_NWE high 7.3 — ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1. Table 4-43. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)(3) Symbol Parameter Min Max Unit tw(NE) EXMC_NE low time 57.1 59.1 ns tV(NOE_NE) EXMC_NEx low to EXMC_NOE low 23.9 — ns tw(NOE) EXMC_NOE low time 32.2 34.2 ns th(NE_NOE) EXMC_NOE high to EXMC_NE high hold time 0 — ns tv(A_NE) EXMC_NEx low to EXMC_A valid 0 — ns tv(A_NOE) Address hold time after EXMC_NOE high 0 — ns tv(BL_NE) EXMC_NEx low to EXMC_BL valid 0 — ns th(BL_NOE) EXMC_BL hold time after EXMC_NOE high 0 — ns tsu(DATA_NE) Data to EXMC_NEx high setup time 33.2 — ns tsu(DATA_NOE) Data to EXMC_NOEx high setup time 33.2 — ns th(DATA_NOE) Data hold time after EXMC_NOE high 0 — ns th(DATA_NE) Data hold time after EXMC_NEx high 0 — ns tv(NADV_NE) EXMC_NEx low to EXMC_NADV low 0 — ns tw(NADV) EXMC_NADV low time 7.3 9.3 ns 69 GD32E103xx Datasheet Th(AD_NADV) (1) (2) (3) EXMC_AD(adress) valid hold time after EXMC_NADV high 7.3 9.3 ns CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1. Table 4-44. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)(3) Symbol Parameter Min Max Unit tw(NE) EXMC_NE low time 40.5 42.5 ns tV(NWE_NE) EXMC_NEx low to EXMC_NWE low 7.3 — ns tw(NWE) EXMC_NWE low time 23.9 25.9 ns th(NE_NWE) EXMC_NWE high to EXMC_NE high hold time 7.3 — ns tv(A_NE) EXMC_NEx low to EXMC_A valid 0 — ns tV(NADV_NE) EXMC_NEx low to EXMC_NADV low 0 — ns tw(NADV) EXMC_NADV low time 7.3 9.3 ns 7.3 — ns th(AD_NADV) EXMC_AD(address) valid hold time after EXMC_NADV high th(A_NWE) Address hold time after EXMC_NWE high 7.3 — ns th(BL_NWE) EXMC_BL hold time after EXMC_NWE high 7.3 — ns tv(BL_NE) EXMC_NEx low to EXMC_BL valid 0 — ns tv(DATA_NADV) EXMC_NADV high to DATA valid 7.3 — ns th(DATA_NWE) Data hold time after EXMC_NWE high 7.3 — ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 120 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime =1. Table 4-45. Synchronous multiplexed PSRAM/NOR read timings(1)(2)(3) Symbol Parameter Min Max Unit tw(CLK) EXMC_CLK period 33.2 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 15.6 — ns td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 15.6 — ns td(CLKL-NOEL) EXMC_CLK low to EXMC_NOE low 0 — ns td(CLKH-NOEH) EXMC_CLK high to EXMC_NOE high 15.6 — ns td(CLKL-ADV) EXMC_CLK low to EXMC_AD valid 0 — ns td(CLKL-ADIV) EXMC_CLK low to EXMC_AD invalid 0 — ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1. Table 4-46. Synchronous multiplexed PSRAM write timings(1)(2)(3) Symbol Parameter Min Max Unit 70 GD32E103xx Datasheet tw(CLK) EXMC_CLK period 33.2 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 15.6 — ns td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 15.6 — ns td(CLKL-NWEL) EXMC_CLK low to EXMC_NWE low 0 — ns td(CLKH-NWEH) EXMC_CLK high to EXMC_NWE high 15.6 — ns td(CLKL-ADIV) EXMC_CLK low to EXMC_AD invalid 0 — ns td(CLKL-DATA) EXMC_A/D valid data after EXMC_CLK low 0 — ns th(CLKL-NBLH) EXMC_CLK low to EXMC_NBL high 0 — ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1. Table 4-47. Synchronous non-multiplexed PSRAM/NOR read timings(1)(2)(3) Symbol Parameter Min Max Unit tw(CLK) EXMC_CLK period 33.2 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 15.6 — ns td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 15.6 — ns td(CLKL-NOEL) EXMC_CLK low to EXMC_NOE low 0 — ns td(CLKH-NOEH) EXMC_CLK high to EXMC_NOE high 15.6 — ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1. Table 4-48. Synchronous non-multiplexed PSRAM write timings(1)(2)(3) Symbol Parameter Min Max Unit tw(CLK) EXMC_CLK period 33.2 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 15.6 — ns td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 15.6 — ns td(CLKL-NWEL) EXMC_CLK low to EXMC_NWE low 0 — ns td(CLKH-NWEH) EXMC_CLK high to EXMC_NWE high 15.6 — ns td(CLKL-DATA) EXMC_A/D valid data after EXMC_CLK low 0 — ns 71 GD32E103xx Datasheet th(CLKL-NBLH) EXMC_CLK low to EXMC_NBL high 0 — ns (1) CL = 30 pF. (2) Guaranteed by design, not tested in production. (3) Based on configure: fHCLK = 120 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable; CLKDivision = 3(EXMC_CLK is 4 divided by HCLK); DataLatency = 1. 4.22. TIMER characteristics Table 4-49. TIMER characteristics(1) Symbol Parameter Conditions Min Max Unit tres Timer resolution time — 1 — tTIMERxCLK fTIMERxCLK = 120 MHz 8.4 — ns Timer external clock — 0 fTIMERxCLK/2 MHz frequency fTIMERxCLK = 120 MHz 0 60 MHz Timer resolution — — 16 bit 16-bit counter clock period — 1 65536 tTIMERxCLK 546 μs fEXT RES tCOUNTER when internal clock is fTIMERxCLK = 120 MHz 0.0084 selected tMAX_COUNT (1) 4.23. Maximum possible count — — fTIMERxCLK = 120 MHz — 65536x65536 tTIMERxCLK 35.7 s Guaranteed by design, not tested in production. WDGT characteristics Table 4-50. FWDGT min/max timeout period at 40 kHz (IRC40K)(1) Prescaler divider PSC[2:0] bits 1/4 (1) Min timeout RLD[11:0] = Max timeout RLD[11:0] 0x000 = 0xFFF 000 0.025 409.525 1/8 001 0.025 819.025 1/16 010 0.025 1638.025 1/32 011 0.025 3276.025 1/64 100 0.025 6552.025 1/128 101 0.025 13104.025 1/256 110 or 111 0.025 26208.025 Unit ms Guaranteed by design, not tested in production. Table 4-51. WWDGT min-max timeout value at 60 MHz (fPCLK1)(1) Min timeout value Prescaler divider PSC[1:0] 1/1 00 68.2 1/2 01 136.4 1/4 10 272.8 1/8 11 545.6 (1) CNT[6:0] = 0x40 Unit Max timeout value CNT[6:0] = 0x7F Unit 4.3 μs 8.6 17.2 ms 34.4 Guaranteed by design, not tested in production. 72 GD32E103xx Datasheet 4.24. Parameter conditions Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 ℃. 73 GD32E103xx Datasheet 5. Package information 5.1. LQFP100 package outline dimensions Figure 5-1. LQFP100 package outline A3 A2 A c θ A1 F eB D D1 51 75 0.25 50 76 L L1 DETAIL: F E1 E b b1 100 c1 c 26 BASE METAL 1 25 b e WITH PLATING B B SECTION B-B Table 5-1. LQFP100 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 15.80 16.00 16.20 D1 13.90 14.00 14.10 E 15.80 16.00 16.20 E1 13.90 14.00 14.10 e — 0.50 — eB 15.05 — 15.35 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° 74 GD32E103xx Datasheet (Original dimensions are in millimeters) Figure 5-2. LQFP100 recommended footprint 16.70 76 100 14.30 75 25 51 50 26 12.30 16.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 75 GD32E103xx Datasheet 5.2. LQFP64 package outline dimensions Figure 5-3. LQFP64 package outline A3 A2 A θ c A1 F eB D D1 33 48 0.25 32 49 L L1 DETAIL: F E1 E b b1 c1 c BASE METAL 64 17 WITH PLATING 1 e b SECTION B-B 16 B B Table 5-2. LQFP64 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 11.80 12.00 12.20 D1 9.90 10.00 10.10 E 11.80 12.00 12.20 E1 9.90 10.00 10.10 e — 0.50 — eB 11.25 — 11.45 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 76 GD32E103xx Datasheet Figure 5-4. LQFP64 recommended footprint 12.70 64 49 10.30 48 16 33 17 32 7.80 12.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 77 GD32E103xx Datasheet LQFP48 package outline dimensions Figure 5-5. LQFP48 package outline A3 A2 A θ A1 c 5.3. F eB D D1 36 0.25 25 L 24 37 L1 DETAIL: F E1 E b b1 13 48 c1c BASE METAL WITH PLATING 1 12 b e SECTION B-B BB Table 5-3. LQFP48 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 8.80 9.00 9.20 D1 6.90 7.00 7.10 E 8.80 9.00 9.20 E1 6.90 7.00 7.10 e — 0.50 — eB 8.10 — 8.25 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 78 GD32E103xx Datasheet Figure 5-6. LQFP48 recommended footprint 9.70 37 48 7.30 36 12 25 24 13 5.80 9.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 79 GD32E103xx Datasheet QFN36 package outline dimensions Figure 5-7. QFN36 package outline Nd D2 D 36 36 1 1 h PIN 1# Laser Mark 2 e b1 b L1 L E2 Ne h E 2 EXPOSED THERMAL PAD ZONE TOP VIEW BOTTOM VIEW A1 A c 5.4. SIDE VIEW Table 5-4. QFN36 package dimensions Symbol Min Typ Max A 0.80 0.85 0.90 A1 0 0.02 0.05 b 0.18 0.23 0.30 b1 — 0.16 — c 0.18 0.20 0.23 D 5.90 6.00 6.10 D2 3.80 3.90 4.00 E 5.90 6.00 6.10 E2 3.80 3.90 4.00 e — 0.50 — h 0.30 0.35 0.40 L 0.50 0.55 0.60 L1 — 0.10 — Nd 3.95 4.00 4.05 Ne 3.95 4.00 4.05 (Original dimensions are in millimeters) 80 GD32E103xx Datasheet Figure 5-8. QFN36 recommended footprint 6.70 36 28 4.80 1 4.28 6.70 3.85 0.28 27 3.85 9 10 18 19 0.95 0.50 (Original dimensions are in millimeters) 81 GD32E103xx Datasheet 5.5. Thermal characteristics Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter “θ”. For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface. θJA: Thermal resistance, junction-to-ambient. θJB: Thermal resistance, junction-to-board. θJC: Thermal resistance, junction-to-case. ᴪJB: Thermal characterization parameter, junction-to-board. ᴪJT: Thermal characterization parameter, junction-to-top center. θJA =(TJ -TA )/PD (5-1) θJB =(TJ -TB )/PD (5-2) θJC =(TJ -TC )/PD (5-3) Where, TJ = Junction temperature. TA = Ambient temperature TB = Board temperature TC = Case temperature which is monitoring on package surface PD = Total power dissipation θJA represents the resistance of the heat flows from the heating junction to ambient air. It is an indicator of package heat dissipation capability. Lower θJA can be considerate as better overall thermal performance. θJA is generally used to estimate junction temperature. θJB is used to measure the heat flow resistance between the chip surface and the PCB board. θJC represents the thermal resistance between the chip surface and the package top case. θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package). Table 5-5. Package thermal characteristics(1) Symbol ΘJA ΘJB Condition Natural convection, 2S2P PCB Cold plate, 2S2P PCB Package Value LQFP100 49.18 LQFP64 54.57 LQFP48 69.64 QFN36 36.82 LQFP100 22.70 LQFP64 35.08 LQFP48 43.16 Unit °C/W °C/W 82 GD32E103xx Datasheet Symbol ΘJC ΨJB ΨJT (1) Condition Cold plate, 2S2P PCB Natural convection, 2S2P PCB Natural convection, 2S2P PCB Package Value QFN36 9.79 LQFP100 12.52 LQFP64 18.11 LQFP48 25.36 QFN36 13.31 LQFP100 32.85 LQFP64 35.41 LQFP48 47.75 QFN36 9.87 LQFP100 0.53 LQFP64 1.10 LQFP48 2.45 QFN36 0.43 Unit °C/W °C/W °C/W Thermal characteristics are based on simulation, and meet JEDEC specification. 83 GD32E103xx Datasheet 6. Ordering information Table 6-1. Part ordering code for GD32E103xx devices Ordering code Flash (KB) Package Package type GD32E103VBT6 128 LQFP100 Green GD32E103V8T6 64 LQFP100 Green GD32E103RBT6 128 LQFP64 Green GD32E103R8T6 64 LQFP64 Green GD32E103CBT6 128 LQFP48 Green GD32E103C8T6 64 LQFP48 Green GD32E103TBU6 128 QFN36 Green GD32E103T8U6 64 QFN36 Green Temperature operating range Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C 84 GD32E103xx Datasheet 7. Revision history Table 7-1. Revision history Revision No. Description Date 1.0 Initial Release Dec. 26, 2017 Modify section 2.6. Pin definitions 1.1 Pin definitions 1.2 Repair history accumulation error 1.4 Dec. 12, 2018 Modify section 5.1. LQFP100 1.3 Oct. 29, 2018 Apr. 22, 2019 package outline dimensions. Modify section 2.6. Pin definitions. Jun. 26, 2019 Remove redundant pin function in LQFP48 and QFN36 package. Add 1.5 functional description of PD0 and PD1 Mar. 6, 2020 to the packages below 100pin. Update electrical characteristics. Modify some function definition of 1.6 TIMER pins and other description Sep. 11, 2020 changes. 1. Modify the function definition of PB15(TIMER11_CH1). 2. TSTG range changed from -55 +150 °C to -65 - 150 °C in section 4.1 Absolute maximum ratings. 3. Modify the description of Supply current (Deep-Sleep mode) in section 1.7 4.3. Power Jan. 4, 2021 consumption. 4. Add I2C timing diagram, modify SPI timing diagram and add I2S timing diagram in section 4.16. I2C characteristics, 4.17. SPI characteristics, 4.18. I2S characteristics. 5. Adjust the number of modules and delete CAN. 1.8 Electrical characteristics update. 1. 1.9 Feb. 25, 2021 Update I2C timing diagram and proofread WDGT min-max timeout value. VIN maximum value cannot exceed 6.5 Dec. 13, 2021 V, 85 GD32E103xx Datasheet changed to 5.5V in Table 4-1. Absolute maximum ratings. 2. Update LQFP100_14X14, LQFP64_10X10, LQFP48_7X7 and QFN36-6X6 package outline and package dimensions, increase recommended footprint, increase thermal resistance description section and parameter section content. 3. Change the LQFP176 and LQFP144 POD diagrams, and add eB parameters to the POD parameters in packages below LQFP100 in section LQFP100 package and dimensions 5.1. outline delete the temperature information in the Condition in resistance the in thermal section 5. Package information. 4. Modify Table 4-1. Absolute maximum ratings and Table 4 12. ESD characteristics. Delete ETM support. 1. Modify wrong pin number in Jul. 1, 2022 LQFP64 POD in section 5.1. LQFP100 package outline dimensions. 2. 1.10 Modify IIC section parameters 4.16. in I2C characteristics. 3. Modify pins name in section 2.6. Pin definitions. 4. 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