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GD32F103T8U6

GD32F103T8U6

  • 厂商:

    GIGADEVICE(兆易创新)

  • 封装:

    QFN-36

  • 描述:

    GD32F103T8U6

  • 数据手册
  • 价格&库存
GD32F103T8U6 数据手册
GigaDevice Semiconductor Inc. GD32F103xx Arm® Cortex®-M3 32-bit MCU Datasheet GD32F103xx Datasheet Table of Contents Table of Contents ........................................................................................................... 1 List of Figures ................................................................................................................ 4 List of Tables .................................................................................................................. 5 1. General description ................................................................................................. 7 2. Device overview ....................................................................................................... 8 2.1. Device information .......................................................................................................... 8 2.2. Block diagram ............................................................................................................... 12 2.3. Pinouts and pin assignment ........................................................................................ 14 2.4. Memory map .................................................................................................................. 18 2.5. Clock tree ...................................................................................................................... 22 2.6. Pin definitions ............................................................................................................... 23 2.6.1. GD32F103Zx LQFP144 pin definitions ................................................................................. 23 2.6.2. GD32F103Vx LQFP100 pin definitions ................................................................................ 31 2.6.3. GD32F103Rx LQFP64 pin definitions .................................................................................. 38 2.6.4. GD32F103Cx LQFP48 pin definitions .................................................................................. 42 2.6.5. GD32F103Tx QFN36 pin definitions .................................................................................... 45 3. Functional description .......................................................................................... 47 3.1. Arm® Cortex®-M3 core .................................................................................................. 47 3.2. On-chip memory ........................................................................................................... 47 3.3. Clock, reset and supply management ......................................................................... 48 3.4. Boot modes ................................................................................................................... 48 3.5. Power saving modes .................................................................................................... 50 3.6. Analog to digital converter (ADC) ................................................................................ 50 3.7. Digital to analog converter (DAC) ................................................................................ 51 3.8. DMA ............................................................................................................................... 51 3.9. General-purpose inputs/outputs (GPIOs) .................................................................... 51 3.10. Timers and PWM generation ................................................................................. 52 3.11. Real time clock (RTC) ............................................................................................ 53 3.12. Inter-integrated circuit (I2C) .................................................................................. 53 3.13. Serial peripheral interface (SPI) ............................................................................ 54 1 GD32F103xx Datasheet 3.14. Universal synchronous asynchronous receiver transmitter (USART) ............... 54 3.15. Inter-IC sound (I2S) ................................................................................................ 54 3.16. Secure digital input and output card interface (SDIO) ......................................... 55 3.17. Universal serial bus full-speed device (USBD) .................................................... 55 3.18. Controller area network (CAN) .............................................................................. 55 3.19. External memory controller (EXMC) ..................................................................... 55 3.20. Debug mode ........................................................................................................... 56 3.21. Package and operation temperature ..................................................................... 56 4. Electrical characteristics ....................................................................................... 57 4.1. Absolute maximum ratings .......................................................................................... 57 4.2. Operating conditions characteristics .......................................................................... 57 4.3. Power consumption ...................................................................................................... 59 4.4. EMC characteristics ...................................................................................................... 67 4.5. Power supply supervisor characteristics.................................................................... 68 4.6. Electrical sensitivity ..................................................................................................... 69 4.7. External clock characteristics...................................................................................... 70 4.8. Internal clock characteristics ....................................................................................... 72 4.9. PLL characteristics ....................................................................................................... 74 4.10. Memory characteristics ......................................................................................... 75 4.11. NRST pin characteristics ....................................................................................... 76 4.12. GPIO characteristics .............................................................................................. 76 4.13. ADC characteristics ............................................................................................... 80 4.14. Temperature sensor characteristics ..................................................................... 82 4.15. DAC characteristics ............................................................................................... 82 4.16. I2C characteristics ................................................................................................. 83 4.17. SPI characteristics ................................................................................................. 84 4.18. I2S characteristics.................................................................................................. 85 4.19. USART characteristics ........................................................................................... 87 4.20. SDIO characteristics .............................................................................................. 87 4.21. CAN characteristics ............................................................................................... 88 4.22. USBD characteristics ............................................................................................. 88 2 GD32F103xx Datasheet 4.23. EXMC characteristics............................................................................................. 89 4.24. TIMER characteristics ............................................................................................ 91 4.25. WDGT characteristics ............................................................................................ 91 4.26. Parameter conditions............................................................................................. 92 5. Package information.............................................................................................. 93 5.1 LQFP144 package outline dimensions ........................................................................ 93 5.2 LQFP100 package outline dimensions ........................................................................ 95 5.3 LQFP64 package outline dimensions .......................................................................... 97 5.4 LQFP48 package outline dimensions .......................................................................... 99 5.5 QFN36 package outline dimensions .......................................................................... 101 5.6 Thermal characteristics .............................................................................................. 103 6. Ordering Information ........................................................................................... 105 7. Revision History................................................................................................... 107 3 GD32F103xx Datasheet List of Figures Figure 2-1. GD32F103x4/6/8/B block diagram ......................................................................................... 12 Figure 2-2. GD32F103xC/D/E/F/G/I/K block diagram .............................................................................. 13 Figure 2-3. GD32F103Zx LQFP144 pinouts ............................................................................................. 14 Figure 2-4. GD32F103Vx LQFP100 pinouts ............................................................................................. 15 Figure 2-5. GD32F103Rx LQFP64 pinouts .............................................................................................. 16 Figure 2-6. GD32F103Cx LQFP48 pinouts .............................................................................................. 16 Figure 2-7. GD32F103Tx QFN36 pinouts ................................................................................................. 17 Figure 2-8. GD32F103xx clock tree .......................................................................................................... 22 Figure 4-1. Recommended power supply decoupling capacitors (1) (2) ................................................. 58 Figure 4-2. Typical supply current consumption in Run mode (For GD32F103x4/6/8/B devices) .... 66 Figure 4-3. Typical supply current consumption in Run mode (For GD32F103xC/D/E/F/G/I/K devices) ...................................................................................................................................................... 66 Figure 4-4. Typical supply current consumption in Sleep mode (For GD32F103x4/6/8/B devices) .. 66 Figure 4-5. Typical supply current consumption in Sleep mode (For GD32F103xC/D/E/F/G/I/K devices) ...................................................................................................................................................... 67 Figure 4-6. Recommended external NRST pin circuit(1) ......................................................................... 76 Figure 4-7. I2C bus timing diagram.......................................................................................................... 84 Figure 4-8. SPI timing diagram - master mode ....................................................................................... 85 Figure 4-9. SPI timing diagram - slave mode .......................................................................................... 85 Figure 4-10. I2S timing diagram - master mode ..................................................................................... 86 Figure 4-11. I2S timing diagram - slave mode ........................................................................................ 87 Figure 4-12. USBD timings: definition of data signal rise and fall time ............................................... 89 Figure 5-1. LQFP144 package outline ..................................................................................................... 93 Figure 5-2. LQFP144 recommended footprint ........................................................................................ 94 Figure 5-3. LQFP100 package outline ..................................................................................................... 95 Figure 5-4. LQFP100 recommended footprint ........................................................................................ 96 Figure 5-5. LQFP64 package outline ....................................................................................................... 97 Figure 5-6. LQFP64 recommended footprint .......................................................................................... 98 Figure 5-7. LQFP48 package outline ....................................................................................................... 99 Figure 5-8. LQFP48 recommended footprint ........................................................................................ 100 Figure 5-9. QFN36 package outline ....................................................................................................... 101 Figure 5-10. QFN36 recommended footprint ........................................................................................ 102 4 GD32F103xx Datasheet List of Tables Table 2-1. GD32F103xx devices features and peripheral list .................................................................. 8 Table 2-2. GD32F103xx devices features and peripheral list (continued) ............................................. 9 Table 2-3. GD32F103xx devices features and peripheral list (continued) ............................................ 11 Table 2-4. GD32F103xx memory map ...................................................................................................... 18 Table 2-5. GD32F103Zx LQFP144 pin definitions ................................................................................... 23 Table 2-6. GD32F103Vx LQFP100 pin definitions ................................................................................... 31 Table 2-7. GD32F103Rx LQFP64 pin definitions .................................................................................... 38 Table 2-8. GD32F103Cx LQFP48 pin definitions .................................................................................... 42 Table 2-9. GD32F103Tx QFN36 pin definitions ....................................................................................... 45 Table 4-1. Absolute maximum ratings (1)(4) .............................................................................................. 57 Table 4-2. DC operating conditions ......................................................................................................... 57 Table 4-3. Clock frequency(1) .................................................................................................................... 58 Table 4-4. Operating conditions at Power up/ Power down (1) .............................................................. 58 Table 4-5. Start-up timings of Operating conditions (For GD32F103x4/6/8/B devices)(1)(2)(3) ............. 58 Table 4-6. Start-up timings of Operating conditions (For GD32F103xC/D/E/F/G/I/K devices)(1)(2)(3) .. 58 Table 4-7. Power saving mode wakeup timings characteristics (for GD32F103x4/6/8/B devices)(1)(2) ..................................................................................................................................................................... 59 Table 4-8. Power saving mode wakeup timings characteristics (for GD32F103xC/D/E/F/G/I/K devices)(1)(2) ................................................................................................................................................. 59 Table 4-9. Power consumption characteristics (for GD32F103x4/6/8/B devices) (2)(3)(4)(5).................... 59 Table 4-10. Power consumption characteristics (for GD32F103xC/D/E/F/G/I/K devices) (2)(3)(4)(5) ....... 63 Table 4-11. EMS characteristics (1) ........................................................................................................... 67 Table 4-12. Power supply supervisor characteristics (For GD32F103x4/6/8/B devices) ................... 68 Table 4-13. Power supply supervisor characteristics (For GD32F103xC/D/E/F/G/I/K devices) ......... 68 Table 4-14. ESD characteristics (1) ............................................................................................................ 69 Table 4-15. Static latch-up characteristics (1) .......................................................................................... 70 Table 4-16. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics(For GD32F103x4/6/8/B devices) .................................................................................... 70 Table 4-17. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics(For GD32F103xC/D/E/F/G/I/K devices) .......................................................................... 70 Table 4-18. High speed external clock characteristics (HXTAL in bypass mode) .............................. 71 Table 4-19. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics(For GD32F103x4/6/8/B devices) ...................................................................................................................... 71 Table 4-20. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics(For GD32F103xC/D/E/F/G/I/K devices) ........................................................................................................... 71 Table 4-21. Low speed external user clock characteristics (LXTAL in bypass mode) ....................... 72 Table 4-22. High speed internal clock (IRC8M) characteristics (For GD32F103x4/6/8/B devices) .... 72 Table 4-23. High speed internal clock (IRC8M) characteristics (For GD32F103 xC/D/E/F/G/I/K devices) ...................................................................................................................................................... 73 Table 4-24. Low speed internal clock (IRC40K) characteristics (For GD32F103x4/6/8/B devices) ... 73 5 GD32F103xx Datasheet Table 4-25. Low speed internal clock (IRC40K) characteristics(For GD32F103 xC/D/E/F/G/I/K devices) ...................................................................................................................................................... 74 Table 4-26. PLL characteristics ................................................................................................................ 74 Table 4-27. Flash memory characteristics (For GD32F103x4/6/8/B devices) ...................................... 75 Table 4-28. Flash memory characteristics (For GD32F103xC/D/E/F/G/I/K devices) ........................... 75 Table 4-29. NRST pin characteristics ...................................................................................................... 76 Table 4-30. I/O port DC characteristics(For GD32F103x4/6/8/B devices)(1) (3) ...................................... 76 Table 4-31. I/O port DC characteristics(For GD32F103xC/D/E/F/G/I/K devices)(1) (3) ........................... 78 Table 4-32. I/O port AC characteristics(For GD32F103x4/6/8/B devices) (1)(2)(4) ................................... 79 Table 4-33. I/O port AC characteristics(For GD32F103xC/D/E/F/G/I/K devices) (1)(2)(4)......................... 80 Table 4-34. ADC characteristics(For GD32F103x4/6/8/B devices) ........................................................ 80 Table 4-35. ADC characteristics(For GD32F103xC/D/E/F/G/I/K devices) ............................................. 81 Table 4-36. ADC RAIN max for fADC = 14 MHz (For GD32F103x4/6/8/B devices) ....................................... 81 Table 4-37. ADC RAIN max for fADC = 14 MHz (For GD32F103xC/D/E/F/G/I/K devices) ............................ 81 Table 4-38. Temperature sensor characteristics (1) ................................................................................ 82 Table 4-39. DAC characteristics(For GD32F103xC/D/E/F/G/I/K devices) ............................................. 82 Table 4-40. I2C characteristics(1) (2)........................................................................................................... 83 Table 4-41. Standard SPI characteristics(1) ............................................................................................. 84 Table 4-42. I2S characteristics (For GD32F103xC/D/E/F/G/I/K devices) (1) (2) ....................................... 85 Table 4-43. USART characteristics(1) ....................................................................................................... 87 Table 4-44. SDIO characteristics (For GD32F103xC/D/E/F/G/I/K devices)(1)(2) ..................................... 87 Table 4-45. USBD start up time (For GD32F103x4/6/8/B devices) ........................................................ 88 Table 4-46. USBD start up time (For GD32F103xC/D/E/F/G/I/K devices).............................................. 88 Table 4-47. USBD DC electrical characteristics (For GD32F103x4/6/8/B devices) ............................. 88 Table 4-48. USBD DC electrical characteristics (For GD32F103xC/D/E/F/G/I/K devices) ................... 88 Table 4-49. USBD full speed-electrical characteristics (For GD32F103x4/6/8/B devices) (1) .............. 89 Table 4-50. USBD full speed-electrical characteristics (For GD32F103xC/D/E/F/G/I/K devices)(1) .... 89 Table 4-51. Synchronous multiplexed PSRAM/NOR read timings(1)(2)(3)............................................... 89 Table 4-52. Synchronous multiplexed PSRAM write timings(1)(2)(3) ....................................................... 90 Table 4-53. Synchronous non-multiplexed PSRAM/NOR read timings(1)(2)(3) ....................................... 90 Table 4-54. Synchronous non-multiplexed PSRAM write timings(1)(2)(3) ............................................... 91 Table 4-55. TIMER characteristics(1) ........................................................................................................ 91 Table 4-56. FWDGT min/max timeout period at 40 kHz (IRC40K)(1) ...................................................... 91 Table 4-57. WWDGT min-max timeout value at 54 MHz (fPCLK1)(1).......................................................... 92 Table 5-1. LQFP144 package dimensions ............................................................................................... 93 Table 5-2. LQFP100 package dimensions ............................................................................................... 95 Table 5-3. LQFP64 package dimensions ................................................................................................. 97 Table 5-4. LQFP48 package dimensions ................................................................................................. 99 Table 5-5. QFN36 package dimensions ................................................................................................. 101 Table 5-6. Package thermal characteristics(1) ....................................................................................... 103 Table 6-1. Part ordering code for GD32F103xx devices ...................................................................... 105 Table 7-1. Revision history ..................................................................................................................... 107 6 GD32F103xx Datasheet 1. General description The GD32F103xx device is a 32-bit general-purpose microcontroller based on the Arm® Cortex®-M3 RISC core with best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F103xx device incorporates the Arm® Cortex®-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general 16-bit timers, two basic timers plus two PWM advanced timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, an USBD, a CAN and a SDIO. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F103xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, video intercom, PC peripherals and so on. 7 GD32F103xx Datasheet 2. Device overview 2.1. Device information Table 2-1. GD32F103xx devices features and peripheral list GD32F103xx Part Number Code Area Flash (KB) Data Area (KB) Total (KB) Timers SRAM (KB) Connectivity T6 T8 TB C4 C6 C8 CB R4 R6 R8 RB V8 VB 16 32 64 128 16 32 64 128 16 32 64 128 64 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 32 64 128 16 32 64 128 16 32 64 128 64 128 6 10 20 20 6 10 20 20 6 10 20 20 20 20 General 2 2 3 3 2 2 3 3 2 2 3 3 3 3 timer(16-bit) (1-2) (1-2) (1-3) (1-3) (1-2) (1-2) (1-3) (1-3) (1-2) (1-2) (1-3) (1-3) (1-3) (1-3) Advanced 1 1 1 1 1 1 1 1 1 1 1 1 1 1 timer(16-bit) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) SysTick 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 3 3 2 2 3 3 3 3 (0-1) (0-1) (0-1) (0-1) (0-1) (0-1) (0-2) (0-2) (0-1) (0-1) (0-2) (0-2) (0-2) (0-2) 1 1 1 1 1 1 2 2 1 1 2 2 2 2 (0) (0) (0) (0) (0) (0) (0-1) (0-1) (0) (0) (0-1) (0-1) (0-1) (0-1) 1 1 1 1 1 1 2 2 1 1 2 2 2 2 (0) (0) (0) (0) (0) (0) (0-1) (0-1) (0) (0) (0-1) (0-1) (0-1) (0-1) CAN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 USBD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO 26 26 26 26 37 37 37 37 51 51 51 51 80 80 EXMC 0 0 0 0 0 0 0 0 0 0 0 0 1 1 EXTI 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Units 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Channels 10 10 10 10 10 10 10 10 16 16 16 16 16 16 USART ADC T4 I2C SPI Package QFN36 LQFP48 LQFP64 LQFP100 8 GD32F103xx Datasheet Table 2-2. GD32F103xx devices features and peripheral list (continued) GD32F103xx Part Number RC Code Area Flash (KB) Data Area (KB) Total (KB) SRAM (KB) General timer(16- RE RF RG RK VC VD VF VG 256 256 256 256 256 256 256 256 256 256 256 256 512 768 1792 2816 0 128 256 512 768 1792 2816 0 RD 128 256 RI VE VI VK 256 256 256 384 512 768 1024 2048 3072 256 384 512 768 1024 2048 3072 48 96 64 64 64 96 96 96 48 64 96 96 96 96 4 4 4 10 10 10 10 4 4 4 10 10 10 10 (1-4) (1-4) (1-4) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4) (1-4) (1-4) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit) Advanced Timers timer(16bit) SysTick Basic 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) Watchdog 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 USART 3 3 3 3 3 3 3 3 3 3 3 3 3 3 UART 2 2 2 2 2 2 2 2 2 2 2 2 2 2 I2C 2 2 2 2 2 2 2 2 2 2 2 2 2 2 timer(16- Connectivity bit) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) CAN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 USBD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO 51 51 51 51 51 51 51 80 80 80 80 80 80 80 EXMC 0 0 0 0 0 0 0 1 1 1 1 1 1 1 EXTI 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Units 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Channels 16 16 16 16 16 16 16 16 16 16 16 16 16 16 SPI I2S ADC SDIO 9 GD32F103xx Datasheet GD32F103xx Part Number DAC Package RC RD RE RF RG RI RK VC VD VE VF VG VI VK 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LQFP64 LQFP100 10 GD32F103xx Datasheet Table 2-3. GD32F103xx devices features and peripheral list (continued) GD32F103xx Flash Part Number ZC ZD ZE ZF ZG ZI ZK Code Area (KB) 256 256 256 256 256 256 256 Data Area (KB) 0 128 256 512 768 1792 2816 Total (KB) 256 384 512 768 1024 2048 3072 48 64 64 96 96 96 96 Connectivity Timers SRAM (KB) General 4 4 4 10 10 10 10 timer(16-bit) (1-4) (1-4) (1-4) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) Advanced 2 2 2 2 2 2 2 timer(16-bit) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) SysTick 1 1 1 1 1 1 1 Basic timer(16- 2 2 2 2 2 2 2 bit) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) Watchdog 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 USART 3 3 3 3 3 3 3 UART 2 2 2 2 2 2 2 I2C 2 2 2 2 2 2 2 3 3 3 3 3 3 3 (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) CAN 1 1 1 1 1 1 1 USBD 1 1 1 1 1 1 1 SPI 2 2 2 2 2 2 2 (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) 1 1 1 1 1 1 1 GPIO 112 112 112 112 112 112 112 EXMC 1 1 1 1 1 1 1 EXTI 16 16 16 16 16 16 16 Units 3 3 3 3 3 3 3 Channels 21 21 21 21 21 21 21 2 2 2 2 2 2 2 I2S ADC SDIO DAC Package LQFP144 11 GD32F103xx Datasheet 2.2. Block diagram Figure 2-1. GD32F103x4/6/8/B block diagram TPIU SW/JTAG Flash Memory Controller Ibus Flash Memory PLL Fmax: 108MHz Dbus FMC Master DMA0 7chs AHB Matrix: Fmax = 108MHz NVIC ICode DCode System ARM Cortex-M3 Processor Fmax: 108MHz POR/PDR Master EXMC Slave Slave LDO 1.2V RCU AHB Peripherals Slave Slave CRC SRAM Controller AHB to APB Bridge 2 IRC 8MHz SRAM HXTAL 4-16MHz AHB to APB Bridge 1 LVD Interrput request CAN0 USART0 Slave 12-bit SAR ADC Slave WWDGT ADC0 TIMER1 ADC1 TIMER2 GPIOA TIMER3 GPIOB GPIOC GPIOD APB1: Fmax = 54MHz SPI0 APB2: Fmax = 108MHz Powered By V DDA Powered By V DDA SPI1 USART1 USART2 GPIOE I2C0 TIMER0 I2C1 EXTI USBD FWDGT RTC 12 GD32F103xx Datasheet Figure 2-2. GD32F103xC/D/E/F/G/I/K block diagram POR/PDR TPIU SW/JTAG DMA0 7chs DMA1 5chs PLL Ibus Dbus Master Master AHB Matrix: Fmax = 108MHz NVIC ICode DCode System ARM Cortex-M3 Processor Fmax: 108MHz Master Flash Memory Controller 1 Flash Memory Flash Memory Controller 2 Flash Memory FMC CRC Fmax: 108MHz LDO 1.2V RCU IRC 8MHz AHB Peripherals Slave EXMC HXTAL 4-16MHz Slave Slave SRAM Controller SRAM SDIO LVD Slave Slave AHB to APB Bridge 2 AHB to APB Bridge 1 Powered By V DDA Interrput request CAN0 USART0 Slave SPI0 Slave WWDGT TIMER1 ADC0 12-bit SAR ADC GPIOB GPIOC APB1: Fmax = 54MHz GPIOA TIMER3 APB2: Fmax = 108MHz ADC2 Powered By V DDA TIMER2 ADC1 TIMER4 TIMER11 TIMER12 TIMER13 GPIOD SPI1/I2S1 GPIOE SPI2/I2S2 GPIOF USART1 GPIOG USART2 TIMER0 UART3 TIMER7 UART4 TIMER8 I2C0 TIMER9 TIMER5 I2C1 TIMER10 TIMER6 USBD EXTI DAC0 DAC1 FWDGT RTC : Blocks are available in GD32F103xF/G/I/K devices 13 GD32F103xx Datasheet 2.3. Pinouts and pin assignment Figure 2-3. GD32F103Zx LQFP144 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109 PE2 1 108 PE3 PE4 2 107 VSS_2 3 106 NC PE5 PE6 4 105 PA13 5 104 PA12 VBAT 6 103 PA11 PC13-TAMPER-RTC PC14-OSC32IN 7 102 PA10 8 101 PA9 PC15-OSC32OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 98 PC8 PF2 12 97 PC7 PF3 PF4 13 96 PC6 14 95 VDD_9 PF5 15 94 VSS_9 VSS_5 16 93 PG8 92 PG7 91 PG6 90 PG5 89 PG4 88 PG3 VDD_2 VDD_5 17 PF6 18 PF7 19 PF8 20 PF9 21 PF10 22 87 PG2 OSCIN 23 86 PD15 OSCOUT 24 85 PD14 NRST 25 84 VDD_8 PC0 26 83 VSS_8 PC1 27 82 PD13 PC2 28 81 PD12 PC3 VSSA 29 80 PD11 30 79 PD10 VREFVREF+ 31 78 PD9 32 77 PD8 VDDA 33 76 PB15 PA0_WKUP 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 GigaDevice GD32F103Zx LQFP144 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD_1 VSS_1 PB11 PB10 PE15 PE13 PE14 PE12 PE11 VDD_7 PE10 VSS_7 PE8 PE9 PE7 PG1 PG0 PF15 PF14 VDD_6 PF13 VSS_6 PF12 PB2 PF11 PB1 PC5 PB0 PA7 PC4 PA6 PA5 VDD_4 PA4 VSS_4 PA3 14 GD32F103xx Datasheet Figure 2-4. GD32F103Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS_2 3 73 NC PE5 PE6 4 72 PA13 5 71 PA12 VBAT 6 PC13-TAMPER-RTC PC14-OSC32IN 7 70 69 PA10 8 68 PA9 PC15-OSC32OUT 9 67 PA8 VSS_5 10 66 PC9 VDD_5 11 65 PC8 64 PC7 63 PC6 14 62 PD15 OSCIN 12 GigaDevice GD32F103Vx LQFP100 VDD_2 PA11 OSCOUT NRST PC0 13 15 61 PD14 PC1 16 60 PD13 PC2 PC3 17 59 PD12 18 58 PD11 VSSA 19 57 PD10 VREFVREF+ 20 56 PD9 21 55 PD8 VDDA 22 54 PB15 PA0-WKUP 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS_1 VDD_1 PB11 PB10 PE15 PE14 PE13 PE11 PE12 PE10 PE9 PE8 PE7 PB2 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VDD_4 PA3 VSS_4 15 GD32F103xx Datasheet Figure 2-5. GD32F103Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PD2 PC12 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 VDD_2 PC13-TAMPER-RTC 2 47 VSS_2 PA13 PC14-OSC32IN 3 46 PC15-OSC32OUT OSCIN 4 45 PA12 5 44 PA11 OSCOUT 6 43 PA10 NRST PC0 7 42 PA9 PC1 9 PC2 PC3 VSSA GigaDevice GD32F103Rx LQFP64 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0-WKUP 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_1 VSS_1 PA15 PB11 PB1 PB10 PB0 PB3 PB2 PC5 PB4 PC4 PA7 PA6 PA5 PA4 VDD_4 VSS_4 PA3 Figure 2-6. GD32F103Cx LQFP48 pinouts PA14 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 48 47 46 45 44 43 42 41 40 39 38 37 VBAT 1 36 VDD_2 PC13-TAMPER-RTC 2 35 VSS_2 PC14-OSC32IN 3 34 PA13 PC15-OSC32OUT OSCIN 4 33 PA12 5 32 PA11 OSCOUT NRST VSSA 6 31 PA10 30 PA9 8 29 VDDA 9 28 PA8 PB15 PA0-WKUP 10 27 PB14 PA1 PA2 11 26 PB13 12 25 PB12 GigaDevice GD32F103Cx LQFP48 7 13 14 15 16 17 18 19 20 21 22 23 24 VSS_1 VDD_1 PB11 PB10 PB2 PB1 PA7 PB0 PA6 PA5 PA4 PA3 16 GD32F103xx Datasheet Figure 2-7. GD32F103Tx QFN36 pinouts PA14 PA2 PA15 PA1 PB3 PB4 PA0-WKUP PB5 VDDA PB6 OSCIN OSCOUT NRST VSSA PB7 BOOT0 VSS_3 VDD_3 36 35 34 33 32 31 30 29 28 1 27 2 26 VDD_2 3 25 PA13 24 5 GigaDevice GD32F103Tx 23 QFN36 6 22 7 21 PA12 PA9 8 PA8 4 20 9 19 10 11 12 13 14 15 16 17 18 VSS_2 PA11 PA10 VDD_1 VSS_1 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 17 GD32F103xx Datasheet 2.4. Memory map Table 2-4. GD32F103xx memory map Pre-defined Regions Bus External device AHB Address Peripherals 0xA000 0000 - 0xA000 0FFF EXMC - SWREG 0x9000 0000 - 0x9FFF FFFF EXMC - PC CARD 0x7000 0000 - 0x8FFF FFFF EXMC - NAND External RAM EXMC 0x6000 0000 - 0x6FFF FFFF NOR/PSRAM/SRA M Peripheral AHB 0x5000 0000 - 0x5003 FFFF Reserved 0x4008 0000 - 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF Reserved 0x4002 BC00 - 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF Reserved 0x4002 6000 - 0x4002 63FF Reserved 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Reserved 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF Reserved 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1C00 - 0x4002 1FFF Reserved 0x4002 1800 - 0x4002 1BFF Reserved 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF RCU 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 18 GD32F103xx Datasheet Pre-defined Regions Bus APB2 APB1 Address Peripherals 0x4001 8000 - 0x4001 83FF SDIO 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF Reserved 0x4001 6C00 - 0x4001 6FFF Reserved 0x4001 6800 - 0x4001 6BFF Reserved 0x4001 5C00 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF Reserved 0x4001 5400 - 0x4001 57FF TIMER10 0x4001 5000 - 0x4001 53FF TIMER9 0x4001 4C00 - 0x4001 4FFF TIMER8 0x4001 4800 - 0x4001 4BFF Reserved 0x4001 4400 - 0x4001 47FF Reserved 0x4001 4000 - 0x4001 43FF Reserved 0x4001 3C00 - 0x4001 3FFF ADC2 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF TIMER7 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF TIMER0 0x4001 2800 - 0x4001 2BFF ADC1 0x4001 2400 - 0x4001 27FF ADC0 0x4001 2000 - 0x4001 23FF GPIOG 0x4001 1C00 - 0x4001 1FFF GPIOF 0x4001 1800 - 0x4001 1BFF GPIOE 0x4001 1400 - 0x4001 17FF GPIOD 0x4001 1000 - 0x4001 13FF GPIOC 0x4001 0C00 - 0x4001 0FFF GPIOB 0x4001 0800 - 0x4001 0BFF GPIOA 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF Reserved 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PMU 19 GD32F103xx Datasheet Pre-defined Regions Bus Address Peripherals 0x4000 6C00 - 0x4000 6FFF BKP 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF CAN0 0x4000 6000 - 0x4000 63FF SRAM Code AHB AHB Shared USBD/CAN SRAM 512 bytes 0x4000 5C00 - 0x4000 5FFF USBD 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF UART3 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1C00 - 0x4000 1FFF TIMER12 0x4000 1800 - 0x4000 1BFF TIMER11 0x4000 1400 - 0x4000 17FF TIMER6 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF Reserved 0x2003 0000 - 0x2005 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2001 C000 - 0x2001 FFFF Reserved 0x2001 8000 - 0x2001 BFFF Reserved 0x2000 0000 - 0x2001 7FFF SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF B000 - 0x1FFF F7FF Boot loader 0x1FFF 7A10 - 0x1FFF AFFF Reserved 20 GD32F103xx Datasheet Pre-defined Regions Bus Address Peripherals 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 0000 - 0x1FFF 77FF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Reserved 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF Reserved 0x083C 0000 - 0x0FFF FFFF Reserved 0x0830 0000 - 0x083B FFFF Reserved 0x0800 0000 - 0x082F FFFF Main Flash 0x0030 0000 - 0x07FF FFFF Reserved 0x0000 0000 - 0x002F FFFF Aliased to Main Flash or Boot loader 21 GD32F103xx Datasheet 2.5. Clock tree Figure 2-8. GD32F103xx clock tree USBD Prescaler ÷1,1.5,2,2.5 CK_USBD 48 MHz (to USBD) CK_I2S I2S enable (to I2S1,2) CK_SDIO SCS[1:0] SDIO enable (to SDIO) CK_EXMC CK_IRC8M 00 8 MHz IRC8M 1 ×2,3,4 …,32 PLL PLLSEL PLLMF 0 /2 CK_PLL 10 (to EXMC) EXMC enable CK_SYS 108 MHz max AHB Prescaler ÷1,2...512 CK_AHB 108 MHz max HCLK AHB enable (to AHB bus,Cortex-M3,SRAM,DMA,FMC) 01 CK_CST ÷8 (to Cortex-M3 SysTick) Clock Monitor /1 or /2 4-16 MHz HXTAL FCLK (free running clock) TIMER1,2,3,4,5,6, 11,12,13 if(APB1 prescale =1)x1 else x 2 CK_HXTAL PREDV0 CK_TIMERx TIMERx enable to TIMER1,2,3,4, 5,6,11,12,13 11 /128 32.768 KHz LXTAL CK_RTC 01 (to RTC) APB1 Prescaler ÷1,2,4,8,16 CK_APB1 PCLK1 54 MHz max to APB1 peripherals 10 RTCSRC[1:0] 40 KHz IRC40K CK_OUT0 Peripheral enable CK_FWDGT (to FWDGT) 0xx 100 101 110 111 NO CLK CK_SYS CK_IRC8M CK_HXTAL /2 CK_PLL TIMER0,7,8,9,10 if(APB2 prescale =1)x1 else x 2 APB2 Prescaler ÷1,2,4,8,16 CK_TIMERx TIMERx enable to TIMER0,7,8,9,10 CK_APB2 PCLK2 108 MHz max Peripheral enable ADC Prescaler ÷2,4,8,12,16 to APB2 peripherals CK_ADCX to ADC0,ADC1,ADC2 14 MHz max CKOUT0SEL[2:0] Legend: HXTAL: High speed external clock LXTAL: Low speed external clock IRC8M: High speed internal clock IRC40K: Low speed internal clock 22 GD32F103xx Datasheet 2.6. Pin definitions 2.6.1. GD32F103Zx LQFP144 pin definitions Table 2-5. GD32F103Zx LQFP144 pin definitions Pin I/O Type(1) Level(2) 1 I/O 5VT PE3 2 I/O 5VT PE4 3 I/O 5VT PE5 4 I/O 5VT Pin Name Pins PE2 Functions description Default: PE2 Alternate: TRACECK, EXMC_A23 Default: PE3 Alternate: TRACED0, EXMC_A19 Default: PE4 Alternate:TRACED1, EXMC_A20 Default: PE5 Alternate:TRACED2, EXMC_A21 Remap: TIMER8_CH0(3) Default: PE6 PE6 5 I/O 5VT Alternate:TRACED3, EXMC_A22 Remap: TIMER8_CH1(3) VBAT Default: VBAT 6 P 7 I/O 8 I/O 9 I/O PF0 10 I/O 5VT PF1 11 I/O 5VT PF2 12 I/O 5VT PF3 13 I/O 5VT PF4 14 I/O 5VT PF5 15 I/O 5VT VSS_5 16 P Default: VSS_5 VDD_5 17 P Default: VDD_5 PF6 18 I/O Default: PF6 PC13TAMPER- Default: PC13 Alternate: TAMPER-RTC RTC PC14OSC32IN PC15OSC32OUT Default: PC14 Alternate: OSC32IN Default: PC15 Alternate: OSC32OUT Default: PF0 Alternate: EXMC_A0 Default: PF1 Alternate: EXMC_A1 Default: PF2 Alternate: EXMC_A2 Default: PF3 Alternate: EXMC_A3 Default: PF4 Alternate: EXMC_A4 Default: PF5 Alternate: EXMC_A5 23 GD32F103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: ADC2_IN4, EXMC_NIORD Remap: TIMER9_CH0(3) Default: PF7 PF7 19 I/O Alternate: ADC2_IN5, EXMC_NREG Remap: TIMER10_CH0(3) Default: PF8 PF8 20 I/O Alternate: ADC2_IN6, EXMC_NIOWR Remap: TIMER12_CH0(3) Default: PF9 PF9 21 I/O Alternate: ADC2_IN7, EXMC_CD Remap: TIMER13_CH0(3) Default: PF10 PF10 22 I/O OSCIN 23 I OSCOUT 24 O NRST 25 I/O PC0 26 I/O PC1 27 I/O PC2 28 I/O PC3 29 I/O VSSA 30 P Default: VSSA VREF- 31 P Default: VREF- VREF+ 32 P Default: VREF+ VDDA 33 P Default: VDDA PA0-WKUP 34 I/O Alternate: ADC2_IN8, EXMC_INTR Default: OSCIN Remap: PD0 Default: OSCOUT Remap: PD1 Default: NRST Default: PC0 Alternate: ADC012_IN10 Default: PC1 Alternate: ADC012_IN11 Default: PC2 Alternate: ADC012_IN12 Default: PC3 Alternate: ADC012_IN13 Default: PA0 Alternate: WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI Default: PA1 PA1 35 I/O Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1 Default: PA2 PA2 36 I/O Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2, TIMER8_CH0(3) Default: PA3 PA3 37 I/O Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1(3) 24 GD32F103xx Datasheet Pin I/O Type(1) Level(2) Pin Name Pins Functions description VSS_4 38 P Default: VSS_4 VDD_4 39 P Default: VDD_4 Default: PA4 PA4 40 Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, I/O DAC_OUT0 Remap:SPI2_NSS, I2S2_WS PA5 41 Default: PA5 I/O Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 42 Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, I/O TIMER7_BRKIN, TIMER12_CH0(3) Remap: TIMER0_BRKIN Default: PA7 PA7 43 Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, I/O TIMER7_CH0_ON, TIMER13_CH0(3) Remap: TIMER0_CH0_ON PC4 44 I/O PC5 45 I/O Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 PB0 46 Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON I/O Remap: TIMER0_CH1_ON Default: PB1 Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON PB1 47 I/O PB2 48 I/O 5VT PF11 49 I/O 5VT PF12 50 I/O 5VT Remap: TIMER0_CH2_ON Default: PB2, BOOT1 Default: PF11 Alternate: EXMC_NIOS16 Default: PF12 Alternate: EXMC_A6 VSS_6 51 P Default: VSS_6 VDD_6 52 P Default: VDD_6 PF13 53 I/O 5VT PF14 54 I/O 5VT PF15 55 I/O 5VT PG0 56 I/O 5VT PG1 57 I/O 5VT Default: PF13 Alternate: EXMC_A7 Default: PF14 Alternate: EXMC_A8 Default: PF15 Alternate: EXMC_A9 Default: PG0 Alternate: EXMC_A10 Default: PG1 25 GD32F103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: EXMC_A11 Default: PE7 PE7 58 I/O 5VT Alternate: EXMC_D4 Remap: TIMER0_ETI Default: PE8 PE8 59 I/O 5VT Alternate: EXMC_D5 Remap: TIMER0_CH0_ON Default: PE9 PE9 60 I/O 5VT Alternate: EXMC_D6 Remap: TIMER0_CH0 VSS_7 61 P Default: VSS_7 VDD_7 62 P Default: VDD_7 PE10 63 I/O Default: PE10 5VT Alternate: EXMC_D7 Remap: TIMER0_CH1_ON Default: PE11 PE11 64 I/O 5VT Alternate: EXMC_D8 Remap: TIMER0_CH1 Default: PE12 PE12 65 I/O 5VT Alternate: EXMC_D9 Remap: TIMER0_CH2_ON Default: PE13 PE13 66 I/O 5VT Alternate: EXMC_D10 Remap: TIMER0_CH2 Default: PE14 PE14 67 I/O 5VT Alternate: EXMC_D11 Remap: TIMER0_CH3 Default: PE15 PE15 68 I/O 5VT Alternate: EXMC_D12 Remap: TIMER0_BRKIN Default: PB10 PB10 69 I/O 5VT Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 Default: PB11 PB11 70 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 VSS_1 71 P Default: VSS_1 VDD_1 72 P Default: VDD_1 PB12 73 I/O 5VT PB13 74 I/O 5VT Default: PB12 Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS Default: PB13 26 GD32F103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK Default: PB14 PB14 75 I/O 5VT Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0(3) Default: PB15 PB15 76 I/O 5VT Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1(3) Default: PD8 PD8 77 I/O 5VT Alternate: EXMC_D13 Remap: USART2_TX Default: PD9 PD9 78 I/O 5VT Alternate: EXMC_D14 Remap: USART2_RX Default: PD10 PD10 79 I/O 5VT Alternate: EXMC_D15 Remap: USART2_CK Default: PD11 PD11 80 I/O 5VT Alternate: EXMC_A16/EXMC_CLE Remap: USART2_CTS Default: PD12 PD12 81 I/O 5VT Alternate: EXMC_A17/EXMC_ALE Remap: TIMER3_CH0, USART2_RTS Default: PD13 PD13 82 I/O 5VT Alternate: EXMC_A18 Remap: TIMER3_CH1 VSS_8 83 P Default: VSS_8 VDD_8 84 P Default: VDD_8 Default: PD14 PD14 85 I/O 5VT Alternate: EXMC_D0 Remap: TIMER3_CH2 Default: PD15 PD15 86 I/O 5VT Alternate: EXMC_D1 Remap: TIMER3_CH3 PG2 87 I/O 5VT PG3 88 I/O 5VT PG4 89 I/O 5VT PG5 90 I/O 5VT Default: PG2 Alternate: EXMC_A12 Default: PG3 Alternate: EXMC_A13 Default: PG4 Alternate: EXMC_A14 Default: PG5 Alternate: EXMC_A15 27 GD32F103xx Datasheet Pin I/O Type(1) Level(2) 91 I/O 5VT PG7 92 I/O 5VT PG8 93 I/O 5VT VSS_9 94 P Default: VSS_9 VDD_9 95 P Default: VDD_9 Pin Name Pins PG6 Functions description Default: PG6 Alternate: EXMC_INT1 Default: PG7 Alternate: EXMC_INT2 Default: PG8 Default: PC6 PC6 96 I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6 Remap: TIMER2_CH0 Default: PC7 PC7 97 I/O 5VT Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7 Remap: TIMER2_CH1 Default: PC8 PC8 98 I/O 5VT Alternate: TIMER7_CH2, SDIO_D0 Remap: TIMER2_CH2 Default: PC9 PC9 99 I/O 5VT Alternate: TIMER7_CH3, SDIO_D1 Remap: TIMER2_CH3 PA8 100 I/O 5VT PA9 101 I/O 5VT PA10 102 I/O 5VT Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT0 Default: PA9 Alternate: USART0_TX, TIMER0_CH1 Default: PA10 Alternate: USART0_RX, TIMER0_CH2 Default: PA11 PA11 103 I/O 5VT Alternate: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3 Default: PA12 PA12 104 I/O 5VT Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP I/O 5VT Default: JTMS, SWDIO PA13 105 NC 106 VSS_2 107 P Default: VSS_2 VDD_2 108 P Default: VDD_2 PA14 109 I/O Remap: PA13 - 5VT Default: JTCK, SWCLK Remap: PA14 Default: JTDI PA15 110 I/O 5VT Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS 28 GD32F103xx Datasheet Pin Name Pins PC10 111 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PC10 Alternate: UART3_TX, SDIO_D2 Remap: USART2_TX, SPI2_SCK, I2S2_CK Default: PC11 PC11 112 I/O 5VT Alternate: UART3_RX, SDIO_D3 Remap: USART2_RX, SPI2_MISO Default: PC12 PC12 113 I/O 5VT Alternate: UART4_TX, SDIO_CK Remap: USART2_CK, SPI2_MOSI, I2S2_SD Default: PD0 PD0 114 I/O 5VT Alternate: EXMC_D2 Remap: CAN0_RX Default: PD1 PD1 115 I/O 5VT Alternate: EXMC_D3 Remap: CAN0_TX PD2 116 I/O 5VT PD3 117 I/O 5VT Default: PD2 Alternate: TIMER2_ETI, SDIO_CMD, UART4_RX Default: PD3 Alternate: EXMC_CLK Remap: USART1_CTS Default: PD4 PD4 118 I/O 5VT Alternate: EXMC_NOE Remap: USART1_RTS Default: PD5 PD5 119 I/O 5VT Alternate: EXMC_NWE Remap: USART1_TX VSS_10 120 Default: VSS_10 VDD_10 121 Default: VDD_10 Default: PD6 PD6 122 I/O 5VT Alternate: EXMC_NWAIT Remap: USART1_RX Default: PD7 PD7 123 I/O 5VT Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK PG9 124 I/O 5VT PG10 125 I/O 5VT PG11 126 I/O 5VT PG12 127 I/O 5VT Default: PG9 Alternate: EXMC_NE1, EXMC_NCE2 Default: PG10 Alternate: EXMC_NCE3_0, EXMC_NE2 Default: PG11 Alternate: EXMC_NCE3_1 Default: PG12 Alternate: EXMC_NE3 29 GD32F103xx Datasheet Pin I/O Type(1) Level(2) 128 I/O 5VT PG14 129 I/O 5VT VSS_11 130 P Default: VSS_11 VDD_11 131 P Default: VDD_11 PG15 132 I/O Pin Name Pins PG13 5VT Functions description Default: PG13 Alternate: EXMC_A24 Default: PG14 Alternate: EXMC_A25 Default: PG15 Default: JTDO PB3 133 I/O 5VT Alternate:SPI2_SCK, I2S2_CK Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK Default: NJTRST PB4 134 I/O 5VT Alternate: SPI2_MISO Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 135 Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD I/O Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 136 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX Default: PB7 PB7 137 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV Remap: USART0_RX BOOT0 138 Default: BOOT0 I Default: PB8 PB8 139 I/O 5VT Alternate: TIMER3_CH2, SDIO_D4, TIMER9_CH0(3) Remap: I2C0_SCL, CAN0_RX Default: PB9 PB9 140 I/O 5VT Alternate: TIMER3_CH3, SDIO_D5, TIMER10_CH0(3) Remap: I2C0_SDA, CAN0_TX Default: PE0 PE0 141 I/O 5VT PE1 142 I/O 5VT VSS_3 143 P Default: VSS_3 VDD_3 144 P Default: VDD_3 Alternate: TIMER3_ETI, EXMC_NBL0 Default: PE1 Alternate: EXMC_NBL1 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available in GD32F103ZF/G/I/K devices. 30 GD32F103xx Datasheet 2.6.2. GD32F103Vx LQFP100 pin definitions Table 2-6. GD32F103Vx LQFP100 pin definitions Pin I/O Type(1) Level(2) 1 I/O 5VT PE3 2 I/O 5VT PE4 3 I/O 5VT PE5 4 I/O 5VT Pin Name Pins PE2 Functions description Default: PE2 Alternate: TRACECK(4), EXMC_A23 Default: PE3 Alternate: TRACED0(4), EXMC_A19 Default: PE4 Alternate:TRACED1(4), EXMC_A20 Default: PE5 Alternate:TRACED2(4), EXMC_A21 Remap: TIMER8_CH0(3) Default: PE6 PE6 5 I/O 5VT Alternate:TRACED3(4), EXMC_A22 Remap: TIMER8_CH1(3) VBAT Default: VBAT 6 P 7 I/O 8 I/O 9 I/O VSS_5 10 P Default: VSS_5 VDD_5 11 P Default: VDD_5 OSCIN 12 I OSCOUT 13 O NRST 14 I/O PC0 15 I/O PC1 16 I/O PC2 17 I/O PC3 18 I/O VSSA 19 P Default: VSSA VREF- 20 P Default: VREF- PC13TAMPERRTC PC14OSC32IN PC15OSC32OUT Default: PC13 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32IN Default: PC15 Alternate: OSC32OUT Default: OSCIN Remap: PD0 Default: OSCOUT Remap: PD1 Default: NRST Default: PC0 Alternate: ADC012_IN10(5) Default: PC1 Alternate: ADC012_IN11(5) Default: PC2 Alternate: ADC012_IN12(5) Default: PC3 Alternate: ADC012_IN13(5) 31 GD32F103xx Datasheet Pin I/O Type(1) Level(2) Pin Name Pins Functions description VREF+ 21 P Default: VREF+ VDDA 22 P Default: VDDA Default: PA0 PA0-WKUP 23 I/O Alternate: WKUP, USART1_CTS, ADC012_IN0(5), TIMER1_CH0, TIMER1_ETI, TIMER4_CH0(4), TIMER7_ETI(4) Default: PA1 PA1 24 I/O Alternate: USART1_RTS, ADC012_IN1(5), TIMER1_CH1, TIMER4_CH1(4) Default: PA2 PA2 25 I/O Alternate: USART1_TX, ADC012_IN2(5), TIMER1_CH2, TIMER4_CH2(4), TIMER8_CH0(3) Default: PA3 PA3 26 I/O Alternate: USART1_RX, ADC012_IN3(5), TIMER1_CH3, TIMER4_CH3(4), TIMER8_CH1(3) VSS_4 27 P Default: VSS_4 VDD_4 28 P Default: VDD_4 Default: PA4 PA4 29 I/O Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0(4) Remap:SPI2_NSS(4), I2S2_WS(4) PA5 30 I/O Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1(4) Default: PA6 PA6 31 I/O Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN(4), TIMER12_CH0(3) Remap: TIMER0_BRKIN Default: PA7 PA7 32 I/O Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON(4), TIMER13_CH0(3) Remap: TIMER0_CH0_ON PC4 33 I/O PC5 34 I/O Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 PB0 35 I/O Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON(4) Remap: TIMER0_CH1_ON Default: PB1 PB1 36 I/O Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON(4) 32 GD32F103xx Datasheet Pin Name Pins PB2 37 Pin I/O Type(1) Level(2) I/O 5VT Functions description Remap: TIMER0_CH2_ON Default: PB2, BOOT1 Default: PE7 PE7 38 I/O 5VT Alternate: EXMC_D4 Remap: TIMER0_ETI Default: PE8 PE8 39 I/O 5VT Alternate: EXMC_D5 Remap: TIMER0_CH0_ON Default: PE9 PE9 40 I/O 5VT Alternate: EXMC_D6 Remap: TIMER0_CH0 VSS_7 - P Default: VSS_7 VDD_7 - P Default: VDD_7 PE10 41 I/O Default: PE10 5VT Alternate: EXMC_D7 Remap: TIMER0_CH1_ON Default: PE11 PE11 42 I/O 5VT Alternate: EXMC_D8 Remap: TIMER0_CH1 Default: PE12 PE12 43 I/O 5VT Alternate: EXMC_D9 Remap: TIMER0_CH2_ON Default: PE13 PE13 44 I/O 5VT Alternate: EXMC_D10 Remap: TIMER0_CH2 Default: PE14 PE14 45 I/O 5VT Alternate: EXMC_D11 Remap: TIMER0_CH3 Default: PE15 PE15 46 I/O 5VT Alternate: EXMC_D12 Remap: TIMER0_BRKIN Default: PB10 PB10 47 I/O 5VT Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 Default: PB11 PB11 48 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 VSS_1 49 P Default: VSS_1 VDD_1 50 P Default: VDD_1 Default: PB12 PB12 51 I/O 5VT Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS(4) 33 GD32F103xx Datasheet Pin Name Pins PB13 52 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PB13 Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK(4) Default: PB14 PB14 53 I/O 5VT Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0(3) Default: PB15 PB15 54 I/O 5VT Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD(4), TIMER11_CH1(3) Default: PD8 PD8 55 I/O 5VT Alternate: EXMC_D13 Remap: USART2_TX Default: PD9 PD9 56 I/O 5VT Alternate: EXMC_D14 Remap: USART2_RX Default: PD10 PD10 57 I/O 5VT Alternate: EXMC_D15 Remap: USART2_CK Default: PD11 PD11 58 I/O 5VT Alternate: EXMC_A16/EXMC_CLE Remap: USART2_CTS Default: PD12 PD12 59 I/O 5VT Alternate: EXMC_A17/EXMC_ALE Remap: TIMER3_CH0, USART2_RTS Default: PD13 PD13 60 I/O 5VT Alternate: EXMC_A18 Remap: TIMER3_CH1 Default: PD14 PD14 61 I/O 5VT Alternate: EXMC_D0 Remap: TIMER3_CH2 Default: PD15 PD15 62 I/O 5VT Alternate: EXMC_D1 Remap: TIMER3_CH3 Default: PC6 PC6 63 I/O 5VT Alternate: I2S1_MCK(4), TIMER7_CH0(4), SDIO_D6(4) Remap: TIMER2_CH0 Default: PC7 PC7 64 I/O 5VT Alternate: I2S2_MCK(4), TIMER7_CH1(4), SDIO_D7(4) Remap: TIMER2_CH1 Default: PC8 PC8 65 I/O 5VT Alternate: TIMER7_CH2(4), SDIO_D0(4) Remap: TIMER2_CH2 34 GD32F103xx Datasheet Pin Name Pins PC9 66 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PC9 Alternate: TIMER7_CH3(4), SDIO_D1(4) Remap: TIMER2_CH3 PA8 67 I/O 5VT PA9 68 I/O 5VT PA10 69 I/O 5VT PA11 70 I/O 5VT Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT0 Default: PA9 Alternate: USART0_TX, TIMER0_CH1 Default: PA10 Alternate: USART0_RX, TIMER0_CH2 Default: PA11 Alternate: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3 Default: PA12 PA12 71 I/O 5VT Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP I/O 5VT Default: JTMS, SWDIO PA13 72 NC 73 VSS_2 74 P Default: VSS_2 VDD_2 75 P Default: VDD_2 PA14 76 I/O 5VT PA15 77 I/O 5VT Remap: PA13 - Default: JTCK, SWCLK Remap: PA14 Default: JTDI Alternate: SPI2_NSS(4), I2S2_WS(4) Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: PC10 PC10 78 I/O 5VT Alternate: UART3_TX(4), SDIO_D2(4) Remap: USART2_TX, SPI2_SCK(4), I2S2_CK(4) Default: PC11 PC11 79 I/O 5VT Alternate: UART3_RX(4), SDIO_D3(4) Remap: USART2_RX, SPI2_MISO(4) Default: PC12 PC12 80 I/O 5VT Alternate: UART4_TX(4), SDIO_CK(4) Remap: USART2_CK, SPI2_MOSI(4), I2S2_SD(4) Default: PD0 PD0 81 I/O 5VT Alternate: EXMC_D2 Remap: CAN0_RX Default: PD1 PD1 82 I/O 5VT Alternate: EXMC_D3 Remap: CAN0_TX PD2 83 I/O 5VT Default: PD2 Alternate: TIMER2_ETI, SDIO_CMD(4), UART4_RX(4) 35 GD32F103xx Datasheet Pin Name Pins PD3 84 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PD3 Alternate: EXMC_CLK Remap: USART1_CTS Default: PD4 PD4 85 I/O 5VT Alternate: EXMC_NOE Remap: USART1_RTS Default: PD5 PD5 86 I/O 5VT Alternate: EXMC_NWE Remap: USART1_TX Default: PD6 PD6 87 I/O 5VT Alternate: EXMC_NWAIT Remap: USART1_RX Default: PD7 PD7 88 I/O 5VT Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK Default: JTDO PB3 89 I/O 5VT Alternate:SPI2_SCK(4), I2S2_CK(4) Remap: PB3, TRACESWO(4), TIMER1_CH1, SPI0_SCK Default: NJTRST PB4 90 I/O 5VT Alternate: SPI2_MISO(4) Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 91 Alternate: I2C0_SMBA, SPI2_MOSI(4), I2S2_SD(4) I/O Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 92 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX Default: PB7 PB7 93 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV Remap: USART0_RX BOOT0 94 I PB8 95 I/O Default: BOOT0 Default: PB8 5VT Alternate: TIMER3_CH2, SDIO_D4(4), TIMER9_CH0(3) Remap: I2C0_SCL, CAN0_RX Default: PB9 PB9 96 I/O 5VT Alternate: TIMER3_CH3, SDIO_D5(4), TIMER10_CH0(3) Remap: I2C0_SDA, CAN0_TX PE0 97 I/O 5VT PE1 98 I/O 5VT VSS_3 99 P Default: PE0 Alternate: TIMER3_ETI, EXMC_NBL0 Default: PE1 Alternate: EXMC_NBL1 Default: VSS_3 36 GD32F103xx Datasheet Pin Name Pins VDD_3 100 Pin I/O Type(1) Level(2) P Functions description Default: VDD_3 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available in GD32F103VF/G/I/K devices. (4) Functions are available in GD32F103VC/D/E/F/G/I/K devices. (5) ADC2 functions are available in GD32F103VC/D/E/F/G/I/K devices. 37 GD32F103xx Datasheet 2.6.3. GD32F103Rx LQFP64 pin definitions Table 2-7. GD32F103Rx LQFP64 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins VBAT 1 P 2 I/O 3 I/O 4 I/O OSCIN 5 I Default: OSCIN OSCOUT 6 O Default: OSCOUT NRST 7 I/O Default: NRST PC0 8 I/O PC1 9 I/O PC2 10 I/O PC3 11 I/O VSSA 12 P Default: VSSA VDDA 13 P Default: VDDA PC13TAMPERRTC PC14OSC32IN PC15OSC32OUT Functions description Default: VBAT Default: PC13 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32IN Default: PC15 Alternate: OSC32OUT Default: PC0 Alternate: ADC012_IN10(5) Default: PC1 Alternate: ADC012_IN11(5) Default: PC2 Alternate: ADC012_IN12(5) Default: PC3 Alternate: ADC012_IN13(5) Default: PA0 PA0-WKUP 14 I/O Alternate: WKUP, USART1_CTS, ADC012_IN0(5), TIMER1_CH0, TIMER1_ETI, TIMER4_CH0(4), TIMER7_ETI(4) Default: PA1 PA1 15 I/O Alternate: USART1_RTS, ADC012_IN1(5), TIMER1_CH1, TIMER4_CH1(4) Default: PA2 PA2 16 I/O Alternate: USART1_TX, ADC012_IN2(5), TIMER1_CH2, TIMER4_CH2(4), TIMER8_CH0(3) Default: PA3 PA3 17 I/O Alternate: USART1_RX, ADC012_IN3(5), TIMER1_CH3, TIMER4_CH3(4), TIMER8_CH1(3) P Default: VSS_4 19 P Default: VDD_4 20 I/O Default: PA4 VSS_4 18 VDD_4 PA4 38 GD32F103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0(4) Remap:SPI2_NSS(4), I2S2_WS(4) PA5 21 Default: PA5 I/O Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1(4) Default: PA6 PA6 22 Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, I/O TIMER7_BRKIN(4), TIMER12_CH0(3) Remap: TIMER0_BRKIN Default: PA7 PA7 23 Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, I/O TIMER7_CH0_ON(4), TIMER13_CH0(3) Remap: TIMER0_CH0_ON PC4 24 I/O PC5 25 I/O PB0 26 I/O Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON(4) Remap: TIMER0_CH1_ON Default: PB1 PB1 27 Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON(4) I/O Remap: TIMER0_CH2_ON PB2 28 I/O 5VT Default: PB2, BOOT1 Default: PB10 PB10 29 I/O 5VT Alternate: I2C1_SCL(6), USART2_TX(6) Remap: TIMER1_CH2 Default: PB11 5VT Alternate: I2C1_SDA(6), USART2_RX(6) PB11 30 I/O VSS_1 31 P Default: VSS_1 VDD_1 32 P Default: VDD_1 PB12 33 I/O Remap: TIMER1_CH3 Default: PB12 5VT Alternate: SPI1_NSS(6), I2C1_SMBA(6), USART2_CK(6), TIMER0_BRKIN, I2S1_WS(4) Default: PB13 PB13 34 I/O 5VT Alternate: SPI1_SCK(6), USART2_CTS(6), TIMER0_CH0_ON, I2S1_CK(4) Default: PB14 PB14 35 I/O 5VT Alternate: SPI1_MISO(6), USART2_RTS(6), TIMER0_CH1_ON, TIMER11_CH0(3) PB15 36 I/O 5VT Default: PB15 39 GD32F103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: SPI1_MOSI(6), TIMER0_CH2_ON, I2S1_SD(4), TIMER11_CH1(3) Default: PC6 PC6 37 I/O 5VT Alternate: I2S1_MCK(4), TIMER7_CH0(4), SDIO_D6(4) Remap: TIMER2_CH0 Default: PC7 PC7 38 I/O 5VT Alternate: I2S2_MCK(4), TIMER7_CH1(4), SDIO_D7(4) Remap: TIMER2_CH1 Default: PC8 PC8 39 I/O 5VT Alternate: TIMER7_CH2(4), SDIO_D0(4) Remap: TIMER2_CH2 Default: PC9 PC9 40 I/O 5VT Alternate: TIMER7_CH3(4), SDIO_D1(4) Remap: TIMER2_CH3 PA8 41 I/O 5VT PA9 42 I/O 5VT PA10 43 I/O 5VT PA11 44 I/O 5VT Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT0 Default: PA9 Alternate: USART0_TX, TIMER0_CH1 Default: PA10 Alternate: USART0_RX, TIMER0_CH2 Default: PA11 Alternate: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3 Default: PA12 PA12 45 I/O 5VT Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP 5VT Default: JTMS, SWDIO PA13 46 I/O VSS_2 47 P Default: VSS_2 VDD_2 48 P Default: VDD_2 PA14 49 I/O 5VT PA15 50 I/O 5VT Remap: PA13 Default: JTCK, SWCLK Remap: PA14 Default: JTDI Alternate: SPI2_NSS(4), I2S2_WS(4) Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: PC10 PC10 51 I/O 5VT Alternate: UART3_TX(4), SDIO_D2(4) Remap: USART2_TX(6), SPI2_SCK(4), I2S2_CK(4) Default: PC11 PC11 52 I/O 5VT Alternate: UART3_RX(4), SDIO_D3(4) Remap: USART2_RX(6), SPI2_MISO(4) PC12 53 I/O 5VT Default: PC12 40 GD32F103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: UART4_TX(4), SDIO_CK(4) Remap: USART2_CK(6), SPI2_MOSI(4), I2S2_SD(4) PD2 54 I/O 5VT PB3 55 I/O 5VT Default: PD2 Alternate: TIMER2_ETI, SDIO_CMD(4), UART4_RX(4) Default: JTDO Alternate:SPI2_SCK(4), I2S2_CK(4) Remap: PB3, TRACESWO(4), TIMER1_CH1, SPI0_SCK Default: NJTRST PB4 56 I/O 5VT Alternate: SPI2_MISO(4) Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 57 Alternate: I2C0_SMBA, SPI2_MOSI(4), I2S2_SD(4) I/O Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 58 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0(6) Remap: USART0_TX Default: PB7 PB7 59 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1(6) Remap: USART0_RX BOOT0 60 I PB8 61 I/O Default: BOOT0 Default: PB8 5VT Alternate: TIMER3_CH2(6), SDIO_D4(4), TIMER9_CH0(3) Remap: I2C0_SCL, CAN0_RX Default: PB9 PB9 62 I/O 5VT Alternate: TIMER3_CH3(6), SDIO_D5(4), TIMER10_CH0(3) Remap: I2C0_SDA, CAN0_TX VSS_3 63 P Default: VSS_3 VDD_3 64 P Default: VDD_3 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available in GD32F103RF/G/I/K devices. (4) Functions are available in GD32F103RC/D/E/F/G/I/K devices. (5) ADC2 functions are available in GD32F103RC/D/E/F/G/I/K devices. (6) Functions are available in GD32F103R8/B/C/D/E/F/G/I/K devices. 41 GD32F103xx Datasheet 2.6.4. GD32F103Cx LQFP48 pin definitions Table 2-8. GD32F103Cx LQFP48 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins VBAT 1 P 2 I/O 3 I/O 4 I/O OSCIN 5 I Default: OSCIN OSCOUT 6 O Default: OSCOUT NRST 7 I/O Default: NRST VSSA 8 P Default: VSSA VDDA 9 P Default: VDDA PC13TAMPERRTC PC14OSC32IN PC15OSC32OUT Functions description Default: VBAT Default: PC13 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32IN Default: PC15 Alternate: OSC32OUT Default: PA0 PA0-WKUP 10 I/O Alternate: WKUP, USART1_CTS, ADC012_IN0(3), TIMER1_CH0, TIMER1_ETI, TIMER4_CH0 PA1 11 I/O PA2 12 I/O PA3 13 I/O PA4 14 I/O PA5 15 I/O Default: PA1 Alternate: USART1_RTS, ADC012_IN1(3), TIMER1_CH1 Default: PA2 Alternate: USART1_TX, ADC012_IN2(3), TIMER1_CH2 Default: PA3 Alternate: USART1_RX, ADC012_IN3(3), TIMER1_CH3 Default: PA4 Alternate: SPI0_NSS, USART1_CK, ADC01_IN4 Default: PA5 Alternate: SPI0_SCK, ADC01_IN5 Default: PA6 PA6 16 I/O Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0 Remap: TIMER0_BRKIN Default: PA7 PA7 17 I/O Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1 Remap: TIMER0_CH0_ON Default: PB0 PB0 18 I/O Alternate: ADC01_IN8, TIMER2_CH2 Remap: TIMER0_CH1_ON Default: PB1 PB1 19 I/O Alternate: ADC01_IN9, TIMER2_CH3 Remap: TIMER0_CH2_ON 42 GD32F103xx Datasheet Pin Name Pins PB2 20 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PB2, BOOT1 Default: PB10 PB10 21 I/O 5VT Alternate: I2C1_SCL(4), USART2_TX(4) Remap: TIMER1_CH2 Default: PB11 PB11 22 I/O 5VT Alternate: I2C1_SDA(4), USART2_RX(4) Remap: TIMER1_CH3 VSS_1 23 P Default: VSS_1 VDD_1 24 P Default: VDD_1 Default: PB12 PB12 25 I/O 5VT Alternate: SPI1_NSS(4), I2C1_SMBA(4), USART2_CK(4), TIMER0_BRKIN Default: PB13 PB13 26 I/O 5VT Alternate: SPI1_SCK(4), USART2_CTS(4), TIMER0_CH0_ON Default: PB14 PB14 27 I/O 5VT Alternate: SPI1_MISO(4), USART2_RTS(4), TIMER0_CH1_ON PB15 28 I/O 5VT PA8 29 I/O 5VT PA9 30 I/O 5VT PA10 31 I/O 5VT PA11 32 I/O 5VT Default: PB15 Alternate: SPI1_MOSI(4), TIMER0_CH2_ON Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT0 Default: PA9 Alternate: USART0_TX, TIMER0_CH1 Default: PA10 Alternate: USART0_RX, TIMER0_CH2 Default: PA11 Alternate: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3 Default: PA12 PA12 33 I/O 5VT Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP 5VT Default: JTMS, SWDIO PA13 34 I/O VSS_2 35 P Default: VSS_2 VDD_2 36 P Default: VDD_2 PA14 37 I/O 5VT PA15 38 I/O 5VT PB3 39 I/O 5VT Remap: PA13 Default: JTCK, SWCLK Remap: PA14 Default: JTDI Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: JTDO Remap: PB3, TIMER1_CH1, SPI0_SCK 43 GD32F103xx Datasheet Pin I/O Type(1) Level(2) 40 I/O 5VT 41 I/O Pin Name Pins PB4 PB5 Functions description Default: NJTRST Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 Alternate: I2C0_SMBA Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 42 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0(4) Remap: USART0_TX Default: PB7 PB7 43 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1(4) Remap: USART0_RX BOOT0 44 Default: BOOT0 I Default: PB8 PB8 45 I/O 5VT Alternate: TIMER3_CH2(4) Remap: I2C0_SCL, CAN0_RX Default: PB9 PB9 46 I/O 5VT Alternate: TIMER3_CH3(4) Remap: I2C0_SDA, CAN0_TX VSS_3 47 P Default: VSS_3 VDD_3 48 P Default: VDD_3 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) ADC2 functions are not available in GD32F103C4/6/8/B devices. (4) Functions are available in GD32F103C8/B devices. 44 GD32F103xx Datasheet 2.6.5. GD32F103Tx QFN36 pin definitions Table 2-9. GD32F103Tx QFN36 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins Functions description OSCIN 2 I Default: OSCIN OSCOUT 3 O Default: OSCOUT NRST 4 I/O Default: NRST VSSA 5 P Default: VSSA VDDA 6 P Default: VDDA PA0-WKUP 7 I/O Default: PA0 Alternate: WKUP, USART1_CTS, ADC012_IN0(3), TIMER1_CH0, TIMER1_ETI PA1 8 I/O PA2 9 I/O PA3 10 I/O PA4 11 I/O PA5 12 I/O PA6 13 I/O Default: PA1 Alternate: USART1_RTS, ADC012_IN1(3), TIMER1_CH1 Default: PA2 Alternate: USART1_TX, ADC012_IN2(3), TIMER1_CH2 Default: PA3 Alternate: USART1_RX, ADC012_IN3(3), TIMER1_CH3 Default: PA4 Alternate: SPI0_NSS, USART1_CK, ADC01_IN4 Default: PA5 Alternate: SPI0_SCK, ADC01_IN5 Default: PA6 Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0 Remap: TIMER0_BRKIN Default: PA7 PA7 14 Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1 I/O Remap: TIMER0_CH0_ON Default: PB0 PB0 15 Alternate: ADC01_IN8, TIMER2_CH2 I/O Remap: TIMER0_CH1_ON Default: PB1 Alternate: ADC01_IN9, TIMER2_CH3 PB1 16 I/O PB2 17 I/O VSS_1 18 P Default: VSS_1 VDD_1 19 P Default: VDD_1 PA8 20 I/O 5VT PA9 21 I/O 5VT PA10 22 I/O 5VT Remap: TIMER0_CH2_ON 5VT Default: PB2, BOOT1 Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT0 Default: PA9 Alternate: USART0_TX, TIMER0_CH1 Default: PA10 45 GD32F103xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: USART0_RX, TIMER0_CH2 Default: PA11 PA11 23 I/O 5VT PA12 24 I/O 5VT PA13 25 I/O 5VT VSS_2 26 P Default: VSS_2 VDD_2 27 P Default: VDD_2 PA14 28 I/O 5VT PA15 29 I/O 5VT PB3 30 I/O 5VT PB4 31 I/O 5VT PB5 32 I/O Alternate: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3 Default: PA12 Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP Default: JTMS, SWDIO Remap: PA13 Default: JTCK, SWCLK Remap: PA14 Default: JTDI Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: JTDO Remap: PB3, TIMER1_CH1, SPI0_SCK Default: NJTRST Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 Alternate: I2C0_SMBA Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 33 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0(4) Remap: USART0_TX Default: PB7 PB7 34 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1(4) Remap: USART0_RX BOOT0 35 I Default: BOOT0 VSS_3 36 P Default: VSS_3 VDD_3 1 P Default: VDD_3 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) ADC2 functions are not available in GD32F103T4/6/8/B devices. (4) Functions are available in GD32F103T8/B devices. 46 GD32F103xx Datasheet 3. Functional description 3.1. Arm® Cortex®-M3 core The Cortex®-M3 processor is the latest generation of Arm® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.  32-bit Arm® Cortex®-M3 processor core  Up to 108 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M3:  Internal Bus Matrix connected with I-Code bus, D-Code bus, System bus, Private Peripheral Bus (PPB) and debug accesses. 3.2.  Nested Vectored Interrupt Controller (NVIC).  Flash Patch and Breakpoint (FPB).  Data Watchpoint and Trace (DWT).  Instrumentation Trace Macrocell (ITM).  Embedded Trace Macrocell (ETM).  Serial Wire JTAG Debug Port (SWJ-DP).  Trace Port Interface Unit (TPIU).  Memory Protection Unit (MPU). On-chip memory  Up to 3072 Kbytes of Flash memory  The region of the MCU executing instructions without waiting time is up to 256K bytes ( in case that Flash size less than or equal to 256K, all memory is no waiting time). A long delay when CPU fetches the instructions out of the range.  Up to 96 Kbytes of SRAM The Arm® Cortex®-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash, is available for storing programs and data, and there is no waiting time within code Flash area when CPU executes instructions. The Table 2-4. GD32F103xx memory map shows the memory map of the GD32F103xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 47 GD32F103xx Datasheet 3.3. Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 16 MHz crystal oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control unit provides a range of frequencies and clock functions. These include an Internal 8M RC oscillator (IRC8M), a High Speed crystal oscillator (HXTAL), a Low Speed Internal 40K RC oscillator (IRC40K), a Low Speed crystal oscillator (LXTAL), a Phase Lock Loop (PLL), a HXTAL clock monitor, clock prescalers, clock multiplexers and clock gating circuitry. The frequency of AHB, APB2 and the APB1 domains can be configured by each prescaler. The maximum frequency of the AHB, APB2 and APB1 domains is 108 MHz/108 MHz/54 MHz. See Figure 2-8. GD32F103xx clock tree for details. GD32F10x Reset Control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The system reset resets the processor core and peripheral IP components except for the SW-DP controller and the Backup domain. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when V DD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present. 3.4. Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main flash memory (default)  Boot from system memory  Boot from on-chip SRAM The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), if devices are GD32F103xF/G/I/K, USART1 (PA2 and PA3) is also available for boot functions. It also can 48 GD32F103xx Datasheet be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option bytes. 49 GD32F103xx Datasheet 3.5. Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only clock of Cortex®-M3 is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC8M, HXTAL and PLLs are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, USB Wakeup and Ethernet Wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.  Standby mode In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin. 3.6. Analog to digital converter (ADC)  12-bit SAR ADC  Up to 1 MSPS for 12-bit resolution  Analog input signal voltage range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor Up to three 12-bit multi-channel ADCs are integrated in the device. Each has a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode. The ADCs can be triggered from the events generated by the general level 0 timers (TIMERx) or the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature sensor generates a voltage that varies linearly with temperature. The analog supply voltage VDDA can vary from 2.6 V to 3.6 V. The output voltage of temperature sensor is internally connected to the ADC_IN16 input channel. To ensure a high accuracy on ADC and DAC, the ADC/DAC independent external reference voltage should be connected to VREF+/VREF- pins. According to the different packages, VREF+ 50 GD32F103xx Datasheet pin can be connected to VDDA pin, or external reference voltage, VREF- pin must be connected to VSSA pin. The VREF+ pin is only available on no less than 100-pin packages. On less than 100-pin packages, the VREF+ pin is not available and it is internally connected to VDDA. The VREF- pin is internally connected to VSSA. 3.7. Digital to analog converter (DAC)  Two 12-bit DACs with independent output channels  8-bit or 12-bit mode in conjunction with the DMA controller The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+. 3.8. DMA  7 channel DMA0 controller and 5 channel DMA1 controller  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S and SDIO The direct memory access (DMA) controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory. Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9. General-purpose inputs/outputs (GPIOs)  Up to 112 fast GPIOs, all mappable on 16 external interrupt lines  Analog input/output configurable  Alternate function input/output configurable There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications. The external interrupt on the GPIO pins of the device have related control and configuration registers in the Interrupt/event Controller Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. The GPIO pins can be used as alternative functional pins by configuring the corresponding registers regardless of the AF input or output pins. Each 51 GD32F103xx Datasheet of the GPIO pins can be configured by software as output (push-pull or open-drain), input, peripheral alternate function or analog mode. Each GPIO pin can be configured as pull-up, pull-down or no pull-up/pull-down. All GPIOs are high-current capable except for analog mode. 3.10. Timers and PWM generation  Up to two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers, and two 16-bit basic timer (TIMER5 & TIMER6)  Up to 4 independent channels of PWM, output compare or input capture for each and external trigger input  16-bit, motor control PWM advanced timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Free watchdog timer and window watchdog timer) The advanced timer (TIMER0 & TIMER7) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 6 independent channels can be used for  Input capture  Output compare  PWM generation (edge-aligned or center-aligned counting modes)  Single pulse mode output If configured as a general 16-bit timer, it can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features. The general timer, known as TIMER1 ~ TIMER4, TIMER8 ~ TIMER10, TIMER11 ~ TIMER13 can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The general timer also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TIMER5 and TIMER6 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F103xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer consists of an 8-stage prescaler and a 12-bit down-counter, it is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application 52 GD32F103xx Datasheet timeout management. The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below: 3.11.  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  32-bit up-counter with a programmable 20-bit prescaler  Alarm function  Interrupt and wake-up event The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator. 3.12. Inter-integrated circuit (I2C)  Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 KHz  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 53 GD32F103xx Datasheet 3.13. Serial peripheral interface (SPI)  Up to three SPI interfaces with a frequency of up to 18 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14. Universal synchronous asynchronous receiver transmitter (USART)  Up to three USARTs and two UARTs with operating frequency up to 6.75 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  USARTs support ISO 7816-3 compliant smart card interface The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART4. 3.15. Inter-IC sound (I2S)  Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz  Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F103xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error. 54 GD32F103xx Datasheet 3.16. Secure digital input and output card interface (SDIO)  Support SD2.0/SDIO2.0/MMC4.2 host interface The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1. 3.17. Universal serial bus full-speed device (USBD)  One full-speed USB Interface with frequency up to 12 Mbit/s  Internal main PLL for USB CLK compliantly The Universal Serial Bus (USB) is a 4-wire bus that supports communication between one or more devices. Full-speed peripheral is compliant with the USB 2.0 specification. The device controller enables 12 Mbit/s data exchange with a USB Host controller. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above. 3.18. Controller area network (CAN)  One CAN2.0B interface with communication frequency up to 1 Mbit/s  Internal main PLL for USB CLK compliantly Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others. 3.19. External memory controller (EXMC)  Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and CF card  Up to 16-bit data bus  Support interface with Motorola 6800 and Intel 8080 type LCD directly 55 GD32F103xx Datasheet External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity. 3.20. Debug mode  Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.21. Package and operation temperature  LQFP144 (GD32F103Zx), LQFP100 (GD32F103Vx), LQFP64 (GD32F103Rx), LQFP48 (GD32F103Cx) and QFN36 (GD32F103Tx)  Operation temperature range: -40°C to +85°C (industrial level) 56 GD32F103xx Datasheet 4. Electrical characteristics 4.1. Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute maximum ratings (1)(4) Symbol VDD External voltage range(2) Min Max Unit VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V VSS - 0.3 VDD + 3.6 V Input voltage on other I/O VSS - 0.3 3.6 V |ΔVDDX| Variations between different VDD power pins — 50 mV |VSSX −VSS| Variations between different ground pins — 50 mV IIO Maximum current for GPIO pins — ±25 mA TA Operating temperature range -40 +85 °C Power dissipation at TA = 85°C of LQFP144 — 820 Power dissipation at TA = 85°C of LQFP100 — 697 Power dissipation at TA = 85°C of LQFP64 — 647 Power dissipation at TA = 85°C of LQFP48 — 621 Power dissipation at TA = 85°C of QFN36 — 926 TSTG Storage temperature range -65 +150 °C TJ Maximum junction temperature — 125 °C VIN PD (1) (2) (3) (4) 4.2. Parameter Input voltage on 5V tolerant pin(3) mW Guaranteed by design, not tested in production. All main power and ground pins should be connected to an external power source within the allowable range. VIN maximum value cannot exceed 5.5 V. It is recommended that VDD and VDDA are powered by the same source. The maximum difference between VDD and VDDA does not exceed 300 mV during power-up and operation. Operating conditions characteristics Table 4-2. DC operating conditions Min(1) Typ Max(1) Unit Symbol Parameter Conditions VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V (1) Based on characterization, not tested in production. 57 GD32F103xx Datasheet Figure 4-1. Recommended power supply decoupling capacitors(1) (2) VBAT 100 nF VSS N * VDD 4.7 μF + N * 100 nF VSS VDDA 1 μF VSSA 10 nF VREF+ 1 μF (1) (2) VREF- 10 nF The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins are not available and internally connected to VDDA and VSSA pins. All decoupling capacitors need to be as close as possible to the pins on the PCB board. Table 4-3. Clock frequency(1) Symbol Parameter Conditions Min Max Unit fHCLK AHB clock frequency — — 108 MHz fAPB1 APB1 clock frequency — — 54 MHz fAPB2 APB2 clock frequency — — 108 MHz Min Max Unit 0 ∞ 20 ∞ (1) Guaranteed by design, not tested in production. Table 4-4. Operating conditions at Power up/ Power down (1) Symbol tVDD (1) Parameter Conditions VDD rise time rate — VDD fall time rate μs/V Guaranteed by design, not tested in production. Table 4-5. Start-up timings of Operating conditions (For GD32F103x4/6/8/B devices)(1)(2)(3) Symbol Parameter tstart-up Start-up time (1) (2) (3) Conditions Typ Clock source from HXTAL 60 Clock source from IRC8M 60 Unit ms Based on characterization, not tested in production. After power-up, the start-up time is the time between the rising edge of NRST high and the main function. PLL is off. Table 4-6. Start-up timings of Operating conditions (For GD32F103xC/D/E/F/G/I/K 58 GD32F103xx Datasheet devices) (1)(2)(3) Symbol Parameter tstart-up Start-up time (1) (2) (3) Conditions Typ Clock source from HXTAL 132 Clock source from IRC8M 132 Unit ms Based on characterization, not tested in production. After power-up, the start-up time is the time between the rising edge of NRST high and the main function. PLL is off. Table 4-7. Power saving mode wakeup timings characteristics (for GD32F103x4/6/8/B devices)(1)(2) Symbol Parameter Typ tSleep Wakeup from Sleep mode 4.5 Wakeup from Deep-sleep mode(LDO On) 6.5 Wakeup from Deep-sleep mode(LDO in low power mode) 6.5 Wakeup from Standby mode 60 tDeep-sleep tStandby (1) (2) 4-8. Power saving GD32F103xC/D/E/F/G/I/K devices) ms mode wakeup timings characteristics Parameter Typ tSleep Wakeup from Sleep mode 4.5 Wakeup from Deep-sleep mode(LDO On) 6 Wakeup from Deep-sleep mode(LDO in low power mode) 6 Wakeup from Standby mode 119 tStandby (for (1)(2) Symbol tDeep-sleep 4.3. μs Based on characterization, not tested in production. The wakeup time is measured from the wakeup event to the point at which the application code reads the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz. Table (1) (2) Unit Unit μs ms Based on characterization, not tested in production. The wakeup time is measured from the wakeup event to the point at which the application code reads the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz. Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 4-9. Power consumption characteristics (for GD32F103x4/6/8/B devices)(2)(3)(4)(5) Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 108 MHz, All peripherals IDD+IDDA Supply current enabled (Run mode) VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 108 MHz, All peripherals — 45.6 — mA — 33.4 — mA disabled 59 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 96 MHz, All peripherals — 40.7 — mA — 29.9 — mA — 31 — mA — 22.9 — mA — 21.3 — mA — 15.8 — mA — 16.4 — mA — 12.3 — mA — 11.5 — mA — 8.7 — mA — 8.3 — mA — 6.4 — mA — 5.1 — mA — 4.1 — mA enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 96 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 72 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 72 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 48 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 48 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 36 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 36 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 24 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 24 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 16 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 16 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 8 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 8 MHz, All peripherals disabled 60 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 108 MHz, CPU clock off, — 19.6 — mA — 6.2 — mA — 17.6 — mA — 5.6 — mA — 13.7 — mA — 4.7 — mA — 9.7 — mA — 3.7 — mA — 7.7 — mA — 3.2 — mA — 5.7 — mA — 2.7 — mA — 4.4 — mA — 2.4 — mA All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 108 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 96 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 96 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 72 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 72 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 48 MHz, CPU clock off, All Supply current peripherals enabled (Sleep mode) VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 48 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 36 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 36 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 24 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 24 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 16 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 16 MHz, CPU clock off, All peripherals disabled 61 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 8 MHz, CPU clock off, All — 3.1 — mA — 2.1 — mA — 259 — μA — 247 — μA — 7.8 — μA — 7.3 — μA — 6.1 — μA — 17.00 — μA — 12.65 — μA — 5.95 — μA — 2.02 — μA peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System Clock = 8 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, LDO in normal power Supply current (Deep-Sleep mode) mode, IRC40K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LDO in low power mode, IRC40K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, RTC on Supply current VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, (Standby mode) RTC off VDD = VDDA = 3.3 V, LXTAL off, IRC40K off, RTC off VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on Battery supply IBAT current (Backup mode) VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on VDD off, VDDA off, VBAT = 2.6 V, LXTAL on with external crystal, RTC on VDD off, VDDA off, VBAT = 1.8 V, LXTAL on with external crystal, RTC on (1) (2) (3) (4) (5) Based on characterization, not tested in production. Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value. When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed, no PLL. When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed, using PLL. When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional power consumption should be considered. 62 GD32F103xx Datasheet Table 4-10. devices) Power consumption characteristics (for GD32F103xC/D/E/F/G/I/K (2)(3)(4)(5) Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals — 59.4 — mA — 37.5 — mA — 53.1 — mA — 33.7 — mA — 40.3 — mA — 25.7 — mA — 27.5 — mA — 17.9 — mA — 21.1 — mA — 13.9 — mA — 14.8 — mA — 10 — mA — 10.6 — mA enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 96 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 96 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 72 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 72 MHz, All peripherals disabled IDD+IDDA Supply current (Run mode) VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 48 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, System clock = 48 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 36 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 36 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 24 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 24 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, All peripherals enabled 63 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 16 MHz, All peripherals — 7.4 — mA — 6.5 — mA — 4.9 — mA — 33.3 — mA — 8.1 — mA — 29.8 — mA — 7.4 — mA — 22.9 — mA — 6.1 — mA — 16 — mA — 4.7 — mA — 12.6 — mA — 4.1 — mA — 9.1 — mA disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 8 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 108 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 108 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 96 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 96 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 72 MHz, CPU clock off, All peripherals enabled Supply current (Sleep mode) VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 72 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 48 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 48 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 36 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 36 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 24 MHz, CPU clock off, All peripherals enabled 64 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 24 MHz, CPU clock off, All — 3.4 — mA — 6.8 — mA — 3 — mA — 4.4 — mA — 2.3 — mA — 585 — μA — 573 — μA — 7.8 — μA — 7.4 — μA — 6.2 — μA — 16.6 — μA — 12.6 — μA — 5.9 — μA — 2 — μA peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 16 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 16 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 8 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 8 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, LDO in normal power Supply current (Deep-Sleep mode) mode, IRC40K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LDO in low power mode, IRC40K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, RTC on Supply current VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, (Standby mode) RTC off VDD = VDDA = 3.3 V, LXTAL off, IRC40K off, RTC off VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on Battery supply IBAT current (Backup mode) VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on VDD off, VDDA off, VBAT = 2.6 V, LXTAL on with external crystal, RTC on VDD off, VDDA off, VBAT = 1.8 V, LXTAL on with external crystal, RTC on (1) (2) (3) (4) (5) Based on characterization, not tested in production. Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value. When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed, no PLL. When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed, using PLL. When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional power consumption should be considered. 65 GD32F103xx Datasheet Figure 4-2. Typical supply current consumption in Run mode (For GD32F103x4/6/8/B devices) 50 45.6 IDD+IDDA (mA) 45 40.7 40 All perlpherals enabled 35 All perlpherals disabled 31 30 33.4 25 29.9 21.3 16.4 20 22.9 11.5 15 15.8 8.3 10 5.1 5 4.1 0 0 12.3 6.4 8.7 20 40 60 80 100 120 System clock (MHz) Figure 4-3. Typical supply current consumption in Run mode (For GD32F103xC/D/E/F/G/I/K devices) 70 59.4 60 53.1 IDD+IDDA (mA) All perlpherals enabled 50 All perlpherals disabled 40.3 40 27.5 30 37.5 33.7 21.1 20 25.7 14.8 10.6 10 6.5 0 4.9 0 17.9 13.9 7.4 10 20 40 60 80 100 120 System clock (MHz) Figure 4-4. Typical supply current consumption in Sleep mode (For GD32F103x4/6/8/B 66 GD32F103xx Datasheet devices) 25 19.6 All perlpherals enabled IDD+IDDA (mA) 20 17.6 All perlpherals disabled 13.7 15 9.7 10 7.7 5.7 4.4 5 3.1 0 0 2.1 2.4 2.7 20 3.7 3.2 40 6.2 5.6 4.7 60 80 100 120 System clock (MHz) Figure 4-5. Typical supply current consumption in Sleep mode (For GD32F103xC/D/E/F/G/I/K devices) 33.3 35 29.8 30 IDD+IDDA (mA) All perlpherals enabled 25 22.9 All perlpherals disabled 20 16 12.6 15 9.1 10 6.8 4.4 5 0 2.3 0 3 3.4 20 4.7 4.1 40 7.4 6.1 60 80 8.1 100 120 System clock (MHz) 4.4. EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the Table 4-11. EMS characteristics (1) , based on the EMS levels and classes compliant with IEC 61000 series standard. Table 4-11. EMS characteristics (1) Symbol Parameter Conditions Level/Class VESD Voltage applied to all device pins to VDD = 3.3 V, TA = + 25 °C 3B 67 GD32F103xx Datasheet Symbol Parameter Conditions Level/Class induce a functional disturbance LQFP144, fHCLK = 108 MHz conforms to IEC 61000-4-2 VFTB (1) 4.5. Fast transient voltage burst applied to VDD = 3.3 V, TA = +25 °C induce a functional disturbance through LQFP144, fHCLK = 108 MHz 100 pF on VDD and VSS pins conforms to IEC 61000-4-4 4A Based on characterization, not tested in production. Power supply supervisor characteristics Table 4-12. Power supply supervisor characteristics (For GD32F103x4/6/8/B devices) Symbol VLVD(1) Parameter Conditions Min Typ Max LVDT = 100(rising edge) — 2.55 — LVDT = 100(falling edge) — 2.48 — LVDT = 101(rising edge) — 2.66 — Low voltage LVDT = 101(falling edge) — 2.58 — Detector level selection LVDT = 110(rising edge) — 2.75 — LVDT = 110(falling edge) — 2.69 — LVDT = 111(rising edge) — 2.86 — LVDT = 111(falling edge) — 2.78 — — — 100 — mV — 2.40 — V — 2.35 — V VLVDhyst(2) LVD hystersis VPOR(1) Power on reset threshold VPDR(1) Unit V Power down reset — threshold VPDRhyst(2) PDR hysteresis — 50 — mV tRSTTEMPO(2) Reset temporization — 2 — ms (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-13. Power supply supervisor characteristics (For GD32F103xC/D/E/F/G/I/K devices) Symbol VLVD(1) Parameter Conditions Min Typ Max LVDT = 000(rising edge) — 2.19 — Low voltage LVDT = 000(falling edge) — 2.08 — Detector level selection LVDT = 001(rising edge) — 2.29 — LVDT = 001(falling edge) — 2.19 — Unit V 68 GD32F103xx Datasheet Symbol VLVDhyst(2) LVD hystersis VPOR(1) Power on reset threshold VPDR(1) Conditions Min Typ Max LVDT = 010(rising edge) — 2.39 — LVDT = 010(falling edge) — 2.29 — LVDT = 011(rising edge) — 2.5 — LVDT = 011(falling edge) — 2.39 — LVDT = 100(rising edge) — 2.6 — LVDT = 100(falling edge) — 2.48 — LVDT = 101(rising edge) — 2.68 — LVDT = 101(falling edge) — 2.58 — LVDT = 110(rising edge) — 2.79 — LVDT = 110(falling edge) — 2.68 — LVDT = 111(rising edge) — 2.89 — LVDT = 111(falling edge) — 2.78 — — — 100 — mV — 2.40 — V — 1.85 — V Power down reset threshold — Unit VPDRhyst(2) PDR hysteresis — 550 — mV tRSTTEMPO(2) Reset temporization — 2 — ms (1) (2) 4.6. Parameter Based on characterization, not tested in production. Guaranteed by design, not tested in production. Electrical sensitivity The device is strained in order to determine its performance in terms of electrical sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up (LU) test is based on the two measurement methods. Table 4-14. ESD characteristics (1) Symbol VESD(HBM) VESD(CDM) (1) Parameter Conditions Electrostatic discharge TA = 25 °C; voltage (human body model) JS-001-2014 Electrostatic discharge TA = 25 °C; voltage (charge device model) JS-002-2014 Min Typ Max Unit — — 3000 V — — 500 V Based on characterization, not tested in production. 69 GD32F103xx Datasheet Table 4-15. Static latch-up characteristics Symbol (1) Parameter Conditions Min Typ Max Unit — — ±100 mA — — 5.4 V I-test LU TA = 25 °C; JESD78 Vsupply over voltage (1) 4.7. Based on characterization, not tested in production. External clock characteristics Table 4-16. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics(For GD32F103x4/6/8/B devices) Symbol Parameter Conditions Min Typ Max Unit fHXTAL(1) Crystal or ceramic frequency 2.6 V ≤ VDD ≤ 3.6 V 4 8 16 MHz RF(2) Feedback resistor VDD = 3.3 V — 400 — kΩ — — 20 30 pF Crystal or ceramic duty cycle — 30 50 70 % Oscillator transconductance Startup — 35 — mA/V Crystal or ceramic operating VDD = 3.3 V, current TA = 25 °C — 1.3 — mA — 3.9 — ms Recommended matching CHXTAL(2) (3) capacitance on OSCIN and OSCOUT Ducy(HXTAL) (2) gm(2) IDDHXTAL(1) tSUHXTAL(1) (1) (2) (3) Crystal or ceramic startup time VDD = 3.3 V, TA = 25 °C Based on characterization, not tested in production. Guaranteed by design, not tested in production. CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. Table 4-17. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics(For GD32F103xC/D/E/F/G/I/K devices) Symbol fHXTAL RF (1) (2) Parameter Conditions Min Typ Max Unit Crystal or ceramic frequency 2.6 V ≤ VDD ≤ 3.6 V 4 8 16 MHz Feedback resistor VDD = 3.3 V — 400 — kΩ — — 20 30 pF Crystal or ceramic duty cycle — 30 50 70 % Oscillator transconductance Startup — 35 — mA/V Crystal or ceramic operating VDD = 3.3 V, current TA = 25 °C — 1.6 — mA — 0.68 — ms Recommended matching CHXTAL (2) (3) capacitance on OSCIN and OSCOUT Ducy(HXTAL) (2) gm(2) IDDHXTAL(1) tSUHXTAL(1) Crystal or ceramic startup time VDD = 3.3 V, TA = 25 °C 70 GD32F103xx Datasheet (1) Based on characterization, not tested in production. (2) Guaranteed by design, not tested in production. (3) CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. Table 4-18. High speed external clock characteristics (HXTAL in bypass mode) Symbol Parameter fHXTAL_ext(1) voltage OSCIN input pin low level (2) (2) CIN(2) Ducy(HXTAL) (1) (2) Typ Max Unit 2.6 V ≤ VDD ≤ 3.6 V 1 — 50 MHz 0.7 VDD — VDD V VSS — 0.3 VDD V VDD = 3.3 V voltage tH/L(HXTAL) (2) tR/F(HXTAL) oscillator frequency Min OSCIN input pin high level VHXTALH(2) VHXTALL External clock source or Conditions (2) OSCIN high or low time — 5 — — ns OSCIN rise or fall time — — — 10 ns OSCIN input capacitance — — 5 — pF Duty cycle — 40 — 60 % Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-19. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics(For GD32F103x4/6/8/B devices) Symbol fLXTAL(1) Parameter Crystal or ceramic frequency Conditions Min Typ Max Unit VDD = 3.3 V — 32.768 — kHz — — 10 — pF — 30 — 70 % — — 11 — μA/V — — 12 — μA — — 0.28 — s Recommended matching CLXTAL(2) (3) capacitance on OSC32IN and OSC32OUT Ducy(LXTAL)(2) gm(2) IDDLXTAL tSULXTAL(1) (4) (1) (2) (3) (4) Crystal or ceramic duty cycle Oscillator transconductance Crystal or ceramic operating current Crystal or ceramic startup time Based on characterization, not tested in production. Guaranteed by design, not tested in production. CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer. Table 4-20. Low speed external clock (LXTAL) generated from a crystal/ceramic 71 GD32F103xx Datasheet characteristics(For GD32F103xC/D/E/F/G/I/K devices) Symbol Parameter Crystal or ceramic fLXTAL(1) frequency Conditions Min Typ Max Unit VDD = 3.3 V — 32.768 — kHz — — 10 — pF — 30 — 70 % — — 11 — μA/V — — 11.6 — μA — — 0.39 — s Recommended matching CLXTAL (2) (3) capacitance on OSC32IN and OSC32OUT Ducy(LXTAL)(2) gm(2) Crystal or ceramic duty cycle Oscillator transconductance Crystal or ceramic operating IDDLXTAL current tSULXTAL(1) (4) Crystal or ceramic startup time (1) Based on characterization, not tested in production. (2) Guaranteed by design, not tested in production. (3) CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. (4) tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer. Table 4-21. Low speed external user clock characteristics (LXTAL in bypass mode) Symbol Parameter fLXTAL_ext(1) Unit VDD = 3.3 V — 32.768 1000 kHz — 0.7 VDD — VDD (2) (2) V — VSS — 0.3 VDD OSC32IN high or low time — 450 — — OSC32IN rise or fall time — — — 50 OSC32IN input capacitance — — 5 — pF Duty cycle — 30 50 70 % voltage CIN(2) 4.8. Max OSC32IN input pin low level tH/L(LXTAL) (2) (1) (2) Typ voltage VLXTALL(2) Ducy(LXTAL) frequency Min OSC32IN input pin high level VLXTALH(2) tR/F(LXTAL) External clock source or oscillator Conditions ns Based on characterization, not tested in production. Guaranteed by design, not tested in production. Internal clock characteristics Table 4-22. High speed internal clock (IRC8M) characteristics (For GD32F103x4/6/8/B 72 GD32F103xx Datasheet devices) Symbol Parameter Conditions Min Typ Max Unit VDD = VDDA = 3.3 V — 8 — MHz -2.5 — +2.5 % VDD = VDDA = 3.3 V, TA = 25 °C -1.0 — +1.0 % — — 0.5 — % DucyIRC8M(2) IRC8M oscillator duty cycle VDD = VDDA = 3.3 V 45 50 55 % IRC8M oscillator operating VDD = VDDA = 3.3 V, current TA = 25 °C — 87 — μA IRC8M oscillator startup VDD = VDDA = 3.3 V, time TA = 25 °C — 2.5 — μs High Speed Internal fIRC8M Oscillator (IRC8M) frequency VDD = VDDA = 3.3 V, IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M TA = -40 °C ~ +85 °C IRC8M oscillator Frequency accuracy, User trimming step(1) IDDAIRC8M(1) tSUIRC8M(1) (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-23. High speed internal clock (IRC8M) characteristics (For GD32F103 xC/D/E/F/G/I/K devices) Symbol Parameter Conditions Min Typ Max Unit VDD = VDDA = 3.3 V — 8 — MHz -2.5 — +2.5 % VDD = VDDA = 3.3 V, TA = 25 °C -1.0 — +1.0 % — — 0.5 — % DucyIRC8M(2) IRC8M oscillator duty cycle VDD = VDDA = 3.3 V 45 50 55 % IRC8M oscillator operating VDD = VDDA = 3.3 V, current TA = 25 °C — 62 — μA IRC8M oscillator startup VDD = VDDA = 3.3 V, time TA = 25 °C — 0.64 — μs High Speed Internal fIRC8M Oscillator (IRC8M) frequency VDD = VDDA = 3.3 V, IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M TA = -40 °C ~ +85 °C(1) IRC8M oscillator Frequency accuracy, User trimming step(1) IDDAIRC8M(1) tSUIRC8M(1) (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-24. Low speed internal clock (IRC40K) characteristics (For GD32F103x4/6/8/B devices) Symbol fIRC40K(1) Parameter Conditions Low Speed Internal oscillator VDD = VDDA = 3.3 V, (IRC40K) frequency TA = -40°C ~ +85 °C Min Typ — 40 Max Unit — kHz 73 GD32F103xx Datasheet Symbol IDDAIRC40K(2) tSUIRC40K(2) (1) (2) Parameter Conditions IRC40K oscillator operating VDD = VDDA = 3.3 V, current TA = 25 °C IRC40K oscillator startup VDD = VDDA = 3.3 V, time TA = 25 °C Min Typ Max Unit — 1.3 — μA — 113 — μs Guaranteed by design, not tested in production. Based on characterization, not tested in production. Table 4-25. Low speed internal clock (IRC40K) characteristics(For GD32F103 xC/D/E/F/G/I/K devices) Symbol fIRC40K(1) IDDAIRC40K(2) tSUIRC40K(2) Parameter Conditions Low Speed Internal oscillator VDD = VDDA = 3.3 V, (IRC40K) frequency TA = -40°C ~ +85 °C IRC40K oscillator operating VDD = VDDA = 3.3 V, current TA = 25 °C IRC40K oscillator startup VDD = VDDA = 3.3 V, time TA = 25 °C Min Typ Max Unit — 40 — kHz — 1.2 — μA — 124 — μs (1) Guaranteed by design, not tested in production. (2) Based on characterization, not tested in production. 4.9. PLL characteristics Table 4-26. PLL characteristics Symbol fPLLIN (1) fPLLOUT (2) fVCO(2) tLOCK(2) (1) (2) Parameter Conditions Min Typ Max Unit PLL input clock frequency — 1 — 25 MHz PLL output clock frequency — 16 — 108 MHz — 32 — 216 MHz — — — 300 μs PLL VCO output clock frequency PLL lock time Based on characterization, not tested in production. Guaranteed by design, not tested in production. 74 GD32F103xx Datasheet 4.10. Memory characteristics Table 4-27. Flash memory characteristics (For GD32F103x4/6/8/B devices) Symbol Parameter Conditions Min(1) Typ(1) Max(2) Unit Number of guaranteed PECYC program /erase cycles TA = -40 °C ~ +85 °C 100 — — kcycle s before failure (Endurance) tRET Data retention time — — 20 — years tPROG Word programming time TA = -40°C ~ +85 °C — 37.5 105 μs tERASE Page erase time TA = -40°C ~ +85 °C — 50 400 ms tMERASE(16K) Mass erase time TA = -40°C ~ +85 °C — 0.3 3 s tMERASE(32K) Mass erase time TA = -40°C ~ +85 °C — 0.6 6 s tMERASE(64K) Mass erase time TA = -40°C ~ +85 °C — 1.2 12 s tMERASE(128K) Mass erase time TA = -40°C ~ +85 °C — 2.4 24 s (1) (2) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-28. Flash memory characteristics (For GD32F103xC/D/E/F/G/I/K devices) Symbol Parameter Conditions Min(1) Typ(1) Max(2) Unit Number of guaranteed PECYC program /erase cycles before failure TA = -40 °C ~ +85 °C 100 — — 20 — kcycle s (Endurance) tRET Data retention time — — tPROG Word programming time TA = -40°C ~ +85 °C — tERASE Page erase time TA = -40°C ~ +85 °C — tMERASE(256K) Mass erase time TA = -40°C ~ +85 °C — 37.5 105/170 years (3) μs 50 400/500 (4) ms 2.4 24 s tMERASE(512K) Mass erase time TA = -40°C ~ +85 °C — 8 64 s tMERASE(1024K) Mass erase time TA = -40°C ~ +85 °C — 16 128 s tMERASE(3072K) Mass erase time TA = -40°C ~ +85 °C — 64 512 s (1) (2) (3) (4) Based on characterization, not tested in production. Guaranteed by design, not tested in production. Flash memory with 256K is 105 us and flash memory >256K is 170 us. Flash memory with 256K is 400 ms and flash memory >256K is 500 ms. 75 GD32F103xx Datasheet 4.11. NRST pin characteristics Table 4-29. NRST pin characteristics Symbol Parameter VIL(NRST)(1) NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage Vhyst(1) VIL(NRST) Typ Max -0.3 — 0.3 VDD VDD = VDDA = 2.6 V 0.7 VDD — — 350 — NRST Input low level voltage -0.3 — 0.3 VDD (1) NRST Input high level voltage VDD = VDDA = 3.3 V 0.7 VDD — Schmidt trigger Voltage hysteresis — 360 — NRST Input low level voltage -0.3 — 0.3 VDD (1) NRST Input high level voltage VDD = VDDA = 3.6 V 0.7 VDD — Vhyst(1) Schmidt trigger Voltage hysteresis Rpu(2) Pull-up equivalent resistor — V mV V VDD + 0.3 (1) VIH(NRST) Unit VDD + 0.3 Schmidt trigger Voltage hysteresis Vhyst(1) (1) (2) Min (1) VIH(NRST) VIL(NRST) Conditions mV V VDD + 0.3 — 370 — mV — 40 — kΩ Based on characterization, not tested in production. Guaranteed by design, not tested in production. Figure 4-6. Recommended external NRST pin circuit(1) VDD VDD External reset circuit 10 kΩ RPU NRST K 100 nF GND (1) 4.12. Unless the voltage on NRST pin go below VIL(NRST) level, the device would not generate a reliable reset. GPIO characteristics Table 4-30. I/O port DC characteristics(For GD32F103x4/6/8/B devices)(1) (3) Symbol Parameter Standard IO Low level input VIL voltage 5V-tolerant IO Low level input voltage Standard IO Low level input VIH voltage 5V-tolerant IO Low level Conditions Min Typ Max Unit 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V 76 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ Max Unit input voltage RPU(2) RPD(2) Internal pull- All pins VIN = VSS — 40 — up resistor PA10 — — 10 — Internal pull- All pins VIN = VDD — 40 — down resistor PA10 — — 10 — kΩ kΩ IO_Speed=50MHz Low level output voltage VDD = 2.6V — 0.12 — for an IO Pin VDD = 3.3 V — 0.1 — (IIO = +4 mA) VDD = 3.6V — 0.1 — Low level output voltage VDD = 2.6V — 0.38 — for an IO Pin VDD = 3.3 V — 0.32 — (IIO = +12 mA) VDD = 3.6V — 0.3 — High level output voltage VDD = 2.6V — 2.32 — for an IO Pin VDD = 3.3 V — 3.06 — (IIO = +8 mA) VDD = 3.6V — 3.37 — VDD = 2.6V — 2.03 — VDD = 3.3 V — 2.76 — VDD = 3.6V — 3.09 — VOL V High level output voltage VOH for an IO Pin V (IIO = +15 mA) High level output voltage for an IO Pin (IIO = +18 mA) IO_Speed=10MHz VOL Low level output voltage for VDD = 2.6V — 0.29 — an IO Pin VDD = 3.3 V — 0.26 — (IIO = +4 mA) VDD = 3.6V — 0.25 — Low level output voltage for VDD = 2.6V — 0.65 — VDD = 3.3 V — 0.51 — VDD = 3.6V — 0.62 — High level output voltage VDD = 2.6V — 1.94 — for an IO Pin VDD = 3.3 V — 2.78 — (IIO = +8 mA) VDD = 3.6V — 3.11 — VDD = 2.6V — 1.71 — VDD = 3.3 V — 2.18 — VDD = 3.6V — 2.85 — an IO Pin (IIO = +8 mA) V Low level output voltage for an IO Pin (IIO = +10 mA) High level output voltage VOH for an IO Pin V (IIO = +10mA) High level output voltage for an IO Pin (IIO = +15mA) IO_Speed=2MHz 77 GD32F103xx Datasheet Symbol VOL Parameter Conditions Min Typ Max Low level output voltage for VDD = 2.6V — 0.59 — an IO Pin VDD = 3.3 V — 0.54 — (IIO = +4 mA) VDD = 3.6V — 0.51 — VDD = 2.6V — 2.14 — VDD = 3.3 V — 2.53 — VDD = 3.6V — 2.89 — Unit V High level output voltage for an IO Pin VOH (IIO = +2mA) High level output voltage for an IO Pin (IIO = +4mA) (1) (2) (3) V Based on characterization, not tested in production. Guaranteed by design, not tested in production. All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which can only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz when they are in output mode (maximum load: 30 pF). Table 4-31. I/O port DC characteristics(For GD32F103xC/D/E/F/G/I/K devices)(1) (3) Symbol Parameter Standard IO Low level input VIL voltage 5V-tolerant IO Low level input voltage Standard IO Low level input VIH voltage 5V-tolerant IO Low level input voltage RPU(2) RPD(2) Conditions Min Typ Max Unit 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V Internal pull- All pins VIN = VSS — 40 — up resistor PA10 — — 10 — Internal pull- All pins VIN = VDD — 40 — down resistor PA10 — — 10 — kΩ kΩ IO_Speed=50MHz Low level output voltage for VDD = 2.6V — 0.27 — an IO Pin VDD = 3.3 V — 0.23 — (IIO = +8 mA) VDD = 3.6V — 0.22 — VDD = 2.6V — 0.43 — VDD = 3.3 V — 0.66 — (IIO = +20 mA) VDD = 3.6V — 0.61 — High level output voltage VDD = 2.6V — 2.3 — Low level output voltage for VOL an IO Pin V (IIO = +12mA) Low level output voltage for an IO Pin VOH for an IO Pin VDD = 3.3 V — 3.05 — (IIO = +8 mA) VDD = 3.6V — 3.36 — High level output voltage VDD = 2.6V — 2.21 — V 78 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ Max VDD = 3.3 V — 2.59 — VDD = 3.6V — 2.95 — Unit for an IO Pin (IIO = +10 mA) High level output voltage for an IO Pin (IIO = +20 mA) IO_Speed=10MHz Low level output voltage for VDD = 2.6V — 0.43 — an IO Pin VDD = 3.3 V — 0.36 — (IIO = +8 mA) VDD = 3.6V — 0.34 — Low level output voltage for VDD = 2.6V — — — an IO Pin VDD = 3.3 V — 0.78 — (IIO = +15 mA) VDD = 3.6V — 0.72 — High level output voltage VDD = 2.6V — 2.06 — for an IO Pin VDD = 3.3 V — 2.87 — (IIO = +8 mA) VDD = 3.6V — 3.2 — High level output voltage VDD = 2.6V — — — for an IO Pin VDD = 3.3 V — 2.39 — (IIO = +15mA) VDD = 3.6V — 2.77 — VOL VOH V V IO_Speed=2MHz VOL VOH (1) (2) (3) Low level output voltage for VDD = 2.6V — 0.44 — an IO Pin VDD = 3.3 V — 0.36 — (IIO = +4 mA) VDD = 3.6V — 0.34 — High level output voltage VDD = 2.6V — 2.22 — for an IO Pin VDD = 3.3 V — 2.99 — (IIO = +4mA) VDD = 3.6V — 3.31 — V V Based on characterization, not tested in production. Guaranteed by design, not tested in production. All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which can only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz when they are in output mode(maximum load: 30 pF). Table 4-32. I/O port AC characteristics(For GD32F103x4/6/8/B devices) (1)(2)(4) GPIOx_MDy[1:0] bit value(3) GPIOx_CTL->MDy[1:0]=10 (IO_Speed = 2MHz) GPIOx_CTL->MDy[1:0] = 01 (IO_Speed = 10MHz) GPIOx_CTL->MDy[1:0]=11 (IO_Speed = 50MHz) (1) Parameter TRise/TFall TRise/TFall TRise/TFall Conditions Typ 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 48.6 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 59.4 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 68.4 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 16 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 19.4 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 25.2 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 2.6 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 3.2 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 4.2 Unit ns ns ns Based on characterization, not tested in production. 79 GD32F103xx Datasheet (2) (3) (4) Unless otherwise specified, all test results given for TA = 25 °C. The I/O speed is configured using the GPIOx_CTL -> MDy[1:0] bits. Only for reference, Depending on user’s design. Table 4-33. I/O port AC characteristics(For GD32F103xC/D/E/F/G/I/K devices) (1)(2)(4) GPIOx_MDy[1:0] bit value(3) Parameter GPIOx_CTL->MDy[1:0]=10 (IO_Speed = 2MHz) GPIOx_CTL->MDy[1:0] = 01 (IO_Speed = 10MHz) GPIOx_CTL->MDy[1:0]=11 (IO_Speed = 50MHz) (1) (2) (3) (4) 4.13. TRise/TFall TRise/TFall TRise/TFall Conditions Typ 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 49.2 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 60 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 70.4 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 23.4 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 27 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 32 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF 3.3 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF 3.5 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF 3.6 Unit ns ns ns Based on characterization, not tested in production. Unless otherwise specified, all test results given for TA = 25 °C. The I/O speed is configured using the GPIOx_CTL -> MDy[1:0] bits. Only for reference, Depending on user’s design. ADC characteristics Table 4-34. ADC characteristics(For GD32F103x4/6/8/B devices) Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 2.6 3.3 3.6 V VIN(1) ADC input voltage range 16 external; 2 internal 0 — VREF+ V VREF+(2) Positive Reference Voltage — 2.6 — VDDA V — — VSSA — V MHz VREF-(2) Negative Reference Voltage fADC(1) ADC clock — 0.6 — 14 fS(1) Sampling rate 12-bit 0.04 — 1 External input impedance See Equation 1 — — 54.8 kΩ — — — 0.2 kΩ — — 32 pF fADC = 14 MHz 0.11 — 17.11 μs 12-bit — 14 — — — — 1 (2) RAIN RADC(2) Input sampling switch resistance CADC(2) Input sampling capacitance ts(2) Sampling time No pin/pad capacitance included Total conversion tCONV(2) time(including sampling time) tSU(2) (1) (2) Startup time MSP S 1/ fADC μs Based on characterization, not tested in production. Guaranteed by design, not tested in production. 80 GD32F103xx Datasheet Table 4-35. ADC characteristics(For GD32F103xC/D/E/F/G/I/K devices) Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 2.6 3.3 3.6 V VIN(1) ADC input voltage range — 0 — VREF+ V VREF+(2) Positive Reference Voltage — 2.6 — VDDA V — — VSSA — V MHz VREF-(2) Negative Reference Voltage fADC(1) ADC clock — 0.6 — 14 fS(1) Sampling rate 12-bit 0.04 — 1 External input impedance See Equation 1 — — 219.8 kΩ — — — 0.5 kΩ — — 8 pF (2) RAIN RADC(2) Input sampling switch resistance No pin/pad capacitance S CADC(2) Input sampling capacitance tCAL(2) Calibration time fADC = 14 MHz — 7.28 — μs Sampling time fADC = 14 MHz 0.11 — 17.11 μs 12-bit — 14 — — — — 1 (2) ts included Total conversion tCONV(2) time(including sampling time) tSU(2) (1) (2) MSP Startup time 1/ fADC μs Based on characterization, not tested in production. Guaranteed by design, not tested in production. Equation 1: RAIN max formula R AIN < Ts fADC ∗CADC ∗ln(2N+2 ) − R ADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 4-36. ADC RAIN max for fADC = 14 MHz (For GD32F103x4/6/8/B devices) Ts (cycles) ts (μs) RAIN max (kΩ) 1.5 0.11 0.1 7.5 0.54 1.5 13.5 0.96 2.9 28.5 2.04 6.3 41.5 2.96 9.3 55.5 3.96 12.5 71.5 5.11 16.2 239.5 17.11 54.8 Table 4-37. ADC RAIN max for fADC = 14 MHz (For GD32F103xC/D/E/F/G/I/K devices) Ts (cycles) ts (μs) RAIN max (kΩ) 1.5 0.11 0.8 7.5 0.54 6.4 13.5 0.96 11.9 81 GD32F103xx Datasheet 4.14. Ts (cycles) ts (μs) RAIN max (kΩ) 28.5 2.04 25.7 41.5 2.96 37.6 55.5 3.96 50.5 71.5 5.11 65.2 239.5 17.11 219.8 Temperature sensor characteristics Table 4-38. Temperature sensor characteristics (1) Symbol Parameter Min Typ Max Unit TL VSENSE linearity with temperature — ±1.5 — ℃ Avg_Slope Average slope — 4.1 — mV/℃ V25 Voltage at 25 °C — 1.45 — V ADC sampling time when reading the temperature — 17.1 — μs tS_temp (1) (2) 4.15. (2) Based on characterization, not tested in production. Shortest sampling time can be determined in the application by multiple iterations. DAC characteristics Table 4-39. DAC characteristics(For GD32F103xC/D/E/F/G/I/K devices) Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 2.6 3.3 3.6 V VREF+(2) Positive Reference Voltage — 2.6 — VDDA V — — VSSA — V 5 — — kΩ — — 15 kΩ — — 50 pF — 0.2 — — V — — — — — 0.5 — — — With no load, middle — 550 VREF-(2) RLOAD(2) Ro(2) CLOAD(2) Negative Reference Voltage Load resistance Impedance output with buffer OFF Load capacitance DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF DAC_OUT Higher DAC_OUT voltage max(2) with buffer OFF IDDA(1) DAC current consumption Resistive load with buffer ON — No pin/pad capacitance included VDDA0.2 — VDDA1LSB — V mV V μA 82 GD32F103xx Datasheet Symbol Parameter Conditions in quiescent mode code(0x800) on the input, VREF+ Min Typ Max Unit — 600 — μA — 86 — μA — 298 — μA = 3.6 V With no load, worst code(0xF1C) on the input, VREF+ = 3.6 V With no load, middle code(0x800) on the input, VREF+ IDDVREF+(1) DAC current consumption = 3.6 V in quiescent mode With no load, worst code(0xF1C) on the input, VREF+ = 3.6 V Tsetting (1) Twakeup (2) Update rate(2) Settling time CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ — 0.3 1 μs Wakeup from off state — — 5 10 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ — — 4 MS/s — 55 80 — dB Max frequency for a correct DAC_OUT change from code i to i±1LSBs Power supply rejection PSRR(2) ratio (to VDDA) (1) (2) 4.16. Based on characterization, not tested in production. Guaranteed by design, not tested in production. I2C characteristics Table 4-40. I2C characteristics(1) (2) Symbol Parameter Conditions tSCL(H) SCL clock high time tSCL(L) tsu(SDA) Standard mode Fast mode Unit Min Max Min Max — 4.0 — 0.6 — μs SCL clock low time — 4.7 — 1.3 — μs SDA setup time — 250 — 100 — ns 3450 0 900 ns th(SDA) SDA data hold time — 0(3) tr(SDA/SCL) SDA and SCL rise time — — 1000 — 300 ns tf(SDA/SCL) SDA and SCL fall time — — 300 — 300 ns th(STA) Start condition hold time — 4.0 — 0.6 — μs — 4.7 — 0.6 — μs — 4.0 — 0.6 — μs — 4.7 — 1.3 — μs ts(STA) ts(STO) tbuff (1) Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Guaranteed by design, not tested in production. 83 GD32F103xx Datasheet To ensure the standard mode I2C frequency, f PCLK1 must be at least 2 MHz. To ensure the fast mode I2C frequency, fPCLK1 must be at least 4 MHz. The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the falling edge of SCL. (2) (3) Figure 4-7. I2C bus timing diagram tsu(STA) SDA 70% 30% tf(SDA) tr(SDA) tSCL(H) th(STA) SCL tbuff th(SDA) tsu(SDA) 70% 30% tSCL(L) 4.17. tr(SCL) tf(SCL) tsu(STO) SPI characteristics Table 4-41. Standard SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency — — — 27 MHz tSCK(H) SCK clock high time tSCK(L) SCK clock low time Master mode, fPCLKx = 108 MHz, presc = 4 Master mode, fPCLKx = 108 MHz, presc = 4 35.13 37.13 39.13 ns 35.13 37.13 39.13 ns SPI master mode tV(MO) Data output valid time — — — 8 ns tSU(MI) Data input setup time — 1 — — ns tH(MI) Data input hold time — 0 — — ns SPI slave mode tSU(NSS) NSS enable setup time — 0 — — ns tH(NSS) NSS enable hold time — 1 — — ns tA(SO) Data output access time — — 9 — ns tDIS(SO) Data output disable time — — 11 — ns tV(SO) Data output valid time — — 11 — ns tSU(SI) Data input setup time — 0 — — ns tH(SI) Data input hold time — 1 — — ns (1) Based on characterization, not tested in production. 84 GD32F103xx Datasheet Figure 4-8. SPI timing diagram - master mode tSCK SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) tSCK(H) tSCK(L) SCK (CKPH=1 CKPL=1) tSU(MI) MISO D[0] LF=1,FF16=0 D[7] tH(MI) D[0] MOSI D[7] tH(MO) tV(MO) Figure 4-9. SPI timing diagram - slave mode NSS tSCK tSU(NSS) SCK (CKPH=0 CKPL=0) tSCK(H) SCK (CKPH=0 CKPL=1) tSCK(L) tH(NSS) tH(SO) tDIS(SO) tV(SO) tA(SO) MISO D[0] D[7] tSU(SI) D[0] MOSI D[7] tH(SI) 4.18. I2S characteristics Table 4-42. I2S characteristics (For GD32F103xC/D/E/F/G/I/K devices) (1) (2) Symbol Parameter fCK Clock frequency Conditions Master mode (data: 32 bits, Audio frequency = 96 kHz) Min Typ Max Unit — 6.25 — MHz 85 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ Max Unit Slave mode 0 — 12.5 — 80 — ns — 80 — ns tH Clock high time tL Clock low time tV(WS) WS valid time Master mode — 3 — ns tH(WS) WS hold time Master mode — 3 — ns tSU(WS) WS setup time Slave mode 0 — — ns tH(WS) WS hold time Slave mode 2 — — ns Slave mode — 50 — % Ducy(SCK) — I2S slave input clock duty cycle tSU(SD_MR) Data input setup time Master mode 1 — — ns tsu(SD_SR) Data input setup time Slave mode 0 — — ns Master receiver 0 — — ns Slave receiver 1 — — ns — — 5 ns 6 — — ns — — 5 ns 0 — — ns tH(SD_MR) Data input hold time tH(SD_SR) (1) (2) tv(SD_ST) Data output valid time th(SD_ST) Data output hold time tv(SD_MT) Data output valid time th(SD_MT) Data output hold time Slave transmitter (after enable edge) Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) Guaranteed by design, not tested in production. Based on characterization, not tested in production. Figure 4-10. I2S timing diagram - master mode tCK CPOL=0 tL CPOL=1 tV(WS) tH tH(WS) WS output tV(SD_MT) SD transmit SD receive tH(SD_MT) D[0] D[0] tSU(SD_MR) tH(SD_MR) 86 GD32F103xx Datasheet Figure 4-11. I2S timing diagram - slave mode tCK CPOL=0 tL CPOL=1 tH tH(WS) WS input tSU(WS) tH(SD_ST) tV(SD_ST) SD transmit D[0] SD receive D[0] tSU(SD_SR) tH(SD_SR) 4.19. USART characteristics Table 4-43. USART characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency fPCLKx = 108 MHz — — 13.5 MHz tSCK(H) SCK clock high time fPCLKx = 108 MHz 37.0 — — ns tSCK(L) SCK clock low time fPCLKx = 108 MHz 37.0 — — ns (1) 4.20. Guaranteed by design, not tested in production. SDIO characteristics Table 4-44. SDIO characteristics (For GD32F103xC/D/E/F/G/I/K devices)(1)(2) Symbol Parameter Conditions Min Typ Max Unit Clock frequency in data transfer mode — 0 — 48 MHz tW(CKL) (3) Clock low time fpp = 48 MHz 10.5 11 — ns tW(CKH) (3) Clock high time fpp = 48 MHz 9.5 10 — ns fPP(3) CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU(4) Input setup time HS fpp = 48 MHz 4 — — ns tIH(4) Input hold time HS fpp = 48 MHz 3 — — ns 13.8 ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV(3) Output valid time HS fpp = 48 MHz — — 87 GD32F103xx Datasheet Symbol Parameter tOH(3) Conditions Output hold time HS Min Typ Max 12 — — ns fpp = 48 MHz Unit CMD, D inputs (referenced to CK) in SD default mode tISUD(4) Input setup time SD fpp = 24 MHz 3 — — ns tIHD(4) Input hold time SD fpp = 24 MHz 3 — — ns CMD, D outputs (referenced to CK) in SD default mode tOVD(3) Output valid default time SD fpp = 24 MHz — 2.4 2.8 ns tOHD(3) Output hold default time SD fpp = 24 MHz 0.8 — — ns (1) (2) (3) (4) 4.21. CLK timing is measured at 50% of VDD. Capacitive load CL = 30 pF. Based on characterization, not tested in production. Guaranteed by design, not tested in production. CAN characteristics Refer to Table 4-30. I/O port DC characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 4.22. USBD characteristics Table 4-45. USBD start up time (For GD32F103x4/6/8/B devices) Symbol (1) tSTARTUP (1) Parameter Max Unit USBD startup time 1 μs Guaranteed by design, not tested in production. Table 4-46. USBD start up time (For GD32F103xC/D/E/F/G/I/K devices) Symbol (1) tSTARTUP (1) Parameter Max Unit USBD startup time 1 μs Guaranteed by design, not tested in production. Table 4-47. USBD DC electrical characteristics (For GD32F103x4/6/8/B devices) Symbol Input levels(1) Parameter Conditions Min Typ Max Unit VDD USBD operating voltage — 3 — 3.6 V VDI Differential input sensitivity I(USBDP, USBDM) 0.2 — — VCM Differential common mode range Includes VDI range 0.8 — 2.5 VSE Single ended receiver threshold — 0.8 — 2.0 Output VOL Static output level low RL of 1.5 kΩ to 3.6 V — 0.064 0.3 levels(2) VOH Static output level high RL of 15 kΩ to VSS 2.8 3.3 3.6 (1) (2) V V Guaranteed by design, not tested in production. Based on characterization, not tested in production. Table 4-48. USBD DC electrical characteristics (For GD32F103xC/D/E/F/G/I/K devices) Symbol Input VDD Parameter Conditions Min Typ Max Unit USBD operating voltage — 3 — 3.6 V 88 GD32F103xx Datasheet Symbol Parameter Conditions Min Typ Max Differential input sensitivity I(USBDP, USBDM) 0.2 — — VCM Differential common mode range Includes VDI range 0.8 — 2.5 VSE Single ended receiver threshold — 0.8 — 2.0 levels(1) VDI Output VOL Static output level low RL of 1.5 kΩ to 3.6 V — 0.064 0.3 levels(2) VOH Static output level high RL of 15 kΩ to VSS 2.8 3.3 3.6 (1) (2) Unit V V Guaranteed by design, not tested in production. Based on characterization, not tested in production. Table 4-49. USBD full speed-electrical characteristics (For GD32F103x4/6/8/B devices) (1) (1) Symbol Parameter Conditions Min Typ Max Unit tR Rise time CL = 50 pF 4 — 20 ns tF Fall time CL = 50 pF 4 — 20 ns tRFM Rise / fall time matching tR / tF 90 — 110 % vCRS Output signal crossover voltage — 1.3 — 2.0 V Guaranteed by design, not tested in production. Table 4-50. USBD full speed-electrical characteristics (For GD32F103xC/D/E/F/G/I/K devices)(1) (1) Symbol Parameter Conditions Min Typ Max Unit tR Rise time CL = 50 pF 4 — 20 ns tF Fall time CL = 50 pF 4 — 20 ns tRFM Rise / fall time matching tR / tF 90 — 110 % vCRS Output signal crossover voltage — 1.3 — 2.0 V Guaranteed by design, not tested in production. Figure 4-12. USBD timings: definition of data signal rise and fall time Crossover points Differential data lines VCRS VSS tf 4.23. tr EXMC characteristics Table 4-51. Synchronous multiplexed PSRAM/NOR read timings(1)(2)(3) Symbol Parameter Min Max Unit tw(CLK) EXMC_CLK period 36.8 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 18.4 — ns 89 GD32F103xx Datasheet Symbol Parameter Min Max Unit td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 18.4 — ns td(CLKL-NOEL) EXMC_CLK low to EXMC_NOE low 0 — ns td(CLKH-NOEH) EXMC_CLK high to EXMC_NOE high 18.4 — ns td(CLKL-ADV) EXMC_CLK low to EXMC_AD valid 0 — ns td(CLKL-ADIV) EXMC_CLK low to EXMC_AD invalid 0 — ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 108 MHz, BurstAccessMode = Enable; Memory Type = PSRAM; WriteBurst = Enable; CLKDivision = 3(EXMC_CLK is 4 divided by HCLK); Data Latency = 1. Table 4-52. Synchronous multiplexed PSRAM write timings(1)(2)(3) Symbol Parameter Min Max Unit tw(CLK) EXMC_CLK period 36.8 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 18.4 — ns td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 18.4 — ns td(CLKL-NWEL) EXMC_CLK low to EXMC_NWE low 0 — ns td(CLKH-NWEH) EXMC_CLK high to EXMC_NWE high 18.4 — ns td(CLKL-ADIV) EXMC_CLK low to EXMC_AD invalid 0 — ns td(CLKL-DATA) EXMC_A/D valid data after EXMC_CLK low 0 — ns th(CLKL-NBLH) EXMC_CLK low to EXMC_NBL high 0 — ns (1) (2) (3) CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: fHCLK = 108 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1. Table 4-53. Synchronous non-multiplexed PSRAM/NOR read timings(1)(2)(3) Symbol Parameter Min Max Unit tw(CLK) EXMC_CLK period 36.8 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 18.4 — ns td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 18.4 — ns td(CLKL-NOEL) EXMC_CLK low to EXMC_NOE low 0 — ns td(CLKH-NOEH) EXMC_CLK high to EXMC_NOE high 18.4 — ns (1) CL = 30 pF. 90 GD32F103xx Datasheet (2) (3) Guaranteed by design, not tested in production. Based on configure: HCLK = 108 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1. Table 4-54. Synchronous non-multiplexed PSRAM write timings(1)(2)(3) Symbol Parameter Min Max Unit tw(CLK) EXMC_CLK period 36.8 — ns td(CLKL-NExL) EXMC_CLK low to EXMC_NEx low 0 — ns td(CLKH-NExH) EXMC_CLK high to EXMC_NEx high 18.4 — ns td(CLKL-NADVL) EXMC_CLK low to EXMC_NADV low 0 — ns td(CLKL-NADVH) EXMC_CLK low to EXMC_NADV high 0 — ns td(CLKL-AV) EXMC_CLK low to EXMC_Ax valid 0 — ns td(CLKH-AIV) EXMC_CLK high to EXMC_Ax invalid 18.4 — ns td(CLKL-NWEL) EXMC_CLK low to EXMC_NWE low 0 — ns td(CLKH-NWEH) EXMC_CLK high to EXMC_NWE high 18.4 — ns td(CLKL-DATA) EXMC_A/D valid data after EXMC_CLK low 0 — ns th(CLKL-NBLH) EXMC_CLK low to EXMC_NBL high 0 — ns (1) (2) (3) 4.24. CL = 30 pF. Guaranteed by design, not tested in production. Based on configure: HCLK = 108 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable; CLKDivision = 3(EXMC_CLK is 4 divided by HCLK); DataLatency = 1. TIMER characteristics Table 4-55. TIMER characteristics(1) Symbol Parameter tres Timer resolution time fEXT Timer external clock frequency RES Timer resolution tCOUNTER 4.25. Min Max Unit — 1 — tTIMERxCLK fTIMERxCLK = 108 MHz 9.3 — ns — 0 fTIMERxCLK/2 MHz fTIMERxCLK = 108 MHz 0 54 MHz — — 16 bit — 1 65536 tTIMERxCLK 607 μs 16-bit counter clock period when internal clock is selected tMAX_COUNT (1) Conditions Maximum possible count fTIMERxCLK = 108 MHz 0.0093 — — fTIMERxCLK = 108 MHz — 65536x65536 tTIMERxCLK 39.8 s Guaranteed by design, not tested in production. WDGT characteristics Table 4-56. FWDGT min/max timeout period at 40 kHz (IRC40K)(1) Prescaler divider PR[2:0] bits 1/4 000 Min timeout RLD[11:0] = Max timeout RLD[11:0] 0x000 = 0xFFF 0.025 409.525 Unit ms 91 GD32F103xx Datasheet Prescaler divider PR[2:0] bits 1/8 (1) Min timeout RLD[11:0] = Max timeout RLD[11:0] 0x000 = 0xFFF 001 0.025 819.025 1/16 010 0.025 1638.025 1/32 011 0.025 3276.025 1/64 100 0.025 6552.025 1/128 101 0.025 13104.025 1/256 110 or 111 0.025 26208.025 Unit Guaranteed by design, not tested in production. Table 4-57. WWDGT min-max timeout value at 54 MHz (fPCLK1)(1) PSC[2:0] 1/1 00 75.8 1/2 01 151.7 1/4 10 303.4 1/8 11 606.8 (1) 4.26. Min timeout value Prescaler divider CNT[6:0] = 0x40 Unit Max timeout value CNT[6:0] = 0x7F Unit 4.8 μs 9.7 19.4 ms 38.8 Guaranteed by design, not tested in production. Parameter conditions Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 ℃. 92 GD32F103xx Datasheet 5. Package information 5.1 LQFP144 package outline dimensions Figure 5-1. LQFP144 package outline A3 c F θ A2A A1 D D1 108 73 109 72 0.25 L L1 DETAIL: F E1 E b b1 c1 c 37 144 BASE METAL WITH PLATING 1 e b BB SECTION B-B 36 Table 5-1. LQFP144 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 21.80 22.00 22.20 D1 19.90 20.00 20.10 E 21.80 22.00 22.20 E1 19.90 20.00 20.10 e — 0.50 — L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 93 GD32F103xx Datasheet Figure 5-2. LQFP144 recommended footprint 22.70 109 144 20.30 108 36 73 72 37 17.80 22.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 94 GD32F103xx Datasheet 5.2 LQFP100 package outline dimensions Figure 5-3. LQFP100 package outline A3 A2 A c θ A1 F eB D D1 51 75 0.25 50 76 L L1 DETAIL: F E1 E b b1 100 c1 c 26 BASE METAL 1 25 b e WITH PLATING B B SECTION B-B Table 5-2. LQFP100 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 15.80 16.00 16.20 D1 13.90 14.00 14.10 E 15.80 16.00 16.20 E1 13.90 14.00 14.10 e — 0.50 — eB 15.05 — 15.35 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 95 GD32F103xx Datasheet Figure 5-4. LQFP100 recommended footprint 16.70 76 100 14.30 75 25 51 50 26 12.30 16.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 96 GD32F103xx Datasheet 5.3 LQFP64 package outline dimensions Figure 5-5. LQFP64 package outline A3 A2 A θ c A1 F eB D D1 33 48 0.25 32 49 L L1 DETAIL: F E1 E b b1 c1 c BASE METAL 64 17 WITH PLATING 1 e b SECTION B-B 16 B B Table 5-3. LQFP64 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 11.80 12.00 12.20 D1 9.90 10.00 10.10 E 11.80 12.00 12.20 E1 9.90 10.00 10.10 e — 0.50 — eB 11.25 — 11.45 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 97 GD32F103xx Datasheet Figure 5-6. LQFP64 recommended footprint 12.70 64 49 10.30 48 16 33 17 32 7.80 12.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 98 GD32F103xx Datasheet LQFP48 package outline dimensions Figure 5-7. LQFP48 package outline A3 A2 A θ A1 c 5.4 F eB D D1 36 0.25 25 L 24 37 L1 DETAIL: F E1 E b b1 13 48 c1c BASE METAL WITH PLATING 1 12 b e SECTION B-B BB Table 5-4. LQFP48 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 8.80 9.00 9.20 D1 6.90 7.00 7.10 E 8.80 9.00 9.20 E1 6.90 7.00 7.10 e — 0.50 — eB 8.10 — 8.25 L 0.45 — 0.75 L1 — 1.00 — θ 0° — 7° (Original dimensions are in millimeters) 99 GD32F103xx Datasheet Figure 5-8. LQFP48 recommended footprint 9.70 37 48 7.30 36 12 25 24 13 5.80 9.70 0.30 1 1.20 0.50 (Original dimensions are in millimeters) 100 GD32F103xx Datasheet QFN36 package outline dimensions Figure 5-9. QFN36 package outline Nd D2 D 36 36 1 1 h PIN 1# Laser Mark 2 e b1 b L1 L E2 Ne h E 2 EXPOSED THERMAL PAD ZONE TOP VIEW BOTTOM VIEW A1 A c 5.5 SIDE VIEW Table 5-5. QFN36 package dimensions Symbol Min Typ Max A 0.80 0.85 0.90 A1 0 0.02 0.05 b 0.18 0.23 0.30 b1 — 0.16 — c 0.18 0.20 0.23 D 5.90 6.00 6.10 D2 3.80 3.90 4.00 E 5.90 6.00 6.10 E2 3.80 3.90 4.00 e — 0.50 — h 0.30 0.35 0.40 L 0.50 0.55 0.60 L1 — 0.10 — Nd 3.95 4.00 4.05 Ne 3.95 4.00 4.05 (Original dimensions are in millimeters) 101 GD32F103xx Datasheet Figure 5-10. QFN36 recommended footprint 6.70 36 28 4.80 1 4.28 6.70 3.85 0.28 27 3.85 9 10 18 19 0.95 0.50 (Original dimensions are in millimeters) 102 GD32F103xx Datasheet 5.6 Thermal characteristics Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter “θ”. For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface. θJA: Thermal resistance, junction-to-ambient. θJB: Thermal resistance, junction-to-board. θJC: Thermal resistance, junction-to-case. ᴪJB: Thermal characterization parameter, junction-to-board. ᴪJT: Thermal characterization parameter, junction-to-top center. θJA =(TJ -TA )/PD (5-1) θJB =(TJ -TB )/PD (5-2) θJC =(TJ -TC )/PD (5-3) Where, TJ = Junction temperature. TA = Ambient temperature TB = Board temperature TC = Case temperature which is monitoring on package surface PD = Total power dissipation θJA represents the resistance of the heat flows from the heating junction to ambient air. It is an indicator of package heat dissipation capability. Lower θJA can be considerate as better overall thermal performance. θJA is generally used to estimate junction temperature. θJB is used to measure the heat flow resistance between the chip surface and the PCB board. θJC represents the thermal resistance between the chip surface and the package top case. θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package). Table 5-6. Package thermal characteristics(1) Symbol θJA θJB Condition Natural convection, 2S2P PCB Cold plate, 2S2P PCB Package Value LQFP144 48.76 LQFP100 57.42 LQFP64 61.80 LQFP48 64.40 QFN36 43.20 LQFP144 35.00 Unit °C/W °C/W 103 GD32F103xx Datasheet Symbol θJC ᴪJB ᴪJT (1) Condition Cold plate, 2S2P PCB Natural convection, 2S2P PCB Natural convection, 2S2P PCB Package Value LQFP100 31.68 LQFP64 42.83 LQFP48 42.32 QFN36 16.51 LQFP144 12.03 LQFP100 13.85 LQFP64 21.98 LQFP48 22.47 QFN36 16.18 LQFP144 35.32 LQFP100 41.28 LQFP64 43.05 LQFP48 42.42 QFN36 16.64 LQFP144 1.86 LQFP100 0.75 LQFP64 1.58 LQFP48 1.74 QFN36 1.07 Unit °C/W °C/W °C/W Thermal characteristics are based on simulation, and meet JEDEC specification. 104 GD32F103xx Datasheet 6. Ordering Information Table 6-1. Part ordering code for GD32F103xx devices Ordering code Flash (KB) Package Package type GD32F103ZKT6 3072 LQFP144 Green GD32F103ZIT6 2048 LQFP144 Green GD32F103ZGT6 1024 LQFP144 Green GD32F103ZFT6 768 LQFP144 Green GD32F103ZET6 512 LQFP144 Green GD32F103ZDT6 384 LQFP144 Green GD32F103ZCT6 256 LQFP144 Green GD32F103VKT6 3072 LQFP100 Green GD32F103VIT6 2048 LQFP100 Green GD32F103VGT6 1024 LQFP100 Green GD32F103VFT6 768 LQFP100 Green GD32F103VET6 512 LQFP100 Green GD32F103VDT6 384 LQFP100 Green GD32F103VCT6 256 LQFP100 Green GD32F103VBT6 128 LQFP100 Green GD32F103V8T6 64 LQFP100 Green GD32F103RKT6 3072 LQFP64 Green GD32F103RIT6 2048 LQFP64 Green GD32F103RGT6 1024 LQFP64 Green GD32F103RFT6 768 LQFP64 Green GD32F103RET6 512 LQFP64 Green GD32F103RDT6 384 LQFP64 Green GD32F103RCT6 256 LQFP64 Green GD32F103RBT6 128 LQFP64 Green Temperature operating range Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C 105 GD32F103xx Datasheet Ordering code Flash (KB) Package Package type GD32F103R8T6 64 LQFP64 Green GD32F103R6T6 32 LQFP64 Green GD32F103R4T6 16 LQFP64 Green GD32F103CBT6 128 LQFP48 Green GD32F103C8T6 64 LQFP48 Green GD32F103C6T6 32 LQFP48 Green GD32F103C4T6 16 LQFP48 Green GD32F103TBU6 128 QFN36 Green GD32F103T8U6 64 QFN36 Green GD32F103T6U6 32 QFN36 Green GD32F103T4U6 16 QFN36 Green Temperature operating range Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C 106 GD32F103xx Datasheet 7. Revision History Table 7-1. Revision history Revision No. Description Date 1.0 Initial Release Mar.8, 2013 1. 2.2 Characteristics values modified and package data updated, refers to Electrical characteristics and Oct.10, 2013 Package information. 1. 2.3 Maximum HXTAL frequency value corrected in Table 413. High speed external clock (HXTAL) generated from Oct.20, 2014 a crystal/ceramic characteristics. 2.4 1. Repair history accumulation error. 1. Add missing pin definitions for GD32F103Rx, 8 to 11,18 2.5 and 19 pins in Table 2-7. GD32F103Rx LQFP64 pin Jan.24, 2018 Dec.10, 2018 definitions. 2.6 2.7 1. Delete EXMC_NADV in PB7 of Table 2-7. GD32F103Rx LQFP64 pin definitions. 1. Delete the PD0,PD1 remap to OSC pins information in July 22, 2019 Feb.15, 2020 packages no less than100 pins, refers to Pin definitions. 1. Integrate the boot loader address in chapter Memory map together. 2.8 2. Add description of VREF+ and VREF- connection in chapter Sep.18, 2020 Analog to digital converter (ADC). 3. Arm® Cortex® written format modification. 1. Table 4-3 update, refers to Table 4-3. Power consumption characteristics (for GD32F103x4/6/8/B 2.9 devices) and Table 4-4. Power consumption Apr.12, 2021 characteristics (for GD32F103xC/D/E/F/G/I/K devices) . 2.10 1. Table 5-2 update, refers to Package information. 1. Delete PD0 / PD1 from OSCIN / OSCOUT remap June 22, 2021 information in chapter 2.6.3 to 2.6.5, ETM related functions modification in chapter 2.6.2 to 2.6.5, refers to Pin definitions. 2.11 2. Modify pinouts, refers to Pinouts and pin assignment. 3. Characteristics values modified, and add new tables, refers to Electrical characteristics. 4. May.23, 2022 Package information and Ordering information update, refer to Package information and Ordering information. 5. Modify Vesd (HBM) and Vesd (CDM) standards, refers to Electrical characteristics. 6. Modify SPI/I2S diagrams, refer to SPI characteristics 107 GD32F103xx Datasheet and I2S characteristics. 7. Modify I2C characteristics, refer to I2C characteristics. 8. Power consumption characteristics update, refer to Power consumption. 1. Modify LQFP64 package information, refer to LQFP64 package outline dimensions. 2.12 2. Update NRST external pin circuit, refer to Figure 4-6. Jun.30, 2022 Recommended external NRST pin circuit(1). 3. EXMC related pin update, refer to Pin definitions. 108 GD32F103xx Datasheet Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights, trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property of their respective owner and referred to for identification purposes only. The Company makes no warranty of any kind, express or implied, with regard to this document or any Product, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company does not assume any liability arising out of the application or use of any Product described in this document. Any information provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Except for customized products which has been expressly identified in the applicable agreement, the Products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The Products are not designed, intended, or authorized for use as components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or Product could cause personal injury, death, property or environmental damage ("Unintended Uses"). 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