GigaDevice Semiconductor Inc.
GD32F207xx
ARM® Cortex®-M3 32-bit MCU
Datasheet
GD32F207xx
Table of Contents
List of Figures ................................................................................................................................3
List of Tables ..................................................................................................................................4
1
Introduction .........................................................................................................................5
2
Device overview ..................................................................................................................6
2.1
Device information .............................................................................................................................. 6
2.2
Block diagram ...................................................................................................................................... 8
2.3
Pinouts and pin assignment .............................................................................................................. 9
2.4
Memory map ...................................................................................................................................... 13
2.5
Clock tree ........................................................................................................................................... 14
2.6
Pin definitions .................................................................................................................................... 15
Functional description ..................................................................................................... 26
3
4
3.1
ARM® Cortex®-M3 core .................................................................................................................... 26
3.2
On-chip memory................................................................................................................................ 26
3.3
Clock, reset and supply management ........................................................................................... 27
3.4
Boot modes ........................................................................................................................................ 27
3.5
Power saving modes ........................................................................................................................ 28
3.6
Analog to digital converter (ADC) ................................................................................................... 28
3.7
Digital to analog converter (DAC) ................................................................................................... 29
3.8
DMA .................................................................................................................................................... 29
3.9
General-purpose inputs/outputs (GPIOs) ...................................................................................... 29
3.10
Timers and PWM generation........................................................................................................... 30
3.11
Real time clock (RTC) and backup registers ................................................................................ 31
3.12
Inter-integrated circuit (I2C) ............................................................................................................. 31
3.13
Serial peripheral interface (SPI)...................................................................................................... 32
3.14
Universal synchronous/asynchronous receiver transmitter (USART/UART) ........................... 32
3.15
Inter-IC sound (I2S) .......................................................................................................................... 32
3.16
Universal serial bus on-the-go full-speed (USB OTG FS) .......................................................... 33
3.17
Controller area network (CAN)........................................................................................................ 33
3.18
Ethernet MAC interface .................................................................................................................... 33
3.19
External memory controller (EXMC) .............................................................................................. 34
3.20
Secure digital input and output card interface (SDIO) ................................................................. 34
3.21
TFT LCD display interface (TLDI)................................................................................................... 34
3.22
Digital camera interface (DCI) ......................................................................................................... 35
3.23
Cryptographic acceleration Unit (CAU) ......................................................................................... 35
3.24
Hash acceleration unit (HAU).......................................................................................................... 35
3.25
Random number generator (RNG) ................................................................................................. 36
3.26
Debug mode ...................................................................................................................................... 36
3.27
Package and operation temperature .............................................................................................. 36
Electrical characteristics ................................................................................................. 37
1 / 49
GD32F207xx
4.1
Absolute maximum ratings .............................................................................................................. 37
4.2
Recommended DC characteristics ................................................................................................. 37
4.3
Power consumption .......................................................................................................................... 38
4.4
EMC characteristics .......................................................................................................................... 39
4.5
Power supply supervisor characteristics ....................................................................................... 39
4.6
Electrical sensitivity........................................................................................................................... 40
4.7
External clock characteristics .......................................................................................................... 40
4.8
Internal clock characteristics ........................................................................................................... 41
4.9
PLL characteristics ........................................................................................................................... 42
4.10
Memory characteristics .................................................................................................................... 42
4.11
GPIO characteristics......................................................................................................................... 42
4.12
ADC characteristics .......................................................................................................................... 43
4.13
DAC characteristics .......................................................................................................................... 43
4.14
I2C characteristics ............................................................................................................................ 43
4.15
SPI characteristics ............................................................................................................................ 44
Package information ........................................................................................................ 45
5
5.1
LQFP package outline dimensions................................................................................................. 45
6
Ordering information ....................................................................................................... 47
7
Revision history ................................................................................................................ 48
2 / 49
GD32F207xx
List of Figures
Figure 1. GD32F207xx block diagram ...................................................................................................................... 8
Figure 2. GD32F207Ix LQFP176 pinouts................................................................................................................. 9
Figure 3. GD32F207Zx LQFP144 pinouts ............................................................................................................. 10
Figure 4. GD32F207Vx LQFP100 pinouts ............................................................................................................. 11
Figure 5. GD32F207Rx LQFP64 pinouts ............................................................................................................... 12
Figure 6. GD32F207xx memory map ..................................................................................................................... 13
Figure 7. GD32F207xx clock tree............................................................................................................................ 14
Figure 8. LQFP package outline .............................................................................................................................. 45
3 / 49
GD32F207xx
List of Tables
Table 1. GD32F207xx devices features and peripheral list................................................................................... 6
Table 2. GD32F207xx pin definitions ...................................................................................................................... 15
Table 3. Absolute maximum ratings ........................................................................................................................ 37
Table 4. DC operating conditions ............................................................................................................................ 37
Table 5. Power consumption characteristics ......................................................................................................... 38
Table 6. EMS characteristics ................................................................................................................................... 39
Table 7. EMI characteristics ..................................................................................................................................... 39
Table 8. Power supply supervisor characteristics ................................................................................................. 39
Table 9. ESD characteristics .................................................................................................................................... 40
Table 10. Static latch-up characteristics................................................................................................................. 40
Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics ...................... 40
Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics ....................... 41
Table 13. High speed internal clock (HSI) characteristics ................................................................................... 41
Table 14. Low speed internal clock (LSI) characteristics ..................................................................................... 41
Table 15. PLL characteristics ................................................................................................................................... 42
Table 16. Flash memory characteristics ................................................................................................................. 42
Table 17. I/O port characteristics ............................................................................................................................. 42
Table 18. ADC characteristics .................................................................................................................................. 43
Table 19. DAC characteristics ................................................................................................................................. 43
Table 20. I2C characteristics .................................................................................................................................... 43
Table 21. SPI characteristics .................................................................................................................................... 44
Table 22. LQFP package dimensions ..................................................................................................................... 46
Table 23. Part ordering code for GD32F207xx devices ....................................................................................... 47
Table 24. Revision history......................................................................................................................................... 48
4 / 49
GD32F207xx
1
Introduction
The GD32F207xx device belongs to the performance line of GD32 MCU Family. It is a new
32-bit general-purpose microcontroller based on the ARM® Cortex®-M3 RISC core with best
cost-performance ratio in terms of processing capacity, reduced power consumption and
peripheral set. The Cortex®-M3 is a next generation processor core which is tightly coupled
with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug
support.
The GD32F207xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating
at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It
provides up to 3072 KB on-chip Flash memory and 256 KB SRAM memory. An extensive
range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up
to three 12-bit 2M SPS ADCs, two 12-bit DACs, up to ten general-purpose 16-bit timers, two
16-bit basic timers plus two 16-bit PWM advanced-control timers, as well as standard and
advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and four
UARTs, two I2Ss, two CANs, a SDIO, an USB device/host/OTG FS and an Ethernet MAC.
Additional peripherals as TFT-LCD Interface (TLDI), EXMC interface with SDRAM extension
support, Digital camera interface (DCI), Cryptographic acceleration unit (CAU), Hash
acceleration unit (HAU), Random number generator (RNG) are included.
The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization of power consumption, an especially important consideration in low power
applications.
The above features make GD32F207xx devices suitable for a wide range of interconnection
and advanced applications, especially in areas such as industrial control, consumer and
handheld equipment, embedded modules, human machine interface, security and alarm
systems, POS and electronic payment, automotive navigation and so on.
5 / 49
GD32F207xx
2
Device overview
2.1
Device information
Table 1. GD32F207xx devices features and peripheral list
GD32F207xx
Part Number
RE
RG
RK
VC
VE
VG
VK
Code Area (KB)
256
512
384
384
256
512
384
384
Data Area (KB)
0
0
640
2688
0
0
640
2688
Total (KB)
256
512
1024
3072
256
512
1024
3072
128
128
256
256
128
128
256
256
GPTM
10
10
10
10
10
10
10
10
Advanced TM
2
2
2
2
2
2
2
2
SysTick
1
1
1
1
1
1
1
1
Basic TM
2
2
2
2
2
2
2
2
Watchdog
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
USART+UART
4+2
4+2
4+2
4+2
4+4
4+4
4+4
4+4
I2C
3
3
3
3
3
3
3
3
SPI/I2S
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
SDIO
1
1
1
1
1
1
1
1
CAN 2.0B
2
2
2
2
2
2
2
2
USB OTG FS
1
1
1
1
1
1
1
1
Ethernet MAC
1
1
1
1
1
1
1
1
TFT-LCD
0
0
0
0
1
1
1
1
Digital Camera
1
1
1
1
1
1
1
1
Crypto/Hash
1
1
1
1
1
1
1
1
GPIO
51
51
51
51
82
82
82
82
EXMC/SDRAM
0/0
0/0
0/0
0/0
1/0
1/0
1/0
1/0
ADC Unit (CHs)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
3(16)
DAC
2
2
2
2
2
2
2
2
Flash
RC
Connectivity
Timers
SRAM (KB)
Package
LQFP64
LQFP100
6 / 49
GD32F207xx
Table 1. GD32F207xx devices features and peripheral list (continued)
GD32F207xx
Part Number
ZE
ZG
ZK
IE
IG
IK
Code Area (KB)
256
512
384
384
512
384
384
Data Area (KB)
0
0
640
2688
0
640
2688
Total (KB)
256
512
1024
3072
512
1024
3072
128
128
256
256
128
256
256
GPTM
10
10
10
10
10
10
10
Advanced TM
2
2
2
2
2
2
2
SysTick
1
1
1
1
1
1
1
Basic TM
2
2
2
2
2
2
2
Watchdog
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
USART+UART
4+4
4+4
4+4
4+4
4+4
4+4
4+4
I2C
3
3
3
3
3
3
3
SPI/I2S
3/2
3/2
3/2
3/2
3/2
3/2
3/2
SDIO
1
1
1
1
1
1
1
CAN 2.0B
2
2
2
2
2
2
2
USB OTG FS
1
1
1
1
1
1
1
Ethernet MAC
1
1
1
1
1
1
1
TFT-LCD
1
1
1
1
1
1
1
Digital Camera
1
1
1
1
1
1
1
Crypto/Hash
1
1
1
1
1
1
1
GPIO
114
114
114
114
140
140
140
EXMC/SDRAM
1/1
1/1
1/1
1/1
1/1
1/1
1/1
ADC Unit (CHs)
3(24)
3(24)
3(24)
3(24)
3(24)
3(24)
3(24)
DAC
2
2
2
2
2
2
2
Flash
ZC
Connectivity
Timers
SRAM (KB)
Package
LQFP144
LQFP176
7 / 49
GD32F207xx
2.2
Block diagram
Figure 1. GD32F207xx block diagram
SW/JTAG
TPIU
ICode DCode System
ARM Cortex-M3
Processor
Fmax:120MHz
NVIC
POR/ PDR
Flash
Memory
PLL
F max : 144MHz
Dbus
Slave
Slave
Master
Slave
Master
DMA2 (7 chs)
Master
AHB Matrix
DMA1(7 chs)
ETH
Flash
Memory
Controller
Ibus
Master
Slave
Slave
EXMC
SRAM1
SRAM2
SRAM3
Slave
HSI
8MHz
DCI
CRYP HASH RNG
AHB2 Peripherals
SDIO
TLDI
LDO
1.2V
USB
OTG CRC RCC
AHB1 Peripherals
AHB to AP B
Brid ge2
HSE
4-25MHz
AHB to AP B
Brid ge1
Master
LVD
Interrput request
WWDG
USART1
Slave
SAR ADC
Slave
SPI1
IWDG
ADC1~3
RTC
EXTI
DAC
GPIOA
CAN1
GPIOB
CAN2
Powered By V DDA
GPIOE
APB1: Fmax = 60MHZ
GPIOD
APB2: Fmax = 120MHz
GPIOC
SPI2~3
TIMER2~4
TIMER5~7
GPIOF
TIMER
12~14
GPIOG
USART2~5
TIMER1
USART7~8
TIMER8
I2C1
TIMER9~11
USART6
Powered By VDDA
I2C2
I2C3
GPIOH
USB FS
GPIOI
8 / 49
GD32F207xx
Pinouts and pin assignment
2.3
Figure 2. GD32F207Ix LQFP176 pinouts
PI2
PI3
VSS
VDD
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG11
PG10
PG12
PG14
PG13
VSS_11
VDD_11
PB3
PG15
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PI4
PI5
PI6
PI7
PE2
1
176175174173172171170169168167166165 164163162161160159158157156155154153152 151150149148147146145144143142141140139138137136135134133
132
PE3
PE4
2
131
PI0
3
130
PH15
PE5
PE6
4
129
5
128
PH14
PH13
VBAT
6
127
VDD_2
PI8
7
126
VSS_2
PC13-TAMPER-RTC
PC14-OSC32_IN
8
125
9
124
NC
PA13
PC15-OSC32_OUT
10
123
PA12
PI9
11
122
PA11
PI10
12
121
PA10
PI11
13
120
PA9
PI1
VSS_5
14
119
PA8
VDD_5
15
118
PC9
PF0
16
117
PF1
17
116
PC8
PC7
PF2
18
115
PC6
PF3
19
114
VDD_9
PF4
20
113
VSS_9
PF5
21
112
PG8
VSS
22
VDD
23
PF6
24
PF7
25
PF8
111
PG7
110
PG6
109
PG5
108
PG4
26
107
PG3
PF9
27
106
PG2
PF10
28
105
PD15
PH0-OSC_IN
29
104
PD14
PH1-OSC_OUT
30
103
VDD_8
NRST
31
102
VSS_8
PC0
32
101
PD13
PC1
33
100
PD12
PC2
34
99
PD11
PC3
35
98
PD10
VSSA
36
97
PD9
VREFVREF+
37
96
PD8
38
95
PB15
VDD
39
94
PB14
PA0_WKUP
40
93
PA1
41
92
PB13
PB12
VDD
GigaDevice GD32F207Ix
LQFP176
PA2
42
91
PH2
43
90
VSS
PH3
44
89
PH12
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
PH11
PH10
PH9
PH8
PH7
VDD_1
PH6
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE9
PE7
PE8
PG1
PI5
PG0
PI4
VDD_6
PI3
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
PH5
PH4
9 / 49
GD32F207xx
Figure 3. GD32F207Zx LQFP144 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109
PE2
1
108
PE3
PE4
2
107
VSS_2
3
106
NC
PE5
PE6
4
105
PA13
5
104
PA12
VBAT
6
103
PA11
PC13-TAMPER-RTC
PC14-OSC32_IN
7
102
PA10
8
101
PA9
PC15-OSC32_OUT
9
100
PA8
PF0
10
99
PC9
VDD_2
PF1
11
98
PC8
PF2
12
97
PC7
PF3
PF4
13
96
PC6
14
95
VDD_9
PF5
15
94
VSS_9
VSS_5
16
93
PG8
92
PG7
91
PG6
90
PG5
89
PG4
VDD_5
17
PF6
18
PF7
19
PF8
20
PF9
21
PF10
22
GigaDevice GD32F207Zx
LQFP144
88
PG3
87
PG2
OSC_IN
23
86
PD15
OSC_OUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
82
PD13
PC2
28
81
PD12
PC3
VSSA
29
80
PD11
30
79
PD10
VREFVREF+
31
78
PD9
32
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE9
PE7
PE8
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
10 / 49
GD32F207xx
Figure 4. GD32F207Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32_IN
7
70
69
PA10
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS_5
10
66
PC9
65
PC8
64
PC7
63
PC6
14
62
PD15
VDD_2
PA11
VDD_5
11
OSC_IN
12
OSC_OUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
GigaDevice GD32F207Vx
LQFP100
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PB2
PE7
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
11 / 49
GD32F207xx
Figure 5. GD32F207Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
PD0-OSC_IN
4
45
PA12
5
44
PA11
PD1 OSC_OUT
6
43
PA10
NRST
PC0
7
42
PA9
PC1
9
PC2
PC3
VSSA
GigaDevice GD32F207Rx
LQFP64
41
PA8
40
PC9
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PB11
PB10
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
12 / 49
GD32F207xx
2.4
Memory map
Figure 6. GD32F207xx memory map
0xFFFF FFFF
4
0xE010 0000
0x1FFF FFFF
0x1FFF F80F
reserved
reserved
0xE000 0000
Cortex-M3 Internal
Peripherals
3
EXMC
Option
Bytes
0x1FFF F800
System
memory
0x1FFF B000
reserved
0x6000 0000
0x082F FFFF
2
Peripherals
0x4000 0000
Flash
memory
1
reserved
0x2000 0000
SRAM
0
reserved
0x0800 0000
Aliased to Flash or
system memory
according to BOOT
0x0000 0000 pins configuration
0x0000 0000
0x5FFF FFFF
0x5006 0C00
0x5006 0800
0x5006 0400
0x5006 0000
0x5005 0400
0x5005 0000
0x5000 0000
0x5000 0000
0x4002 A000
0x4002 8000
0x4002 3400
0x4002 3000
0x4002 2400
0x4002 2000
0x4002 1400
0x4002 1000
0x4002 0800
0x4002 0400
0x4002 0000
0x4001 8400
0x4001 8000
0x4001 7C00
0x4001 7800
0x4001 7400
0x4001 7000
0x4001 6C00
0x4001 6800
0x4001 5800
0x4001 5400
0x4001 5000
0x4001 4C00
0x4001 4000
0x4001 3C00
0x4001 3800
0x4001 3400
0x4001 3000
0x4001 2C00
0x4001 2800
0x4001 2400
0x4001 2000
0x4001 1C00
0x4001 1800
0x4001 1400
0x4001 1000
0x4001 0C00
0x4001 0800
0x4001 0400
0x4001 0000
0x4000 C400
0x4000 C000
0x4000 8000
0x4000 7C00
0x4000 7800
0x4000 7400
0x4000 7000
0x4000 6C00
0x4000 6800
0x4000 6400
0x4000 6000
0x4000 5C00
0x4000 5800
0x4000 5400
0x4000 5000
0x4000 4C00
0x4000 4800
0x4000 4400
0x4000 4000
0x4000 3C00
0x4000 3800
0x4000 3400
0x4000 3000
0x4000 2C00
0x4000 2800
0x4000 2400
0x4000 2000
0x4000 1C00
0x4000 1800
0x4000 1400
0x4000 1000
0x4000 0C00
0x4000 0800
0x4000 0400
0x4000 0000
reserved
RNG
HASH
CRYP
reserved
DCI
reserved
USBOTG
reserved
ETH
reserved
CRC
reserved
FMC
reserved
RCC
reserved
DMA2
DMA1
reserved
SDIO
reserved
Port I
Port H
USART6
reserved
TLDI
reserved
TIMER11
TIMER10
TIMER9
reserved
ADC3
USART1
TIMER8
SPI1
TIMER1
ADC2
ADC1
Port G
Port F
Port E
Port D
Port C
Port B
Port A
EXTI
AFIO
reserved
I2C3
reserved
UART8
UART7
DAC
PWR
BKP
CAN2
CAN1
USB/CAN shared
USB FS
I2C2
I2C1
USART5
USART4
USART3
USART2
reserved
SPI3
SPI2
reserved
IWDG
WWDG
RTC
reserved
TIMER14
TIMER13
TIMER12
TIMER7
TIMER6
TIMER5
TIMER4
TIMER3
TIMER2
13 / 49
GD32F207xx
2.5
Clock tree
Figure 7. GD32F207xx clock tree
CK_HSE
PLLT prescaler
(PLLTPS )
÷2,3...63
1 PLLT input clock
0
CK_HSI
PLLTSEL
VCO input clock ×49,50,
…,432
CK_VCO
PLLTR prescaler
(PLLTRPS )
÷2,3...7
CK_PLLTR
TCDI prescaler
(TCDIPS )
÷2,4,8,16
USB OTG
Prescaler
÷1,1.5,2,2.5
48 MHz
CK_TCDI
PLLTMF
(to FMC)
1
SCS[1:0]
CK_USB OTG
(to USB OTG)
CK_FMC
CK_HSI
8 MHz
HSI RC
00
×2,3,4
…,32
PLL
0
/2
1
PLLSEL
PLLPREDV
0
3-25 MHz
HSE XTAL
1
CK_PLL
PLLMF
/1,2,3…
15,16
10
AHB
Prescaler
÷1,2...512
CK_SYS
120 MHz max
CK_AHB
120 MHz max
CK_RNG
Peripheral enable
(to RNG )
01
CK_HAU
Peripheral enable
(to HAU)
Peripheral enable
(to CAU )
Clock
Monitor
CK_CAU
PREDV1SEL
EXT1 to
CK_OUT
CK_HSE
CK_DCI
Peripheral enable
(to DCI)
CK_EXMC
×8,9,10…,
14,16,20
PLL2
CK_PLL2
×8,9,10…,
14,16,20
PLL3
PREDV2
(to EXMC)
AHB enable
(to AHB bus,Cortex-M3,SRAM,DMA)
HCLK
PLL2MF
/1,2,3…
15,16
EXMC enable
(by hardware)
0
CK_PLL3
x2
CK_CST
CK_I2S
÷8
1 (to I2S2,3)
(to Cortex-M3 SysTick)
FCLK
I2S2/3SEL
(free running clock)
PLL3MF
/128
32.768 KHz
LSE OSC
11
CK_RTC
01
(to RTC)
RTCSRC[1:0]
40 KHz
LSI RC
CK_IWDG
(to IWDG)
CKOUTDIV
÷1,2...64
00xx
0100
0101
0110
0111
NO CLK
CK_SYS
CK_HSI
CK_HSE
/2
CK_PLL
CK_PLL2
/2
CK_PLL3
1000
1001
1010
1011
EXT1
CK_PLL3
CK_APB1
60 MHz max
PCLK1
to APB1 peripherals
Peripheral enable
TIMER2,3,4,5,6,7,
12,13,14 if(APB1
prescale =1)x1
else x 2
10
CK_OUT
APB1
Prescaler
÷1,2,4,8,16
APB2
Prescaler
÷1,2,4,8,16
TIMERx
enable
CK_TIMERx
to TIMER2,3,4,5,
6,7,12,13,14
CK_APB2
120 MHz max
PCLK2
to APB2 peripherals
Peripheral enable
TIMER1,8,9,10,11
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,8,12,16
CK_TIMERx
TIMERx
enable
to
TIMER1,8,9,10,11
CK_ADCX to ADC1,2,3
14 MHz max
CKOUTSEL[3:0]
CK_OUT2
CKOUT2DIV
÷1,2...64
00xx
0100
0101
0110
0111
NO CLK
CK_SYS
CK_HSI
CK_HSE
CK_PLL
/2
CK_PLL2
CK_PLL3
/2
1000
1001
1010
1011
EXT1
CK_PLL3
CKOUT2SEL[3:0]
0 CK_MACTX
1
Ethernet
PHY
/2,20
0 CK_MACRX
1
CK_MACRMII
Legend:
HSE = High speed external clock
HSI = High speed internal clock
LSE = Low speed external clock
LSI = Low speed internal clock
14 / 49
GD32F207xx
2.6
Pin definitions
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
Table 2. GD32F207xx pin definitions
Functions description
Default: PE2
PE2
1
1
1
-
I/O 5VT Alternate: TRACECK, EXMC_A23
Remap: ETH_MII_TXD3
Default: PE3
PE3
2
2
2
-
I/O 5VT
PE4
3
3
3
-
I/O 5VT Alternate:TRACED1, EXMC_A20
Alternate: TRACED0, EXMC_A19
Default: PE4
Remap: DCMI_D4, LCD_B0
Default: PE5
PE5
4
4
4
-
I/O 5VT Alternate:TRACED2, EXMC_A21
Remap: TM9_CH1, DCMI_D6, LCD_G0
Default: PE6
PE6
5
5
5
-
I/O 5VT Alternate:TRACED3, EXMC_A22
Remap: TM9_CH2, DCMI_D7, LCD_G1
VBAT
6
6
6
1
P
Default: VBAT
PI8
7
-
-
-
I/O
Default: PI8
8
7
7
2
I/O 5VT
9
8
8
3
I/O
10
9
9
4
I/O
PC13TAMPERRTC
PC14OSC32_IN
PC15OSC32_OUT
Default: PC13
Alternate: TAMPER, RTC
Default: PC14
Alternate: OSC32_IN
Default: PC15
Alternate: OSC32_OUT
Default: PI9
PI9
11
-
-
-
I/O 5VT Alternate: EXMC_D30
Remap: LCD_VSYNC, CAN1_RX
Default: PI10
PI10
12
-
-
-
I/O 5VT Alternate: EXMC_D31
PI11
13
-
-
-
I/O 5VT Default: PI11
VSS
14
-
-
-
P
Default: VSS
VDD
15
-
-
-
P
Default: VDD
PF0
16
10
-
-
Remap: LCD_HSYNC, ETH_MII_RX_ER
Default: PF0
I/O 5VT Alternate: EXMC_A0
Remap: I2C2_SDA
Default: PF1
PF1
17
11
-
-
I/O 5VT Alternate: EXMC_A1
Remap: I2C2_SCL
15 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
Default: PF2
PF2
18
12
-
-
I/O 5VT Alternate: EXMC_A2
Remap: I2C2_SMBA
Default: PF3
PF3
19
13
-
-
I/O 5VT Alternate: EXMC_A3
Remap: ADC3_IN9
Default: PF4
PF4
20
14
-
-
I/O 5VT Alternate: EXMC_A4
Remap: ADC3_IN14
Default: PF5
PF5
21
15
-
-
I/O 5VT Alternate: EXMC_A5
Remap: ADC3_IN15
VSS_5
22
16
10
-
P
VDD_5
23
17
11
-
P
Default: VSS_5
Default: VDD_5
Default: PF6
PF6
24
18
-
-
I/O
Alternate: ADC3_IN4, EXMC_NIORD
Remap: TM10_CH1, UART7_RX
Default: PF7
PF7
25
19
-
-
I/O
Alternate: ADC3_IN5, EXMC_NREG
Remap: TM11_CH1, UART7_TX
Default: PF8
PF8
26
20
-
-
I/O
Alternate: ADC3_IN6, EXMC_NIOWR
Remap: TM13_CH1
Default: PF9
PF9
27
21
-
-
I/O
Alternate: ADC3_IN7, EXMC_CD
Remap: TM14_CH1
Default: PF10
PF10
28
22
-
-
I/O
Alternate: ADC3_IN8, EXMC_INTR
Remap: DCMI_D11, LCD_DE
PH0-
29
23
12
5
I
30
24
13
6
O
NRST
31
25
14
7
I/O
PC0
32
26
15
8
I/O
OSC_IN
PH1OSC_OUT
Default: OSC_IN
Remap: PD0, PH0
Default: OSC_OUT
Remap: PD1, PH1
Default: NRST
Default: PC0
Alternate: ADC_IN10
Remap: EXMC_SDNWE
PC1
33
27
16
9
I/O
Default: PC1
Alternate: ADC_IN11, ETH_MII_MDC, ETH_RMII_MDC
Default: PC2
PC2
34
28
17
10
I/O
Alternate: ADC_IN12, ETH_MII_TXD2
Remap: EXMC_SDNE0, SPI2_MISO
PC3
35
29
18
11
I/O
Default: PC3
16 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
Alternate: ADC_IN13, ETH_MII_TX_CLK
Remap: EXMC_SDCKE0, SPI2_MOSI, I2S2_SD
VSSA
36
30
19
12
P
Default: VSSA
VREF-
37
31
20
-
P
Default: VREF-
VREF+
38
32
21
-
P
Default: VREF+
VDDA
39
33
22
13
P
Default: VDDA
Default: PA0
PA0-WKUP
40
34
23
14
I/O
Alternate: WKUP, USART2_CTS, ADC_IN0, TM2_CH1_ETR,
TM5_CH1, TM8_ETR, ETH_MII_CRS_WKUP
Remap: UART4_TX
Default: PA1
PA1
41
35
24
15
I/O
Alternate: USART2_RTS, ADC_IN1, TM2_CH2,
TM5_CH2,ETH_MII_RX_CLK, ETH_RMII_REF_CLK
Remap: UART4_RX
Default: PA2
PA2
42
36
25
16
I/O
Alternate: USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3,
TM9_CH1,ETH_MII_MDIO, ETH_RMII_MDIO, SPI1_IO3
Default: PH2
PH2
43
-
-
-
I/O 5VT Alternate: EXMC_SDCKE0
Remap: LCD_R0, ETH_MII_CRS_WKUP
Default: PH3
PH3
44
-
-
-
I/O 5VT Alternate: EXMC_SDNE0
Remap: LCD_R1, ETH_MII_COL
Default: PH4
PH4
45
-
-
-
I/O 5VT
PH5
46
-
-
-
I/O 5VT Alternate: EXMC_SDNWE
Remap: I2C2_SCL, LCD_R0
Default: PH5
Remap: I2C2_SDA
Default: PA3
PA3
47
37
26
17
I/O
Alternate: USART2_RX, ADC_IN3, TM2_CH4, TM5_CH4, TM9_CH2,
ETH_MII_COL, SPI1_IO4
Remap: LCD_B5
VSS_4
48
38
27
18
P
VDD_4
49
39
28
19
P
Default: VSS_4
Default: VDD_4
Default: PA4
PA4
50
40
29
20
I/O
Alternate: SPI1_NSS, USART2_CK, DAC_OUT1, ADC12_IN4,
DCMI_HSYNC
Remap: SPI3_NSS, I2S3_WS, LCD_VSYNC
Default: PA5
PA5
51
41
30
21
I/O
Alternate: SPI1_SCK, ADC12_IN5, DAC_OUT2
Remap: TM2_CH1_ETR, TM8_CH1N
PA6
52
42
31
22
I/O
Default: PA6
Alternate: SPI1_MISO, ADC12_IN6, TM3_CH1, TM8_BKIN,
17 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
TM13_CH1, DCMI_PIXCLK
Remap: TM1_BKIN, LCD_G2
Default: PA7
PA7
53
43
32
23
I/O
Alternate: SPI1_MOSI, ADC12_IN7, TM3_CH2, TM8_CH1N,
TM14_CH1, ETH_MII_RX_DV, ETH_RMII_CRS_DV
Remap: TM1_CH1N
PC4
54
44
33
24
I/O
PC5
55
45
34
25
I/O
PB0
56
46
35
26
I/O
Default: PC4
Alternate: ADC12_IN14, ETH_MII_RXD0. ETH_RMII_RXD0
Default: PC5
Alternate: ADC12_IN15, ETH_MII_RXD1, ETH_RMII_RXD1
Default: PB0
Alternate: ADC12_IN8, TM3_CH3, TM8_CH2N, ETH_MII_RXD2
Remap: TM1_CH2N, LCD_R3
Default: PB1
PB1
57
47
36
27
I/O
Alternate: ADC12_IN9, TM3_CH4, TM8_CH3N, ETH_MII_RXD3
Remap: TM1_CH3N, LCD_R6
I/O 5VT Default: PB2, BOOT1
PB2
58
48
37
28
PF11
59
49
-
-
I/O 5VT
PF12
60
50
-
-
I/O 5VT
VSS_6
61
51
-
-
P
Default: VSS_6
VDD_6
62
52
-
-
P
Default: VDD_6
PF13
63
53
-
-
I/O 5VT
PF14
64
54
-
-
I/O 5VT
PF15
65
55
-
-
I/O 5VT
PG0
66
56
-
-
I/O 5VT
PG1
67
57
-
-
I/O 5VT
Default: PF11
Alternate: EXMC_NIOS16, DCMI_D12, EXMC_SDNRAS
Default: PF12
Alternate: EXMC_A6
Default: PF13
Alternate: EXMC_A7
Default: PF14
Alternate: EXMC_A8
Default: PF15
Alternate: EXMC_A9
Default: PG0
Alternate: EXMC_A10
Default: PG1
Alternate: EXMC_A11
Default: PE7
PE7
68
58
38
-
I/O 5VT Alternate: EXMC_D4, UART7_RX
Remap: TM1_ETR
Default: PE8
PE8
69
59
39
-
I/O 5VT Alternate: EXMC_D5, UART7_TX
Remap: TM1_CH1N
Default: PE9
PE9
70
60
40
-
VSS_7
71
61
-
-
I/O 5VT Alternate: EXMC_D6
Remap: TM1_CH1
P
Default: VSS_7
18 / 49
LQFP176
LQFP144
LQFP100
LQFP64
Pin Type(1)
Pins
VDD_7
72
62
-
-
P
PE10
73
63
41
-
Pin Name
I/O(2) Level
GD32F207xx
Functions description
Default: VDD_7
Default: PE10
I/O 5VT Alternate: EXMC_D7
Remap: TM1_CH2N
Default: PE11
PE11
74
64
42
-
I/O 5VT Alternate: EXMC_D8
Remap: TM1_CH2, LCD_G3
Default: PE12
PE12
75
65
43
-
I/O 5VT Alternate: EXMC_D9
Remap: TM1_CH3N, LCD_B4
Default: PE13
PE13
76
66
44
-
I/O 5VT Alternate: EXMC_D10
Remap: TM1_CH3, LCD_DE
Default: PE14
PE14
77
67
45
-
I/O 5VT Alternate: EXMC_D11
Remap: TM1_CH4, LCD_CLK
Default: PE15
PE15
78
68
46
-
I/O 5VT Alternate: EXMC_D12
Remap: TM1_BKIN, LCD_R7
Default: PB10
PB10
79
69
47
29
I/O 5VT Alternate: I2C2_SCL, USART3_TX, ETH_MII_RX_ER
Remap: TM2_CH3, LCD_G4, SPI2_SCK, I2S2_CK
Default: PB11
PB11
80
70
48
30
I/O 5VT
Alternate: I2C2_SDA, USART3_RX, ETH_MII_TX_EN,
ETH_RMII_TX_EN
Remap: TM2_CH4, LCD_G5
VSS_1
81
71
49
31
P
Default: VSS_1
VDD_1
82
72
50
32
P
Default: VDD_1
Default: PH6
PH6
83
-
-
-
I/O 5VT Alternate: EXMC_SDNE1
Remap: I2C2_SMBA, TM12_CH1, ETH_MII_RXD2, DCMI_D8
Default: PH7
PH7
84
-
-
-
I/O 5VT Alternate: EXMC_SDCKE1
Remap: I2C3_SCL, ETH_MII_RXD3, DCMI_D9
Default: PH8
PH8
85
-
-
-
I/O 5VT Alternate: EXMC_D16
Remap: LCD_R2, I2C3_SDA, DCMI_HSYNC
Default: PH9
PH9
86
-
-
-
I/O 5VT Alternate: EXMC_D17
Remap: LCD_R3, I2C3_SMBA, TM12_CH2, DCMI_D0
Default: PH10
PH10
87
-
-
-
I/O 5VT Alternate: EXMC_D18
Remap: LCD_R4, TM5_CH1, DCMI_D1
19 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
Default: PH11
PH11
88
-
-
-
I/O 5VT Alternate: EXMC_D19
Remap: LCD_R5, TM5_CH2, DCMI_D2
Default: PH12
I/O 5VT Alternate: EXMC_D20
PH12
89
-
-
-
VSS
90
-
-
-
P
Default: VSS
VDD
91
-
-
-
P
Default: VDD
Remap: LCD_R6, TM5_CH3, DCMI_D3
Default: PB12
PB12
92
73
51
33
I/O 5VT Alternate: SPI2_NSS, I2C2_SMBA, USART3_CK, TM1_BKIN,
I2S2_WS, CAN2_RX, ETH_MII_TXD0, ETH_RMII_TXD0
Default: PB13
PB13
93
74
52
34
I/O 5VT Alternate: SPI2_SCK, USART3_CTS, TM1_CH1N, I2S2_CK,
CAN2_TX , ETH_MII_TXD1, ETH_RMII_TXD1
PB14
94
75
53
35
I/O 5VT
PB15
95
76
54
36
I/O 5VT
PD8
96
77
55
-
Default: PB14
Alternate: SPI2_MISO, USART3_RTS, TM1_CH2N, TM12_CH1
Default: PB15
Alternate: SPI2_MOSI, TM1_CH3N, I2S2_SD, TM12_CH2
Default: PD8
I/O 5VT Alternate: EXMC_D13
Remap: USART3_TX, ETH_MII_RX_DV, ETH_RMII_CRS_DV
Default: PD9
PD9
97
78
56
-
I/O 5VT Alternate: EXMC_D14
Remap: USART3_RX, ETH_MII_RXD0, ETH_RMII_RXD0
Default: PD10
PD10
98
79
57
-
I/O 5VT Alternate: EXMC_D15
Remap: USART3_CK, ETH_MII_RXD1, ETH_RMII_RXD1, LCD_B3
Default: PD11
PD11
99
80
58
-
I/O 5VT Alternate: EXMC_A16
Remap: USART3_CTS, ETH_MII_RXD2
Default: PD12
PD12
100
81
59
-
I/O 5VT Alternate: EXMC_A17
Remap: TM4_CH1, USART3_RTS
Default: PD13
I/O 5VT Alternate: EXMC_A18
PD13
101
82
60
-
VSS_8
102
83
-
-
P
Default: VSS_8
VDD_8
103
84
-
-
P
Default: VDD_8
Remap: TM4_CH2
Default: PD14
PD14
104
85
61
-
I/O 5VT Alternate: EXMC_D0
Remap: TM4_CH3
PD15
105
86
62
-
I/O 5VT
Default: PD15
Alternate: EXMC_D1
20 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
Remap: TM4_CH4
PG2
106
87
-
-
I/O 5VT
PG3
107
88
-
-
I/O 5VT
PG4
108
89
-
-
I/O 5VT
PG5
109
90
-
-
I/O 5VT
Default: PG2
Alternate: EXMC_A12
Default: PG3
Alternate: EXMC_A13
Default: PG4
Alternate: EXMC_A14, EXMC_BA0
Default: PG5
Alternate: EXMC_A15, EXMC_BA1
Default: PG6
PG6
110
91
-
-
I/O 5VT Alternate: EXMC_INT2
Remap: DCMI_D12, LCD_R7
Default: PG7
PG7
111
92
-
-
I/O 5VT Alternate: EXMC_INT3, DCMI_D13
Remap: USART6_CK, LCD_CLK
Default: PG8
PG8
112
93
-
-
I/O 5VT Alternate: EXMC_SDCLK, USART6_RTS
Remap: ETH_PPS_OUT
VSS_9
113
94
-
-
P
Default: VSS_9
VDD_9
114
95
-
-
P
Default: VDD_9
PC6
115
96
63
37
Default: PC6
I/O 5VT Alternate: I2S2_MCK; TM8_CH1, SDIO_D6, USART6_TX
Remap: TM3_CH1, DCMI_D0, LCD_HSYNC
Default: PC7
PC7
116
97
64
38
I/O 5VT Alternate: I2S3_MCK; TM8_CH2, SDIO_D7, USART6_RX
Remap: TM3_CH2, DCMI_D1, LCD_G6
Default: PC8
PC8
117
98
65
39
I/O 5VT Alternate: TM8_CH3, SDIO_D0, DCMI_D2, USART6_CK
Remap: TM3_CH3
Default: PC9
PC9
118
99
66
40
I/O 5VT Alternate: TM8_CH4, SDIO_D1, DCMI_D3, MCO2
Remap: TM3_CH4, I2C3_SDA
Default: PA8
PA8
119
100 67
41
I/O 5VT Alternate: USART1_CK, TM1_CH1, MCO, VCORE, OTG_FS_SOF
Remap: LCD_R6, I2C3_SCL
Default: PA9
PA9
120
101 68
42
I/O 5VT Alternate: USART1_TX, TM1_CH2, OTG_FS_VBUS, DCMI_D0
Remap: I2C3_SMBAI
Default: PA10
PA10
121
102 69
43
I/O 5VT
PA11
122
103 70
44
I/O 5VT Alternate: USART1_CTS, CANRX, OTG_FS_DM, USBDM, TM1_CH4
Alternate: USART1_RX, TM1_CH3, OTG_FS_ID, DCMI_D1
Default: PA11
Remap: LCD_R4
21 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
Default: PA12
PA12
123
104 71
45
I/O 5VT
Alternate: USART1_RTS, OTG_FS_DP, CAN1_TX,
TM1_ETR,USBDP
Remap: LCD_R5
I/O 5VT
Default: JTMS, SWDIO
PA13
124
105 72
46
NC
125
106 73
-
VSS_2
126
107 74
47
P
Default: VSS_2
VDD_2
127
108 75
48
P
Default: VDD_2
PH13
128
Remap: PA13
-
Default: PH13
-
-
-
I/O 5VT Alternate: EXMC_D21
Remap: LCD_G2, TM8_CH1N, CAN1_TX
Default: PH14
PH14
129
-
-
-
I/O 5VT Alternate: EXMC_D22
Remap: LCD_G3, TM8_CH2N, DCMI_D4
Default: PH15
PH15
130
-
-
-
I/O 5VT Alternate: EXMC_D23
Remap: LCD_G4, TM8_CH3N, DCMI_D11
Default: PI0
PI0
131
-
-
I/O 5VT Alternate: EXMC_D24
Remap: LCD_G5, TM5_CH4, SPI2_NSS, I2S2_WS, DCMI_D13
Default: PI1
PI1
132
-
-
-
I/O 5VT Alternate: EXMC_D25
Remap: LCD_G6, SPI2_SCK, I2S2_CK, DCMI_D8
Default: PI2
PI2
133
-
-
-
I/O 5VT Alternate: EXMC_D26
Remap: LCD_G7, TM8_CH4, SPI2_MISO, DCMI_D9
Default: PI3
I/O 5VT Alternate: EXMC_D27
PI3
134
-
-
-
VSS
135
-
-
-
P
Default: VSS
VDD
136
-
-
-
P
Default: VDD
PA14
137
Remap: TM8_ETR, SPI2_MOSI, I2S2_SD, LCD_R1, DCMI_D10
109 76
49
I/O 5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
138
110 77
50
I/O 5VT Alternate: SPI3_NSS, I2S3_WS
Remap: TM2_CH1_ETR, PA15, SPI1_NSS
Default: PC10
PC10
139
111 78
51
I/O 5VT Alternate: UART4_TX, SDIO_D2, DCMI_D8
Remap: USART3_TX, SPI3_SCK, I2S3_CK, LCD_R2
Default: PC11
PC11
140
112 79
52
I/O 5VT Alternate: UART4_RX, SDIO_D3, DCMI_D4
Remap: USART3_RX, SPI3_MISO
22 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
Default: PC12
PC12
141
113 80
53
I/O 5VT Alternate: UART5_TX, SDIO_CK, DCMI_D9
Remap: USART3_CK, SPI3_MOSI, I2S3_SD
Default: PD0
PD0
142
114 81
5
I/O 5VT Alternate: EXMC_D2
Remap: CAN1_RX, OSC_IN
Default: PD1
PD1
143
115 82
6
I/O 5VT Alternate: EXMC_D3
Remap: CAN1_TX, OSC_OUT
PD2
144
116 83
54
I/O 5VT
Default: PD2
Alternate: TM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11
Default: PD3
PD3
145
117 84
-
I/O 5VT Alternate: EXMC_CLK
Remap: USART2_CTS, DCMI_D5, LCD_G7, SPI2_SCK, I2S2_CK
Default: PD4
PD4
146
118 85
-
I/O 5VT Alternate: EXMC_NOE
Remap: USART2_RTS
Default: PD5
PD5
147
119 86
-
I/O 5VT Alternate: EXMC_NWE
Remap: USART2_TX
VSS_10
148
120
-
-
P
Default: VSS_10
VDD_10
149
121
-
-
P
Default: VDD_10
PD6
150
122 87
Default: PD6
-
I/O 5VT Alternate: EXMC_NWAIT
Remap: USART2_RX, DCMI_D10, LCD_B2, SPI3_MOSI, I2S3_SD
Default: PD7
PD7
151
123 88
-
I/O 5VT Alternate: EXMC_NE1, EXMC_NCE2
Remap: USART2_CK
Default: PG9
PG9
152
124
-
-
I/O 5VT Alternate: EXMC_NE2, EXMC_NCE3
Remap: DCMI_VSYNC, USART6_RX
Default: PG10
PG10
153
125
-
-
I/O 5VT Alternate: EXMC_NCE4_1, EXMC_NE3
Remap: DCMI_D2, LCD_G3, LCD_B2
Default: PG11
PG11
154
126
-
-
I/O 5VT Alternate: EXMC_NCE4_2
Remap: DCMI_D3, LCD_B3, ETH_MII_TX_EN, ETH_RMII_TX_EN
Default: PG12
PG12
155
127
-
-
I/O 5VT Alternate: EXMC_NE4
Remap: USART6_RTS, LCD_B4, LCD_B1
Default: PG13
PG13
156
128
-
-
I/O 5VT Alternate: EXMC_A24
Remap: USART6_CTS, ETH_MII_TXD0, ETH_RMII_TXD0
23 / 49
I/O(2) Level
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
Pin Type(1)
GD32F207xx
Functions description
Default: PG14
PG14
157
129
-
-
I/O 5VT Alternate: EXMC_A25
Remap: USART6_TX, ETH_MII_TXD1, ETH_RMII_TXD1
VSS_11
158
130
-
-
P
Default: VSS_10
VDD_11
159
131
-
-
P
Default: VDD_10
Default: PG15
PG15
160
132
-
-
I/O 5VT Alternate: EXMC_SDNCAS, USART6_CTS
Remap: DCMI_D13
Default: JTDO
PB3
161
133 89
55
I/O 5VT Alternate:SPI3_SCK, I2S3_CK
Remap: PB3, TRACESWO, TM2_CH2, SPI1_SCK
Default: NJTRST
PB4
162
134 90
56
I/O 5VT Alternate: SPI3_MISO
Remap: TM3_CH1, PB4, SPI1_MISO
Default: PB5
PB5
163
135 91
57
I/O
Alternate: I2C1_SMBA, SPI3_MOSI, I2S3_SD, ETH_MII_PPS,
ETH_RMII_PPS_OUT, DCMI_D10
Remap: TM3_CH2, SPI1_MOSI, CAN2_RX, EXMC_SDCKE1
Default: PB6
PB6
164
136 92
58
I/O 5VT Alternate: I2C1_SCL, TM4_CH1, DCMI_D5
Remap: USART1_TX, CAN2_TX, EXMC_SDNE1, SPI1_IO3
Default: PB7
PB7
165
137 93
59
I/O 5VT Alternate: I2C1_SDA , TM4_CH2, EXMC_NADV, DCMI_VSYNC
Remap: USART1_RX, SPI1_IO4
BOOT0
166
138 94
60
I
Default: BOOT0
Default: PB8
PB8
167
139 95
61
I/O 5VT
Alternate: TM4_CH3, TM10_CH1, ETH_MII_TXD3, SDIO_D4,
DCMI_D6
Remap: I2C1_SCL, CAN1_RX, LCD_B6
Default: PB9
PB9
168
140 96
62
I/O 5VT Alternate: TM4_CH4, TM11_CH1, SDIO_D5, DCMI_D7
Remap: I2C1_SDA, CAN1_TX, LCD_B7, SPI2_NSS, I2S2_WS
Default: PE0
PE0
169
141 97
-
I/O 5VT Alternate: TM4_ETR, EXMC_NBL0, UART8_RX
Remap: DCMI_D2
Default: PE1
PE1
170
142 98
-
I/O 5VT Alternate: EXMC_NBL1, UART8_TX
Remap: DCMI_D3
VSS_3
171
143 99
63
P
Default: VSS_3
VDD_3
172
144 100 64
P
Default: VDD_3
PI4
173
-
-
-
I/O 5VT
Default: PI4
Alternate: EXMC_NBL2
24 / 49
Pin Type(1)
LQFP64
LQFP100
LQFP144
Pin Name
LQFP176
Pins
I/O(2) Level
GD32F207xx
Functions description
Remap: LCD_B4, TM8_BKIN, DCMI_D5
Default: PI5
PI5
174
-
-
-
I/O 5VT Alternate: EXMC_NBL3
Remap: LCD_B5, TM8_CH1, DCMI_VSYNC
Default: PI6
PI6
175
-
-
-
I/O 5VT Alternate: EXMC_D28
Remap: LCD_B6, TM8_CH2, DCMI_D6
Default: PI7
PI7
176
-
-
-
I/O 5VT Alternate: EXMC_D29
Remap: LCD_B7, TM8_CH3, DCMI_D7
Notes:
1.
Type: I = input, O = output, P = power.
2.
I/O Level: 5VT = 5 V tolerant.
25 / 49
GD32F207xx
3
Functional description
3.1
ARM® Cortex®-M3 core
The Cortex®-M3 processor is the latest generation of ARM® processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M3 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
On-chip memory
Up to 3072 Kbytes of Flash memory, including code Flash and data Flash
Up to 256 Kbytes of SRAM
The ARM® Cortex®-M3 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most,
which includes code Flash and data Flash is available for storing programs and data, and
accessed (R/W) at CPU clock speed with zero wait states. Up to 256 Kbytes of inner SRAM
is composed of SRAM1, SRAM2, and SRAM3 that can be accessed at same time. The Figure
of GD32F207xx memory map shows the memory map of the GD32F207xx series of devices,
including Flash, SRAM, peripheral, and other pre-defined regions.
26 / 49
GD32F207xx
3.3
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types. Several prescalers allow the frequency configuration of the AHB and two APB
domains. The maximum frequency of the AHB and two APB domains is 72 MHz. See Figure
9 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are
always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device
remains in reset mode when VDD is below a specified threshold. The embedded low voltage
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates
an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the Flash memory by using USART1, USART2, CAN2, USB OTG FS in device
mode. It also can be used to transfer and update the Flash memory code, the data and the
vector table sections. In default condition, boot from bank 1 of Flash memory is selected. It
also supports to boot from bank 2 of Flash memory by setting a bit in option bytes.
27 / 49
GD32F207xx
3.5
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the Deep-sleep mode including the 16 external lines, the RTC alarm, the
LVD output, and USB wakeup. When exiting the Deep-sleep mode, the HSI is selected
as the system clock.
Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
HSI, HSE and PLL are disabled. The contents of SRAM and registers (except Backup
Registers) are lost. There are four wakeup sources for the Standby mode, including the
external reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge on
WKUP pin.
3.6
Analog to digital converter (ADC)
12-bit SAR ADC engine with up to 2M SPS conversion rate
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
Up to three 12-bit 2M SPS multi-channel ADC are integrated in the device. It is a total of up
to 16 multiplexed external channels with 2 internal channels for temperature sensor and
voltage reference measurement. The conversion range is between 2.6 V < VDDA < 3.6 V. An
on-chip 16-bit hardware oversample scheme improves performances while off-loading the
related computational burden from the MCU. An analog watchdog block can be used to detect
the channels, which are required to remain within a specific threshold window. A configurable
channel management block of analog inputs also can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced usages.
The ADC can be triggered from the events generated by the general-purpose timers (TMx)
and the advanced-control timers (TM1 and TM8) with internal connection. The temperature
sensor can be used to generate a voltage that varies linearly with temperature. It is internally
28 / 49
GD32F207xx
connected to the ADC_IN16 input channel which is used to convert the sensor output voltage
into a digital value.
3.7
Digital to analog converter (DAC)
12-bit DAC converter of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller
The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is
designed with integrated resistor strings structure. The DAC channels can be triggered by the
timer update outputs or EXTI with DMA support. The maximum output value of the DAC is
VREF+.
3.8
DMA
14 channels DMA controller and each channel are configurable (7 for DMA1 and 7 for
DMA2)
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO, DCMI, CAU
and HAU
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9
General-purpose inputs/outputs (GPIOs)
Up to 140 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)
Analog input/output configurable
Alternate function input/output configurable
There are up to 140 general purpose I/O pins (GPIO) in GD32F207xx, named PA0 ~ PA15,
PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~
PH15 and PI0 ~ PI11 to implement logic input/output functions. Each of the GPIO ports has
related control and configuration registers to satisfy the requirements of specific applications.
The external interrupts on the GPIO pins of the device have related control and configuration
registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with
other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of
the GPIO pins can be configured by software as output (push-pull or open-drain), as input
(with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO
29 / 49
GD32F207xx
pins are shared with digital or analog alternate functions. All GPIOs are high-current capable
except for analog inputs.
3.10
Timers and PWM generation
Two 16-bit advanced-control timer (TM1 & TM8), ten 16-bit general-purpose timers (TM2
Up to 4 independent channels of PWM, output compare or input capture for each general-
~ TM5, TM9 ~ TM14), and two 16-bit basic timer (TM6 & TM7)
purpose timer (GPTM) and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time
generation for output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (Independent watchdog and window watchdog)
The advanced-control timer (TM1 & TM8) can be used as a three-phase PWM multiplexed
on 6 channels. It has complementary PWM outputs with programmable dead-time generation.
It can also be used as a complete general-purpose timer. The 4 independent channels can
be used for input capture, output compare, PWM generation (edge- or center-aligned counting
modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has
the same functions as the TMx timer. It can be synchronized with external signals or to
interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), known TM2 ~ TM5, TM9 ~ TM14 as can be used for a
variety of purposes including general time, input signal pulse width measurement or output
waveform generation such as a single pulse generation or PWM output, up to 4 independent
channels for input capture/output compare. The GPTM is based on a 16-bit auto-reload
up/downcounter and a 16-bit prescaler. TM2 ~ TM5 and TM9/TM12 also supports an encoder
interface with two inputs using quadrature decoder.
The basic timer, known as TM6 & TM7, are mainly used for DAC trigger generation. They can
also be used as a simple 16-bit time base.
The GD32F207xx have two watchdog peripherals, Independent watchdog and window
watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit
prescaler, It is clocked from an independent 40 kHz internal RC and as it operates
independently of the main clock, it can operate in stop and standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in debug
mode.
30 / 49
GD32F207xx
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It
features:
3.11
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC) and backup registers
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
84 bytes backup registers for data protection
The real time clock is an independent timer which provides a set of continuously running
counters in backup registers to provide a real calendar function, and provides an alarm
interrupt or an expected interrupt. It is not reset by a system or power reset, or when the
device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and
is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from
external crystal oscillator.
The Backup registers are located in the Backup domain that remains powered-on by VBAT
even if VDD power is shut down, they are forty two 16-bit (84 bytes) registers for data protection
of user application data, and the wake-up action from standby mode or system reset are not
affect these registers.
In addition, the backup registers can be used to implement the tamper detection, RTC
calibration function and waveform detection.
3.12
Inter-integrated circuit (I2C)
Up to three I2C bus interfaces can support both master and slave mode with a frequency
up to 400 kHz
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400
kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the
situation where more than one master attempts to transmit data to the I2C bus at the same
time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking
for I2C data.
31 / 49
GD32F207xx
3.13
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad wire configuration available in master mode
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
3.14
Universal synchronous/asynchronous receiver transmitter
(USART/UART)
Up to four USARTs and four UARTs with operating frequency up to 7.5 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
The USART (USART1, USART2, USART3, USART6) and UART (UART4, UART5, UART7,
UART8) are used to translate data between parallel and serial interfaces, provides a flexible
full duplex data exchange using synchronous or asynchronous transfer. It is also commonly
used for RS-232 standard communication. The USART/UART includes a programmable baud
rate generator which is capable of dividing the system clock to produce a dedicated clock for
the USART/UART transmitter and receiver. The USART/UART also supports DMA function
for high speed data communication.
3.15
Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with
SPI2 and SPI3
Support either master or slave mode Audio
Sampling frequencies from 8 kHz up to 192 kHz are supported.
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32F207xx contain an I2S-bus interface that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI2 and
SPI3. The audio sampling frequencies from 8 kHz to 192 kHz is supported with less than 0.5%
accuracy error.
32 / 49
GD32F207xx
3.16
Universal serial bus on-the-go full-speed (USB OTG FS)
One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG
mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction
formatting is performed by the hardware, including CRC generation and checking. The status
of a completed USB transfer or error condition is indicated by status registers. An interrupt is
also generated if enabled. The dedicated 48 MHz clock is generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) and the operating frequency divided
from APB1 should be 12 MHz above.
3.17
Controller area network (CAN)
Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for USB CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The
CAN protocol has been used extensively in industrial automation and automotive applications.
It can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three
message deep for reception. It also provides 14 scalable/configurable identifier filter banks
for selecting the incoming messages needed and discarding the others.
3.18
Ethernet MAC interface
IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588
The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully
supports IEEE 1588 standards. The embedded MAC provides the interface to the required
external network physical interface (PHY) for LAN bus connection via an internal media
independent interface (MII) or a reduced media independent interface (RMII). The number of
MII signals provided up to 17 with 25 MHz output and RMII up to 9 with 50 MHz output. The
function of 32-bit CRC checking is also available.
33 / 49
GD32F207xx
3.19
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
CF card, SDRAM with up to 32-bit data bus
Provide ECC calculating hardware module for NAND Flash memory block
Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits
Column Address, 2-bits internal banks address
SDRAM Memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64
MB)
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory except NAND Flash and CF card. The EXMC also can be
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
The EXMC of GD32F207xx in LQFP144 package above also supports synchronous dynamic
random access memory (SDRAM). It translates AHB transactions into the appropriate
SDRAM protocol, and meanwhile, makes sure the access time requirements of the external
SDRAM devices are satisfied.
3.20
Secure digital input and output card interface (SDIO)
Support SD2.0/SDIO2.0/MMC4.2 host interface
The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD
memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media
card system specification version 4.2 with DMA supported. In addition, this interface is also
compliant with CE-ATA digital protocol rev1.1.
3.21
TFT LCD display interface (TLDI)
24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)
Supports up to SVGA (800x600) resolution
The TFT LCD display interface provides a parallel digital RGB (Red, Green, Blue) and signals
for horizontal, vertical synchronization, Pixel Clock and Data Enable as output to interface
directly to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels.
34 / 49
GD32F207xx
3.22
Digital camera interface (DCI)
Digital video/picture capture
8/10/12/14 data width supported
High transfer efficiency with DMA interface
Video/picture crop supported
Various pixel formats supported including JPEG/YCrCb/RG
Hard/embedded synchronous signals supported
DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera
via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation
and sustain up to 27 MB/s at 27 MHz or 48 MB/s at 48 MHz.
3.23
Cryptographic acceleration Unit (CAU)
Supports DES, 3DES or AES algorithm
DES/3DES supports Electronic codebook (ECB) or Cipher block chaining (CBC) mode
3DES supports 64bits-key, 128bits-key or 192bits-key
AES supports 128bits-key, 192bits-key or 256 bits-key
AES supports Electronic codebook (ECB), Cipher block chaining (CBC) mode or Counter
mode (CTR) mode
Support DMA mode for input data flow
The Cryptographic Acceleration Unit supports acceleration of DES, 3DES or AES (128, 192,
or 256) algorithms. The DES/3DES supports Electronic codebook (ECB) or Cipher block
chaining (CBC) mode. The AES supports Electronic codebook (ECB), Cipher block chaining
(CBC) mode or Counter mode (CTR) mode.
3.24
Hash acceleration unit (HAU)
Supports SHA-1, SHA-224 and SHA-256 algorithms, compliant with FIPS PUB 180-2
(Federal Information Processing Standards Publication 180-2)
Supports MD5 compliant with IETF RFC 1321 (Internet Engineering Task Force Request
For Comments number 1321)
Supports HMAC (keyed-hash message authentication code) algorithm
Automatic swapping to comply with the big-endian or little-endian for MD5, SHA-1, SHA224 and SHA-256 algorithms
Automatic padding to fit module 512
Support DMA mode for input data flow
The HAU supports acceleration of SHA-1, SHA-224, SHA-256, MD5 algorithm and the HMAC
(keyed-hash message authentication code) algorithm, which calling the SHA-1, SHA-224,
SHA-256 or MD5 hash function to calculate key, message, digest three times.
35 / 49
GD32F207xx
3.25
Random number generator (RNG)
About 40 period PLL clock consumed between two consecutive random numbers
Disable RNG module will reduce the chip power consumption
32-bit random value seed is generated from analog noise
The random number generator (RNG) module can generate a 32-bit value using continuous
analog noise.
3.26
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.27
Package and operation temperature
LQFP176 (GD32F207Ix), LQFP144 (GD32F207Zx), LQFP100 (GD32F207Vx),
LQFP64 (GD32F207Rx)
Operation temperature range: -40°C to +85°C (industrial level)
36 / 49
GD32F207xx
4
Electrical characteristics
4.1
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 3. Absolute maximum ratings
Symbol
Min
Max
Unit
VDD
External voltage range
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V tolerant pin
VSS - 0.3
VDD + 4.0
V
Input voltage on other I/O
VSS - 0.3
4.0
V
Maximum current for GPIO pins
—
25
mA
Injected current on 5V tolerant pin
—
±5
mA
Injected current on other I/O
—
±5
mA
Injected current on all I/O
—
±25
mA
Operating temperature range
-40
+85
°C
Storage temperature range
-55
+150
°C
Maximum junction temperature
—
125
°C
VIN
IIO
IINJ
∑IINJ
TA
TSTG
TJ
4.2
Parameter
Recommended DC characteristics
Table 4. DC operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
37 / 49
GD32F207xx
4.3
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 5. Power consumption characteristics
Symbol
Parameter
Conditions
Ma
Min
Typ
—
130.15
—
mA
—
56.43
—
mA
—
117.45
—
mA
—
51.07
—
mA
-—
79.03
—
mA
—
35.05
—
mA
—
93.05
—
mA
—
12.54
—
mA
—
1.21
—
mA
—
1.18
—
mA
Supply current VDD=VDDA=3.3V, LSE off, LSI on, RTC on
—
7.49
—
μA
(Standby
VDD=VDDA=3.3V, LSE off, LSI on, RTC off
—
7.18
—
μA
mode)
VDD=VDDA=3.3V, LSE off, LSI off, RTC off
—
6.02
—
μA
VBAT=3.6V, LSE on, RTC on, LSE High driving
—
2.77
—
μA
VBAT=3.3V, LSE on, RTC on, LSE High driving
—
2.48
—
μA
VBAT=2.6V, LSE on, RTC on, LSE High driving
—
1.86
—
μA
VBAT=3.6V, LSE on, RTC on,LSE Mid High driving
—
1.11
—
μA
VBAT=3.3V, LSE on, RTC on,LSE Mid High driving
—
1.04
—
μA
VBAT=2.6V, LSE on, RTC on,LSE Mid High driving
—
0.93
—
μA
VBAT=3.6V, LSE on, RTC on, LSE Mid Low driving
—
0.84
—
μA
VBAT=3.3V, LSE on, RTC on, LSE Mid Low driving
—
0.77
—
μA
VBAT=2.6V, LSE on, RTC on, LSE Mid Low driving
—
0.63
—
μA
VDD=VDDA=3.3V, HSE=25MHz, System clock=120
x
Unit
MHz, All peripherals enabled
VDD=VDDA=3.3V, HSE=25MHz, System clock
=120 MHz, All peripherals disabled
VDD=VDDA=3.3V, HSE=25MHz, System clock=108
Supply current MHz, All peripherals enabled
(Run mode)
VDD=VDDA=3.3V, HSE=25MHz, System clock
=108 MHz, All peripherals disabled
VDD=VDDA=3.3V, HSE=25MHz, System clock
=72MHz, All peripherals enabled
VDD=VDDA=3.3V, HSE=25MHz, System Clock =72
MHz, All peripherals disabled
IDD
VDD=VDDA=3.3V, HSE=8MHz, CPU clock off,
Supply current System clock=120 MHz, All peripherals enabled
(Sleep mode)
VDD=VDDA=3.3V, HSE=8MHz, CPU clock off,
System clock=120 MHz, All peripherals disabled
Supply current
(Deep-Sleep
mode)
VDD=VDDA=3.3V, Regulator in Run mode, LSI on,
RTC on, All GPIOs analog mode
VDD=VDDA=3.3V, Regulator in Low Power mode,
LSI on, RTC on, All GPIOs analog mode
IBAT
Battery supply
current
38 / 49
GD32F207xx
4.4
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the following table, based on the EMS levels and classes compliant with IEC 61000
series standard.
Table 6. EMS characteristics
Symbol
VESD
Parameter
Conditions
Voltage applied to all device pins to
VDD = 3.3 V, TA = +25 °C
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
Level/Class
induce a functional disturbance through
100 pF on VDD and VSS pins
3B
VDD = 3.3 V, TA = +25 °C
4A
conforms to IEC 61000-4-4
EMI (Electromagnetic Interference) emission testing result is given in the following table,
compliant with IEC 61967-2 standard which specifies the test board and the pin loading.
Table 7. EMI characteristics
Symbol
Parameter
Conditions
VDD = 3.3 V,
SEMI
Peak level
TA = +25 °C,
compliant with IEC
61967-2
4.5
Conditions
Tested
frequency band
Unit
56M
72M
120M
0.1 to 2 MHz
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