GD32EPRTxx Datasheet
GigaDevice Semiconductor Inc.
GD32EPRTxx
Arm® Cortex®-M33 32-bit MCU
Datasheet
GD32EPRTxx Datasheet
Table of Contents
Table of Contents ........................................................................................................... 1
List of Figures ................................................................................................................ 4
List of Tables .................................................................................................................. 5
1. General description ................................................................................................. 7
2. Device overview ....................................................................................................... 8
2.1.
Device information ...................................................................................................... 8
2.2.
Block diagram .............................................................................................................. 9
2.3.
Pinouts and pin assignment ..................................................................................... 10
2.4.
Memory map .............................................................................................................. 12
2.5.
Clock tree ................................................................................................................... 16
2.6.
Pin definitions ............................................................................................................ 18
2.6.1.
GD32EPRTVDT6 LQFP100 pin definitions .......................................................................... 18
2.6.2.
GD32EPRTRDT6 LQFP64 pin definitions ............................................................................ 25
3. Functional description .......................................................................................... 30
3.1.
Arm® Cortex®-M33 core ............................................................................................. 30
3.2.
Embedded memory ................................................................................................... 30
3.3.
Clock, reset and supply management ...................................................................... 31
3.4.
Boot modes ................................................................................................................ 31
3.5.
Power saving modes ................................................................................................. 32
3.6.
Analog to digital converter (ADC) ............................................................................ 33
3.7.
Digital to analog converter (DAC) ............................................................................. 33
3.8.
DMA ............................................................................................................................ 33
3.9.
General-purpose inputs/outputs (GPIOs) ................................................................ 34
3.10.
Timers and PWM generation ................................................................................. 34
3.11.
Real time clock (RTC) ............................................................................................ 35
3.12.
Inter-integrated circuit (I2C) .................................................................................. 36
3.13.
Serial peripheral interface (SPI) ............................................................................ 36
3.14.
Universal synchronous asynchronous receiver transmitter (USART) ............... 37
3.15.
Inter-IC sound (I2S) ................................................................................................ 37
3.16.
Universal Serial Bus full-speed device interface (USBD) .................................... 37
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GD32EPRTxx Datasheet
3.17.
Ethernet (ENET) ...................................................................................................... 38
3.18.
External memory controller (EXMC) ..................................................................... 38
3.19.
Serial/Quad Parallel Interface (SQPI) .................................................................... 38
3.20.
Debug mode ........................................................................................................... 39
3.21.
Package and operation temperature ..................................................................... 39
4. Electrical characteristics ....................................................................................... 40
4.1.
Absolute maximum ratings ....................................................................................... 40
4.2.
Operating conditions characteristics ....................................................................... 40
4.3.
Power consumption .................................................................................................. 42
4.4.
EMC characteristics .................................................................................................. 51
4.5.
Power supply supervisor characteristics ................................................................ 51
4.6.
Electrical sensitivity .................................................................................................. 52
4.7.
External clock characteristics .................................................................................. 53
4.8.
Internal clock characteristics ................................................................................... 55
4.9.
PLL characteristics.................................................................................................... 56
4.10.
Memory characteristics ......................................................................................... 58
4.11.
NRST pin characteristics ....................................................................................... 59
4.12.
GPIO characteristics .............................................................................................. 60
4.13.
Temperature sensor characteristics ..................................................................... 61
4.14.
ADC characteristics ............................................................................................... 61
4.15.
DAC characteristics ............................................................................................... 64
4.16.
I2C characteristics ................................................................................................. 65
4.17.
SPI characteristics ................................................................................................. 65
4.18.
I2S characteristics.................................................................................................. 66
4.19.
USART characteristics ........................................................................................... 67
4.20.
USBD characteristics ............................................................................................. 67
4.21.
EXMC characteristics............................................................................................. 68
4.22.
Serial/Quad Parallel Interface (SQPI) characteristics .......................................... 72
4.23.
TIMER characteristics ............................................................................................ 72
4.24.
WDGT characteristics ............................................................................................ 73
4.25.
Parameter condition............................................................................................... 73
5. Package information.............................................................................................. 74
2
GD32EPRTxx Datasheet
5.1.
LQFP100 package outline dimensions..................................................................... 74
5.2.
LQFP64 package outline dimensions....................................................................... 75
6. Ordering information ............................................................................................. 76
7. Revision history ..................................................................................................... 77
3
GD32EPRTxx Datasheet
List of Figures
Figure 2-1. GD32EPRTxx block diagram ................................................................................................... 9
Figure 2-2. GD32EPRTVDT6 LQFP100 pinouts ...................................................................................... 10
Figure 2-3. GD32EPRTRDT6 LQFP64 pinouts ......................................................................................... 11
Figure 2-4. GD32EPRTxx clock tree......................................................................................................... 16
Figure 4-1. Recommended power supply decoupling capacitors
(1)(2)
................................................. 41
Figure 4-2. Typical supply current consumption in Run mode ............................................................ 48
Figure 4-3. Typical supply current consumption in Sleep mode .......................................................... 48
Figure 4-4. Recommended external NRST pin circuit............................................................................ 59
Figure 4-5. I/O port AC characteristics definition ................................................................................... 61
Figure 4-6. USBD timings: definition of data signal rise and fall time ................................................. 67
Figure 5-1. LQFP100 package outline ..................................................................................................... 74
Figure 5-2. LQFP64 package outline ....................................................................................................... 75
4
GD32EPRTxx Datasheet
List of Tables
Table 2-1. GD32EPRTxx devices features and peripheral list ................................................................ 8
Table 2-2. GD32EPRTxx memory map .................................................................................................... 12
Table 2-3. GD32EPRTVDT6 LQFP100 pin definitions ............................................................................ 18
Table 2-4. GD32EPRTRDT6 LQFP64 pin definitions .............................................................................. 25
Table 4-1. Absolute maximum ratings (1)(4) .............................................................................................. 40
Table 4-2. DC operating conditions ......................................................................................................... 40
Table 4-3. Clock frequency (1) ................................................................................................................... 41
Table 4-4. Operating conditions at Power up/ Power down
Table 4-5. Start-up timings of Operating conditions
(1)(2)(3)
(1)
.............................................................. 41
.................................................................... 41
Table 4-6. Power saving mode wakeup timings characteristics (1)(2) .................................................... 42
Table 4-7. Power consumption characteristics (2)(3)(4)(5) ......................................................................... 42
Table 4-8. Peripheral current consumption characteristics (1) .............................................................. 49
Table 4-9. EMS characteristics (1) ............................................................................................................. 51
Table 4-10. Power supply supervisor characteristics............................................................................ 51
Table 4-11. ESD characteristics (1) ........................................................................................................... 52
Table 4-12. Static latch-up characteristics (1) .......................................................................................... 52
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics. 53
Table 4-14. High speed external clock characteristics (HXTAL in bypass mode) .............................. 53
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics .. 53
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode) ....................... 54
Table 4-17. High speed internal clock (IRC8M) characteristics ............................................................ 55
Table 4-18. Low speed internal clock (IRC40K) characteristics ........................................................... 55
Table 4-19. High speed internal clock (IRC48M) characteristics .......................................................... 56
Table 4-20. PLL characteristics ................................................................................................................ 56
Table 4-21. PLL1 characteristics .............................................................................................................. 57
Table 4-22. PLL2 characteristics .............................................................................................................. 57
Table 4-23. PLLUSB characteristics ........................................................................................................ 57
Table 4-24. Flash memory characteristics .............................................................................................. 58
Table 4-25. SIP PSRAM memory characteristics (1) (2) ............................................................................ 58
Table 4-26. NRST pin characteristics ...................................................................................................... 59
Table 4-27. I/O port DC characteristics (1)(3) ............................................................................................. 60
Table 4-28. I/O port AC characteristics (1)(2) ............................................................................................. 60
Table 4-29. Temperature sensor characteristics (1) ................................................................................ 61
Table 4-30. ADC characteristics ............................................................................................................... 61
Table 4-31. ADC RAIN max for fADC = 35 MHz ............................................................................................ 62
Table 4-32. ADC dynamic accuracy at fADC = 14 MHz (1) ......................................................................... 62
Table 4-33. ADC dynamic accuracy at fADC = 35 MHz (1) ......................................................................... 63
Table 4-34. ADC static accuracy at fADC = 14 MHz (1) .............................................................................. 63
Table 4-35. DAC characteristics ............................................................................................................... 64
Table 4-36. I2C characteristics (1)(2)(3) ....................................................................................................... 65
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GD32EPRTxx Datasheet
Table 4-37. Standard SPI characteristics
Table 4-38. I2S characteristics
(1)(2)
(1)
............................................................................................ 65
.......................................................................................................... 66
Table 4-39. USART characteristics (1) ...................................................................................................... 67
Table 4-40. USBD start up time ................................................................................................................ 67
Table 4-41. USBD DC electrical characteristics ..................................................................................... 67
Table 4-42. USBD full speed-electrical characteristics (1) ...................................................................... 67
Table 4-43. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)(3)(4) ..................... 68
Table 4-44. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)(3)(4) .................... 68
(1)(2)(3)(4)
Table 4-45. Asynchronous multiplexed PSRAM/NOR read timings
Table 4-46. Asynchronous multiplexed PSRAM/NOR write timings
Table 4-47. Synchronous multiplexed PSRAM/NOR read timings
Table 4-48. Synchronous multiplexed PSRAM write timings
(1)(2)(3)(4)
(1)(2)(3)(4)
(1)(2)(3)(4)
........................................ 69
........................................ 69
........................................... 70
................................................... 70
Table 4-49. Synchronous non-multiplexed PSRAM/NOR read timings (1)(2)(3)(4) ................................... 71
Table 4-50. Synchronous non-multiplexed PSRAM write timings (1)(2)(3)(4) ........................................... 71
Table 4-51.SQPI characteristics ............................................................................................................... 72
Table 4-52. TIMER characteristics (1) ....................................................................................................... 72
Table 4-53. FWDGT min/max timeout period at 40 kHz (IRC40K)
Table 4-54. WWDGT min-max timeout value at 90 MHz (fPCLK1)
(1)
(1)
..................................................... 73
........................................................ 73
Table 5-1. LQFP100 package dimensions ............................................................................................... 74
Table 5-2. LQFP64 package dimensions ................................................................................................. 75
Table 6-1. Part ordering code for GD32EPRTxx devices ....................................................................... 76
Table 7-1. Revision history ....................................................................................................................... 77
6
GD32EPRTxx Datasheet
1.
General description
The GD32EPRTxx device belongs to the high performance line of GD32 MCU family. It is a
new 32-bit general-purpose microcontroller based on the Arm® Cortex®-M33 core. The
Cortex®-M33 processor is a 32-bit processor that possesses low interrupt latency and lowcost debug. The characteristics of integrated and advanced make the Cortex®-M33 processor
suitable for market products that require microcontrollers with high performance and low
power consumption. The processor is based on the ARMv8 architecture and supports a
powerful and scalable instruction set including general data processing I/O control tasks,
advanced data processing bit field manipulations and DSP.
The GD32EPRTxx device incorporates the Arm® Cortex®-M33 32-bit processor core
operating at up to 180 MHz frequency with Flash accesses 0~4 waiting time to obtain
maximum efficiency. It provides 384 KB embedded Flash memory, 96 KB SRAM memory and
4 MB PSRAM. An extensive range of enhanced I/Os and peripherals connected to two APB
buses. The devices offer three 12-bit ADCs, two DACs, three general 16-bit timers, a general
32-bit timer, two basic timers, two PWM advanced timers, as well as standard and advanced
communication interfaces: up to three SPIs, three I2Cs, six USARTs, two I2Ss, an USBD and
an ENET. Additional peripherals as EXMC interface, Serial/Quad Parallel Interface (SQPI)
are included.
The device operates from a 1.62 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32EPRTxx devices suitable for a wide range of applications,
especially in areas such as industrial control, motor drives, user interface, power monitor and
alarm systems, consumer and handheld equipment, gaming and GPS, E-bike, optical module
and so on.
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GD32EPRTxx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32EPRTxx devices features and peripheral list
Part Number
GD32EPRTxx
RDT6
VDT6
FLASH (KB)
384
384
SRAM (KB)/PSRAM (MB)
96 / 4
96 / 4
General timer(16-bit)
Timers
General timer(32-bit)
Advanced timer(16-bit)
SysTick
1
1
(1)
(1)
2
2
(0,7)
(0,7)
1
1
2
2
(5-6)
SHRTIMER
0
0
Watchdog
2
2
RTC
1
1
USART
UART
Connectivity
3
(2-4)
(5-6)
Basic timer(16-bit)
ADC
3
(2-4)
4
4
(0-2,5)
(0-2,5)
2
2
(3-4)
(3-4)
3
3
(0-2)
(0-2)
3/2
3/2
(0-2)/(1-2)
(0-2)/(1-2)
Ethernet
1
1
CAN
0
0
USBD
1
1
GPIO
51
80
EXMC
1
1
DAC
2
2
CMP
0
0
TMU
0
0
Units
3
3
Channels
16
16
LQFP64
LQFP100
I2C
SPI/I2S
Package
8
GD32EPRTxx Datasheet
2.2.
Block diagram
Figure 2-1. GD32EPRTxx block diagram
SW/JTAG
TPIU
NVIC
Code System
ARM Cortex-M33
Processor
Fmax:180MHz
POR/ PDR
Flash
Memory
Controller
Cbus
Flash
Memory
PLL
F max : 180MHz
Master
FMC SQPI CRC
GP DMA 12 chs
AHB Peripherals
Slave
ENET
Master
AHB Matrix
Master
Slave
EXMC
Slave
Slave
LDO
1.1V
RCU
SRAM
Controller
AHB to APB
Bridge2
IRC
8MHz
SRAM
HXTAL
4-32MHz
AHB to APB
Bridge1
LVD
Interrput request
USBD
USART0
Slave
USART5
Slave
WWDGT
SPI0
12-bit
SAR ADC
TIMER1~3
ADC0~2
SPI1~2\
I2S1~2
Powered By V DDA
EXTI
USART1~2
GPIOA
GPIOD
I2C0
APB1: Fmax = 90MHZ
GPIOC
APB2: Fmax = 180MHz
GPIOB
Powered By VDDA
I2C1
I2C2
FWDGT
GPIOE
RTC
TIMER0
TIMER7
DAC
TIMER4~6
UART3~4
CTC
9
GD32EPRTxx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32EPRTVDT6 LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32IN
7
70
69
PA10
8
68
PA9
PC15-OSC32OUT
9
67
PA8
VSS_5
10
66
PC9
VDD_5
11
65
PC8
64
PC7
63
PC6
62
PD15
OSCIN
GigaDevice
GD32EPRTVDT6
LQFP100
12
VDD_2
PA11
OSCOUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP0
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
14
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
10
GD32EPRTxx Datasheet
Figure 2-3. GD32EPRTRDT6 LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
PB8
BOOT0
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32IN
3
46
PA13
PC15-OSC32OUT
PD0-OSCIN
4
45
PA12
5
44
PA11
PD1-OSCOUT
6
43
PA10
NRST
PC0
7
42
PA9
PC1
9
PC2
PC3
VSSA
GigaDevice
GD32EPRTRDT6
LQFP64
41
PA8
40
PC9
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_1
VSS_1
PB11
PB10
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
11
GD32EPRTxx Datasheet
2.4.
Memory map
Table 2-2. GD32EPRTxx memory map
Pre-defined
Regions
Bus
External
device
AHB3
External RAM
Address
Peripherals
0xC000 0000 - 0xDFFF FFFF
Reserved
0xB000 0000 - 0xBFFF FFFF
SQPI_PSRAM(MEM)
0xA000 1400 - 0xAFFF FFFF
Reserved
0xA000 1000 - 0xA000 13FF
SQPI_PSRAM(REG)
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
0x9000 0000 - 0x9FFF FFFF
EXMC - PC CARD
0x7000 0000 - 0x8FFF FFFF
EXMC - NAND
0x6000 0000 - 0x6FFF FFFF
Peripheral
AHB1
EXMC NOR/PSRAM/SRAM
0x5000 0000 - 0x5003 FFFF
Reserved
0x4008 0400 - 0x4FFF FFFF
Reserved
0x4008 0000 - 0x4008 03FF
Reserved
0x4004 0000 - 0x4007 FFFF
Reserved
0x4002 BC00 - 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Reserved
0x4002 A000 - 0x4002 AFFF
Reserved
0x4002 8000 - 0x4002 9FFF
ENET
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
Reserved
0x4002 6000 - 0x4002 63FF
Reserved
0x4002 5000 - 0x4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Reserved
0x4002 3800 - 0x4002 3BFF
Reserved
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
Reserved
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1C00 - 0x4002 1FFF
Reserved
0x4002 1800 - 0x4002 1BFF
Reserved
0x4002 1400 - 0x4002 17FF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA1
12
GD32EPRTxx Datasheet
Pre-defined
Regions
Bus
APB2
APB1
Address
Peripherals
0x4002 0000 - 0x4002 03FF
DMA0
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
Reserved
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
Reserved
0x4001 7400 - 0x4001 77FF
Reserved
0x4001 7000 - 0x4001 73FF
USART5
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
Reserved
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
Reserved
0x4001 5400 - 0x4001 57FF
Reserved
0x4001 5000 - 0x4001 53FF
Reserved
0x4001 4C00 - 0x4001 4FFF
Reserved
0x4001 4800 - 0x4001 4BFF
Reserved
0x4001 4400 - 0x4001 47FF
Reserved
0x4001 4000 - 0x4001 43FF
Reserved
0x4001 3C00 - 0x4001 3FFF
ADC2
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
TIMER7
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
0x4001 2000 - 0x4001 23FF
Reserved
0x4001 1C00 - 0x4001 1FFF
Reserved
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 CC00 - 0x4000 CFFF
Reserved
0x4000 C800 - 0x4000 CBFF
CTC
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
I2C2
0x4000 8C00 - 0x4000 BFFF
Reserved
0x4000 8800 - 0x4000 8BFF
Reserved
13
GD32EPRTxx Datasheet
Pre-defined
Regions
Bus
Address
Peripherals
0x4000 8400 - 0x4000 87FF
USBSRAM_B
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
Reserved
0x4000 6400 - 0x4000 67FF
Reserved
0x4000 6000 - 0x4000 63FF
SRAM
AHB
USBD SRAM 512
bytes
0x4000 5C00 - 0x4000 5FFF
USBD
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
I2S2_add
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
I2S1_add
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
Reserved
0x4000 1C00 - 0x4000 1FFF
Reserved
0x4000 1800 - 0x4000 1BFF
Reserved
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2007 0000 - 0x3FFF FFFF
Reserved
0x2006 0000 - 0x2006 FFFF
Reserved
0x2003 0000 - 0x2005 FFFF
Reserved
0x2002 0000 - 0x2002 FFFF
Reserved
0x2000 0000 - 0x2001 FFFF
SRAM
14
GD32EPRTxx Datasheet
Pre-defined
Regions
Code
Bus
AHB
Address
Peripherals
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF B000 - 0x1FFF F7FF
Boot loader
0x1FFF 7800 - 0x1FFF AFFF
Reserved
0x1FFF 7000 - 0x1FFF 77FF
OTP
0x1FFF 0000 - 0x1FFF 6FFF
Reserved
0x1FFE C010 - 0x1FFE FFFF
Reserved
0x1FFE C000 - 0x1FFE C00F
Reserved
0x1001 0000 - 0x1FFE BFFF
Reserved
0x1000 0000 - 0x1000 FFFF
Reserved
0x083C 0000 - 0x0FFF FFFF
Reserved
0x0830 0000 - 0x083B FFFF
Reserved
0x0808 0000 - 0x082F FFFF
Reserved
0x0800 0000 - 0x0807 FFFF
Main Flash
0x0030 0000 - 0x07FF FFFF
Reserved
0x0010 0000 - 0x002F FFFF
Reserved
0x0008 0000 - 0x000F FFFF
Reserved
0x0002 0000 - 0x0007 FFFF
Aliased to Main Flash
0x0000 0000 - 0x0001 FFFF
or Boot loader
15
GD32EPRTxx Datasheet
2.5.
Clock tree
Figure 2-4. GD32EPRTxx clock tree
CK_PLLUSB
USBHS PHY clock 24Mhz to 60Mhz
(to USBHS in high-speed
mode)
CK48MSEL[1:0]
PLLUSBPR
ESEL
PLLUSBMF
PLLUSBPREDV
CK_IRC48M
1
CK_HXTAL
0
×16,17…,
127
PLLUSB
/1,2,3…
15
0
1
USBHSDV
480MHz
max
CK_PLL2
11
10
/2,4…1
6
USBHS
Presacaler
/1,1.5,2,2.5
3,3.5,4
CK_PLL1
PLLUSBPRE
DVSEL
PHSEL
48 MHz/
60MHz
0
00
0
CK_USBHS
1
(to USBHS)
1
01
USBHSSEL
From USBHS
(to FMC)
CRS
CK_IRC48M
CK_FMC
CK_CTC
CK_PLLSRC
48 MHz
IRC48M
SCS[1:0]
CK_IRC8M
8 MHz
IRC8M
00
/2
×2,3,4
…,64
PLL
0
1
PLLPRESEL
CK_IRC48M
1
0
4-32 MHz
HXTAL
PLLSEL
PREDV0
0
1
CK_PLL
PLLMF
/1,2,3…
15,16
CK_SYS
10
180 MHz max
AHB
Prescaler
÷1,2...512
CK_AHB
180 MHz max
CK_EXMC
EXMC enable
(by hardware)
(to EXMC)
HCLK
01
AHB enable
(to AHB bus,Cortex-M33,SRAM,DMA)
CK_CST
Clock
Monitor
÷8
(to Cortex-M33 SysTick)
FCLK
PREDV0SEL
EXT1 to
CK_OUT
(free running clock)
CK_HXTAL
APB1
Prescaler
÷1,2,4,8,16
CK_APB1
PCLK1
to APB1 peripherals
90 MHz max
Peripheral enable
×8,9,10…1
2,,14,16,20
PLL1
×8,9,10…,14
,16,18…,32,
34...64,80
PLL2
11
32.768 KHz
LXTAL
CK_PLL2
x2
CK_I2Sx
1
to I2S
APB2
Prescaler
÷1,2,4,8,16
(to RTC)
10
TIMER0,7,8,9,10
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,6，
8,12,16
CK_FWDGT
(to FWDGT)
CK_APB2
PCLK2
to APB2 peripherals
180 MHz max
Peripheral enable
I2SxSEL
CK_RTC
RTCSRC[1:0]
0
I2S enable
PLL2MF
01
40 KHz
IRC40K
CK_TIMERx
to
TIMER1,2,3,4,5,6,1
1,12,13
TIMERx
enable
PLL1MF
/1,2,3…
15,16
PREDV1
/128
TIMER1,2,3,4,5,6,
11,12,13 if(APB1
prescale =1)x1
else x 2
CK_PLL1
ADC
Prescaler
÷5,6,10,20
CK_TIMERx
TIMERx
enable
to
TIMER0,7,8,9,10
ADCPSC[3]
0
CK_ADCX t o ADC0,1,2
1
35 MHz max
SHRTIMERSEL
CK_OUT0
00xx
0100
0101
0110
0111
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
/2
CK_PLL
CK_PLL1
/2
CK_PLL2
1000
1001
1010
1011
1100
1101
1110
EXT1
CK_PLL2
CK_IRC48M
/8
CK_IRC48M
/32
CK_PLLU
CK_APB2
0
CK_SYS
1
CK_SHRTIMER
USART5SEL[1:0]
CK_APB2
CK_SYS
CK_LXTAL
CK_IRC8M
00
01
10
11
CK_USART5
CKOUT0SEL[3:0]
0 CK_MACTX
I2C2SEL[1:0]
1
Ethernet
PHY
MII_RMII_SEL
/2,20
CK_APB1
00
1 CK_MACRX
CK_SYS
01
0
CK_IRC8M
1x
CK_I2C2
CK_MACRMII
Note:
The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency
of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB
prescaler is not 1).
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC8M: Internal 8M RC oscillator
IRC40K: Internal 40K RC oscillator
16
GD32EPRTxx Datasheet
IRC48M: Internal 48M RC oscillator
17
GD32EPRTxx Datasheet
2.6.
Pin definitions
2.6.1.
GD32EPRTVDT6 LQFP100 pin definitions
Table 2-3. GD32EPRTVDT6 LQFP100 pin definitions
Pin
I/O
Type(1)
Level(2)
1
I/O
5VT
PE3
2
I/O
5VT
PE4
3
I/O
5VT
PE5
4
I/O
5VT
PE6
5
I/O
5VT
VBAT
6
P
7
I/O
8
I/O
9
I/O
VSS_5
10
P
Default: VSS_5
VDD_5
11
P
Default: VDD_5
OSCIN
12
I
OSCOUT
13
O
NRST
14
I/O
PC0
15
I/O
Pin Name
Pins
PE2
PC13TAMPER-
Functions description(3)
Default: PE2
Alternate2: TRACECK, EXMC_A23
Default: PE3
Alternate2: TRACED0, EXMC_A19
Default: PE4
Alternate2:TRACED1, EXMC_A20
Default: PE5
Alternate2:TRACED2, EXMC_A21
Default: PE6
Alternate2:TRACED3, EXMC_A22, WKUP2
Default: VBAT
Default: PC13
Alternate2: TAMPER-RTC, WKUP1
RTC
PC14OSC32IN
PC15OSC32OUT
Default: PC14
Alternate2: OSC32IN
Default: PC15
Alternate2: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate2: ADC012_IN10
Default: PC1
PC1
16
I/O
Alternate2: ADC012_IN11, ETH_MII_MDC,
ETH_RMII_MDC
Default: PC2
PC2
17
I/O
Alternate1: I2S1_ADD_SD
Alternate2: ADC012_IN12, ETH_MII_TXD2
PC3
18
I/O
Default: PC3
Alternate2: ADC012_IN13, ETH_MII_TX_CLK
18
GD32EPRTxx Datasheet
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Pin Name
Pins
VSSA
19
P
Default: VSSA
VREF-
20
P
Default: VREF-
VREF+
21
P
Default: VREF+
VDDA
22
P
Default: VDDA
Default: PA0
PA0-WKUP0
23
I/O
Alternate2: WKUP0, USART1_CTS, ADC012_IN0,
TIMER1_CH0, TIMER1_ETI, TIMER4_CH0,
TIMER7_ETI, ETH_MII_CRS
Default: PA1
PA1
24
I/O
Alternate2: USART1_RTS, ADC012_IN1, TIMER4_CH1,
TIMER1_CH1, ETH_MII_RX_CLK, ETH_RMII_REF_CLK
Default: PA2
PA2
25
I/O
Alternate2: USART1_TX, TIMER4_CH2, ADC012_IN2,
TIMER1_CH2, ETH_MII_MDIO, ETH_RMII_MDIO,
SPI0_IO2, WKUP3
Default: PA3
Alternate2: USART1_RX, TIMER4_CH3, ADC012_IN3,
PA3
26
I/O
VSS_4
27
P
Default: VSS_4
VDD_4
28
P
Default: VDD_4
TIMER1_CH3, ETH_MII_COL, SPI0_IO3
Default: PA4
PA4
29
I/O
Alternate2: SPI0_NSS, USART1_CK, DAC_OUT0,
ADC01_IN4
Remap: SPI2_NSS, I2S2_WS
PA5
30
I/O
Default: PA5
Alternate2: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
31
I/O
Alternate2: SPI0_MISO, TIMER7_BRKIN, ADC01_IN6,
TIMER2_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
32
I/O
Alternate2: SPI0_MOSI, TIMER7_CH0_ON, ADC01_IN7,
TIMER2_CH1, ETH_MII_RX_DV, ETH_RMII_CRS_DV
Remap: TIMER0_CH0_ON
Default: PC4
PC4
33
I/O
Alternate2: ADC01_IN14, ETH_MII_RXD0,
ETH_RMII_RXD0
Default: PC5
PC5
34
I/O
Alternate2: ADC01_IN15, ETH_MII_RXD1,
ETH_RMII_RXD1, WKUP4
PB0
35
I/O
Default: PB0
Alternate2: ADC01_IN8, TIMER2_CH2,
19
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
TIMER7_CH1_ON, ETH_MII_RXD2
Remap: TIMER0_CH1_ON
Default: PB1
PB1
36
Alternate2: ADC01_IN9, TIMER2_CH3,
I/O
TIMER7_CH2_ON, ETH_MII_RXD3
Remap: TIMER0_CH2_ON
PB2
37
I/O
5VT
Default: PB2, BOOT1
Default: PE7
PE7
38
I/O
5VT
Alternate2: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
39
I/O
5VT
Alternate2: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
PE9
40
I/O
5VT
Alternate2: EXMC_D6
Remap: TIMER0_CH0
Default: PE10
PE10
41
I/O
5VT
Alternate2: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
42
I/O
5VT
Alternate2: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
43
I/O
5VT
Alternate2: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
44
I/O
5VT
Alternate2: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
45
I/O
5VT
Alternate2: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
46
I/O
5VT
Alternate2: EXMC_D12
Remap: TIMER0_BRKIN
Default: PB10
PB10
47
I/O
5VT
Alternate2: I2C1_SCL, USART2_TX, ETH_MII_RX_ER
Remap: TIMER1_CH2
Default: PB11
PB11
48
I/O
5VT
Alternate2: I2C1_SDA, USART2_RX, ETH_MII_TX_EN,
ETH_RMII_TX_EN
Remap: TIMER1_CH3
VSS_1
49
P
Default: VSS_1
VDD_1
50
P
Default: VDD_1
20
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Default: PB12
PB12
51
I/O
5VT
Alternate2: SPI1_NSS, I2S1_WS, I2C1_SMBA,
USART2_CK, TIMER0_BRKIN, ETH_MII_TXD0,
ETH_RMII_TXD0
Default: PB13
PB13
52
I/O
5VT
Alternate2: SPI1_SCK, I2S1_CK, USART2_CTS,
TIMER0_CH0_ON, ETH_MII_TXD1, ETH_RMII_TXD1,
I2C1_TXFRAME
Default: PB14
PB14
53
I/O
5VT
Alternate1: I2S1_ADD_SD
Alternate2: SPI1_MISO, USART2_RTS,
TIMER0_CH1_ON
Default: PB15
PB15
54
I/O
5VT
Alternate2: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
WKUP6
Default: PD8
PD8
55
I/O
5VT
Alternate2: EXMC_D13
Remap: USART2_TX, ETH_MII_RX_DV,
ETH_RMII_CRS_DV
Default: PD9
PD9
56
I/O
5VT
Alternate2: EXMC_D14
Remap: USART2_RX, ETH_MII_RXD0,
ETH_RMII_RXD0
Default: PD10
PD10
57
I/O
5VT
Alternate2: EXMC_D15
Remap: USART2_CK, ETH_MII_RXD1,
ETH_RMII_RXD1
Default: PD11
PD11
58
I/O
5VT
Alternate2: EXMC_A16
Remap: USART2_CTS, ETH_MII_RXD2
Default: PD12
PD12
59
I/O
5VT
Alternate2: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS, ETH_MII_RXD3
Default: PD13
PD13
60
I/O
5VT
Alternate2: EXMC_A18
Remap: TIMER3_CH1
Default: PD14
PD14
61
I/O
5VT
Alternate2: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
62
I/O
5VT
Alternate2: EXMC_D1
Remap: TIMER3_CH3, CTC_SYNC
PC6
63
I/O
5VT
Default: PC6
21
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Alternate1: USART5_TX
Alternate2: I2S1_MCK, TIMER7_CH0
Remap: TIMER2_CH0
Default: PC7
PC7
64
I/O
5VT
Alternate1: USART5_RX
Alternate2: I2S2_MCK, TIMER7_CH1
Remap: TIMER2_CH1
Default: PC8
PC8
65
I/O
5VT
Alternate1: USART5_CK
Alternate2: TIMER7_CH2
Remap: TIMER2_CH2
Default: PC9
PC9
66
I/O
5VT
Alternate1: I2C2_SDA
Alternate2: TIMER7_CH3
Remap: TIMER2_CH3
Default: PA8
PA8
67
I/O
5VT
Alternate1: I2C2_SCL
Alternate2: USART0_CK, TIMER0_CH0, CK_OUT,
CTC_SYNC
Default: PA9
PA9
68
I/O
5VT
Alternate1: I2C2_SMBA
Alternate2: USART0_TX, TIMER0_CH1
PA10
69
I/O
5VT
Default: PA10
Alternate2: USART0_RX, TIMER0_CH2
Default: PA11
PA11
70
I/O
5VT
Alternate1: USART5_TX
Alternate2: USART0_CTS, USBDM, TIMER0_CH3
Default: PA12
PA12
71
I/O
5VT
Alternate1: USART5_RX
Alternate2: USART0_RTS, USBDP, TIMER0_ETI
I/O
5VT
Default: JTMS, SWDIO
PA13
72
NC
73
VSS_2
74
P
Default: VSS_2
VDD_2
75
P
Default: VDD_2
PA14
76
I/O
Remap: PA13
-
5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
77
I/O
5VT
Alternate2: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS
Default: PC10
PC10
78
I/O
5VT
Alternate1: I2C2_SCL
Alternate2: UART3_TX
22
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
79
I/O
5VT
Alternate1: I2S2_ADD_SD
Alternate2: UART3_RX
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
80
I/O
5VT
Alternate2: UART4_TX
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
81
I/O
5VT
Alternate2: EXMC_D2
Remap: OSCIN
Default: PD1
PD1
82
I/O
5VT
Alternate2: EXMC_D3
Remap: OSCOUT
PD2
83
I/O
5VT
Default: PD2
Alternate2: TIMER2_ETI, UART4_RX
Default: PD3
PD3
84
I/O
5VT
Alternate2: EXMC_CLK
Remap: USART1_CTS
Default: PD4
PD4
85
I/O
5VT
Alternate2: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
86
I/O
5VT
Alternate2: EXMC_NWE
Remap: USART1_TX
Default: PD6
PD6
87
I/O
5VT
Alternate2: EXMC_NWAIT
Remap: USART1_RX
Default: PD7
PD7
88
I/O
5VT
Alternate2: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
Default: JTDO
PB3
89
I/O
5VT
Alternate2: SPI2_SCK, I2S2_CK
Remap: TIMER1_CH1, PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
90
I/O
5VT
Alternate1: I2C2_SDA, I2S2_ADD_SD
Alternate2: SPI2_MISO, I2C0_TXFRAME
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
Alternate1: I2C2_SCL
PB5
91
I/O
Alternate2: I2C0_SMBA, SPI2_MOSI, I2S2_SD,
ETH_MII_PPS_OUT, ETH_RMII_PPS_OUT, WKUP5
Remap: TIMER2_CH1, SPI0_MOSI
23
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Default: PB6
PB6
92
I/O
5VT
Alternate2: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, SPI0_IO2
Default: PB7
PB7
93
I/O
5VT
Alternate2: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
BOOT0
94
Default: BOOT0
I
Default: PB8
PB8
95
I/O
5VT
Alternate1: I2C2_SDA
Alternate2: TIMER3_CH2, ETH_MII_TXD3
Remap: I2C0_SCL
Default: PB9
PB9
96
I/O
5VT
Alternate2: TIMER3_CH3
Remap: I2C0_SDA
Default: PE0
PE0
97
I/O
5VT
PE1
98
I/O
5VT
VSS_3
99
P
Default: VSS_3
VDD_3
100
P
Default: VDD_3
Alternate2: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate2: EXMC_NBL1
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Alternate1: The specified function can be mapped to the specific pin by configuring
AFIO_PCFA ~ AFIO_PCFG registers.
Alternate2: These functions can be enabled with correct GPIO and function module mode
configurations.
Remap: A group of the specified module functions can be mapped to the specified pins
by configuring AFIO_PCF0 ~ AFIO_PCF1 registers.
24
GD32EPRTxx Datasheet
2.6.2.
GD32EPRTRDT6 LQFP64 pin definitions
Table 2-4. GD32EPRTRDT6 LQFP64 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
OSCIN
5
I
OSCOUT
6
O
NRST
7
I/O
PC0
8
I/O
PC1
9
I/O
PC13TAMPERRTC
PC14OSC32IN
PC15OSC32OUT
Functions description(3)
Default: VBAT
Default: PC13
Alternate2: TAMPER-RTC, WKUP1
Default: PC14
Alternate2: OSC32IN
Default: PC15
Alternate2: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate2: ADC012_IN10
Default: PC1
Alternate2: ADC012_IN11, ETH_MII_MDC,
ETH_RMII_MDC
Default: PC2
PC2
10
I/O
Alternate1: I2S1_ADD_SD
Alternate2: ADC012_IN12, ETH_MII_TXD2
Default: PC3
PC3
11
I/O
VSSA
12
P
Default: VSSA
VDDA
13
P
Default: VDDA
Alternate2: ADC012_IN13, ETH_MII_TX_CLK
Default: PA0
PA0-WKUP0
14
I/O
Alternate2: WKUP0, USART1_CTS, ADC012_IN0,
TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI,
ETH_MII_CRS
Default: PA1
PA1
15
I/O
Alternate2: USART1_RTS, ADC012_IN1, TIMER4_CH1,
TIMER1_CH1, ETH_MII_RX_CLK, ETH_RMII_REF_CLK
Default: PA2
PA2
16
I/O
Alternate2: USART1_TX, TIMER4_CH2, ADC012_IN2,
TIMER1_CH2, ETH_MII_MDIO, ETH_RMII_MDIO,
SPI0_IO2, WKUP3
PA3
17
I/O
Default: PA3
Alternate2: USART1_RX, TIMER4_CH3, ADC012_IN3,
25
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
TIMER1_CH3, ETH_MII_COL, SPI0_IO3
VSS_4
18
P
Default: VSS_4
VDD_4
19
P
Default: VDD_4
Default: PA4
PA4
20
Alternate2: SPI0_NSS, USART1_CK, DAC_OUT0,
I/O
ADC01_IN4
Remap: SPI2_NSS, I2S2_WS
PA5
21
Default: PA5
I/O
Alternate2: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
22
Alternate2: SPI0_MISO, TIMER7_BRKIN, ADC01_IN6,
I/O
TIMER2_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
23
Alternate2: SPI0_MOSI, TIMER7_CH0_ON, ADC01_IN7,
I/O
TIMER2_CH1, ETH_MII_RX_DV, ETH_RMII_CRS_DV
Remap: TIMER0_CH0_ON
Default: PC4
PC4
24
Alternate2: ADC01_IN14, ETH_MII_RXD0,
I/O
ETH_RMII_RXD0
Default: PC5
PC5
25
Alternate2: ADC01_IN15, ETH_MII_RXD1,
I/O
ETH_RMII_RXD1, WKUP4
Default: PB0
PB0
26
Alternate2: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON,
I/O
ETH_MII_RXD2
Remap: TIMER0_CH1_ON
Default: PB1
PB1
27
Alternate2: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON,
I/O
ETH_MII_RXD3
Remap: TIMER0_CH2_ON
PB2
28
I/O
5VT
Default: PB2, BOOT1
Default: PB10
PB10
29
I/O
5VT
Alternate2: I2C1_SCL, USART2_TX, ETH_MII_RX_ER
Remap: TIMER1_CH2
Default: PB11
5VT
Alternate2: I2C1_SDA, USART2_RX, ETH_MII_TX_EN,
PB11
30
I/O
VSS_1
31
P
Default: VSS_1
VDD_1
32
P
Default: VDD_1
PB12
33
I/O
ETH_RMII_TX_EN
Remap: TIMER1_CH3
5VT
Default: PB12
26
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Alternate2: SPI1_NSS, I2S1_WS, I2C1_SMBA,
USART2_CK, TIMER0_BRKIN, ETH_MII_TXD0,
ETH_RMII_TXD0
Default: PB13
PB13
34
I/O
5VT
Alternate2: SPI1_SCK, I2S1_CK, USART2_CTS,
TIMER0_CH0_ON, ETH_MII_TXD1, ETH_RMII_TXD1,
I2C1_TXFRAME
Default: PB14
PB14
35
I/O
5VT
Alternate1: I2S1_ADD_SD
Alternate2: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON
Default: PB15
PB15
36
I/O
5VT
Alternate2: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD,
WKUP6
Default: PC6
PC6
37
I/O
5VT
Alternate1: USART5_TX
Alternate2: I2S1_MCK, TIMER7_CH0
Remap: TIMER2_CH0
Default: PC7
PC7
38
I/O
5VT
Alternate1: USART5_RX
Alternate2: I2S2_MCK, TIMER7_CH1
Remap: TIMER2_CH1
Default: PC8
PC8
39
I/O
5VT
Alternate1: USART5_CK
Alternate2: TIMER7_CH2
Remap: TIMER2_CH2
Default: PC9
PC9
40
I/O
5VT
Alternate1: I2C2_SDA
Alternate2: TIMER7_CH3
Remap: TIMER2_CH3
Default: PA8
PA8
41
I/O
5VT
Alternate1: I2C2_SCL
Alternate2: USART0_CK, TIMER0_CH0, CK_OUT,
CTC_SYNC
Default: PA9
PA9
42
I/O
5VT
Alternate1: I2C2_SMBA
Alternate2: USART0_TX, TIMER0_CH1
PA10
43
I/O
5VT
PA11
44
I/O
5VT
Default: PA10
Alternate2: USART0_RX, TIMER0_CH2
Default: PA11
Alternate1: USART5_TX
Alternate2: USART0_CTS, USBDM, TIMER0_CH3
PA12
45
I/O
5VT
Default: PA12
Alternate1: USART5_RX
27
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Alternate2: USART0_RTS, USBDP, TIMER0_ETI
5VT
Default: JTMS, SWDIO
PA13
46
I/O
VSS_2
47
P
Default: VSS_2
VDD_2
48
P
Default: VDD_2
PA14
49
I/O
5VT
PA15
50
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
Alternate2: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS
Default: PC10
PC10
51
I/O
5VT
Alternate1: I2C2_SCL
Alternate2: UART3_TX
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
52
I/O
5VT
Alternate1: I2S2_ADD_SD
Alternate2: UART3_RX
Remap: USART2_RX, SPI2_MISO
Default: PC12
PC12
53
I/O
5VT
Alternate2: UART4_TX
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
PD2
54
I/O
5VT
PB3
55
I/O
5VT
Default: PD2
Alternate2: TIMER2_ETI, UART4_RX
Default: JTDO
Alternate2: SPI2_SCK, I2S2_CK
Remap: TIMER1_CH1, PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
56
I/O
5VT
Alternate1: I2C2_SDA, I2S2_ADD_SD
Alternate2: SPI2_MISO, I2C0_TXFRAME
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
Alternate1: I2C2_SCL
PB5
57
Alternate2: I2C0_SMBA, SPI2_MOSI, I2S2_SD,
I/O
ETH_MII_PPS_OUT, ETH_RMII_PPS_OUT, WKUP5
Remap: TIMER2_CH1, SPI0_MOSI
Default: PB6
PB6
58
I/O
5VT
Alternate2: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, SPI0_IO2
Default: PB7
PB7
59
I/O
BOOT0
60
I
5VT
Alternate2: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
Default: BOOT0
28
GD32EPRTxx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description(3)
Default: PB8
PB8
61
I/O
5VT
Alternate1: I2C2_SDA
Alternate2: TIMER3_CH2, ETH_MII_TXD3
Remap: I2C0_SCL
Default: PB9
PB9
62
I/O
5VT
Alternate2: TIMER3_CH3
Remap: I2C0_SDA
VSS_3
63
P
Default: VSS_3
VDD_3
64
P
Default: VDD_3
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Alternate1: The specified function can be mapped to the specific pin by configuring
AFIO_PCFA ~ AFIO_PCFG registers.
Alternate2: These functions can be enabled with correct GPIO and function module mode
configurations.
Remap: A group of the specified module functions can be mapped to the specified pins
by configuring AFIO_PCF0 ~ AFIO_PCF1 registers.
29
GD32EPRTxx Datasheet
3.
Functional description
3.1.
Arm® Cortex®-M33 core
The Cortex®-M33 processor is a 32-bit processor that possesses low interrupt latency and
low-cost debug. The characteristics of integrated and advanced make the Cortex®-M33
processor suitable for market products that require microcontrollers with high performance
and low power consumption.
32-bit Arm® Cortex®-M33 processor core
Up to 180 MHz operation frequency
Ultra-low power, energy-efficient operation
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M33 processor is based on the ARMv8 architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M33:
Internal Bus Matrix connected with Code bus, System bus, and Private Peripheral Bus
(PPB) and debug accesses
3.2.
Nested Vectored Interrupt Controller (NVIC)
Breakpoint Unit (BPU)
Data Watchpoint and Trace (DWT)
Instrumentation Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
Memory Protection Unit (MPU)
Floating Point Unit (FPU)
DSP Extension (DSP)
Embedded memory
Up to 384 Kbytes of Flash memory
Up to 96 Kbytes of SRAM with hardware parity checking
Up to 4 Mbytes of PSRAM embedded
384 Kbytes of inner Flash, 96 Kbytes of inner SRAM and 4 Mbytes of inner PSRAM at most
is available for storing programs and data, both accessed (R/W) at CPU clock speed with 0~4
waiting time. Table 2-2. GD32EPRTxx memory map shows the memory map of the
GD32EPRTxx series of devices, including code, SRAM, peripheral, and other pre-defined
regions.
30
GD32EPRTxx Datasheet
3.3.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
1.62 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types. Several prescalers allow the frequency configuration of the AHB and two APB
domains. The maximum frequency of the AHB, APB2 and APB1 domains is 180 MHz/180
MHz/90 MHz. See Figure 2-4. GD32EPRTxx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are
always active, and ensures proper operation starting from 1.56 V and down to 1.52V. The
device remains in reset mode when VDD is below a specified threshold. The embedded low
voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and
generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 1.62 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 1.62 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL.
VBAK range: 1.62 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in
the internal boot ROM memory (system memory). It is used to reprogram the Flash memory
by using USART0 (PA9 and PA10) or USART1 (PD5 and PD6).
31
GD32EPRTxx Datasheet
3.5.
Power saving modes
The MCU supports five kinds of power saving modes to achieve even lower power
consumption. They are Sleep, Deep-sleep, Deep-sleep 1, Deep-sleep 2 and Standby mode.
These operating modes reduce the power consumption and allow the application to achieve
the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.1V domain are off, and all of IRC8M, IRC48M,
HXTAL and PLLs are disabled. The contents of SRAM and registers are preserved. Any
interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep
mode including the 16 external lines, the RTC alarm, LVD output, USB wakeup, Ethernet
wakeup, I2C2 wakeup and USART5 wakeup. When exiting the deep-sleep mode, the
IRC8M is selected as the system clock.
Deep-sleep 1 mode
In Deep-sleep 1 mode, all clocks in the 1.1V domain are off, and all of IRC8M, IRC48M,
HXTAL and PLLs are disabled. The power of COREOFF1 domain is cut off. The contents
of registers in COREOFF1 domain are lost. Any interrupt or wakeup event from EXTI
lines can wake up the system from the deep-sleep 1 mode including the 16 external lines,
the RTC alarm, LVD output, USB wakeup, Ethernet wakeup, I2C2 wakeup and USART5
wakeup. Waking up from Deep-sleep 1 mode needs an additional delay to power on
COREOFF1 domain. When exiting the deep-sleep 1 mode, the IRC8M is selected as the
system clock.
Deep-sleep 2 mode
In Deep-sleep 2 mode, all clocks in the 1.1V domain are off, and all of IRC8M, IRC48M,
HXTAL and PLLs are disabled. The power of COREOFF0/COREOFF1 domain is cut off.
The contents of SRAM except for the first 32K and registers in COREOFF0/COREOFF1
domain are lost. Any interrupt or wakeup event from EXTI lines can wake up the system
from the deep-sleep mode including the 16 external lines, the RTC alarm, LVD output,
USB wakeup, Ethernet wakeup, I2C2 wakeup and USART5 wakeup. Waking up from
Deep-sleep 2 mode needs an additional delay to power on COREOFF1 domain. Waking
up
from
Deep-sleep
2
mode
needs
an
additional
delay
to
power
on
COREOFF0/COREOFF1 domain. When exiting the deep-sleep 2 mode, the IRC8M is
selected as the system clock.
Standby mode
In Standby mode, the whole 1.1V domain is power off, the LDO is shut down, and all of
IRC8M, IRC48M, HXTAL and PLL are disabled. There are four wakeup sources for the
Standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT
reset, and the rising edge on WKUP pins.
32
GD32EPRTxx Datasheet
3.6.
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 2.5 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VREF- to VREF+
Temperature sensor
Three 12-bit 2.5 MSPS multi-channel ADCs are integrated in the device. It has a total of 18
multiplexed channels: up to 16 external channels, 1 channel for internal temperature sensor
(VSENSE) and 1 channel for internal reference voltage (V REFINT). The input voltage range is
between VREF- and VREF+. An on-chip hardware oversampling scheme improves performance
while off-loading the related computational burden from the CPU. The analog watchdog
allows the application to detect whether the input voltage goes outside the user-defined higher
or lower thresholds. A configurable channel management block can be used to perform
conversions in single, continuous, scan or discontinuous mode to support more advanced
use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx),
and the advanced timers (TIMER0 and TIMER7). The temperature sensor can be used to
generate a voltage that varies linearly with temperature. It is internally connected to the
ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.
To ensure a high accuracy on ADC and DAC, the ADC/DAC independent external reference
voltage should be connected to VREF+/VREF- pins. According to the different packages, VREF+
pin can be connected to VDDA pin, or external reference voltage, VREF- pin must be connected
to VSSA pin. The VREF+ pin is only available on no less than 100-pin packages, or else the VREF+
pin is not available and internally connected to VDDA. The VREF- pin is only available on no less
than 100-pin packages, or else the VREF- pin is not available and internally connected to VSSA.
3.7.
Digital to analog converter (DAC)
Two 12-bit DACs with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller
The 12-bit buffered DAC is used to generate variable analog outputs. The DAC channels can
be triggered by the timer, or EXTI with DMA support. In dual DAC channel operation,
conversions could be done independently or simultaneously. The maximum output value of
the DAC is VREF+.
3.8.
DMA
7 channels for DMA0 controller and 5 channels for DMA1 controller
Peripherals supported: Timers, ADCs, DACs, SPIs, I2Cs, USARTs and I2S
33
GD32EPRTxx Datasheet
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9.
General-purpose inputs/outputs (GPIOs)
Up to 112 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 80 general purpose I/O pins (GPIO) in GD32EPRTxx, named PA0 ~ PA15,
PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15 and PE0 ~ PE15 to implement logic input/output
functions. Each of the GPIO ports has related control and configuration registers to satisfy
the requirements of specific applications. The external interrupts on the GPIO pins of the
device have related control and configuration registers in the Interrupt/event controller (EXTI).
The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum
flexibility on the package pins. Each of the GPIO pins can be configured by software as output
(push-pull or open-drain), input, peripheral alternate function or analog mode. Most of the
GPIO pins are shared with digital or analog alternate functions.
3.10.
Timers and PWM generation
Two 16-bit advanced timer (TIMER0, TIMER7), one 32-bit general timer (TIMER1), up to
three 16-bit general timers (TIMER2 ~ TIMER4), and two 16-bit basic timer (TIMER5,
TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0, TIMER7) can be used as a three-phase PWM multiplexed on
6 channels. It has complementary PWM outputs with programmable dead-time generation. It
can also be used as a complete general timer. The 4 independent channels can be used for
input capture, output compare, PWM generation (edge- or center- aligned counting modes)
and single pulse mode output. If configured as a general 16-bit timer, it has the same functions
as the TIMERx timer. It can be synchronized with external signals or to interconnect with other
34
GD32EPRTxx Datasheet
general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal
pulse width measurement or output waveform generation such as a single pulse generation
or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 is
based on a 32-bit auto-reload up/down counter and a 16-bit prescaler. TIMER2 ~ TIMER4 is
based on a 16-bit auto-reload up/down counter and a 16-bit prescaler. The general timer also
supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 &TIMER6, are mainly used for DAC trigger generation.
They can also be used as a simple 16-bit time base.
The GD32EPRTxx have two watchdog peripherals, free watchdog timer and window
watchdog timer. They offer a combination of high safety level, flexibility of use and timing
accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-stage prescaler.
It is clocked from an independent 40 KHz internal RC and as it operates independently of the
main clock, it can operate in deep-sleep, deep-sleep 1, deep-sleep 2 and standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a freerunning timer for application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early wakeup interrupt capability and the counter can be frozen in
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.11.
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC)
32-bit programmable counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wakeup event
The real time clock is an independent timer which provides a set of continuously running
counters in backup registers to provide a real calendar function, and provides an alarm
interrupt or an expected interrupt. The RTC features a 32-bit programmable counter for longterm measurement using the compare register to generate an alarm. A 20-bit prescaler is
used for the time base clock and is by default configured to generate a time base of 1 second
from a clock at 32.768 KHz from external crystal oscillator.
35
GD32EPRTxx Datasheet
3.12.
Inter-integrated circuit (I2C)
I2C0 and I2C1:
Support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
SMBus 2.0 and PMBus compatible
Supports SAM_V mode
I2C2:
Support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
SMBus 3.0 and PMBus 1.3 compatible
Wakeup from Deep-sleep mode on address match
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode,
up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also
has an arbitration detect function to prevent the situation where more than one master
attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided
in I2C interface to perform packet error checking for I2C data.
3.13.
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). All SPIs can be served by the
DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking. Quad-SPI master mode is also supported in SPI0.
36
GD32EPRTxx Datasheet
3.14.
Universal synchronous asynchronous receiver transmitter
(USART)
USART0~2, UART3~4:
Maximum speed up to 22.5 MBits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
USART5:
Maximum speed up to 22.5 MBits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
Dual clock domain
Wake up from Deep-sleep mode
The USART (USART0, USART1, USART2, USART5) are used to translate data between
parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous
or asynchronous transfer. It is also commonly used for RS-232 standard communication. The
USART includes a programmable baud rate generator which is capable of dividing the system
clock to produce a dedicated clock for the USART transmitter and receiver. The USART also
supports DMA function for high speed data communication.
3.15.
Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 4-wire serial lines. GD32EPRTxx contain an I2S-bus interface that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and
SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported.
3.16.
Universal Serial Bus full-speed device interface (USBD)
USB 2.0 full-speed device controller.
Support USB 2.0 Link Power Management.
Dedicated 512-byte SRAM used for data packet buffer.
Integrated USB PHY.
37
GD32EPRTxx Datasheet
The Universal Serial Bus full-speed device interface (USBD) module contains a full-speed
internal USB PHY and no more external PHY chip is needed. USBD supports all the four
types of transfer (control, bulk, interrupt and isochronous) defined in USB 2.0 protocol. USBD
supports 8 USB endpoints that can be individually configured.
3.17.
Ethernet (ENET)
IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN
10/100 Mbit/s rates with dedicated DMA controller and SRAM
Support hardware precision time protocol (PTP) with conformity to IEEE 1588
The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully
supports IEEE 1588 standards. The embedded MAC provides the interface to the required
external network physical interface (PHY) for LAN bus connection via an internal media
independent interface (MII) or a reduced media independent interface (RMII). The number of
MII signals provided up to 16 with 25 MHz output and RMII up to 7 with 50 MHz output. The
function of 32-bit CRC checking is also available.
3.18.
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
PC card
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory except NAND Flash and PC card. The EXMC also can be
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
3.19.
Serial/Quad Parallel Interface (SQPI)
SQPI controller support configuring output clock frequency which is divided by HCLK.
SQPI controller support no address phase and data phase operation which is named
special command by the controller.
SQPI controller support 256MB external memory space.
Logic memory address range: 0xB000_0000 - 0xBFFF_FFFF.
SQPI controller support 6 types mode for different combination of command, address,
wait cycle, and data phase.
Serial/Quad Parallel Interface (SQPI) is a controller for external serial/dual/quad parallel
38
GD32EPRTxx Datasheet
interface memory peripheral. For example: SQPI-PSRAM and SQPI-FLASH. With this
controller, users can use external SQPI interface memory as SRAM simply.
Note: There is a 4 Mbytes PSRAM embedded, and the SQPI interface is internally connected
to GPIOF ports: SQPI_DO – PF0, SQPI_D1 – PF4, SQPI_D2 – PF2, SQPI_D3 – PF10,
SQPI_CLK – PF8, SQPI_CSN – PF6. Users should configure the GPIOF corresponding bits
to SQPI function before using the embedded PSRAM.
3.20.
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.21.
Package and operation temperature
LQFP100 (GD32EPRTVDT6) and LQFP64 (GD32EPRTRDT6).
Operation temperature range: -40°C to +85°C (industrial level)
39
GD32EPRTxx Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 4-1. Absolute maximum ratings (1)(4)
Symbol
Parameter
Min
Max
Unit
VDD
External voltage range(2)
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V tolerant pin(3)
VSS - 0.3
VDD + 3.6
V
Input voltage on other I/O
VSS - 0.3
3.6
V
|ΔVDDx|
Variations between different VDD power pins
—
50
mV
|VSSX −VSS|
Variations between different ground pins
—
50
mV
IIO
Maximum current for GPIO pins
—
±25
mA
TA
Operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
(1)
(2)
(3)
(4)
4.2.
Guaranteed by design, not tested in production.
All main power and ground pins should be connected to an external power source within the allowable range.
VIN maximum value cannot exceed 6.5 V.
It is recommended that VDD and VDDA are powered by the same source. The maximum difference between V DD
and VDDA does not exceed 300 mV during power-up and operation.
Operating conditions characteristics
Table 4-2. DC operating conditions
Symbol
Parameter
Conditions
VDD
Supply voltage
—
VDDA
VBAT
Analog supply voltage, fADCMAX = 35 MHz
Analog supply voltage, fADCMAX = 14 MHz
Battery supply voltage
—
—
Min(1) Typ Max(1) Unit
1.71
3.3
3.6
2.4
3.3
3.6
1.71
—
2.4
1.71
—
3.6
V
V
V
(1) Based on characterization, not tested in production.
40
GD32EPRTxx Datasheet
Figure 4-1. Recommended power supply decoupling capacitors
(1)(2)
VBAT
100 nF
VSS
N * VDD
4.7 μF + N * 100 nF
VSS
VDDA
1 μF
10 nF
VSSA
VREF+
1 μF
10 nF
VREF-
(1) The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins
are not available and internally connected to VDDA and VSSA pins.
(2) All decoupling capacitors need to be as close as possible to the pins on the PCB board.
Table 4-3. Clock frequency (1)
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
AHB clock frequency
—
—
180
MHz
fAPB1
APB1 clock frequency
—
—
90
MHz
fAPB2
APB2 clock frequency
—
—
180
MHz
Min
Max
Unit
0
∞
20
∞
(1) Guaranteed by design, not tested in production.
Table 4-4. Operating conditions at Power up/ Power down
Symbol
tVDD
Parameter
(1)
Conditions
VDD rise time rate
—
VDD fall time rate
μs/ V
(1) Guaranteed by design, not tested in production.
Table 4-5. Start-up timings of Operating conditions
Symbol
Parameter
tstart-up
Start-up time
(1)(2)(3)
Conditions
Typ
Clock source from HXTAL
—
Clock source from IRC8M
—
Unit
μs
(1) Based on characterization, not tested in production.
(2) After power-up, the start-up time is the time between the rising edge of NRST high and the first I/O instruction
conversion in SystemInit function.
(3) PLL is off.
41
GD32EPRTxx Datasheet
Table 4-6. Power saving mode wakeup timings characteristics (1)(2)
Symbol
Parameter
Typ
tSleep
Wakeup from Sleep mode
—
Wakeup from Deep-sleep mode (LDO On)
—
Wakeup from Deep-sleep mode (LDO in low power mode)
—
Wakeup from Standby mode
—
tDeep-sleep
tStandby
Unit
μs
(1) Based on characterization, not tested in production.
(2) The wakeup time is measured from the wakeup event to the point at which the application code reads the first
instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz.
4.3.
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 4-7. Power consumption characteristics (2)(3)(4)(5)
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 180 MHz, All peripherals
—
59.8
—
mA
—
26.1
—
mA
—
53.6
—
mA
—
23.5
—
mA
—
41
—
mA
—
18.2
—
mA
—
37.2
—
mA
—
16.6
—
mA
—
33.4
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 180 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 160 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 160 MHz, All peripherals
disabled
IDD+IDDA
Supply current
(Run mode)
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
enabled
42
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
—
15
—
mA
—
25.7
—
mA
—
11.8
—
mA
—
18
—
mA
—
7.96
—
mA
—
14
—
mA
—
6.49
—
mA
—
9.73
—
mA
—
4.83
—
mA
—
7.2
—
mA
—
3.9
—
mA
—
4.62
—
mA
—
2.9
—
mA
—
—
—
mA
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
enabled
43
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
—
—
—
mA
—
—
—
mA
—
—
—
mA
—
47.8
—
mA
—
9.5
—
mA
—
42.8
—
mA
—
8.7
—
mA
—
32.8
—
mA
—
7.07
—
mA
—
29.8
—
mA
—
6.57
—
mA
—
26.7
—
mA
—
6.1
—
mA
—
20.7
—
mA
disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System clock = 2 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 180 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 180 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 160 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 160 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
All peripherals enabled
Supply current
(Sleep mode)
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
peripherals enabled
44
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
—
5.1
—
mA
—
14.5
—
mA
—
4.1
—
mA
—
11.4
—
mA
—
3.6
—
mA
—
8.3
—
mA
—
3.1
—
mA
—
6.2
—
mA
—
2.7
—
mA
—
4.2
—
mA
—
2.4
—
mA
—
—
—
mA
—
—
—
mA
—
—
—
mA
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
peripherals enabled
45
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
—
—
—
mA
—
μA
—
μA
—
μA
—
μA
peripherals disabled
VDD = VDDA = 3.3 V, LDO in run mode,
IRC40K off, RTC off, All GPIOs analog
—
mode
VDD = VDDA = 3.3 V, LDO in low power
Supply current
(Deep-Sleep
mode)
mode, IRC40K off, RTC off, All GPIOs
—
analog mode
VDD = VDDA = 3.3 V, Main LDO in under
drive mode, IRC40K off, RTC off, All
—
GPIOs analog mode
VDD = VDDA = 3.3 V, Low Power LDO in
under drive mode, IRC40K off, RTC off, All
—
GPIOs analog mode
VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
RTC on
Supply current VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
(Standby mode)
RTC off
VDD = VDDA = 3.3 V, LXTAL off, IRC40K off,
RTC off
461.3
3
413.0
0
258.0
0
210.6
7
—
3.79
—
μA
—
3.58
—
μA
—
3.08
—
μA
—
1.95
—
μA
—
1.82
—
μA
—
1.67
—
μA
—
1.59
—
μA
—
1.53
—
μA
—
1.40
—
μA
—
1.25
—
μA
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 2.5 V, LXTAL on
with external crystal, RTC on, LXTAL High
Battery supply
IBAT
current (Backup
mode)
driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 2.5 V, LXTAL on
with external crystal, RTC on, LXTAL
46
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
Medium High driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL
—
1.18
—
μA
—
1.12
—
μA
—
0.99
—
μA
—
0.84
—
μA
—
0.77
—
μA
—
1.00
—
μA
—
0.87
—
μA
—
0.72
—
μA
—
0.64
—
μA
Medium High driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 2.5 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 2.5 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 1.8 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
(1) Based on characterization, not tested in production.
(2) Unless otherwise specified, all values given for TA = 25 °C and test result is mean value.
(3) When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed,
no PLL.
(4) When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed,
using PLL.
(5) When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional
power consumption should be considered.
47
GD32EPRTxx Datasheet
Figure 4-2. Typical supply current consumption in Run mode
Figure 4-3. Typical supply current consumption in Sleep mode
48
GD32EPRTxx Datasheet
Table 4-8. Peripheral current consumption characteristics (1)
Peripherals(4)
APB1
APB2
AHB1
Typical consumption at TA = 25 ℃
（TYP）
CTC
—
I2C2
—
DAC(2)
—
PMU
—
BKP
—
I2C1
—
I2C0
—
UART4
—
UART3
—
USART2
—
USART1
—
SPI2/I2S2
—
SPI1/I2S1
—
FWDGT
—
WWDGT
—
RTC
—
TIMER5
—
TIMER4
—
TIMER3
—
TIMER2
—
TIMER1
—
USART5
—
USART0
—
SPI0
—
TIMER0
—
ADC1(3)
—
ADC0(3)
—
GPIOE
—
GPIOD
—
GPIOC
—
GPIOB
—
GPIOA
—
EXTI
—
AFIO
—
ENET
—
CRC
—
FMC
—
DMA1
—
DMA0
—
Unit
mA
(1) Based on characterization, not tested in production.
49
GD32EPRTxx Datasheet
(2) DEN0 and DEN1 bits in the DAC_CTL register are set to 1, and the converted value set to 0x800.
(3) system clock = fHCLK = 180 Mhz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit is set to 1.
(4) If there is no other description, then HXTAL = 25 MHz, system clock = fHCLK = 180 MHz, fAPB1 = fHCLK/2, fAPB2 =
fHCLK.
50
GD32EPRTxx Datasheet
4.4.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in Table 4-9. EMS characteristics (1), based on the EMS levels and classes compliant
with IEC 61000 series standard.
Table 4-9. EMS characteristics (1)
Symbol
VESD
VFTB
Parameter
Conditions
Voltage applied to all device pins to
induce a functional disturbance
Level/Class
VDD = 3.3 V, TA = 25 °C
—
LQFP144, fHCLK = 180 MHz
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VDD = 3.3 V, TA = 25 °C
induce a functional disturbance through
LQFP144, fHCLK = 180 MHz
100 pF on VDD and VSS pins
conforms to IEC 61000-4-4
—
(1) Based on characterization, not tested in production.
4.5.
Power supply supervisor characteristics
Table 4-10. Power supply supervisor characteristics
Symbol
VLVD(1)
Parameter
Conditions
Min
Typ
Max
LVDT = 000(rising edge)
—
—
—
LVDT = 000(falling edge)
—
—
—
LVDT = 001(rising edge)
—
—
—
LVDT = 001(falling edge)
—
—
—
LVDT = 010(rising edge)
—
—
—
LVDT = 010(falling edge)
—
—
—
Low voltage
LVDT = 011(rising edge)
—
—
—
Detector level selection
LVDT = 011(falling edge)
—
—
—
LVDT = 100(rising edge)
—
—
—
LVDT = 100(falling edge)
—
—
—
LVDT = 101(rising edge)
—
—
—
LVDT = 101(falling edge)
—
—
—
LVDT = 110(rising edge)
—
—
—
LVDT = 110(falling edge)
—
—
—
Unit
V
51
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
LVDT = 111(rising edge)
—
—
—
LVDT = 111(falling edge)
—
—
—
Unit
VLVDhyst(2)
LVD hysteresis
—
—
100
—
mV
VPOR(1)
Power on reset threshold
—
—
1.56
—
V
—
—
1.52
—
V
—
—
40
—
mV
Falling edge
—
2.8
—
V
Rising edge
—
2.9
—
V
Falling edge
—
2.5
—
V
Rising edge
—
2.6
—
V
Falling edge
—
2.2
—
V
Rising edge
—
2.3
—
V
VPDR(1)
Power down reset
threshold
VPDRhyst(2)
PDR hysteresis
VBOR3(2)
Brownout level 3 threshold
VBOR2(2)
Brownout level 2 threshold
VBOR1(2)
Brownout level 1 threshold
VBORhyst(2)
BOR hysteresis
—
—
100
—
mV
tRSTTEMPO(2)
Reset temporization
—
—
2.88
—
ms
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
4.6.
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up
(LU) test is based on the two measurement methods.
Table 4-11. ESD characteristics (1)
Symbol
VESD(HBM)
VESD(CDM)
Parameter
Conditions
Electrostatic discharge
TA=25 °C;
voltage (human body model)
JESD22-A114
Electrostatic discharge
TA=25 °C;
voltage (charge device model)
JESD22-C101
Min
Typ
Max
Unit
—
—
—
V
—
—
—
V
Min
Typ
Max
Unit
—
—
—
mA
—
—
—
V
(1) Based on characterization, not tested in production.
Table 4-12. Static latch-up characteristics (1)
Symbol
Parameter
Conditions
I-test
LU
TA=25 °C; JESD78
Vsupply over voltage
(1) Based on characterization, not tested in production.
52
GD32EPRTxx Datasheet
4.7.
External clock characteristics
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics
Symbol
fHXTAL
RF
(1)
(2)
CHXTAL(2)(3)
Parameter
Conditions
Min
Typ
Max
Unit
Crystal or ceramic frequency
1.71 V ≤ VDD ≤ 3.6 V
4
8
32
MHz
Feedback resistor
VDD = 3.3 V
—
400
—
kΩ
Recommended load capacitance
—
—
20
30
on OSCIN and OSCOUT
pF
Ducy(HXTAL)(2)
Crystal or ceramic duty cycle
—
30
50
70
%
gm(2)
Oscillator transconductance
Startup
—
25
—
mA/V
—
—
—
mA
—
2
—
ms
IDDHXTAL
(1)
VDD = 3.3 V, fHCLK =
Crystal or ceramic operating
fIRC8M = 8 MHz
current
TA = 25 °C
VDD = 3.3 V, fHCLK =
tSUHXTAL(1)
Crystal or ceramic startup time
fIRC8M = 8 MHz
TA = 25 °C
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
(3) CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN
and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer.
For CS, it is PCB and MCU pin stray capacitance.
Table 4-14. High speed external clock characteristics (HXTAL in bypass mode)
Symbol
fHXTAL_ext(1)
VHXTALH(2)
VHXTALL(2)
Parameter
Conditions
External clock source or
1.71 V ≤ VDD ≤ 3.6
oscillator frequency
V
OSCIN input pin high level
voltage
OSCIN input pin low level
Min
Typ
Max
Unit
1
—
50
MHz
0.7 VDD
—
VDD
V
VSS
—
0.3 VDD
V
VDD = 3.3 V
voltage
OSCIN high or low time
—
5
—
—
ns
OSCIN rise or fall time
—
—
—
10
ns
CIN(2)
OSCIN input capacitance
—
—
5
—
pF
Ducy(HXTAL)(2)
Duty cycle
—
40
—
60
%
tH/L(HXTAL)(2)
tR/F(HXTAL)
(2)
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic
53
GD32EPRTxx Datasheet
characteristics
Symbol
Parameter
Crystal or ceramic
fLXTAL(1)
frequency
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
—
32.768
—
kHz
—
—
10
—
pF
—
30
—
70
%
—
4
—
—
6
—
Recommended matching
CLXTAL
(2)(3)
capacitance on OSC32IN
and OSC32OUT
Ducy(LXTAL)(2)
Crystal or ceramic duty
cycle
Lower driving
capability
Medium low driving
gm(2)
Oscillator transconductance
capability
Medium high driving
—
12
—
—
18
—
LXTALDRI[1:0] = 00
—
0.7
—
Crystal or ceramic operating
LXTALDRI[1:0] = 01
—
0.8
—
current
LXTALDRI[1:0] = 10
—
1.2
—
LXTALDRI[1:0] = 11
—
1.5
—
—
—
2
—
capability
Higher driving
capability
IDDLXTAL(1)
tSULXTAL(1)(4)
μA/V
Crystal or ceramic startup
time
μA
s
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
(3) CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on SC32IN
and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic
manufacturer. For CS, it is PCB and MCU pin stray capacitance.
(4) tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator
stabilization flags is SET. This value varies significantly with the crystal manufacturer.
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode)
Symbol
Parameter
fLXTAL_ext(1)
VLXTALH(2)
VLXTALL
External clock source or
oscillator frequency
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
—
32.768
1000
kHz
—
0.7 VDD
—
VDD
OSC32IN input pin high level
voltage
OSC32IN input pin low level
(2)
voltage
V
—
VSS
—
0.3 VDD
tH/L(LXTAL)(2)
OSC32IN high or low time
—
450
—
—
tR/F(LXTAL)(2)
OSC32IN rise or fall time
—
—
—
50
CIN(2)
OSC32IN input capacitance
—
—
5
—
pF
Duty cycle
—
30
50
70
%
Ducy(LXTAL)
(2)
ns
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
54
GD32EPRTxx Datasheet
4.8.
Internal clock characteristics
Table 4-17. High speed internal clock (IRC8M) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = VDDA = 3.3 V
—
8
—
MHz
-2.5
—
+2.5
%
-1.8
—
+1.8
%
VDD = VDDA = 3.3 V, TA = 25 °C
-1.0
—
+1.0
%
—
—
0.5
—
%
VDD = VDDA = 3.3 V
45
50
55
%
VDD = VDDA = 3.3 V,
—
80
—
μA
VDD = VDDA = 3.3 V,
—
1.5
—
μs
Min
Typ
Max
Unit
20
40
45
kHz
—
0.4
—
μA
—
80
—
μs
High Speed Internal
fIRC8M
Oscillator (IRC8M)
frequency
VDD = VDDA = 3.3 V,
TA = -40 °C ~ +85 °C(1)
IRC8M oscillator Frequency
VDD = VDDA = 3.3 V,
accuracy, Factory-trimmed
ACCIRC8M
TA = 0 °C ~ +85 °C(1)
IRC8M oscillator Frequency
accuracy, User trimming
step(1)
DucyIRC8M(2) IRC8M oscillator duty cycle
IDDAIRC8M(1)
tSUIRC8M(1)
IRC8M oscillator operating
current
IRC8M oscillator startup
time
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
Table 4-18. Low speed internal clock (IRC40K) characteristics
Symbol
fIRC40K(1)
IDDAIRC40K(2)
tSUIRC40K(2)
Parameter
Conditions
Low Speed Internal oscillator
VDD = VDDA = 3.3 V,
(IRC40K) frequency
TA = -40 °C ~ +85 °C
IRC40K oscillator operating
current
IRC40K oscillator startup
time
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 180 MHz
TA = 25 °C
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 180 MHz
TA = 25 °C
(1) Guaranteed by design, not tested in production.
(2) Based on characterization, not tested in production.
55
GD32EPRTxx Datasheet
Table 4-19. High speed internal clock (IRC48M) characteristics
Symbol
fIRC48M
Parameter
Conditions
Min
Typ
VDD = 3.3 V
—
48
—
MHz
-4.0
—
+5.0
%
-3.0
—
+3.0
%
-2.0
—
+2.0
%
—
—
0.12
—
%
VDD = VDDA = 3.3 V
45
50
55
%
—
—
—
μA
—
—
—
μs
High Speed Internal Oscillator
(IRC48M) frequency
VDD = VDDA = 3.3 V,
TA = -40 °C ~ +85 °C(1)
IRC48M oscillator Frequency
VDD = VDDA = 3.3 V,
accuracy, Factory-trimmed
TA = 0 °C ~ +85 °C (1)
ACCIRC48M
VDD = VDDA = 3.3 V,
TA = 25 °C
IRC48M oscillator Frequency
accuracy, User trimming step(1)
DIRC48M(2)
IDDAIRC48M(1)
IRC48M oscillator duty cycle
IRC48M oscillator operating
current
Max Unit
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 180
MHz
VDD = VDDA = 3.3 V,
tSUIRC48M(1)
IRC48M oscillator startup time fHCLK = fHXTAL_PLL = 180
MHz
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
4.9.
PLL characteristics
Table 4-20. PLL characteristics
Symbol
fPLLIN
(1)
fPLLOUT
(2)
fVCO(2)
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
2
—
16
MHz
PLL output clock frequency
—
16
—
200
MHz
—
32
—
400
MHz
PLL VCO output clock
frequency
tLOCK(2)
PLL lock time
—
—
—
300
μs
IDDA(1)(3)
Current consumption on VDDA
VCO freq = 400 MHz
—
700
—
μA
IDD(1)(3)
Current consumption on VDD
VCO freq = 400 MHz
—
500
—
μA
—
40
—
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
Cycle to cycle Jitter
（peak to peak）
(1)
(2)
(3)
(4)
System clock
ps
—
400
—
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
System clock = IRC8M = 8 MHz, PLL clock source = IRC8M/2 = 4 MHz, fPLLOUT = 200 MHz.
Value given with main PLL running.
56
GD32EPRTxx Datasheet
Table 4-21. PLL1 characteristics
Symbol
fPLLIN
(1)
fPLLOUT
(2)
fVCO(2)
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
2
—
16
MHz
PLL output clock frequency
—
16
—
100
MHz
—
32
—
200
MHz
PLL VCO output clock
frequency
tLOCK(2)
PLL lock time
—
—
—
300
μs
IDDA(1)
Current consumption on VDDA
VCO freq = 200 MHz
—
400
—
μA
IDD(1)
Current consumption on VDD
VCO freq = 200 MHz
—
250
—
μA
JitterPLL(1)
Cycle to cycle Jitter
—
—
40
—
ps
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
2
—
16
MHz
PLL output clock frequency
—
16
—
200
MHz
—
32
—
400
MHz
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
Table 4-22. PLL2 characteristics
Symbol
fPLLIN
(1)
fPLLOUT
(2)
fVCO(2)
PLL VCO output clock
frequency
tLOCK(2)
PLL lock time
—
—
—
300
μs
IDDA(1)
Current consumption on VDDA
VCO freq = 200 MHz
—
700
—
μA
IDD(1)
Current consumption on VDD
VCO freq = 200 MHz
—
500
—
μA
JitterPLL(1)
Cycle to cycle Jitter
—
—
40
—
ps
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
Table 4-23. PLLUSB characteristics
Symbol
fPLLIN
(1)
fPLLOUT
(2)
fVCO(2)
tLOCK(2)
IDD(1)
JitterPLL(1)
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
4
—
25
MHz
PLL output clock frequency
—
—
480
—
MHz
—
—
480
—
MHz
—
—
—
300
μs
VCO freq = 480 MHz
—
2.5
—
mA
—
—
40
—
ps
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
57
GD32EPRTxx Datasheet
4.10.
Memory characteristics
Table 4-24. Flash memory characteristics
Symbol
Conditions
Min(1)
Typ(1)
Max
Unit
TA = -40 °C ~ +85 °C
10
—
—
kcycles
Parameter
Number of guaranteed
PECYC
program /erase cycles
before failure (Endurance)
tRET
Data retention time
—
10
—
—
years
tPROG
Word programming time
TA = -40 °C ~ +85 °C
—
37.5
—
μs
tERASE
Page erase time
TA = -40 °C ~ +85 °C
—
11
—
ms
tMERASE
Mass erase time
TA = -40 °C ~ +85 °C
—
12
—
s
(1) Based on characterization, not tested in production.
Table 4-25. SIP PSRAM memory characteristics (1) (2)
Symbol
ISB_STDroom
ISB
ICC
tCLK for read
tCLK for others
tRST
Parameter
Standby current (standard room
temp)
Standby current
Operation current(standard room
temp)
For Read(‘h03) and Read ID(‘h9F)
command
For command except read and read
ID command
Time between end of RST CMD to
next valid CMD
Conditions
Min
Max
Unit
TA = +25 °C
—
40
μA
TA = -40 °C ~ +85 °C
—
150
μA
TA = +25 °C
—
6
mA
TA = -40 °C ~ +85 °C
2
33
MHz
TA = -40 °C ~ +85 °C
2
45
MHz
TA = -40 °C ~ +85 °C
50
—
ns
(1)
Guaranteed by design, not tested in production.
(2)
Need to configure specified pins to PSRAM functions respectively (PF0 to SQPI_D0, PF2 to SQPI_D2, PF4 to
SQPI_D1, PF6 to SQPI_CSN, PF8 to SQPI_CLK and PF10 to SQPI_D3).
58
GD32EPRTxx Datasheet
4.11.
NRST pin characteristics
Table 4-26. NRST pin characteristics
Symbol
VIL(NRST)
NRST Input low level voltage
(1)
NRST Input high level voltage
VIH(NRST)
—
—
—
—
—
—
—
NRST Input low level voltage
—
—
—
(1)
NRST Input high level voltage
—
—
—
VDD = VDDA = 2.5 V
Schmidt trigger Voltage hysteresis
—
—
—
(1)
NRST Input low level voltage
—
—
—
(1)
NRST Input high level voltage
—
—
—
VDD = VDDA = 3.3 V
Unit
V
mV
V
mV
V
Schmidt trigger Voltage hysteresis
—
—
—
(1)
NRST Input low level voltage
—
—
—
(1)
NRST Input high level voltage
—
—
—
—
—
—
mV
—
40
—
kΩ
Vhyst(1)
VIH(NRST)
Vhyst(1)
Rpu
Max
—
VIH(NRST)
(2)
Typ
—
Vhyst(1)
VIL(NRST)
VDD = VDDA = 1.71 V
Min
Schmidt trigger Voltage hysteresis
VIH(NRST)
VIL(NRST)
Conditions
(1)
Vhyst(1)
VIL(NRST)
Parameter
(1)
VDD = VDDA = 3.6 V
Schmidt trigger Voltage hysteresis
—
Pull-up equivalent resistor
mV
V
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
Figure 4-4. Recommended external NRST pin circuit
VDD
VDD
External reset circuit
10 kΩ
RPU
NRST
K
100 nF
GND
59
GD32EPRTxx Datasheet
4.12.
GPIO characteristics
Table 4-27. I/O port DC characteristics (1)(3)
Symbol
Parameter
Standard IO Low level input
VIL
voltage
5V-tolerant IO Low level
input voltage
Standard IO Low level input
VIH
voltage
5V-tolerant IO Low level
input voltage
VOL
VOL
VOH
VOH
RPU(2)
RPD(2)
Conditions
Min
Typ
1.8 V ≤ VDD = VDDA ≤ 3.6 V
—
—
1.8 V ≤ VDD = VDDA ≤ 3.6 V
—
—
1.8 V ≤ VDD = VDDA ≤ 3.6 V
1.8 V ≤ VDD = VDDA ≤ 3.6 V
—
—
Max
—
—
Unit
V
V
—
—
V
—
—
V
Low level output voltage
VDD = 1.8V
—
—
—
for an IO Pin
VDD = 3.3 V
—
—
—
(IIO = +8 mA)
VDD = 3.6V
—
—
—
Low level output voltage
VDD = 1.8V
—
—
—
for an IO Pin
VDD = 3.3 V
—
—
—
(IIO = +20 mA)
VDD = 3.6V
—
—
—
High level output voltage
VDD = 1.8V
—
—
—
for an IO Pin
VDD = 3.3 V
—
—
—
(IIO = +8 mA)
VDD = 3.6V
—
—
—
High level output voltage
VDD = 1.8V
—
—
—
for an IO Pin
VDD = 3.3 V
—
—
—
(IIO = +20 mA)
VDD = 3.6V
—
—
—
Internal pull-up
All pins
—
—
—
—
resistor
PA10
—
—
—
—
Internal pull-
All pins
—
—
—
—
down resistor
PA10
—
—
—
—
V
V
V
V
kΩ
kΩ
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
(3) All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which can
only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz when they
are in output mode(maximum load: 30 pF).
Table 4-28. I/O port AC characteristics (1)(2)
GPIOx_MDy[1:0] bit value(3)
Parameter
GPIOx_CTL->MDy[1:0]=10
Maximum
（IO_Speed = 2MHz）
frequency(4)
GPIOx_CTL->MDy[1:0] = 01
Maximum
（IO_Speed = 10MHz）
frequency(4)
GPIOx_CTL->MDy[1:0]=11
Maximum
Conditions
Max
1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF
—
Unit
MHz
MHz
MHz
60
GD32EPRTxx Datasheet
GPIOx_MDy[1:0] bit
value(3)
（IO_Speed = 50MHz）
Parameter
Conditions
Max
frequency(4)
1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 10 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 30 pF
—
1.8 ≤ VDD ≤ 3.6 V, CL = 50 pF
—
GPIOx_CTL->MDy[1:0]=11 and
Maximum
GPIOx_SPDy=1
frequency(4)
（IO_Speed = MAX）
Unit
MHz
(1) Based on characterization, not tested in production.
(2) Unless otherwise specified, all test results given for TA = 25 °C.
(3) The I/O speed is configured using the GPIOx_CTL -> MDy[1:0] bits. Refer to the GD32E50x user manual which
is selected to set the GPIO port output speed.
(4) The maximum frequency is defined in Figure 4-5. I/O port AC characteristics definition, and maximum
frequency cannot exceed 180 MHz.
Figure 4-5. I/O port AC characteristics definition
90%
EXTERNAL
OUTPUT
ON 50pF
90%
50%
50%
10%
10%
tf(IO)out
tr(IO)out
T
If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved .
The duty cycle is （45%-55%）when loaded by 50 pF
4.13.
Temperature sensor characteristics
Table 4-29. Temperature sensor characteristics (1)
Symbol
Parameter
Min
Typ
Max
Unit
TL
VSENSE linearity with temperature
—
—
—
°C
Avg_Slope
Average slope
—
—
—
mV/°C
V25
Voltage at 25 °C
—
—
—
V
tS_temp(2)
ADC sampling time when reading the temperature
—
—
—
μs
(1) Based on characterization, not tested in production.
(2) Shortest sampling time can be determined in the application by multiple iterations.
4.14.
ADC characteristics
Table 4-30. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
1.71
3.3
3.6
V
VIN(1)
ADC input voltage range
—
0
—
VREF+
V
VREF+(2)
Positive Reference Voltage
—
1.8
—
VDDA
V
Negative Reference
—
—
VSSA
—
V
VREF-
(2)
61
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA = 1.71 V to 2.4 V
0.1
—
14
MHz
VDDA = 2.4 V to 3.6 V
0.1
—
35
MHz
12-bit
0.007
—
2.86
10-bit
0.008
—
3.33
MSP
8-bit
0.01
—
4
S
6-bit
0.012
—
5
Voltage
fADC(1)
ADC clock
fS(1)
Sampling rate
(1)
Analog input voltage
16 external; 2 internal
0
—
VDDA
V
(2)
External input impedance
See Equation 1
—
—
37.73
kΩ
—
—
—
0.55
kΩ
—
—
5.5
pF
VAIN
RAIN
Input sampling switch
RADC(2)
resistance
No pin/pad capacitance
CADC(2)
Input sampling capacitance
tCAL(2)
Calibration time
fADC = 40 MHz
—
3.275
—
μs
Sampling time
fADC = 40 MHz
0.0375
—
5.99
μs
12-bit
—
14
—
10-bit
—
12
—
1/
8-bit
—
10
—
fADC
6-bit
—
8
—
—
—
—
1
(2)
ts
included
Total conversion
tCONV(2)
time(including sampling
time)
tSU(2)
Startup time
μs
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
Equation 1:
RAIN max formula RAIN <
Ts
fADC *CADC * ln (2N+2 )
-RADC
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-31. ADC RAIN max for fADC = 35 MHz
Ts (cycles)
ts (μs)
RAIN max (kΩ)
1.5
0.0429
0.25
7.5
0.2143
3.46
13.5
0.3857
6.68
28.5
0.8143
14.71
41.5
1.1857
21.67
55.5
1.5857
29.16
71.5
2.0429
37.73
239.5
6.8429
N/A
Table 4-32. ADC dynamic accuracy at fADC = 14 MHz (1)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC = 14 MHz
—
—
—
bits
62
GD32EPRTxx Datasheet
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
SNDR
Signal-to-noise and distortion ratio
VDDA = VREF+ = 3.3 V
—
—
—
SNR
Signal-to-noise ratio
Input Frequency = 20 kHz
—
—
—
THD
Total harmonic distortion
Temperature = 25 °C
—
—
—
Max Unit
dB
(1) Based on characterization, not tested in production.
Table 4-33. ADC dynamic accuracy at fADC = 35 MHz (1)
Symbol
Parameter
Test conditions
Min
Typ
ENOB
Effective number of bits
fADC = 35 MHz
—
—
—
SNDR
Signal-to-noise and distortion ratio
VDDA = VREF+ = 3.3 V
—
—
—
SNR
Signal-to-noise ratio
Input Frequency = 20 kHz
—
—
—
THD
Total harmonic distortion
Temperature = 25 °C
—
—
—
Typ
Max
—
—
—
—
—
—
bits
dB
(1) Based on characterization, not tested in production.
Table 4-34. ADC static accuracy at fADC = 14 MHz (1)
Symbol
Parameter
Offset
Offset error
DNL
Differential linearity error
INL
Integral linearity error
Test conditions
fADC = 14 MHz
VDDA = VREF+ = 3.3 V
Unit
LSB
(1) Based on characterization, not tested in production.
63
GD32EPRTxx Datasheet
4.15.
DAC characteristics
Table 4-35. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
1.8
3.3
3.6
V
—
1.8
—
VDDA
V
—
—
VSSA
—
V
5
—
—
kΩ
—
—
—
15
kΩ
No pin/pad capacitance included
—
—
50
pF
—
0.2
—
—
V
—
—
—
—
—
0.5
—
—
—
—
400
—
uA
—
450
—
uA
—
100
—
uA
—
150
—
uA
DAC in 12-bit mode
—
—
±2
LSB
VREF+(2)
VREF-(2)
RLOAD(2)
Ro(2)
CLOAD(2)
Positive Reference
Voltage
Negative Reference
Voltage
Load resistance
Impedance output with
buffer OFF
Load capacitance
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer ON
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer ON
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer OFF
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer OFF
Resistive load with
buffer ON
With no load, middle code(0x800)
IDDA(1)
DAC current consumption
on the input, VREF+ = 3.6 V
in quiescent mode
With no load, worst code(0xF1C)
on the input, VREF+ = 3.6 V
With no load, middle code(0x800)
IDDVREF+(1)
DAC current consumption
on the input, VREF+ = 3.6 V
in quiescent mode
With no load, worst code(0xF1C)
on the input, VREF+ = 3.6 V
DNL(1)
Differential non-linearity
error
VDDA0.2
—
VDDA1LSB
V
mV
V
INL(1)
Integral non-linearity
DAC in 12-bit mode
—
—
±4
LSB
Offset(1)
Offset error
DAC in 12-bit mode
—
—
10
LSB
GE(1)
Tsetting
Gain error
DAC in 12-bit mode
—
—
0.5
%
(1)
Settling time
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
—
—
0.5
μs
(2)
Wakeup from off state
—
—
—
5
μs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
—
—
4
MS/s
—
55
80
—
dB
Twakeup
Max frequency for a
Update
correct DAC_OUT
rate(2)
change from code i to
i±1LSBs
PSRR(2)
Power supply rejection
64
GD32EPRTxx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ratio
(to VDDA)
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
4.16.
I2C characteristics
Table 4-36. I2C characteristics (1)(2)(3)
Symbol
Parameter
Condition Standard mode
s
Fast mode
Fast mode
plus
Unit
Min
Max
Min
Max
Min
Max
tSCL(H)
SCL clock high time
—
4.0
—
0.6
—
0.2
—
μs
tSCL(L)
SCL clock low time
—
4.7
—
1.3
—
0.5
—
μs
tsu(SDA)
SDA setup time
—
2
—
0.8
—
0.1
—
ns
th(SDA)
SDA data hold time
—
250
—
250
—
130
—
ns
—
—
1000
20
300
—
120
ns
—
4
300
4
300
4
120
ns
—
4.0
—
0.6
—
0.26
—
μs
tr(SDA/SCL)
tf(SDA/SCL)
th(STA)
SDA and SCL rise
time
SDA and SCL fall
time
Start condition hold
time
(1) Guaranteed by design, not tested in production.
(2) To ensure the standard mode I2C frequency, fPCLK1 must be at least 2 MHz, To ensure the fast mode I2C
frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode plus I2C frequency, fPCLK1 must be at least a
multiple of 10 MHz.
(3) The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the falling
edge of SCL.
4.17.
SPI characteristics
Table 4-37. Standard SPI characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
22.5
MHz
tSCK(H)
SCK clock high time
tSCK(L)
SCK clock low time
Master mode, fPCLKx = 90 MHz,
presc = 8
Master mode, fPCLKx = 90 MHz,
presc = 8
43.94 44.44 44.94
ns
43.94 44.44 44.94
ns
SPI master mode
tV(MO)
Data output valid time
—
—
5
6
ns
tH(MO)
Data output hold time
—
3
—
—
ns
tSU(MI)
Data input setup time
—
1
—
—
ns
tH(MI)
Data input hold time
—
0
—
—
ns
65
GD32EPRTxx Datasheet
SPI slave mode
tSU(NSS)
NSS enable setup time
—
0
—
—
ns
tH(NSS)
NSS enable hold time
—
1
—
—
ns
tA(SO)
Data output access time
—
5
—
9
ns
tDIS(SO)
Data output disable time
—
6
—
10
ns
tV(SO)
Data output valid time
—
—
10
12
ns
tH(SO)
Data output hold time
—
8
—
—
ns
tSU(SI)
Data input setup time
—
0
—
—
ns
tH(SI)
Data input hold time
—
1
—
—
ns
Typ
Max
Unit
(1) Based on characterization, not tested in production.
4.18.
I2S characteristics
Table 4-38. I2S characteristics (1)(2)
Symbol
Parameter
Conditions
Master mode (data: 16 bits,
fCK
Clock frequency
Audio frequency = 96 kHz)
Slave mode
Min
3.075
3.077 3.079
MHz
0
—
10
162
—
—
ns
163
—
—
ns
tH
Clock high time
tL
Clock low time
tV(WS)
WS valid time
Master mode
0
—
—
ns
tH(WS)
WS hold time
Master mode
0
—
—
ns
tSU(WS)
WS setup time
Slave mode
0
—
—
ns
tH(WS)
WS hold time
Slave mode
2
—
—
ns
Slave mode
—
50
—
%
Ducy(SCK)
—
I2S slave input clock duty
cycle
tSU(SD_MR)
Data input setup time
Master mode
1
—
—
ns
tsu(SD_SR)
Data input setup time
Slave mode
0
—
—
ns
Master receiver
0
—
—
ns
Slave receiver
1
—
—
ns
—
—
12
ns
7
—
—
ns
—
—
6
ns
2
—
—
ns
tH(SD_MR)
tH(SD_SR)
Data input hold time
tv(SD_ST)
Data output valid time
th(SD_ST)
Data output hold time
tv(SD_MT)
Data output valid time
th(SD_MT)
Data output hold time
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
(1) Guaranteed by design, not tested in production.
(2) Based on characterization, not tested in production
66
GD32EPRTxx Datasheet
4.19.
USART characteristics
Table 4-39. USART characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 180 MHz
—
—
90
MHz
tSCK(H)
SCK clock high time
fPCLKx = 180 MHz
5
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 180 MHz
5
—
—
ns
(1) Guaranteed by design, not tested in production.
4.20.
USBD characteristics
Table 4-40. USBD start up time
Symbol
Parameter
Max
Unit
tSTARTUP(1)
USBD startup time
1
μs
(1) Guaranteed by design, not tested in production.
Table 4-41. USBD DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
VDD
USBFS operating voltage
—
3
—
3.6
Input
VDI
Differential input sensitivity
—
0.2
—
—
levels(1)
VCM
Differential common mode range
Includes VDI range
0.8
—
2.5
VSE
Single ended receiver threshold
—
1.3
—
2.0
VOL
Static output level low
RL of 1.0 kΩ to 3.6 V
—
0.064
0.3
levels (2) VOH
Static output level high
RL of 15 kΩ to VSS
2.8
3.3
3.6
Output
Max Unit
V
V
(1) Guaranteed by design, not tested in production.
(2) Based on characterization, not tested in production.
Table 4-42. USBD full speed-electrical characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tR
Rise time
CL = 50 pF
4
—
20
ns
tF
Fall time
CL = 50 pF
4
—
20
ns
tRFM
Rise/ fall time matching
tR / tF
90
—
110
%
vCRS
Output signal crossover voltage
—
1.3
—
2.0
V
(1) Guaranteed by design, not tested in production.
Figure 4-6. USBD timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
VCRS
VSS
tf
tr
67
GD32EPRTxx Datasheet
4.21.
EXMC characteristics
Table 4-43. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
27
29
ns
tV(NOE_NE)
EXMC_NEx low to EXMC_NOE low
0
—
ns
tw(NOE)
EXMC_NOE low time
27
29
ns
th(NE_NOE)
EXMC_NOE high to EXMC_NE high hold time
0
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tsu(DATA_NE)
Data to EXMC_NEx high setup time
21.4
—
ns
tsu(DATA_NOE)
Data to EXMC_NOEx high setup time
21.4
—
ns
th(DATA_NOE)
Data hold time after EXMC_NOE high
0
—
ns
th(DATA_NE)
Data hold time after EXMC_NEx high
0
—
ns
tv(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
4.6
6.6
ns
(1)
(2)
(3)
(4)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: fHCLK = 180 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
Table 4-44. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
15.8
17.8
ns
tV(NWE_NE)
EXMC_NEx low to EXMC_NWE low
4.6
—
ns
tw(NWE)
EXMC_NWE low time
4.6
6.6
ns
th(NE_NWE)
EXMC_NWE high to EXMC_NE high hold time
4.6
6.6
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tV(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
4.6
6.6
ns
10.2
—
ns
th(AD_NADV)
EXMC_AD(address) valid hold time after
EXMC_NADV high
th(A_NWE)
Address hold time after EXMC_NWE high
4.6
—
ns
th(BL_NWE)
EXMC_BL hold time after EXMC_NWE high
4.6
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
15.8
17.8
ns
tv(DATA_NADV)
EXMC_NADV high to DATA valid
4.6
—
ns
th(DATA_NWE)
Data hold time after EXMC_NWE high
4.6
6.6
ns
(1)
(2)
(3)
(4)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: fHCLK = 180 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
68
GD32EPRTxx Datasheet
Table 4-45. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
38.2
40.2
ns
tV(NOE_NE)
EXMC_NEx low to EXMC_NOE low
15.8
—
ns
tw(NOE)
EXMC_NOE low time
21.4
23.4
ns
th(NE_NOE)
EXMC_NOE high to EXMC_NE high hold time
0
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tv(A_NOE)
Address hold time after EXMC_NOE high
0
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
th(BL_NOE)
EXMC_BL hold time after EXMC_NOE high
0
—
ns
tsu(DATA_NE)
Data to EXMC_NEx high setup time
22.4
—
ns
tsu(DATA_NOE)
Data to EXMC_NOEx high setup time
22.4
—
ns
th(DATA_NOE)
Data hold time after EXMC_NOE high
0
—
ns
th(DATA_NE)
Data hold time after EXMC_NEx high
0
—
ns
tv(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
4.6
6.6
ns
4.6
6.6
ns
Th(AD_NADV)
(1)
(2)
(3)
(4)
EXMC_AD(adress) valid hold time after
EXMC_NADV high
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: fHCLK = 180 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
Table 4-46. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
27
29
ns
tV(NWE_NE)
EXMC_NEx low to EXMC_NWE low
7.3
—
ns
tw(NWE)
EXMC_NWE low time
15.8
17.8
ns
th(NE_NWE)
EXMC_NWE high to EXMC_NE high hold time
4.6
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tV(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
4.6
6.6
ns
4.6
—
ns
th(AD_NADV)
EXMC_AD(address) valid hold time after
EXMC_NADV high
th(A_NWE)
Address hold time after EXMC_NWE high
4.6
—
ns
th(BL_NWE)
EXMC_BL hold time after EXMC_NWE high
4.6
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tv(DATA_NADV)
EXMC_NADV high to DATA valid
4.6
—
ns
th(DATA_NWE)
Data hold time after EXMC_NWE high
4.6
—
ns
(1)
(2)
(3)
(4)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: fHCLK = 180 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
69
GD32EPRTxx Datasheet
Table 4-47. Synchronous multiplexed PSRAM/NOR read timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
22.4
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
10.2
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
10.2
—
ns
td(CLKL-NOEL)
EXMC_CLK low to EXMC_NOE low
0
—
ns
td(CLKH-NOEH)
EXMC_CLK high to EXMC_NOE high
10.2
—
ns
td(CLKL-ADV)
EXMC_CLK low to EXMC_AD valid
0
—
ns
td(CLKL-ADIV)
EXMC_CLK low to EXMC_AD invalid
0
—
ns
(1)
(2)
(3)
(4)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: fHCLK = 180 MHz, BurstAccessMode = Enable; Memory Type = PSRAM; WriteBurst = Enable;
CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); Data Latency = 1.
Table 4-48. Synchronous multiplexed PSRAM write timings
(1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
22.4
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
10.2
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
10.2
—
ns
td(CLKL-NWEL)
EXMC_CLK low to EXMC_NWE low
0
—
ns
td(CLKH-NWEH)
EXMC_CLK high to EXMC_NWE high
10.2
—
ns
td(CLKL-ADIV)
EXMC_CLK low to EXMC_AD invalid
0
—
ns
td(CLKL-DATA)
EXMC_A/D valid data after EXMC_CLK low
0
—
ns
th(CLKL-NBLH)
EXMC_CLK low to EXMC_NBL high
0
—
ns
(1)
(2)
(3)
(4)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: fHCLK = 180 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst = Enable;
CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
70
GD32EPRTxx Datasheet
Table 4-49. Synchronous non-multiplexed PSRAM/NOR read timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
22.4
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
10.2
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
10.2
—
ns
td(CLKL-NOEL)
EXMC_CLK low to EXMC_NOE low
0
—
ns
td(CLKH-NOEH)
EXMC_CLK high to EXMC_NOE high
10.2
—
ns
(1)
(2)
(3)
(4)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: HCLK=180 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst =
Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
Table 4-50. Synchronous non-multiplexed PSRAM write timings (1)(2)(3)(4)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
EXMC_CLK period
22.4
—
ns
td(CLKL-NExL)
EXMC_CLK low to EXMC_NEx low
0
—
ns
td(CLKH-NExH)
EXMC_CLK high to EXMC_NEx high
10.2
—
ns
td(CLKL-NADVL)
EXMC_CLK low to EXMC_NADV low
0
—
ns
td(CLKL-NADVH)
EXMC_CLK low to EXMC_NADV high
0
—
ns
td(CLKL-AV)
EXMC_CLK low to EXMC_Ax valid
0
—
ns
td(CLKH-AIV)
EXMC_CLK high to EXMC_Ax invalid
10.2
—
ns
td(CLKL-NWEL)
EXMC_CLK low to EXMC_NWE low
0
—
ns
td(CLKH-NWEH)
EXMC_CLK high to EXMC_NWE high
10.2
—
ns
td(CLKL-DATA)
EXMC_A/D valid data after EXMC_CLK low
0
—
ns
th(CLKL-NBLH)
EXMC_CLK low to EXMC_NBL high
0
—
ns
(1)
(2)
(3)
(4)
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Based on configure: HCLK = 180 MHz, BurstAccessMode = Enable; MemoryType = PSRAM; WriteBurst =
Enable; CLKDivision = 3 (EXMC_CLK is 4 divided by HCLK); DataLatency = 1.
71
GD32EPRTxx Datasheet
4.22.
Serial/Quad Parallel Interface (SQPI) characteristics
Table 4-51.SQPI characteristics
Symbol
Parameter
Min
Typ
Max
Unit
CLK period
11.0(4)
—
—
ns
CLK high level duty for even clock divided
45
50
55
CLK high level duty for odd clock divided
45
—
71
tKHKL(3)
CLK rise or fall time
—
—
tCPH(2)
CE# high between subsequent burst operations
22.2
—
—
ns
tCEM(2)
CE# low pulse width
88.8
—
—
ns
tCSP(2)
CE# setup time to CLK rising edge
5.5
—
177.7
ns
tCHD(2)
CE# hold time from CLK rising edge
5.5
—
177.7
ns
tSP(2)
Setup time to active CLK edge
5.5
—
177.7
ns
tHD(2)
Hold time from active CLK edge
5.5
—
177.7
ns
CE# rise to data output high-Z
—
0
—
ns
CLK fall to data output valid delay
—
0
—
ns
Data hold time from CLK falling edge
—
0
—
ns
tCLK(2)
tCD(2)
tHZ
(2)
tACLK(2)
(2)
tKOH
(1)
(2)
(3)
(4)
4.23.
%
ns
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Output driven mode is 50 MHz.
This is designed minimal period. The operating minimal clock period is 22.2 ns(45 MHz = 180 MHz/4).
TIMER characteristics
Table 4-52. TIMER characteristics (1)
Symbol
Parameter
tres
Timer resolution time
fEXT
Conditions
Min
Max
Unit
—
1
—
tTIMERxCLK
fTIMERxCLK = 180 MHz
5.6
—
ns
Timer external clock
—
0
fTIMERxCLK/2
MHz
frequency
fTIMERxCLK = 180 MHz
0
90
MHz
—
16
TIMER1
—
32
—
1
65536
tTIMERxCLK
fTIMERxCLK = 180 MHz
0.0056
367
μs
—
—
fTIMERxCLK = 180 MHz
—
TIMERx (except
RES
TIMER1)
Timer resolution
16-bit counter clock period
tCOUNTER
when internal clock is
selected
tMAX_COUNT
Maximum possible count
bit
65536x65536 tTIMERxCLK
24.1
s
(1) Guaranteed by design, not tested in production.
72
GD32EPRTxx Datasheet
4.24.
WDGT characteristics
Table 4-53. FWDGT min/max timeout period at 40 kHz (IRC40K)
Prescaler divider
PR[2:0] bits
1/4
(1)
Min timeout RLD[11:0] = Max timeout RLD[11:0]
0x000
= 0xFFF
000
0.1
409.6
1/8
001
0.2
819.2
1/16
010
0.4
1638.4
1/32
011
0.8
3276.8
1/64
100
1.6
6553.6
1/128
101
3.2
13107.2
1/256
110 or 111
6.4
26214.4
Unit
ms
(1) Guaranteed by design, not tested in production.
Table 4-54. WWDGT min-max timeout value at 90 MHz (fPCLK1) (1)
Min timeout value
Prescaler divider
PSC[2:0]
1/1
00
45.5
1/2
01
91.0
1/4
10
182.0
1/8
11
364.1
CNT[6:0] = 0x40
Unit
Max timeout value
CNT[6:0] = 0x7F
Unit
2.91
μs
5.83
11.65
ms
23.30
(1) Guaranteed by design, not tested in production.
4.25.
Parameter condition
Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 °C.
73
GD32EPRTxx Datasheet
5.
Package information
5.1.
LQFP100 package outline dimensions
Figure 5-1. LQFP100 package outline
Table 5-1. LQFP100 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
D
15.80
16.0
16.20
D1
13.90
14.0
14.10
E
15.80
16.0
16.20
E1
13.90
14.0
14.10
θ
0°
3.5°
7°
c
0.13
—
0.17
c1
0.12
0.13
0.14
L
0.45
0.6
0.75
L1
—
1.0 REF
—
b
0.18
0.20
0.26
b1
0.17
0.20
0.23
eB
15.05
—
15.35
e
—
0.50 BSC
—
74
GD32EPRTxx Datasheet
(Original dimensions are in millimeters)
5.2.
LQFP64 package outline dimensions
Figure 5-2. LQFP64 package outline
Table 5-2. LQFP64 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
D
11.80
12.00
12.20
D1
9.90
10.00
10.10
E
11.80
12.00
12.20
E1
9.90
10.00
10.10
θ
0°
3.5°
7°
c
0.13
—
0.17
L
0.45
0.60
0.75
L1
—
1.00 REF
—
b
0.17
0.20
0.27
e
—
0.50 BSC
—
eB
11.25
—
11.45
(Original dimensions are in millimeters)
75
GD32EPRTxx Datasheet
6.
Ordering information
Table 6-1. Part ordering code for GD32EPRTxx devices
Ordering code
GD32EPRTRDT
6
GD32EPRTVDT
6
Flash
384 KB
384 KB
SRAM
96 KB + 4 MB
PSRAM
96 KB + 4 MB
PSRAM
Package
Package type
LQFP64
Green
LQFP100
Green
Temperature
operating range
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
76
GD32EPRTxx Datasheet
7.
Revision history
Table 7-1. Revision history
Revision No.
Description
Date
1.0
Initial Release
Jun.17, 2020
77
GD32EPRTxx Datasheet
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