GigaDevice Semiconductor Inc.
GD32W515xx
Arm® Cortex®-M33 32-bit MCU
Datasheet
Revision 1.1
(Jul. 2022)
GD32W515xx Datasheet
Table of Contents
Table of Contents ..................................................................................................... 1
List of Figures .......................................................................................................... 4
List of Tables ............................................................................................................ 5
1. General description ........................................................................................... 7
2. Device overview ................................................................................................. 8
2.1.
Device information ................................................................................................ 8
2.2.
Block diagram ........................................................................................................ 9
2.3.
Pinouts and pin assignment ............................................................................... 10
2.4.
Memory map ........................................................................................................ 12
2.5.
Clock tree ............................................................................................................. 16
2.6.
Pin definitions ...................................................................................................... 18
2.6.1.
GD32W515Px QFN56 pin definitions ............................................................................. 18
2.6.2.
GD32W515Tx QFN36 pin definitions ............................................................................. 23
2.6.3.
GD32W515xx pin alternate functions ............................................................................. 26
3. Functional description..................................................................................... 29
3.1.
Arm® Cortex®-M33 core ....................................................................................... 29
3.2.
On-chip memory .................................................................................................. 29
3.3.
Clock, reset and supply management ................................................................ 30
3.4.
Boot modes.......................................................................................................... 30
3.5.
Power saving modes ........................................................................................... 32
3.6.
Electronic fuse (EFUSE) ...................................................................................... 33
3.7.
Instruction cache (ICACHE) ................................................................................ 33
3.8.
General-purpose inputs / outputs (GPIOs) ........................................................ 34
3.9.
TrustZone protection controller union (TZPCU) ................................................ 34
3.10.
CRC calculation unit (CRC) ............................................................................. 35
3.11.
True Random number generator (TRNG) ....................................................... 35
3.12.
Direct memory access controller (DMA)......................................................... 35
3.13.
Analog to digital converter (ADC) ................................................................... 36
3.14.
Real time clock (RTC) ...................................................................................... 36
3.15.
Timers and PWM generation ........................................................................... 37
1
GD32W515xx Datasheet
3.16.
Universal synchronous asynchronous receiver transmitter (USART) ......... 38
3.17.
Inter-integrated circuit (I2C) ............................................................................ 38
3.18.
Serial peripheral interface (SPI) ...................................................................... 39
3.19.
Inter-IC sound (I2S) .......................................................................................... 39
3.20.
Serial / Quad Parallel Interface (SQPI) ............................................................ 39
3.21.
Quad-SPI interface (QSPI) ............................................................................... 40
3.22.
Secure digital input and output card interface (SDIO) ................................... 40
3.23.
Universal serial bus full-speed interface (USBFS) ......................................... 40
3.24.
Digital camera interface (DCI) ......................................................................... 40
3.25.
Touch sensing interface (TSI) ......................................................................... 41
3.26.
Cryptographic acceleration Unit (CAU) .......................................................... 41
3.27.
Hash acceleration unit (HAU) .......................................................................... 41
3.28.
Public Key Cryptographic Acceleration Unit (PKCAU) .................................. 42
3.29.
High-Performance Digital Filter (HPDF) .......................................................... 42
3.30.
Infrared ray port (IFRP) .................................................................................... 43
3.31.
Wi-Fi .................................................................................................................. 43
3.31.1.
Standards Supported ..................................................................................................... 43
3.31.2.
Wi-Fi MAC ...................................................................................................................... 43
3.31.3.
Wi-Fi PHY ....................................................................................................................... 44
3.31.4.
Wi-Fi Radio ..................................................................................................................... 44
3.32.
Debug mode ..................................................................................................... 44
3.33.
Package and operation temperature............................................................... 44
4. Electrical characteristics ................................................................................. 45
4.1.
Absolute maximum ratings ................................................................................. 45
4.2.
Operating conditions characteristics ................................................................. 45
4.3.
Power consumption ............................................................................................ 47
4.4.
EMC characteristics ............................................................................................ 54
4.5.
Power supply supervisor characteristics .......................................................... 54
4.6.
Electrical sensitivity ............................................................................................ 55
4.7.
External clock characteristics ............................................................................ 56
4.8.
Internal clock characteristics ............................................................................. 58
4.9.
PLL characteristics ............................................................................................. 59
4.10.
Memory characteristics ................................................................................... 60
2
GD32W515xx Datasheet
4.11.
NRST pin characteristics ................................................................................. 60
4.12.
GPIO characteristics ........................................................................................ 61
4.13.
ADC characteristics ......................................................................................... 64
4.14.
Temperature sensor characteristics ............................................................... 65
4.15.
I2C characteristics ........................................................................................... 66
4.16.
SPI characteristics ........................................................................................... 67
4.17.
I2S characteristics ........................................................................................... 68
4.18.
USART characteristics..................................................................................... 70
4.19.
SDIO characteristics ........................................................................................ 71
4.20.
USBFS characteristics ..................................................................................... 71
4.21.
TIMER characteristics ...................................................................................... 72
4.22.
WDGT characteristics ...................................................................................... 73
4.23.
HPDF Characteristics....................................................................................... 73
4.24.
Serial / Quad Parallel Interface (SQPI) Characteristics .................................. 75
4.25.
Wi-Fi Radio characteristics ............................................................................. 75
4.26.
Parameter conditions....................................................................................... 77
5. Package information ........................................................................................ 78
5.1.
QFN56 package outline dimensions .................................................................. 78
5.2.
QFN36 package outline dimensions .................................................................. 80
5.3.
Thermal characteristics ...................................................................................... 82
6. Ordering information ....................................................................................... 84
7. Revision history ............................................................................................... 85
3
GD32W515xx Datasheet
List of Figures
Figure 2-1. GD32W515xx block diagram ............................................................................................. 9
Figure 2-2. GD32W515Px QFN56 pinouts ......................................................................................... 10
Figure 2-3. GD32W515Tx QFN36 pinouts ......................................................................................... 11
Figure 2-4. GD32W515xx clock tree .................................................................................................. 16
Figure 4-1. Recommended power supply decoupling capacitors (1)(2)(3) ......................................... 46
Figure 4-2. Recommended external NRST pin circuit(1) .................................................................. 61
Figure 4-3. I/O port AC characteristics definition ............................................................................ 64
Figure 4-4. I2C bus timing diagram ................................................................................................... 67
Figure 4-5. SPI timing diagram - master mode ................................................................................ 68
Figure 4-6. SPI timing diagram - slave mode ................................................................................... 68
Figure 4-7. I2S timing diagram - master mode ................................................................................. 69
Figure 4-8. I2S timing diagram - slave mode .................................................................................... 70
Figure 4-9. USBFS timings: definition of data signal rise and fall time ........................................ 72
Figure 5-1. QFN56 package outline ................................................................................................... 78
Figure 5-2. QFN56 recommended footprint ...................................................................................... 79
Figure 5-3. QFN36 package outline ................................................................................................... 80
Figure 5-4. QFN36 recommended footprint ...................................................................................... 81
4
GD32W515xx Datasheet
List of Tables
Table 2-1. GD32W515xx devices features and peripheral list .......................................................... 8
Table 2-2. GD32W515xx memory map .............................................................................................. 12
Table 2-3. GD32W515Px QFN56 pin definitions ............................................................................... 18
Table 2-4. GD32W515Tx QFN36 pin definitions ............................................................................... 23
Table 2-5. Port A alternate functions summary ............................................................................... 26
Table 2-6. Port B alternate functions summary ............................................................................... 27
Table 2-7. Port C alternate functions summary ............................................................................... 28
Table 3-1. BOOT0 modes.................................................................................................................... 31
Table 3-2. BOOT1 modes.................................................................................................................... 31
Table 3-3. Boot address modes when TrustZone is disabled (TZEN=0) ....................................... 31
Table 3-4. Boot modes when TrustZone is enabled (TZEN=1) ....................................................... 31
Table 4-1. Absolute maximum ratings (1)(4) ....................................................................................... 45
Table 4-2. DC operating conditions ................................................................................................... 45
Table 4-3. Clock frequency (1) ............................................................................................................. 46
Table 4-4. Operating conditions at Power up / Power down
Table 4-5. Start-up timings of Operating conditions
(1)(2)(3)
....................................................... 46
(1)
............................................................. 47
Table 4-6. Power saving mode wakeup timings characteristics (1)(2) ............................................. 47
Table 4-7. Wi-Fi Power consumption characteristics ...................................................................... 47
Table 4-8. Wi-Fi Power consumption characteristics(1)(2)(3) ............................................................. 47
Table 4-9. Power consumption characteristics (2)(3)(4)(5)(6) ................................................................ 48
Table 4-10. EMS characteristics (1) .................................................................................................... 54
Table 4-11. Power supply supervisor characteristics ..................................................................... 54
Table 4-12. ESD characteristics (1) ..................................................................................................... 56
Table 4-13. Static latch-up characteristics (1) ................................................................................... 56
Table 4-14. High speed external clock (HXTAL) generated from a crystal / ceramic
characteristics ..................................................................................................................................... 56
Table 4-15. High speed external user clock characteristics (HXTAL in bypass mode) ............... 56
Table 4-16. Low speed external clock (LXTAL) generated from a crystal / ceramic
characteristics ..................................................................................................................................... 57
Table 4-17. Low speed external user clock characteristics (LXTAL in bypass mode) ................ 57
Table 4-18. High speed internal clock (IRC16M) characteristics.................................................... 58
Table 4-19. Low speed internal clock (IRC32K) characteristics ..................................................... 58
Table 4-20. PLL characteristics ......................................................................................................... 59
Table 4-21. PLLDIG characteristics ................................................................................................... 59
Table 4-22. PLLI2S characteristics .................................................................................................... 59
Table 4-23. Flash memory characteristics........................................................................................ 60
Table 4-24. NRST pin characteristics ................................................................................................ 60
Table 4-25. I/O port DC characteristics (1)(3) ...................................................................................... 61
Table 4-26. I/O port AC characteristics (1)(2) ...................................................................................... 63
Table 4-27. ADC characteristics ........................................................................................................ 64
5
GD32W515xx Datasheet
Table 4-28. ADC RAIN max for fADC = 35 MHz
(1)
................................................................................. 64
Table 4-29. ADC dynamic accuracy at fADC = 35 MHz (1) .................................................................. 65
Table 4-30. ADC static accuracy at fADC = 35 MHz............................................................................ 65
Table 4-31. Temperature sensor characteristics (1) .......................................................................... 65
Table 4-32. I2C characteristics (1)(2)(3) ................................................................................................. 66
Table 4-33. Standard SPI characteristics (1) ...................................................................................... 67
Table 4-34. I2S characteristics (1) ....................................................................................................... 68
Table 4-35. USART characteristics (1) ................................................................................................ 70
Table 4-36. SDIO characteristics (1)(2) ................................................................................................. 71
Table 4-37. USBFS start up time ........................................................................................................ 71
Table 4-38. USBFS DC electrical characteristics ............................................................................. 72
Table 4-39. USBFS full speed-electrical characteristics (1) ............................................................. 72
Table 4-40. TIMER characteristics (1) ................................................................................................. 72
Table 4-41. FWDGT min/max timeout period at 32 kHz (IRC32K) (1) ............................................... 73
Table 4-42. WWDGT min-max timeout value at 45 MHz (fPCLK1) (1) .................................................. 73
Table 4-43. HPDF characteristics (1)(2)................................................................................................ 73
Table 4-44. SQPI characteristics ....................................................................................................... 75
Table 4-45. Transmitter power characteristics (1)(2) .......................................................................... 75
Table 4-46. Receiver sensitivity characteristics (1) .......................................................................... 75
Table 4-47. Rx Maximum Input Level (1)(2) ......................................................................................... 76
Table 4-48. Adjacent Channel Rejection
(1)(4)
.................................................................................... 77
Table 5-1. QFN56 package dimensions ............................................................................................ 78
Table 5-2. QFN36 package dimensions ............................................................................................ 80
Table 5-3. Package thermal characteristics(1) .................................................................................. 82
Table 6-1. Part ordering code for GD32W515xx devices ................................................................ 84
Table 7-1. Revision history................................................................................................................. 85
6
GD32W515xx Datasheet
1.
General description
The GD32W515xx is a highly integrated 2.4GHz Wi-Fi System-on-Chip (SoC) that
includes an ARM Cortex®-M33 processor with Trustzone, a single stream IEEE
802.11b/g/n MAC/baseband/radio, a power amplifier (PA), and a receive low-noise
amplifier (LNA). It is an optimized SoC designed for a broad array of smart devices for
Internet of Things (IoT) applications. The Cortex®-M33 processor is a 32-bit processor
that possesses low interrupt latency and low-cost debug. The Cortex®-M33 processor is
a 32-bit processor that possesses low interrupt latency and low-cost debug. The
characteristics of integrated and advanced make the Cortex®-M33 processor suitable for
market products that require microcontrollers with high performance and low power
consumption. The Cortex®-M33 processor is based on the ARMv8 architecture and
supports a powerful and scalable instruction set including general data processing I/O
control tasks, advanced data processing bit field manipulations and DSP.
The GD32W515xx device incorporates the Arm® Cortex®-M33 32-bit processor core
operating at up to 180 MHz frequency to obtain maximum efficiency. It provides up to
2048 KB on-chip Flash memory or support up to 32MB of EXT Flash memory and up to
448 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected
to two APB buses. The devices offer a 12-bit ADC, up to four general 16-bit timers, two
general 32-bit timers, one basic timer, one PWM advanced timer, as well as standard
and advanced communication interfaces: up to two SPIs, a SQPI, a SDIO, two I2Cs,
three USARTs, one I2S, an USBFS and a Wi-Fi. Additional peripherals as TrustZone
protection controller union (TZPCU), digital camera interface (DCI), touch sensing
interface (TSI), high-performance digital filter (HPDF), quad-SPI interface (QSPI) are
included.
The device operates from a 1.62 to 3.63 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32W515xx devices suitable for a wide range of
applications, especially in areas such as industrial control, motor drives, user interface,
power monitor and alarm systems, consumer and handheld equipment, gaming and GPS,
E-bike, optical module and so on.
7
GD32W515xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32W515xx devices features and peripheral list
Part Number
GD32W515xx
P0
TI
TG
FLASH (KB)
2048
0
2048
1024
SRAM (KB)
448
448
448
384
Timers
PI
General
4
4
3
3
timer(16-bit)
(3-4,15-16)
(3-4,15-16)
(4,15-16)
(4,15-16)
General
2
2
2
2
timer(32-bit)
(1-2)
(1-2)
(1-2)
(1-2)
Advanced
1
1
1
1
timer(16-bit)
(0)
(0)
(0)
(0)
SysTick
1
1
1
1
Basic
1
1
1
1
timer(16-bit)
(5)
(5)
(5)
(5)
Watchdog
2
2
2
2
RTC
1
1
1
1
USART
Connectivity
I2C
3
3
3
(0-2)
(0-2)
(0-2)
2
2
2
2
(0-1)
(0-1)
(0-1)
(0-1)
2/1
2/1
2/1
2/1
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
(0-1)/(1)
SDIO
1
1
1
1
QSPI
1
1
1
1
SQPI
1
1
1
1
USBFS
1
1
1
1
Wi-Fi
1
1
1
1
GPIO
43
43
25
25
HPDF
1
1
0
0
DCI
1
1
0
0
12
12
7
7
1
1
1
1
Units
1
1
1
1
Channels
9
9
5
5
SPI/I2S
TSI
(Channels)
TZGPC
ADC
3
(0-2)
Package
QFN56
QFN36
8
GD32W515xx Datasheet
2.2.
Block diagram
Figure 2-1. GD32W515xx block diagram
POR/ PDR
SW/JTAG
TPIU
NVIC
Code System
Arm Cortex-M33
Processor
Fmax:180MHz
Cbus
Icache
Flash
Memory
CRC
EFUSE
PLL
Slave
F max : 180MHz
AHB1:Fmax=180MHz
TSI
GPIO
TZSPC
DCI
CAU
TZIAC
USBFS
RCU
Master
P
M
P
Master
Master
Master
AHB Matrix
M
GP DMA1 8 chs
SRAM
Master
Master
GP DMA0 8 chs
SRAM
Controller
Flash
Memory
Controller
Slave
TRNG
PKCAU
IRC
16 MHz
Slave
AHB2:Fmax=180MHz
Master
Slave
Slave
QSPI
TZBMPCX
TZMPB
HAU
AHB3:Fmax=180MHz
TZWMMPC1
LDO
1.2V
HXTAL
20-52MHz
TZWMMPC2
SQPI
LVD
WIFI
RF
PHY
MAC
Master
Slave
AHB to APB
Bridge
AHB to APB
Bridge
Powered By VDDA
Interrput request
USART2
12-bit
SAR ADC
Slave
WWDGT
Slave
SPI0
FWDGT
ADC
PMU
EXTI
SPI1/I2S1
Powered By V DDA
WIFI_RF
APB1: Fmax = 45MHZ
SDIO
APB2: Fmax = 90MHz
HPDF
USART0~1
I2C0
I2C1
SYSCFG
I2S1_add
TIMER15
RTC
TIMER16
TIMER5
TIMER0
TIMER1~4
9
GD32W515xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32W515Px QFN56 pinouts
PB14
VDD
PB15
PA8
PA9
PA10
PA11
PA12-WKUP3
PB3
PB4
PC6
PC7
PB6
PB5
PB7
1
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
PB8
2
41
PB9
PC8-BOOT0
3
40
PA15-WKUP1
PA13
PA14
PC14-OSC32IN
PC15-OSC32OUT
4
5
6
7
8
9
PB12
PB11
PB10
PB2-WKUP2
PB1
PB0
34
PC5
PC4
33
32
PA7
PA6
31
30
PA5
PA4
14
29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
PC3
VBAT
AVDD33_ANA
10
11
RF
12
13
NC
NC
39
38
37
36
35
GigaDevice
GD32W515Px
QFN56
PB13
GND
PC2
PC0
PC1
PA2-WKUP0
PA3
PA1
PA0
VDDA
XTAL2
XTAL1
AVDD33_CLK
PU
AVDD33_PA
NRST
10
GD32W515xx Datasheet
Figure 2-3. GD32W515Tx QFN36 pinouts
VDD
PB15
PA8
PA9
PC14-OSC32IN
PC15-OSC32OUT
PA10
PA13
PA14
PA11
PA15-WKUP1
2
PA12-WKUP3
1
PB3
PB4
PC8-BOOT0
36 35 34 33 32 31 30 29 28
27
PB13
26
PB12
25
PB11
24
PA7
23
PA6
22
PA5
21
PA4
20
PA3
GigaDevice
GD32W515Tx
QFN36
3
4
5
6
GND
AVDD33_ANA
7
RF
8
NC
19
9
10 11 12 13 14 15 16 17 18
PA2-WKUP0
PA1
PA0
VDDA
XTAL2
XTAL1
AVDD33_CLK
AVDD33_PA
PU
NRST
11
GD32W515xx Datasheet
2.4.
Memory map
Table 2-2. GD32W515xx memory map
Pre-defined
Regions
Bus
-
External
device
Secure
Non-Secure
boundary address
boundary address
Peripherals
-
0xE000 1000 - 0xE00F FFFF
Cortex M33 internal peripherals
-
0x9800 0000 - 0xDFFF FFFF
Reserved
-
0x9000 0000 - 0x97FF FFFF
QSPI_FLASH(MEM)
-
0x6800 0000 - 0x8FFF FFFF
Reserved
-
0x6000 0000 - 0x67FF FFFF
SQPI_PSRAM(MEM)
0x5C06 3000 - 0x5FFF FFFF
0x4C06 3000 - 0x4FFF FFFF
Reserved
0x5C06 1000 - 0x5C06 2FFF
0x4C06 1000 - 0x4C06 2FFF
PKCAU
0x5C06 0C00 - 0x5C06 0FFF
0x4C06 0C00 - 0x4C06 0FFF
Reserved
0x5C06 0800 - 0x5C06 0BFF
0x4C06 0800 - 0x4C06 0BFF
TRNG
0x5C06 0400 - 0x5C06 07FF
0x4C06 0400 - 0x4C06 07FF
HAU
0x5C06 0000 - 0x5C06 03FF
0x4C06 0000 - 0x4C06 03FF
CAU
0x5C05 0400 - 0x5C05 FFFF
0x4C05 0400 - 0x4C05 FFFF
Reserved
0x5C05 0000 - 0x5C05 03FF
0x4C05 0000 - 0x4C05 03FF
DCI
0x5C04 0000 - 0x5C04 FFFF
0x4C04 0000 - 0x4C04 FFFF
Reserved
0x5C00 0000 - 0x5C03 FFFF
0x4C00 0000 - 0x4C03 FFFF
Reserved
0x5904 0000 - 0x5BFF FFFF
0x4904 0000 - 0x4BFF FFFF
Reserved
0x5900 0000 - 0x5903 FFFF
0x4900 0000 - 0x4903 FFFF
USBFS
0x500B 1000 - 0x58FF FFFF
0x400B 1000 - 0x48FF FFFF
Reserved
0x500B 0800 - 0x500B 0FFF
0x400B 0800 - 0x400B 0FFF
Reserved
0x500B 0400 - 0x500B 07FF
0x400B 0400 - 0x400B 07FF
TZBMPC3
0x500B 0000 - 0x500B 03FF
0x400B 0000 - 0x400B 03FF
TZBMPC2
0x500A 1000 - 0x500A FFFF
0x400A 1000 - 0x400A FFFF
Reserved
0x500A 0C00 - 0x500A 0FFF
0x400A 0C00 - 0x400A 0FFF
TZBMPC1
0x500A 0800 - 0x500A 0BFF
0x400A 0800 - 0x400A 0BFF
TZBMPC0
0x500A 0400 - 0x500A 07FF
0x400A 0400 - 0x400A 07FF
TZIAC
0x500A 0000 - 0x500A 03FF
0x400A 0000 - 0x400A 03FF
TZSPC
0x5008 0400 - 0x5009 FFFF
0x4008 0400 - 0x4009 FFFF
Reserved
0x5008 0000 - 0x5008 03FF
0x4008 0000 - 0x4008 03FF
ICACHE
0x5003 3000 - 0x5007 FFFF
0x4003 3000 - 0x4007 FFFF
Reserved
0x5003 0000 - 0x5003 2FFF
0x4003 0000 - 0x4003 2FFF
Wi-Fi
0x5002 BC00 - 0x5002 FFFF
0x4002 BC00 - 0x4002 FFFF
Reserved
0x5002 B000 - 0x5002 BBFF
0x4002 B000 - 0x4002 BBFF
Reserved
0x5002 A000 - 0x5002 AFFF
0x4002 A000 - 0x4002 AFFF
Reserved
0x5002 8000 - 0x5002 9FFF
0x4002 8000 - 0x4002 9FFF
Reserved
0x5002 6800 - 0x5002 7FFF
0x4002 6800 - 0x4002 7FFF
Reserved
0x5002 6400 - 0x5002 67FF
0x4002 6400 - 0x4002 67FF
DMA1
0x5002 6000 - 0x5002 63FF
0x4002 6000 - 0x4002 63FF
DMA0
AHB3
AHB2
Peripheral
AHB1
12
GD32W515xx Datasheet
Pre-defined
Regions
Bus
APB2
Secure
Non-Secure
boundary address
boundary address
Peripherals
0x5002 5C00 - 0x5002 5FFF
0x4002 5C00 - 0x4002 5FFF
Reserved
0x5002 5800 - 0x5002 5BFF
0x4002 5800 - 0x4002 5BFF
QSPI_FLASH(REG)
0x5002 5400 - 0x5002 57FF
0x4002 5400 - 0x4002 57FF
SQPI_PSRAM(REG)
0x5002 5000 - 0x5002 53FF
0x4002 5000 - 0x4002 53FF
Reserved
0x5002 4000 - 0x5002 4FFF
0x4002 4000 - 0x4002 4FFF
TSI
0x5002 3C00 - 0x5002 3FFF
0x4002 3C00 - 0x4002 3FFF
Reserved
0x5002 3800 - 0x5002 3BFF
0x4002 3800 - 0x4002 3BFF
RCU
0x5002 3400 - 0x5002 37FF
0x4002 3400 - 0x4002 37FF
Reserved
0x5002 3000 - 0x5002 33FF
0x4002 3000 - 0x4002 33FF
CRC
0x5002 2C00 - 0x5002 2FFF
0x4002 2C00 - 0x4002 2FFF
Reserved
0x5002 2800 - 0x5002 2BFF
0x4002 2800 - 0x4002 2BFF
EFUSE
0x5002 2400 - 0x5002 27FF
0x4002 2400 - 0x4002 27FF
Reserved
0x5002 2000 - 0x5002 23FF
0x4002 2000 - 0x4002 23FF
FMC
0x5002 1C00 - 0x5002 1FFF
0x4002 1C00 - 0x4002 1FFF
Reserved
0x5002 1800 - 0x5002 1BFF
0x4002 1800 - 0x4002 1BFF
Reserved
0x5002 1400 - 0x5002 17FF
0x4002 1400 - 0x4002 17FF
Reserved
0x5002 1000 - 0x5002 13FF
0x4002 1000 - 0x4002 13FF
Reserved
0x5002 0C00 - 0x5002 0FFF
0x4002 0C00 - 0x4002 0FFF
Reserved
0x5002 0800 - 0x5002 0BFF
0x4002 0800 - 0x4002 0BFF
GPIOC
0x5002 0400 - 0x5002 07FF
0x4002 0400 - 0x4002 07FF
GPIOB
0x5002 0000 - 0x5002 03FF
0x4002 0000 - 0x4002 03FF
GPIOA
0x5001 8800 - 0x5001 FFFF
0x4001 8800 - 0x4001 FFFF
Reserved
0x5001 8400 - 0x5001 87FF
0x4001 8400 - 0x4001 87FF
TIMER16
0x5001 8000 - 0x5001 83FF
0x4001 8000 - 0x4001 83FF
TIMER15
0x5001 7C00 - 0x5001 7FFF
0x4001 7C00 - 0x4001 7FFF
Reserved
0x5001 7800 - 0x5001 7BFF
0x4001 7800 - 0x4001 7BFF
Wi-Fi_RF
0x5001 6800 - 0x5001 77FF
0x4001 6800 - 0x4001 77FF
Reserved
0x5001 6000 - 0x5001 67FF
0x4001 6000 - 0x4001 67FF
HPDF
0x5001 5800 - 0x5001 5FFF
0x4001 5800 - 0x4001 5FFF
Reserved
0x5001 5400 - 0x5001 57FF
0x4001 5400 - 0x4001 57FF
Reserved
0x5001 4C00 - 0x5001 53FF
0x4001 4C00 - 0x4001 53FF
Reserved
0x5001 4800 - 0x5001 4BFF
0x4001 4800 - 0x4001 4BFF
Reserved
0x5001 4400 - 0x5001 47FF
0x4001 4400 - 0x4001 47FF
Reserved
0x5001 4000 - 0x5001 43FF
0x4001 4000 - 0x4001 43FF
Reserved
0x5001 3C00 - 0x5001 3FFF
0x4001 3C00 - 0x4001 3FFF
EXTI
0x5001 3800 - 0x5001 3BFF
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x5001 3400 - 0x5001 37FF
0x4001 3400 - 0x4001 37FF
Reserved
0x5001 3000 - 0x5001 33FF
0x4001 3000 - 0x4001 33FF
SPI0
0x5001 2C00 - 0x5001 2FFF
0x4001 2C00 - 0x4001 2FFF
SDIO
0x5001 2400 - 0x5001 2BFF
0x4001 2400 - 0x4001 2BFF
Reserved
13
GD32W515xx Datasheet
Pre-defined
Regions
Bus
Secure
Non-Secure
boundary address
boundary address
0x5001 2000 - 0x5001 23FF
0x4001 2000 - 0x4001 23FF
ADC
0x5001 1400 - 0x5001 1FFF
0x4001 1400 - 0x4001 1FFF
Reserved
0x5001 1000 - 0x5001 13FF
0x4001 1000 - 0x4001 13FF
USART2
0x5001 0800 - 0x5001 0FFF
0x4001 0800 - 0x4001 0FFF
Reserved
0x5001 0400 - 0x5001 07FF
0x4001 0400 - 0x4001 07FF
Reserved
0x5001 0000 - 0x5001 03FF
0x4001 0000 - 0x4001 03FF
TIMER0
0x5000 7400 - 0x5000 FFFF
0x4000 D000 - 0x4000 FFFF
Reserved
0x5000 CC00 - 0x5000 CFFF
0x4000 CC00 - 0x4000 CFFF
Reserved
0x5000 7400 - 0x5000 CBFF
0x4000 7400 - 0x4000 CBFF
Reserved
0x5000 7000 - 0x5000 73FF
0x4000 7000 - 0x4000 73FF
PMU
0x5000 6C00 - 0x5000 6FFF
0x4000 6C00 - 0x4000 6FFF
Reserved
0x5000 5C00 - 0x5000 6BFF
0x4000 5C00 - 0x4000 6BFF
Reserved
0x5000 5800 - 0x5000 5BFF
0x4000 5800 - 0x4000 5BFF
I2C1
0x5000 5400 - 0x5000 57FF
0x4000 5400 - 0x4000 57FF
I2C0
0x5000 4C00 - 0x5000 53FF
0x4000 4C00 - 0x4000 53FF
Reserved
0x5000 4800 - 0x5000 4BFF
0x4000 4800 - 0x4000 4BFF
USART0
0x5000 4400 - 0x5000 47FF
0x4000 4400 - 0x4000 47FF
USART1
0x5000 4000 - 0x5000 43FF
0x4000 4000 - 0x4000 43FF
Reserved
0x5000 3C00 - 0x5000 3FFF
0x4000 3C00 - 0x4000 3FFF
Reserved
0x5000 3800 - 0x5000 3BFF
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x5000 3400 - 0x5000 37FF
0x4000 3400 - 0x4000 37FF
I2S1_add
0x5000 3000 - 0x5000 33FF
0x4000 3000 - 0x4000 33FF
FWDGT
0x5000 2C00 - 0x5000 2FFF
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x5000 2800 - 0x5000 2BFF
0x4000 2800 - 0x4000 2BFF
RTC
0x5000 2400 - 0x5000 27FF
0x4000 2400 - 0x4000 27FF
Reserved
0x5000 2000 - 0x5000 23FF
0x4000 2000 - 0x4000 23FF
Reserved
0x5000 1C00 - 0x5000 1FFF
0x4000 1C00 - 0x4000 1FFF
Reserved
0x5000 1800 - 0x5000 1BFF
0x4000 1800 - 0x4000 1BFF
Reserved
0x5000 1400 - 0x5000 17FF
0x4000 1400 - 0x4000 17FF
Reserved
0x5000 1000 - 0x5000 13FF
0x4000 1000 - 0x4000 13FF
TIMER5
0x5000 0C00 - 0x5000 0FFF
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x5000 0800 - 0x5000 0BFF
0x4000 0800 - 0x4000 0BFF
TIMER3
0x5000 0400 - 0x5000 07FF
0x4000 0400 - 0x4000 07FF
TIMER2
0x5000 0000 - 0x5000 03FF
0x4000 0000 - 0x4000 03FF
TIMER1
0x3007 0000 - 0x3FFF FFFF
0x2007 0000 - 0x2FFF FFFF
Reserved
0x3004 0000 - 0x2006 FFFF
0x2004 0000 - 0x2006 FFFF
SRAM3 (192KB)
0x3002 0000 - 0x3003 FFFF
0x2002 0000 - 0x2003 FFFF
SRAM2 (128KB)
0x3001 0000 - 0x3001 FFFF
0x2001 0000 - 0x2001 FFFF
SRAM1 (64KB)
0x3000 0000 - 0x3000 FFFF
0x2000 0000 - 0x2000 FFFF
SRAM0 (64KB)
-
0x1000 0000 - 0x1FFF FFFF
External memories remap
APB1
SRAM
Code
AHB
AHB
Peripherals
14
GD32W515xx Datasheet
Pre-defined
Regions
Bus
Secure
Non-Secure
boundary address
boundary address
Peripherals
-
0x0BFF 8000 - 0x0BFF FFFF
Reserved
0x0FF8 8000 - 0x0FFF FFFF
0x0BF8 0000 – 0x0BFF 7FFF
Reserved
0x0FF8 4000 – 0x0FF8 7FFF
-
ROM(16KB)
0x0FF8 0000 – 0x0FF8 3FFF
-
GSSA(16KB)
0x0FF4 E000 – 0x0FF7 FFFF
0x0BF4 E000 – 0x0BF7 FFFF
ROM(200KB)
-
0x0BF4 6000 – 0x0BF4 CFFF
Reserved
-
0x0BF4 0000 - 0x0BF4 5FFF
ROM(24KB)
0x0E07 0000 - 0x0FF4 DFFF
0x0A07 0000 - 0x0BF3 FFFF
Reserved
0x0E04 0000 - 0x0E06 FFFF
0x0A04 0000 - 0x0A06 FFFF
SRAM3 (192KB)
0x0E02 0000 - 0x0E03 FFFF
0x0A02 0000 - 0x0A03 FFFF
SRAM2 (128KB)
0x0E01 0000 - 0x0E01 FFFF
0x0A01 0000 - 0x0A01 FFFF
SRAM1 (64KB)
0x0E00 0000 - 0x0E00 FFFF
0x0A00 0000 - 0x0A00 FFFF
SRAM0 (64KB)
0x0C20 0000 - 0x0DFF FFFF
0x0820 0000 - 0x09FF FFFF
Reserved
0x0C00 0000 - 0x0C1F FFFF
0x0800 0000 - 0x081F FFFF
Flash memory
-
0x0000 0000 - 0x07FF FFFF
External memories remap
15
GD32W515xx Datasheet
2.5.
Clock tree
Figure 2-4. GD32W515xx clock tree
CK_HXTAL
/2 to /32
11
32.768 KHz
LXTAL OSC
CK_RTC
01
(to RTC)
10
RTCSRC[1:0]
CK_FWDGT
32 KHz
IRC32K
CK_OUT1
(to FWDGT)
00
01
10
11
CKOUT1DIV
÷1,2,3,4,5
CK_SYS
CK_PLLI2S
CK_HXTAL
CK_PLLDIG
CKOUT1SEL[1:0]
HCLK
(to AHB bus,CortexM33,SRAM,DMA,peripherals)
AHB enable
CK_OUT0
00
01
10
11
CKOUT0DIV
÷1,2,3,4,5
CK_IRC16M
CK_LXTAL
CK_HXTAL
CK_CST
÷8
(to Cortex-M33 SysTick)
FCLK
CK_PLLP
(free running clock)
APB1
Prescaler
÷4,8,16
FMC
CKOUT0SEL[1:0]
CK_APB1
IRC16
MDIV
16 MHz
IRC16M
Peripheral enable
CK_IRC16M
00
CK_HXTAL
01
CK_PLLP
10
CK_PLLDIG
CK_SYS
180 MHz max
AHB
Prescaler
÷1,2...512
CK_AHB
TIMER1,2,3,4,5
CK_APB1 x1
x2 or x4
TIMERx enable
APB2
Prescaler
÷2,4,8,16
90 MHz max
180 MHz max
CK_APB2
Clock
Monitor
TIMER0,15,16
CK_APB2 x1
x2 or x4
0
180 MHz max
TIMERx enable
1
CK_TIMERx
to TIMER0,15,16
ADCCK[2]
/PLLP
VCO
PCLK2
to APB2 peripherals
Peripheral enable
PLLSEL
/PSC
CK_TIMERx
to TIMER1,2,3,4,
5
180 MHz max
11
20-52 MHz
HXTAL
PCLK1
to APB1 peripherals
45 MHz max
SCS[1:0]
/DIGFS
YSDIV
xN
PLL
USBFSSEL
0
ADC
Prescaler
÷2,4,6,8
0
ADC
Prescaler
÷5,6,10,20
1
35 MHz max
/USBFSDIV
1
VCO
Peripheral enable
SDIOSEL
xN
PLLDIG
CK_IRC16M
CK_HXTAL
/PLLFI
2SDIV
CK_ADC to ADC
00
01
10
11
to USBFS/TRNG
CK_SDIO
/SDIODIV
Peripheral enable
to SDIO
CK160_WIFI
RFDIV
Peripheral enable
/PLLI2
SPSC
to WIFI11N
CK80_WIFI
÷2
Peripheral enable
to WIFI11N
CK40_WIFI
÷4
Peripheral enable
to WIFI11N
CK44DSM_WIFI
÷3.6
Peripheral enable
to WIFI11N
HPDFAUDIOS
EL[1:0]
/PLLI2SDIV
VCO
00
CK_HPDFAU
DIO
01
xN
10
PLLI2S
CK_IRC16M
HPDFSEL
11
I2SSEL[1:0]
CK_APB2
0
CK_SYS
1
Peripheral enable
to HPDFAUDIO
CK_HPDF
Peripheral enable
to HPDF
00
CK_I2S
01
Peripheral enable
10
USART0SEL[1:0]
CK_APB1
CK_SYS
CK_LXTAL
CK_IRC16M
00
01
10
11
to I2S
USART2SEL[1:0]
CK_USART0
to USART0
CK_APB2
CK_SYS
CK_LXTAL
CK_IRC16M
00
01
10
11
I2C0SEL[1:0]
CK_USART2
CK_APB1
CK_SYS
to USART2
CK_IRC16M
00
CK_I2C0
01
1x
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
16
GD32W515xx Datasheet
IRC16M: Internal 16M RC oscillator
IRC32K: Internal 32K RC oscillator
17
GD32W515xx Datasheet
2.6.
Pin definitions
2.6.1.
GD32W515Px QFN56 pin definitions
Table 2-3. GD32W515Px QFN56 pin definitions
Pin Name
Pins
PB7
1
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PB7
Alternate: I2S1_WS, SPI1_NSS, EVENTOUT,
TIMER3_CH1, I2C0_SDA, USART0_RX, DCI_VSYNC
Default: PB8
PB8
2
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, EVENTOUT,
TIMER3_CH2, SDIO_D4, DCI_D6
Default: PB9
PB9
3
I/O
5VT
Alternate: I2S1_SD, SPI1_MOSI, EVENTOUT,
TIMER1_CH1, TIMER3_CH3, SDIO_D5, DCI_D7
Default: PC8
PC8-BOOT0
4
I/O
5VT
Alternate: I2C0_SDA, USART0_TX, I2C1_SDA,
EVENTOUT, TIMER2_CH2, SDIO_D0, DCI_D2
Additional: BOOT0
Default: JTDI, PA15
PA15WKUP1
5
I/O
5VT
Alternate: I2C0_SCL, USART0_RX, I2C1_SCL,
EVENTOUT, SPI0_NSS
Additional: WKUP1
Default: JTMS, SWDIO, PA13
PA13
6
I/O
5VT
Alternate: USART0_CTS, USART1_CTS,
I2C0_SMBA, EVENTOUT, TSITG
Default: JTCK, SWCLK, PA14
Alternate: USART0_RTS / USART0_DE,
PA14
7
I/O
5VT
USART1_RTS / USART1_DE, I2C1_SMBA,
EVENTOUT
Additional: BOOT1
PC14OSC32IN
Default: PC14
8
I/O
5VT
Alternate: USART0_CK, USART1_CK, EVENTOUT
Additional: OSC32IN
Default: PC15
PC15OSC32OUT
9
I/O
5VT
Alternate: IFRP_OUT, EVENTOUT
Additional: RTC_TAMP0, RTC_OUT, RTC_TS,
OSC32OUT
VBAT
AVDD33_AN
A
RF
10
P
Default: VBAT
11
P
Default: AVDD33_ANA
12
AI/AO
Default: RF
18
GD32W515xx Datasheet
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
NC
13
-
NC
14
-
PU
15
I
NRST
16
I/O
AVDD33_PA
17
P
Default: AVDD33_PA
18
P
Default: AVDD33_CLK
XTAL1
19
AI
Default: XTAL1
XTAL2
20
AO
Default: XTAL2
VDDA
21
P
Default: VDDA
AVDD33_CL
K
Functions description
Default: PU
Default: NRST
Default: PA0
Alternate: USART0_TX, TSI_G0_IO0, USART1_CTS,
PA0
22
I/O
5VT
EVENTOUT, TIMER1_CH0, TIMER1_ETI,
TIMER4_CH0
Additional: ADC_IN0
Default: PA1
Alternate: USART0_RX, TSI_G0_IO1, USART1_RTS /
PA1
23
I/O
5VT
USART1_DE, EVENTOUT, TIMER1_CH1,
TIMER4_CH1
Additional: ADC_IN1
Default: PA2
Alternate: USART0_CK, TSI_G0_IO2, TIMER0_CH0,
PA2-WKUP0
24
I/O
5VT
EVENTOUT, TIMER1_CH2, TIMER4_CH2,
I2S1_CKIN, USART1_TX, HPDF_AUDIO
Additional: ADC_IN2, WKUP0, RTC_TAMP1
Default: PA3
Alternate: USART1_CK, TSI_G0_IO3,
PA3
25
I/O
5VT
TIMER0_CH0_ON,
HPDF_DATAIN1, EVENTOUT, TIMER1_CH3,
TIMER4_CH3, I2S1_MCK, USART1_RX, RTC_OUT
Additional: ADC_IN3
Default: PC0
PC0
26
I/O
5VT
Alternate: USART1_TX, TIMER0_CH3, I2C0_SMBA,
HPDF_CKIN0, EVENTOUT, DCI_D4
Additional: ADC_IN4
Default: PC1
Alternate: I2S1_SD, USART1_RX, DCI_HSYNC,
PC1
27
I/O
5VT
TIMER0_BRKIN, I2C1_SMBA, HPDF_CKIN1,
EVENTOUT, SPI1_MOSI, DCI_D8
Additional: ADC_IN5
PC2
28
I/O
5VT
Default: PC2
Alternate: HPDF_CKOUT, I2C1_SDA, I2C0_SCL,
19
GD32W515xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER4_CH0, TIMER0_CH0, DCI_VSYNC,
TIMER0_ETI, EVENTOUT, SPI1_MISO,
I2S1_ADD_SD, DCI_D9
Additional: ADC_IN6
Default: PC3
Alternate: I2S1_SD, HPDF_DATAIN0, I2C1_SCL,
PC3
29
I/O
5VT
I2C0_SDA, TIMER4_CH1, TIMER0_CH0_ON,
DCI_PIXCLK, TIMER1_CH0, TIMER1_ETI,
EVENTOUT, SPI1_MOSI, DCI_D11
Additional: ADC_IN7
Default: PA4
Alternate: I2S1_ADD_SD, SPI1_MOSI, I2S1_SD,
PA4
30
I/O
5VT
SPI0_MOSI, QSPI_SCK, TIMER4_CH2, DCI_HSYNC,
USART1_TX, TIMER0_CH1, EVENTOUT, SPI0_NSS,
USART1_CK
Additional: ADC_IN8
Default: PA5
PA5
31
I/O
5VT
Alternate: I2S1_MCK, SPI0_MISO, QSPI_CSN,
TIMER4_CH3, DCI_VSYNC, USART1_RX,
TIMER0_CH1_ON, EVENTOUT, SPI0_SCK
Default: PA6
Alternate: I2S1_CKIN, SPI0_SCK, QSPI_IO0,
PA6
32
I/O
5VT
TIMER2_CH0, DCI_PIXCLK, USART2_TX,
TIMER0_CH1, TIMER1_CH1,
EVENTOUT, SPI0_MISO, I2S1_MCK, SDIO_CMD,
HPDF_AUDIO
Default: PA7
Alternate: SPI1_NSS, I2S1_WS, SPI0_NSS,
PA7
33
I/O
5VT
QSPI_IO1, TIMER2_CH1, DCI_D7, USART2_RX,
TIMER0_CH1_ON,
TIMER1_CH2, EVENTOUT, TIMER0_CH0_ON,
SPI0_MOSI
Default: PC4
PC4
34
I/O
5VT
Alternate: I2S1_ADD_SD, SPI0_IO2, QSPI_IO2,
TIMER2_CH2, DCI_D6, EVENTOUT, SQPI_CLK,
DCI_D12
Default: PC5
PC5
35
I/O
5VT
Alternate: CK_OUT1, SPI0_IO3, QSPI_IO3,
TIMER2_CH3, TIMER2_CH0, DCI_D5, DCI_D7,
EVENTOUT, USART2_RX, SQPI_CSN, DCI_D13
Default: PB0
PB0
36
I/O
5VT
Alternate: TSI_G1_IO0, TIMER3_CH0, TIMER2_CH1,
DCI_D4, DCI_D6, EVENTOUT, TIMER0_CH1_ON,
20
GD32W515xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
SDIO_D1
Default: PB1
PB1
37
I/O
5VT
Alternate: TSI_G1_IO1, TIMER3_CH1, TIMER2_CH2,
DCI_D3, DCI_D5, EVENTOUT, TIMER0_CH2_ON,
SDIO_D2
Default: PB2
Alternate: TSI_G1_IO2, TIMER3_CH2, TIMER2_CH3,
PB2-WKUP2
38
I/O
5VT
DCI_D2, DCI_D4, EVENTOUT, TIMER1_CH3,
SDIO_CK
Additional: WKUP2
Default: PB10
PB10
39
I/O
5VT
Alternate: TSI_G1_IO3, TIMER3_CH3, TIMER0_CH1,
DCI_D1, DCI_D3, IFRP_OUT, EVENTOUT,
TIMER1_CH2, TIMER3_ETI, USART2_TX, SDIO_D7
Default: PB11
PB11
40
I/O
5VT
Alternate: USBFS_ID, TSI_G2_IO0,
TIMER0_CH1_ON, DCI_D0, DCI_D2, EVENTOUT,
I2S1_CKIN, USART2_RX, SDIO_D6
Default: PB12
PB12
41
I/O
5VT
Alternate: I2S1_WS, USBFS_DP, TSI_G2_IO1,
DCI_D1, TIMER0_CH3, EVENTOUT,
TIMER0_BRKIN, SPI1_NSS, USART2_CK
Default: PB13
PB13
42
I/O
5VT
Alternate: USBFS_DM, TSI_G2_IO2, DCI_D0,
EVENTOUT, TIMER15_CH0, TIMER0_CH0_ON,
SPI1_SCK, I2S1_CK, USART2_CTS
Default: PB14
Alternate: TSI_G2_IO3, EVENTOUT,
PB14
43
I/O
5VT
TIMER15_BRKIN, TIMER0_CH1_ON, SPI1_MISO,
I2S1_ADD_SD, USART2_RTS / USART2_DE
Additional: USBFS_VBUS
VDD
44
Default: VDD
P
Default: PB15
PB15
45
I/O
5VT
Alternate: I2S1_SD, USART1_TX, USART0_TX,
I2C0_SCL, I2C1_SCL, IFRP_OUT, EVENTOUT,
RTC_REFIN, TIMER0_CH2_ON, SPI1_MOSI
Default: PA8
Alternate: CK_OUT0, USART1_RX, USART0_RX,
PA8
46
I/O
5VT
I2C0_SDA, I2C1_SDA, EVENTOUT, TIMER15_CH0,
TIMER0_CH0, USART0_CK, USBFS_SOF, SDIO_D1,
RTC_OUT
PA9
47
I/O
5VT
Default: PA9
Alternate: SPI0_MOSI, SDIO_CMD, SQPI_CLK,
21
GD32W515xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
QSPI_SCK, EVENTOUT, TIMER15_CH0_ON,
TIMER0_CH1, SPI1_SCK, I2S1_CK, USART0_TX,
SDIO_D2, DCI_D0
Default: PA10
PA10
48
I/O
5VT
Alternate: SPI0_MISO, SDIO_D0, SQPI_CSN,
QSPI_CSN, EVENTOUT, TIMER16_CH0,
TIMER0_CH2, DCI_D1
Default: PA11
PA11
49
I/O
5VT
Alternate: SPI0_SCK, SDIO_CK, SQPI_D0,
QSPI_IO0, EVENTOUT, TIMER16_BRKIN,
TIMER0_CH3, DCI_D2
Default: PA12
PA12WKUP3
Alternate: SPI0_NSS, SDIO_D1, SQPI_D1, QSPI_IO1,
50
I/O
5VT
EVENTOUT, TIMER16_CH0_ON, TIMER0_ETI,
USART0_RTS / USART0_DE, DCI_D3
Additional: WKUP3
Default: JTDO, TRACESWO, PB3
PB3
51
I/O
5VT
Alternate: USART2_CTS, SPI0_IO2, SDIO_D2,
SQPI_D2, QSPI_IO2, EVENTOUT, TIMER15_BRKIN,
TIMER1_CH1, SPI0_SCK, USART0_RX
Default: NJTRST, PB4
PB4
52
I/O
5VT
Alternate: USART2_RTS / USART2_DE, SPI0_IO3,
SDIO_D3, SQPI_D3, QSPI_IO3, TIMER1_CH0,
TIMER1_ETI, EVENTOUT, SPI0_MISO
Default: PC6
PC6
53
I/O
5VT
Alternate: USART2_TX, TIMER1_CH1, TIMER0_CH1,
TIMER0_BRKIN, TRACECK, TIMER16_BRKIN,
TIMER2_CH0, I2S1_MCK, SDIO_D6, DCI_D0
Default: PC7
Alternate: USART2_RX, TIMER1_CH2,
PC7
54
I/O
5VT
TIMER0_CH1_ON, TIMER0_ETI, TIMER16_CH0,
TIMER2_CH1, SPI1_SCK, I2S1_CK, SDIO_D7,
DCI_D1
Default: PB5
PB5
55
I/O
5VT
Alternate: USART2_CK, TIMER1_CH3, IFRP_OUT,
EVENTOUT, TSITG, SPI0_MOSI, DCI_D10
Default: PB6
PB6
56
I/O
5VT
Alternate: SPI1_MISO, EVENTOUT,
DCI_D5
Note:
(1) Type: I = input, O = output, A = analog, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
22
GD32W515xx Datasheet
2.6.2.
GD32W515Tx QFN36 pin definitions
Table 2-4. GD32W515Tx QFN36 pin definitions
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PC8
PC8-BOOT0
1
I/O
5VT
Alternate: I2C0_SDA, USART0_TX, I2C1_SDA,
EVENTOUT, TIMER2_CH2, SDIO_D0
Additional: BOOT0
Default: JTDI, PA15
PA15WKUP1
2
I/O
5VT
Alternate:
I2C0_SCL,
USART0_RX,
I2C1_SCL,
EVENTOUT, SPI0_NSS
Additional: WKUP1
Default: JTMS, SWDIO, PA13
PA13
3
I/O
5VT
Alternate: USART0_CTS, USART1_CTS, I2C0_SMBA,
EVENTOUT, TSITG
Default: JTCK, SWCLK, PA14
PA14
4
I/O
5VT
Alternate: USART0_RTS / USART0_DE, USART1_RTS
/ USART1_DE, I2C1_SMBA, EVENTOUT
Additional: BOOT1
PC14OSC32IN
Default: PC14
5
I/O
5VT
Alternate: USART0_CK, USART1_CK, EVENTOUT
Additional: OSC32IN
Default: PC15
PC15OSC32OUT
6
I/O
5VT
Alternate: IFRP_OUT, EVENTOUT
Additional: RTC_TAMP0, RTC_OUT, RTC_TS,
OSC32OUT
AVDD33_AN
Default: AVDD33_ANA
7
P
RF
8
AI/AO
NC
9
PU
10
I
NRST
11
I/O
AVDD33_PA
12
P
Default: AVDD33_PA
13
P
Default: AVDD33_CLK
XTAL1
14
AI
Default: XTAL1
XTAL2
15
AO
Default: XTAL2
VDDA
16
P
Default: VDDA
A
AVDD33_CL
K
Default: RF
Default: PU
Default: NRST
Default: PA0
PA0
17
I/O
5VT
Alternate: USART0_TX, TSI_G0_IO0, USART1_CTS,
EVENTOUT, TIMER1_CH0, TIMER1_ETI,
TIMER4_CH0
23
GD32W515xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Additional: ADC_IN0
Default: PA1
Alternate: USART0_RX, TSI_G0_IO1, USART1_RTS /
PA1
18
I/O
5VT
USART1_DE, EVENTOUT, TIMER1_CH1,
TIMER4_CH1
Additional: ADC_IN1
Default: PA2
Alternate: USART0_CK, TSI_G0_IO2, TIMER0_CH0,
PA2-WKUP0
19
I/O
5VT
EVENTOUT, TIMER1_CH2, TIMER4_CH2, I2S1_CKIN,
USART1_TX
Additional: ADC_IN2, WKUP0, RTC_TAMP1
Default: PA3
Alternate: USART1_CK, TSI_G0_IO3,
PA3
20
I/O
5VT
TIMER0_CH0_ON, EVENTOUT, TIMER1_CH3,
TIMER4_CH3, I2S1_MCK, USART1_RX, RTC_OUT
Additional: ADC_IN3
Default: PA4
Alternate: I2S1_ADD_SD, SPI1_MOSI, I2S1_SD,
PA4
21
I/O
5VT
SPI0_MOSI, QSPI_SCK, TIMER4_CH2, USART1_TX,
TIMER0_CH1, EVENTOUT, SPI0_NSS, USART1_CK
Additional: ADC_IN8
Default: PA5
PA5
22
I/O
5VT
Alternate: I2S1_MCK, SPI0_MISO, QSPI_CSN,
TIMER4_CH3, USART1_RX, TIMER0_CH1_ON,
EVENTOUT, SPI0_SCK
Default: PA6
Alternate: I2S1_CKIN, SPI0_SCK, QSPI_IO0,
PA6
23
I/O
5VT
TIMER2_CH0, USART2_TX, TIMER0_CH1,
TIMER1_CH1, EVENTOUT, SPI0_MISO, I2S1_MCK,
SDIO_CMD
Default: PA7
Alternate: SPI1_NSS, I2S1_WS, SPI0_NSS, QSPI_IO1,
PA7
24
I/O
5VT
TIMER2_CH1, USART2_RX, TIMER0_CH1_ON,
TIMER1_CH2, EVENTOUT, TIMER0_CH0_ON,
SPI0_MOSI
Default: PB11
PB11
25
I/O
5VT
Alternate: USBFS_ID, TSI_G2_IO0, TIMER0_CH1_ON,
EVENTOUT, I2S1_CKIN, USART2_RX, SDIO_D6
Default: PB12
PB12
26
I/O
5VT
Alternate: I2S1_WS, USBFS_DP, TSI_G2_IO1,
TIMER0_CH3, EVENTOUT, TIMER0_BRKIN,
SPI1_NSS, USART2_CK
PB13
27
I/O
5VT
Default: PB13
24
GD32W515xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: USBFS_DM, TSI_G2_IO2, EVENTOUT,
TIMER15_CH0, TIMER0_CH0_ON, SPI1_SCK,
I2S1_CK, USART2_CTS
VDD
28
Default: VDD
P
Default: PB15
PB15
29
I/O
5VT
Alternate: I2S1_SD, USART1_TX, USART0_TX,
I2C0_SCL, I2C1_SCL, IFRP_OUT, EVENTOUT,
RTC_REFIN, TIMER0_CH2_ON, SPI1_MOSI
Default: PA8
Alternate: CK_OUT0, USART1_RX, USART0_RX,
PA8
30
I/O
5VT
I2C0_SDA, I2C1_SDA, EVENTOUT, TIMER15_CH0,
TIMER0_CH0, USART0_CK, USBFS_SOF, SDIO_D1,
RTC_OUT
Default: PA9
Alternate: SPI0_MOSI, SDIO_CMD, SQPI_CLK,
PA9
31
I/O
5VT
QSPI_SCK, EVENTOUT, TIMER15_CH0_ON,
TIMER0_CH1, SPI1_SCK, I2S1_CK, USART0_TX,
SDIO_D2
Default: PA10
PA10
32
I/O
5VT
Alternate: SPI0_MISO, SDIO_D0, SQPI_CSN,
QSPI_CSN, EVENTOUT, TIMER16_CH0,
TIMER0_CH2
Default: PA11
PA11
33
I/O
5VT
Alternate: SPI0_SCK, SDIO_CK, SQPI_D0, QSPI_IO0,
EVENTOUT, TIMER16_BRKIN, TIMER0_CH3
Default: PA12
PA12WKUP3
Alternate: SPI0_NSS, SDIO_D1, SQPI_D1, QSPI_IO1,
34
I/O
5VT
EVENTOUT, TIMER16_CH0_ON, TIMER0_ETI,
USART0_RTS / USART0_DE
Additional: WKUP3
Default: JTDO, TRACESWO, PB3
PB3
35
I/O
5VT
Alternate: USART2_CTS, SPI0_IO2, SDIO_D2,
SQPI_D2, QSPI_IO2, EVENTOUT, TIMER15_BRKIN,
TIMER1_CH1, SPI0_SCK, USART0_RX
Default: NJTRST, PB4
PB4
36
I/O
5VT
Alternate: USART2_RTS / USART2_DE, SPI0_IO3,
SDIO_D3, SQPI_D3, QSPI_IO3, TIMER1_CH0,
TIMER1_ETI, EVENTOUT, SPI0_MISO
Note:
(1) Type: I = input, O = output, A = analog, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
25
GD32W515xx Datasheet
GD32W515xx pin alternate functions
2.6.3.
Table 2-5. Port A alternate functions summary
Pin
AF0
Name
PA0
AF1
AF2
TIME
R1_C TIME
USAR
H0/TI R4_C
T0_TX
MER1 H0
_ETI
AF3
AF4
AF5
AF6
AF7
USAR
T1_CT
S
EVEN
TOUT
USAR
T1_RT
S/
USAR
T1_D
E
EVEN
TOUT
HPDF
EVEN
_AUDI
TOUT
(1)
O
USAR TIME TIME
T0_R R1_C R4_C
X
H1
H1
TSI_G
0_IO1
PA2
USAR TIME TIME
T0_C R1_C R4_C
K
H2
H2
TIME
TSI_G I2S1_
USAR
R0_C
0_IO2 CKIN
T1_TX
H0
PA3
USAR TIME TIME
T1_C R1_C R4_C
K
H3
H3
TSI_G I2S1_
0_IO3 MCK
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
AF9 AF10 AF11 AF12 AF13 AF14 AF15
TSI_G
0_IO0
PA1
PA4
AF8
TIME
USAR
R0_C RTC_
T1_R
H0_O OUT
X
N
SPI1_
I2S1_
TIME
USAR TIME
USAR
SPI0_ QSPI_
SPI0_ MOSI/
ADD_
R4_C
T1_C R0_C
T1_TX
MOSI SCK
NSS I2S1_
SD
H2
K
H1
SD
TIME
USAR
TIME
I2S1_ QSPI_ SPI0_ SPI0_
R0_C
T1_R
R4_C
MCK CSN MISO SCK
H1_O
X
H3
N
TIME
TIME
QSPI_ I2S1_ SPI0_ I2S1_ SPI0_
R2_C
R0_C
IO0 CKIN MISO MCK SCK
H0
H1
SPI1_ TIME
TIME
TIME
USAR
NSS/I R0_C
QSPI_ SPI0_ SPI0_ R0_C DCI_D
R2_C
T2_R
2S1_ H0_O
IO1
NSS MOSI H1_O 7(1)
H1
X
WS
N
N
TIME USAR USAR
USAR TIME
CK_O
I2C0_ I2C1_
R0_C T0_R T1_R
T0_C R15_
UT0
SDA SDA
H0
X
X
K
CH0
SPI1_
TIME
TIME
SPI0_
SDIO_ SQPI_ QSPI_ SCK/I
USAR R15_
R0_C
MOSI
CMD CLK SCK 2S1_C
T0_TX CH0_
H1
K
ON
TIME
TIME
SPI0_
SDIO_ SQPI_ QSPI_
R0_C
R16_
MISO
D0
CSN CSN
H2
CH0
TIME
TIME
SPI0_
SDIO_ SQPI_ QSPI_
R0_C
R16_B
SCK
CK
D0
IO0
H3
RKIN
USAR
T0_RT
TIME
QSPI_
SPI0_ S / SQPI_
R0_E
IO1
NSS USAR D1
TI
T0_D
E
JTMS/
USAR USAR
I2C0_
SWDI
TSITG
T0_CT T1_CT
SMBA
O
S
S
USAR USAR
T0_RT T1_RT
JTCK/
I2C1_
S/
S/
SWCL
SMBA
USAR USAR
K
T0_D T1_D
E
E
HPDF
EVEN
_DAT
TOUT
AIN1(1)
DCI_H
SYNC(
1)
DCI_V
SYNC(
1)
TIME
USAR
R1_C
T2_TX
H1
EVEN
TOUT
EVEN
TOUT
DCI_P HPDF
SDIO_
EVEN
IXCLK _AUDI
CMD
TOUT
(1)
(1)
O
TIME
R1_C
H2
EVEN
TOUT
USBF
RTC_
S_SO
OUT
F
TIME
R16_
CH0_
ON
SDIO_
D1
EVEN
TOUT
SDIO_ DCI_D
D2
0(1)
EVEN
TOUT
DCI_D
1(1)
EVEN
TOUT
DCI_D
2(1)
EVEN
TOUT
SDIO_ DCI_D
D1
3(1)
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
26
GD32W515xx Datasheet
Pin
AF0
Name
PA15
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9 AF10 AF11 AF12 AF13 AF14 AF15
USAR
I2C0_ SPI0_ I2C1_
T0_R
SCL NSS SCL
X
JTDI
EVEN
TOUT
Table 2-6. Port B alternate functions summary
Pin
Name
PB0
PB1
PB2
PB3
AF0
AF1
TIME
R0_C
H1_O
N(1)
TIME
R0_C
H2_O
N(1)
TIME
R1_C
H3(1)
JTDO/ TIME
TRAC R1_C
ESWO H1
PB4
TIME
R1_C
NJTR
H0/TI
ST
MER1
_ETI
PB5
TIME
IFRP_
(1) R1_C
OUT
H3(1)
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9 AF10 AF11 AF12 AF13 AF14 AF15
TIME TIME TSI_G
R2_C R3_C 1_IO0(
1)
H1(1) H0(1)
EVEN
SDIO_ DCI_D DCI_D
TOUT(
D1(1)
4(1)
6(1)
1)
TIME TIME TSI_G
R3_C R2_C 1_IO1(
1)
H1(1) H2(1)
EVEN
SDIO_ DCI_D DCI_D
TOUT(
D2(1)
3(1)
5(1)
1)
TIME TIME TSI_G
R3_C R2_C 1_IO2(
1)
H2(1) H3(1)
EVEN
SDIO_ DCI_D DCI_D
TOUT(
CK(1)
2(1)
4(1)
1)
USAR
SPI0_ SPI0_I
SQPI_
T0_R
SCK
O2
D2
X
USAR
T2_RT
QSPI_
SPI0_ SPI0_I S / SQPI_
IO3
MISO O3 USAR D3
T2_D
E
SPI0_
USAR
TSITG
MOSI(
T2_C
(1)
1)
K(1)
SPI1_
MISO(
QSPI_
IO2
PB6
USAR TIME
SDIO_
T2_CT R15_B
D2
S
RKIN
EVEN
TOUT
SDIO_
D3
EVEN
TOUT
DCI_D
10(1)
DCI_D
5(1)
1)
TIME
R3_C
H1(1)
PB7
TIME
R3_C
H2(1)
PB8
PB9
PB10
PB11
PB12
PB13
PB14
TIME TIME
R1_C R3_C
H1(1) H3(1)
TIME TIME
R1_C R3_E
H2(1)
TI(1)
TIME
R0_C
H1_O
N
TIME TIME
R0_B R0_C
RKIN
H3
TIME
R0_C
H0_O
N
TIME
R0_C
H1_O
SPI1_
I2C0_ NSS(1)
SDA(1) /I2S1_
WS(1)
SPI1_
SCK(1)
/I2S1_
CK(1)
SPI1_
MOSI(
1)/I2S1
_SD(1)
TIME TSI_G
R3_C 1_IO3(
1)
H3(1)
TSI_G I2S1_
2_IO0 CKIN
USAR
T0_R
X(1)
SPI1_
USAR
TSI_G NSS/I
T2_C
2_IO1 2S1_
K
WS
SPI1_
USAR
TSI_G SCK/I
T2_CT
2_IO2 2S1_C
S
K
TSI_G SPI1_ I2S1_ USAR
2_IO3( MISO( ADD_ T2_RT
1)
1)
SD(1) S(1) /
TIME
R15_B
RKIN(1
1)
1)
1)
EVEN
TOUT(
1)
EVEN
TOUT(
1)
EVEN
SDIO_ DCI_D DCI_D
TOUT(
D7(1)
1(1)
3(1)
1)
USBF
S_ID
TIME
R15_
CH0
EVEN
TOUT(
EVEN
TOUT(
SDIO_ DCI_D
D5(1)
7(1)
USAR
T2_R
X
1)
DCI_V
SYNC(
SDIO_ DCI_D
D4(1)
6(1)
USAR TIME
IFRP_
T2_TX R0_C
(1)
(1)
(1) OUT
H1
EVEN
TOUT(
SDIO_ DCI_D DCI_D EVEN
D6
0(1)
2(1) TOUT
USBF
S_DP
DCI_D
1(1)
EVEN
TOUT
USBF
S_DM
DCI_D
0(1)
EVEN
TOUT
EVEN
TOUT(
1)
27
GD32W515xx Datasheet
Pin
Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
N(1)
PB15
TIME
RTC_ R0_C
REFIN H2_O
N
AF7
AF8
USAR
T2_D
E(1)
)
AF9 AF10 AF11 AF12 AF13 AF14 AF15
SPI1_
I2C0_ MOSI/ I2C1_ USAR USAR IFRP_
SCL I2S1_ SCL
T1_TX T0_TX OUT
SD
EVEN
TOUT
Table 2-7. Port C alternate functions summary
Pin
Name
PC0
AF0
AF1
USAR
T1_TX
PC2
PC3
PC4
PC5
PC6
PC7
PC15
AF5
AF6
AF7
AF8
AF9 AF10 AF11 AF12 AF13 AF14 AF15
HPDF EVEN
DCI_D
_CKIN TOUT(
(1)
4
1)
0(1)
1)
SPI1_
MOSI(
1)/I2S1
_SD(1)
I2C1_
SMBA(
1)
TIME TIME TIME
R0_E R0_C R4_C
TI(1)
H0(1) H0(1)
TIME
R1_C TIME
H0(1)/T R4_C
IMER1 H1(1)
_ETI(1)
I2S1_ TIME
ADD_ R2_C
SD(1) H2(1)
TIME TIME
CK_O
R2_C R2_C
UT1(1)
H0(1) H3(1)
TIME
TIME
TRAC R0_B
R2_C
ECK(1) RKIN(1
H0(1)
)
DCI_H
HPDF EVEN
DCI_D
SYNC(
_CKIN TOUT(
(1)
8
1)
1)
1(1)
SPI1_ I2S1_
I2C0_
MISO( ADD_
SCL(1)
1)
SD(1)
QSPI_
IO3(1)
I2C1_
SDA(1)
DCI_V
HPDF EVEN
DCI_D
SYNC(
_CKO TOUT(
(1)
9
1)
1)
UT(1)
SPI1_
I2C0_ MOSI( I2C1_
SDA(1) 1)/I2S1 SCL(1)
_SD(1)
TIME
R0_C
H0_O
N(1)
DCI_P
HPDF EVEN
DCI_D
IXCLK
_DAT TOUT(
(1)
11
(1)
1)
AIN0(1)
SPI0_I
O2(1)
SQPI_
CLK(1)
DCI_D DCI_D
6(1)
12(1)
QSPI_
IO2(1)
TIME
TIME
R0_C
R2_C
H1_O
H1(1)
N(1)
TIME
R2_C
H2
TIME
R0_E
TI(1)
AF4
I2C0_
SMBA(
TIME
USAR
R0_B
T1_R
RKIN(1
X(1)
)
PC8
PC14
AF3
TIME
R0_C
H3(1)
(1)
PC1
AF2
USAR
SPI0_I
SQPI_
T2_R
O3(1)
CSN(1)
(1)
X
TIME
TIME TIME USAR
I2S1_
R16_B
R0_C
R1_C T2_TX
MCK(1)
RKIN(1
(1)
H1(1) H1(1)
)
SPI1_
SCK(1)
/I2S1_
CK(1)
TIME USAR TIME
R16_ T2_R R1_C
CH0(1) X(1)
H2(1)
I2C0_ I2C1_ USAR
SDA SDA T0_TX
USAR USAR
T0_C T1_C
K
K
IFRP_
OUT
EVEN
TOUT(
1)
EVEN
DCI_D DCI_D DCI_D
TOUT(
7(1)
13(1)
5(1)
1)
SDIO_ DCI_D
D6(1)
0(1)
SDIO_ DCI_D
D7(1)
1(1)
SDIO_ DCI_D
D0
2(1)
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Note:
(1) Functions are available on GD32W515Px devices only.
28
GD32W515xx Datasheet
3.
Functional description
3.1.
Arm® Cortex®-M33 core
The Cortex®-M33 processor is a 32-bit processor that possesses low interrupt latency
and low-cost debug. The characteristics of integrated and advanced make the Cortex®M33 processor suitable for market products that require microcontrollers with high
performance and low power consumption.
32-bit Arm® Cortex®-M33 processor core
Up to 180 MHz operation frequency
Ultra-low power, energy-efficient operation
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M33 processor is based on the ARMv8 architecture and supports both
Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also
provided by Cortex®-M33:
Internal Bus Matrix connected with Code bus, System bus, and Private Peripheral
Bus (PPB) and debug accesses
Nested Vectored Interrupt Controller (NVIC)
Breakpoint Unit (BPU)
Data Watchpoint and Trace (DWT)
Instrumentation Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
Arm® TrustZone® technology, using the ARMv8-M main extension supporting
secure and non-secure states
Memory Protection Unit (MPU), supporting 8 regions for secure and 8 regions for
non-secure.
3.2.
Configurable secure attribute unit (SAU) supporting up to 8 memory regions
Floating Point Unit (FPU)
DSP Extension (DSP)
On-chip memory
Up to 2048 Kbytes of SIP Flash memory
Up to 32M bytes of EXT Flash memory
Up to 448 Kbytes of SRAM with hardware parity checking
2048 Kbytes of inner Flash or 32M bytes of EXT Flash memory, and 448 Kbytes of inner
SRAM at most is available for storing programs and data. Table 2-2. GD32W515xx
memory map shows the memory map of the GD32W515xx series of devices, including
29
GD32W515xx Datasheet
code, SRAM, peripheral, and other pre-defined regions.
3.3.
Clock, reset and supply management
Internal 16 MHz factory-trimmed RC and external 20 to 52 MHz crystal oscillator
Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
1.62 to 3.63 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low
voltage detector (LVD)
The Clock Control Unit (CCTL) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low
speed two types. Several prescalers allow the frequency configuration of the AHB and
two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 180
MHz/90 MHz/45MHz. See Figure 2-4. GD32W515xx clock tree for details on the clock
tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the
processor core and peripheral IP components. Power-on reset (POR) and power-down
reset (PDR) are always active, and ensures proper operation starting from 1.54 V and
down to 1.50V. The device remains in reset mode when VDD is below a specified threshold.
The embedded low voltage detector (LVD) monitors the power supply, compares it to the
voltage threshold and generates an interrupt as a warning message for leading the MCU
into security.
Power supply schemes:
VDD range: 1.62 to 3.63 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA is 0 V.
VDDA range: 2.7 to 3.63 V, external analog power supplies for ADC, reset blocks,
RCs and PLL.
VBAK range: 1.62 to 3.63 V, power supply for RTC unit, LXTAL oscillator, BPOR, and
two pads, including PC14 to PC15 when VDD is not present.
3.4.
Boot modes
At startup, a BOOT0 pin, a BOOT1 pin are used to select the boot memory address.
The BOOT0 value may come from the BOOT0 pin or from the value of SWBOOT0 bit in
the EFUSE_CTL register to free the GPIO pad if needed.
The BOOT1 value may come from the PA14 pin or from the value of SWBOOT1 bit in
the EFUSE_CTL register to free the GPIO pad if needed.
30
GD32W515xx Datasheet
Table 3-1. BOOT0 modes
SWBOOT0
EFBOOT0
BOOT0 PC8 pin
BOOT0
0
-
0
0
0
-
1
1
1
0
-
0
1
1
-
1
Table 3-2. BOOT1 modes
BOOT1 PA14
SWBOOT1
EFBOOT1
0
-
0
0
0
-
1
1
1
0
-
0
1
1
-
1
pin
BOOT1
Refer to Table 3-3. Boot address modes when TrustZone is disabled (TZEN=0) and
Table 3-4. Boot modes when TrustZone is enabled (TZEN=1) for boot address when
TrustZone is disabled and enabled respectively. When the EFBOOTLK bit in the
EFUSE_CTL register is set, the boot memory address selected according to boot1 and
boot0.
Table 3-3. Boot address modes when TrustZone is disabled (TZEN=0)
EFBOOTLK
BOOT0
BOOT1
Boot address
Boot area
SIP Flash when
0
0
-
0x08000000
cfg_qspi is 0
QSPI Flash when
cfg_qspi is 1
0
1
0
0x0BF40000
Bootloader / ROM
0
1
1
0x0A000000
SRAM0
SIP Flash when
1
0
-
0x08000000
cfg_qspi is 0
QSPI Flash when
cfg_qspi is 1
1
1
-
0x0BF40000
Bootloader / ROM
When TrustZone is enabled by setting the TZEN option bit, the boot space must be in
secure area.
Table 3-4. Boot modes when TrustZone is enabled (TZEN=1)
GSSAC
MD ==
EFBOOTLK
BOOT0
BOOT1
EFSB
8’hc(1)
Boot
address
Boot area
SPI Flash when
0
0
0
-
0
0x0C000000
cfg_qspi is 0
QSPI Flash when
31
GD32W515xx Datasheet
GSSAC
MD ==
EFBOOTLK
BOOT0
BOOT1
EFSB
8’hc(1)
Boot
address
Boot area
cfg_qspi is 1
0
0
0
-
1
0X0FF84000
secure boot
0
0
1
0
-
0x0FF80000
GSSA
0
0
1
1
-
0x0E000000
SRAM0
SPI Flash when
-
1
0
-
0
0x0C000000
cfg_qspi is 0
QSPI Flash when
cfg_qspi is 1
-
1
0
-
1
0X0FF84000
secure boot
-
1
1
-
-
0x0FF80000
GSSA
1
0
-
-
-
0x0FF80000
GSSA
Note: (1) When the GSSACMD bit field is 0x0C, it means 1, otherwise it means 0.
The BOOTx (x=0/1) value (either coming from the pin or the EFBOOTx bit) is latched
upon reset release. It is up to the user to set BOOTx values to select the required boot
mode. The BOOTx pin or EFBOOTx bit (depending on the EFBOOTLK and SWBOOTx
bit value in the EFUSE_CTL register) is also re-sampled when exiting from Standby mode.
Consequently, they must be kept in the required Boot mode configuration in Standby
mode. After startup delay, the selection of the boot area is done before releasing the
processor reset.
The embedded boot loader is located in the System memory, which is used to reprogram
the Flash memory. The boot loader can be activated through one of the following serial
interfaces: USART0 (PA8, PB15), USART1 (PA2, PA3) and USART2 (PB10, PB11).
3.5.
Power saving modes
The MCU supports five kinds of power saving modes to achieve even lower power
consumption. They are Sleep, Deep-sleep, Standby, SRAM_sleep and WIFI_sleep mode.
These operating modes reduce the power consumption and allow the application to
achieve the best balance between the CPU operating time, speed and power
consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate
and any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC16M, HXTAL
and PLLs are disabled. The contents of SRAM0 and registers are preserved. In nonsecure mode, any interrupt or wakeup event from EXTI lines can wake up the system
from the deep-sleep mode including the 16 external lines, the RTC alarm non-secure,
32
GD32W515xx Datasheet
LVD output, VLVDF interrupt, WIFI11N wakeup, USBFS wakeup, RTC Tamper and
Timestamp non-secure, RTC Wakeup event non-secure, I2C0 wakeup and
USART0/USART2 wakeup. In secure mode, any interrupt or wakeup event from
EXTI lines can wake up the system from the deep-sleep mode including the 16
external lines, the RTC Alarm secure, LVD output, VLVDF interrupt, WIFI11N
wakeup, USBFS wakeup, RTC Tamper and Timestamp secure, RTC Wakeup event
secure, I2C0 wakeup and USART0/USART2 wakeup. When exiting the deep-sleep
mode, the IRC16M is selected as the system clock.
Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and
all of IRC16M, HXTAL and PLLs are disabled. There are four wakeup sources for
the Standby mode, including the external reset from NRST pin, the RTC alarm/time
stamp/tamper/auto wakeup events, the FWDGT reset, and the rising edge on WKUP
pins.
SRAM_sleep mode
In SRAM_sleep mode, at least one of SRAM1/SRAM2/SRAM3 is power off. When
the SRAM enters SRAM_sleep mode, the content of SRAM will lost.
SRAM1/SRAM2/SRAM3 can be configured power on or power off when in
run/sleep/deep_sleep mode. SRAM1/SRAM2/SRAM3 are power off when in
standby mode/BKP_ONLY mode.
WIFI_sleep mode
In WIFI_sleep mode, WIFI_OFF domain power off. When exit from WIFI_sleep
mode, Wi-Fi is active mode, all Wi-Fi power on.
3.6.
Electronic fuse (EFUSE)
One-time programmable nonvolatile EFUSE storage cells organized as 256*8 bit.
All bits in the efuse cannot be rollback from 1 to 0.
Can only be accessed through corresponding registers.
The Efuse controller has efuse macro that store system parameters. As a non-volatile
unit of storage, the bit of efuse macro cannot be restored to 0 once it is programmed to
1. According to the software operation, the Efuse controller can program all the bits in the
system parameters.
3.7.
Instruction cache (ICACHE)
Support 32KB cache with 2 ways, 1024 cache lines per way and 16B per cache line.
Support fetch address without any wait state if cache hit.
Support two performance counters: 32-bit hit monitor counter and16-bit miss monitor
counter.
Support TrustZone security and configure registers to be protected at system level.
33
GD32W515xx Datasheet
The instruction cache (ICACHE) is based on C-AHB code bus of Cortex-M33 processor.
It is necessary to improve performance in fetching instruction and data from both internal
and external memories.
3.8.
General-purpose inputs / outputs (GPIOs)
Up to 43 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 43 general purpose I/O pins (GPIO) in GD32W515xx, named PA0 ~
PA15, PB0 ~ PB15, PC0 ~ PC8, and PC14 ~ PC15 to implement logic input/output
functions. Each GPIO port has related control and configuration registers to satisfy the
requirements of specific applications. The external interrupts on the GPIO pins of the
device have related control and configuration registers in the Interrupt/Event Controller
Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to
obtain maximum flexibility on the package pins.
Each of the GPIO pins can be configured by software as output (push-pull or open-drain),
input, peripheral alternate function or analog mode. Most of the GPIO pins are shared
with digital or analog alternate functions.
3.9.
TrustZone protection controller union (TZPCU)
TZSPC, TZBMPC and TZIAC have independent 32-bit AHB interface.
For TZSPC, whether non-secure/non-privilege access is supported that is defined
by secure/privilege configuration registers.
For TZBMPC and TZIAC, only secure access is supported.
For securable slave/master peripherals, secure/privilege state is defined in TZSPC
registers.
For off-chip memories, the size of non-secure area is defined in TZSPC registers.
For on-chip RAM, the secure states of all blocks is defined in TZBMPC registers.
This section describes the TrustZone® protection controller union. Three different subblocks, TrustZone® security privilege controller (TZSPC), TrustZone® block-based
memory protection controller (TZBMPC) and TrustZone ® illegal access controller (TZIAC),
are used to configure system security or privileg in a product with programmable-security
and privileged attributes. TZSPC is used to defines the secure/privilege state for
securable slave/master peripherals. TrustZone® mark memory protection controller
(TZMMPC) do the security checking of off-chip memories based on the size of nonsecure area which is defined in TZSPC. For the on-chip RAM, the security checking is
done based on block level which is configured by the TZBMPC through an AHB interface.
TZIAC is used to enable all illegal access events for slave/master peripherals in system.
If an interrupt is enabled, a dedicated interrupt signal is asserted and generates a secure
34
GD32W515xx Datasheet
interrupt towards NVIC whenever a security violation is detected. The interrupt is cleared
by writing to the appropriate register of TZIAC.
3.10.
CRC calculation unit (CRC)
32-bit data input and 32-bit data output. Calculation period is 4 AHB clock cycles for
32-bit input data size from data entered to the calculation result available.
Free 8-bit register is unrelated to calculation and can be used for any other goals by
any other peripheral devices.
Fixed polynomial: 0x4C11DB7
X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1
A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital
networks and storage devices to detect accidental changes to raw data. This CRC
calculation unit can be used to calculate 32 bit CRC code with fixed polynomial.
3.11.
True Random number generator (TRNG)
About 40 periods of TRNG_CLK are needed between two consecutive random
numbers
Disable TRNG module will significantly reduce the chip power consumption
32-bit random value seed is generated from analog noise, so the random number is
a true random number.
The true random number generator (TRNG) module can generate a 32-bit random value
by using continuous analog noise.
3.12.
Direct memory access controller (DMA)
8 channels for DMA0 controller and 8 channels for DMA1 controller.
Peripherals supported: Timers, ADC, SPIs, I2S, QSPI, I2Cs, USARTs, DCI, CAU,
HAU, SDIO and HPDF.
The flexible general-purpose DMA controllers provide a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby
increasing system performance by off-loading the MCU from copying large amounts of
data and avoiding frequent interrupts to serve peripherals needing more data or having
available data. Three types of access method are supported: peripheral to memory,
memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA
channel requests are determined by software configuration and hardware channel
number. Transfer size of source and destination are independent and configurable.
35
GD32W515xx Datasheet
3.13.
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 2.5 MSPS
Hardware oversampling ratio adjustable from 2x to 256x improves resolution to 16bit
Input voltage range: 0 to VDDA
Temperature sensor
A 12-bit 2.5 MSPS multi-channel ADC is integrated in the device. It has a total of 12
multiplexed channels: up to 9 external channels, 1 channel for internal temperature
sensor (VSENSE), 1 channel for internal reference voltage (V REFINT) and one channel for
external battery power supply (VBAT) channel. The input voltage range is between 0 and
VDDA. An on-chip hardware oversampling scheme improves performance while offloading the related computational burden from the CPU. The analog watchdog allows the
application to detect whether the input voltage goes outside the user-defined higher or
lower thresholds. A configurable channel management block can be used to perform
conversions in single, continuous, scan or discontinuous mode to support more advanced
use.
The ADC can be triggered from the events generated by the general level 0 timers
(TIMERx, x=1, 2, 3, 4) and the advanced timers (TIMER0) with internal connection. The
temperature sensor can be used to generate a voltage that varies linearly with
temperature. It is internally connected to the ADC_IN9 input channel which is used to
convert the sensor output voltage in a digital value.
To ensure a high accuracy on ADC, the independent power supply VDDA is implemented
to achieve better performance of analog circuits. VDDA can be externally connected to VDD
through the external filtering circuit that avoids noise on V DDA, and VSSA should be
connected to VSS through the specific circuit independently.
3.14.
Real time clock (RTC)
Independent binary-coded decimal (BCD) format timer / counter with twenty 32-bit
backup registers.
Calendar with sub-second, second, minute, hour, week day, day, month and year
automatically correction.
Alarm function with wake up from deep-sleep and standby mode capability.
On-the-fly correction for synchronization with master clock. Digital calibration with
0.95 ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running
counters in backup registers to provide a real calendar function, and provides an alarm
interrupt or an expected interrupt. It is not reset by a system or power reset, or when the
device wakes up from standby mode. In the RTC unit, there are two prescalers used for
36
GD32W515xx Datasheet
implementing the calendar and other functions. One prescaler is a 7-bit asynchronous
prescaler and the other is a 15-bit synchronous prescaler.
3.15.
Timers and PWM generation
One 16-bit advanced timer (TIMER0), two 32-bit general timer (TIMER1, TIMER2),
up to four 16-bit general timers (TIMER3, TIMER4, TIMER15 ~ TIMER16), and one
16-bit basic timer (TIMER5)
Up to 4 independent channels of PWM, output compare or input capture for each
general timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation
for output match
Encoder interface controller with two inputs using quadrature decoder
Two 24-bit SysTick timers down counter, a Non-secure SysTick timer and a Secure
SysTick timer
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable dead-time generation.
It can also be used as a complete general timer. The 4 independent channels can be
used for input capture, output compare, PWM generation (edge- or center- aligned
counting modes) and single pulse mode output. If configured as a general 16-bit timer, it
has the same functions as the TIMERx. It can be synchronized with external signals or
to interconnect with other general timers together which have the same architecture and
features.
The general timer can be used for a variety of purposes including general time, input
signal pulse width measurement or output waveform generation such as a single pulse
generation or PWM output, up to 4 independent channels for input capture/output
compare. TIMER1 and TIMER2 are based on a 32-bit auto-reload up/down counter and
a 16-bit prescaler. TIMER3 and TIMER4 is based on a 16-bit auto-reload up/down
counter and a 16-bit prescaler. TIMER15 ~ TIMER16 are based on a 16-bit auto-reload
up counter and a 16-bit prescaler. The general timer also supports an encoder interface
with two inputs using quadrature decoder.
The basic timer TIMER5, is mainly used as a simple 16-bit time base.
The GD32W515xx have two watchdog peripherals, free watchdog timer and window
watchdog timer. They offer a combination of high safety level, flexibility of use and timing
accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-stage
prescaler. It is clocked from an independent 32 KHz internal RC and as it operates
independently of the main clock, it can operate in deep-sleep and standby modes. It can
be used either as a watchdog to reset the device when a problem occurs, or as a freerunning timer for application timeout management.
37
GD32W515xx Datasheet
The window watchdog is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked
from the main clock. It has an early wakeup interrupt capability and the counter can be
frozen in debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.16.
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Universal synchronous asynchronous receiver transmitter
(USART)
Maximum speed up to 11.25 MBits/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
Dual clock domain
Wake up from Deep-sleep mode
The USART (USART0, USART1, USART2) are used to translate data between parallel
and serial interfaces, provides a flexible full duplex data exchange using synchronous or
asynchronous transfer. It is also commonly used for RS-232 standard communication.
The USART includes a programmable baud rate generator which is capable of dividing
the system clock to produce a dedicated clock for the USART transmitter and receiver.
The USART also supports DMA function for high speed data communication.
3.17.
Inter-integrated circuit (I2C)
Support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
SMBus 3.0 and PMBus 1.3 compatible
Wakeup from Deep-sleep mode on I2C0 address match
The I2C interface is an internal circuit allowing communication with an external I2C
interface which is an industry standard two line serial interface used for connection to
external hardware. These two serial lines are known as a serial data line (SDA) and a
serial clock line (SCL). The I2C module provides different data transfer rates: up to 100
38
GD32W515xx Datasheet
KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode
plus. The I2C module also has an arbitration detect function to prevent the situation where
more than one master attempts to transmit data to the I2C bus at the same time. A CRC8 calculator is also provided in I2C interface to perform packet error checking for I2C data.
3.18.
Serial peripheral interface (SPI)
Up to two SPI interfaces with a frequency of up to 22.5 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)
The SPI interface uses 4 pins, among which are the serial data input and output lines
(MISO & MOSI), the clock line (SCK) and the slave select line (NSS). All SPIs can be
served by the DMA controller. The SPI interface may be used for a variety of purposes,
including simplex synchronous transfers on two lines with a possible bidirectional data
line or reliable communication using CRC checking. Quad-SPI master mode is also
supported in SPI0.
3.19.
Inter-IC sound (I2S)
Sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital
audio applications by 4-wire serial lines. GD32W515xx contain an I2S-bus interface that
can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with
SPI1. The audio sampling frequency from 8 KHz to 192 KHz is supported.
3.20.
Serial / Quad Parallel Interface (SQPI)
SQPI controller support configuring output clock frequency which is divided by HCLK.
SQPI controller support no address phase and data phase operation which is named
special command by the controller.
SQPI controller support 256MB external memory space.
Logic memory address range: 0x6000_0000 - 0x6FFF_FFFF.
SQPI controller support 6 types mode for different combination of command,
address, waitcycle, and data phase.
Serial/Quad Parallel Interface (SQPI) is a controller for external serial/dual/quad parallel
interface memory peripheral. For example: SQPI-PSRAM and SQPI-FLASH. With this
controller, users can use external SQPI interface memory as SRAM simply.
39
GD32W515xx Datasheet
3.21.
Quad-SPI interface (QSPI)
Four functional modes: indirect(address extend), status-polling, memory-mapped
and FMC mode
Fully programmable command format for both indirect and memory mapped mode
Integrated FIFO for transmission/reception
8, 16, or 32-bit data accesses
DMA channel for indirect mode
Support TrustZone architecture to isolate the secure area and non-secure area
The QSPI is a specialized interface that communicate with Flash memories. This
interface support single, dual or quad SPI FLASH.
3.22.
Secure digital input and output card interface (SDIO)
Support SD2.0/SDIO2.0/MMC4.2 host interface
The Secure Digital Input and Output Card Interface (SDIO) provides access to external
SD memory cards specifications version 2.0, SDIO card specification version 2.0 and
multi-media card system specification version 4.2 with DMA supported. In addition, this
interface is also compliant with CE-ATA digital protocol rev1.1.
3.23.
Universal serial bus full-speed interface (USBFS)
One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USBCLK compliantly
Internal USBFS PHY support
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction
formatting is performed by the hardware, including CRC generation and checking. It
supports both host and device modes, as well as OTG mode with Host Negotiation
Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed
USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is
needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous)
defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated
from the internal main PLL (the clock source must use an HXTAL crystal oscillator).
3.24.
Digital camera interface (DCI)
Digital video/picture capture
8/10/12/14 data width supported
40
GD32W515xx Datasheet
High transfer efficiency with DMA interface
Video/picture crop supported
Various pixel formats supported including JPEG/YCrCb/RGB
Hard/embedded synchronous signals supported
DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a
camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA
operation.
3.25.
Touch sensing interface (TSI)
3 fully parallel groups implemented.
9 IOs configurable for capacitive sensing Channel Pins and 3 for Sample Pins.
Configurable transfer sequence frequency.
Touch Sensing Interface (TSI) provides a convenient solution for touch keys, sliders and
capacitive proximity sensing applications. The controller builds on charge transfer
method. Placing a finger near fringing electric fields adds capacitance to the system and
TSI is able to measure this capacitance change using charge transfer method.
3.26.
Cryptographic acceleration Unit (CAU)
Supports DES, TDES or AES (128, 192, or 256) algorithms.
DES/TDES supports Electronic codebook (ECB) or Cipher block chaining (CBC)
mode
AES supports 128bits-key, 192bits-key or 256 bits-key
AES supports Electronic codebook (ECB), Cipher block chaining (CBC) mode,
Counter mode (CTR) mode, Galois/counter mode (GCM), Galois message
authentication code mode (GMAC), Counter with CBC-MAC (CCM), cipher message
authentication code mode (CMAC), Cipher Feedback mode (CFB) and Output
Feedback mode (OFB).
DMA transfer for incoming and outgoing data is supported
The Cryptographic Acceleration Unit supports acceleration of DES, TDES or AES (128,
192, or 256) algorithms. The DES/TDES supports Electronic codebook (ECB) or Cipher
block chaining (CBC) mode. The AES supports Electronic codebook (ECB), Cipher block
chaining (CBC) mode, Counter mode (CTR) mode, Galois/counter mode (GCM), Galois
message authentication code mode (GMAC), Counter with CBC-MAC (CCM), Cipher
Feedback mode (CFB) and Output Feedback mode (OFB).
3.27.
Hash acceleration unit (HAU)
Supports SHA-1, SHA-224 and SHA-256 algorithms, compliant with FIPS PUB 18041
GD32W515xx Datasheet
2 (Federal Information Processing Standards Publication 180-2)
Supports MD5 compliant with IETF RFC 1321 (Internet Engineering Task Force
Request For Comments number 1321)
Supports HMAC (keyed-hash message authentication code) algorithm
Automatic swapping to comply with the big-endian or little-endian for MD5, SHA-1,
SHA-224 and SHA-256 algorithms
Automatic padding to fit module 512
Support DMA mode for input data flow
The HAU supports acceleration of SHA-1, SHA-224, SHA-256, MD5 algorithm and the
HMAC (keyed-hash message authentication code) algorithm, which calling the SHA-1,
SHA-224, SHA-256 or MD5 hash function to calculate key, message, digest three times.
3.28.
Public Key Cryptographic Acceleration Unit (PKCAU)
Support RSA/DH algorithms with up to 3136 bits of operands
Support ECC algorithm with up to 640 bits of operands
Embedded RAM of 3584 bytes
Conversion between the Montgomery domain and the natural domain
only 32-bit access is supported
Public key encryption is also called asymmetric encryption, asymmetric encryption
algorithms use different keys for encryption and decryption. The Public Key
Cryptographic Acceleration Unit (PKCAU) can accelerate RSA (Rivest, Shamir and
Adleman), Diffie-Hellmann (DH key exchange) and ECC (elliptic curve cryptography) in
GF(p) (Galois domain). These operations are performed in the Montgomery domain to
improve computational efficiency.
3.29.
High-Performance Digital Filter (HPDF)
Two multiplex digital serial input channels
Two internal digital parallel input channels
Up to 24 bit output data resolution
Flexible conversion configuration function
Configurable Sinc filter and integrator
A high performance digital filter module (HPDF) for external sigma delta (Σ-Δ) modulator
is integrated in GD32W515xx. HPDF supports SPI interface and Manchester-coded
single-wire interface. The external sigma delta modulator can be connected with MCU by
the serial interface, and the serial data stream output by sigma delta modulator can be
filtered. In addition, HPDF also supports the parallel data stream input function to filter
the data in the internal memory of the MCU.
42
GD32W515xx Datasheet
3.30.
Infrared ray port (IFRP)
The IFRP output signal is decided by TIMER15_CH0 and TIMER16_CH0.
To get correct infrared ray signal, TIMER15 should generate low frequency
modulation envelope signal, and TIMER16 should generate high frequency carrier
signal.
Infrared ray port (IFRP) is used to control infrared light LED, and send out infrared data
to implement infrared ray remote control.
There is no register in this module, which is controlled by TIMER15 and TIMER16. The
IFRP_OUT pin can be configured by GPIO alternate function selected register.
3.31.
Wi-Fi
3.31.1.
Standards Supported
3.31.2.
802.11b/g/n(2.4G) compatible
802.11e QoS Enhancement (WMM)
802.11i (WPA, WPA2). Open, shared key, and pair-wise key authentication services
Wi-Fi WPS
Wi-Fi Direct
Integrated TCP/IP protocol
Wi-Fi MAC
Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput
(HT).
Support for immediate ACK and Block-ACK policies.
Support for power management schemes, including WMM power-save, power-save
multi-poll (PSMP), and multiphase PSMP operation.
Interframe space timing support, including RIFS.
Support for RTS/CTS and CTS-to-self frame sequences for protecting frame
exchanges.
Back-off counters in hardware for supporting multiple priorities as specified in the
WMM specification.
Timing
synchronization
function
(TSF),
network
allocation
vector
(NAV)
maintenance, and target beacon transmission time (TBTT) generation in hardware.
Hardware engine for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, and
support for key management.
Programmable independent basic service set (IBSS) or infrastructure basic service
set or Access Point functionality.
43
GD32W515xx Datasheet
3.31.3.
Wi-Fi PHY
Single antenna 1x1 stream in 20MHz and 40MHz channels
Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps
Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps
Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800ns guard interval: 6.5,
13.0, 19.5, 26, 39, 52.0, 58.5, 65.0Mbps
Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 400ns guard interval: 7.2,
14.4, 21.7, 28.9, 43.3, 57.8, 65, 72.2Mbps
Supports IEEE 802.11n HT modulations MCS0-7, 40MHz, 800ns guard interval:
13.5, 27, 40.5, 54, 81, 108, 121.5, 135Mbps
Supports IEEE 802.11n HT modulations MCS0-7, 40MHz, 400ns guard interval: 15,
30, 45, 60, 90, 120, 135, 150Mbps
IEEE 802.11n mixed mode operation
Per packet TX power control
Advanced
channel
estimation/equalization,
automatic
gain
control,
CCA,
carrier/symbol recovery, and frame detection
Digital calibration algorithms to handle CMOS RF chip process, voltage, and
temperature (PVT) variations
3.31.4.
3.32.
Per-packet channel quality and signal-strength measurements
Compliance with FCC and other worldwide regulatory requirements
Wi-Fi Radio
Fractional-N for multiple reference clock support
Integrated PA with power control
Optimized Tx gain distribution for linearity and noise performance
Direct conversion architecture
On-chip gain selectable LNA with optimized noise figure
High dynamic range AGC
Frequency Range 2.4G-2.5G
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.33.
Package and operation temperature
QFN56 (GD32W515Px) and QFN36 (GD32W515Tx).
Operation temperature range: -40°C to +85°C (industrial level).
44
GD32W515xx Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without
permanently damaging the device. Note that the device is not guaranteed to operate
properly at the maximum ratings. Exposure to the absolute maximum rating conditions
for extended periods may affect device reliability.
Table 4-1. Absolute maximum ratings (1)(4)
Symbol
Parameter
Min
Max
Unit
VDD
External voltage range(2)
- 0.3
3.63
V
VDDA
External analog supply voltage
- 0.3
3.63
V
VBAT
External battery supply voltage
- 0.3
3.63
V
AVDD33_ANA
Wi-Fi Analog voltage
- 0.3
3.63
V
AVDD33_PA
Wi-Fi PA voltage
- 0.3
3.63
V
AVDD33_CLK
Wi-Fi Clock voltage
- 0.3
3.63
V
- 0.3
VDD + 3.63
V
Input voltage on other I/O
- 0.3
3.63
V
|ΔVDDx|
Variations between different VDD power pins
—
50
mV
IIO
Maximum current for GPIO pin
—
±25
mA
TA
Operating temperature range
-40
+85
°C
Power dissipation at TA = 85°C of QFN56
—
1044
Power dissipation at TA = 85°C of QFN36
—
939
TSTG
Storage temperature range
-65
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
PD
(1)
(2)
(3)
(4)
4.2.
Input voltage on 5V tolerant
pin(3)
mW
Guaranteed by design, not tested in production.
All main power and ground pins should be connected to an external power source within the allowable
range.
VIN maximum value cannot exceed 5.5 V.
It is recommended that VDD and VDDA are powered by the same source. The maximum difference between
VDD and VDDA does not exceed 300 mV during power-up and operation.
Operating conditions characteristics
Table 4-2. DC operating conditions
Symbol
Parameter
VDD
Supply voltage
VDDA
Analog supply voltage
VBAT
Battery supply voltage
Conditions
Min(1) Typ Max(1) Unit
—
1.62(2)
3.3
3.63
—
2.7
3.3
3.63
—
2.7
3.3
3.63
—
1.62(2)
3.3
3.63
—
2.7
3.3
3.63
V
V
V
45
GD32W515xx Datasheet
Min(1) Typ Max(1) Unit
Symbol
Parameter
Conditions
AVDD33_ANA
Wi-Fi Analog voltage
—
3.0
3.3
3.63
V
AVDD33_PA
Wi-Fi PA voltage
—
3.0
3.3
3.63
V
AVDD33_CLK
Wi-Fi Clock voltage
—
3.0
3.3
3.63
V
(1)
(2)
Based on characterization, not tested in production.
Only for GD32W515P0Q6.
Figure 4-1. Recommended power supply decoupling capacitors(1)(2)(3)
VDD/VBAT
GND
10uF+N*100 nF
VDDA
GND
1uF+10 nF
AVDD33
GND
10 μF+N*1 μF
(1)
(2)
(3)
When using precision internal reference voltage, and a bypass capacitor about 0.1 μF (or 1 μF connected
in parallel, which is recommended) to ground is required.
AVDD33 include AVDD33_PA, AVDD33_ANA, AVDD33_CLK.
All decoupling capacitors need to be as close as possible to the pins on the PCB board.
Table 4-3. Clock frequency (1)
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
AHB clock frequency
—
—
180
MHz
fAPB1
APB1 clock frequency
—
—
45
MHz
fAPB2
APB2 clock frequency
—
—
90
MHz
Min
Max
Unit
—
∞
20
—
(1)
Guaranteed by design, not tested in production.
Table 4-4. Operating conditions at Power up / Power down
Symbol
tVDD
(1)
Parameter
VDD rise time rate
VDD fall time rate
(1)
Conditions
—
μs /V
Guaranteed by design, not tested in production.
46
GD32W515xx Datasheet
Table 4-5. Start-up timings of Operating conditions
Symbol
Parameter
tstart-up
Start-up time
(1)
(2)
(3)
(1)(2)(3)
Conditions
Typ
Clock source from HXTAL
1415
Clock source from IRC16M
246
Unit
μs
Based on characterization, not tested in production.
After power-up, the start-up time is the time between the rising edge of NRST high and the first I/O
instruction.
PLL is off.
Table 4-6. Power saving mode wakeup timings characteristics (1)(2)
Symbol
Parameter
Typ
tSleep
Wakeup from Sleep mode
7.2
Wakeup from Deep-sleep mode (LDO On)
1.7
Wakeup from Deep-sleep mode (LDO in low power mode)
1.7
Wakeup from Deep-sleep mode (LDO On and Low driver mode)
62
tDeep-sleep
Wakeup from Deep-sleep mode (LDO in low power and Low driver
mode)
tStandby
(1)
(2)
4.3.
Wakeup from Standby mode
Unit
μs
62
261
Based on characterization, not tested in production.
The wakeup time is measured from the wakeup event to the point at which the application code reads
the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC16M = System clock = 16 MHz.
Power consumption
GD32W515xx is designed with advanced power management technologies and suitable
for Internet of Things applications.
Table 4-7. Wi-Fi Power consumption characteristics
Power Mode
MCU State
Wi-Fi State
Active
Active
Active
Wi-Fi Sleep
Active
Mild Sleep
Power on, PLL off, Clock gated
Hibernation
Shutdown
Power save mode: Wi-Fi wake up periodically to
listen beacon frame to stay connected to the AP.
Power save mode: Wi-Fi wake up periodically to
listen beacon frame to stay connected to the AP.
Mostly power off, only the wake
up source is power on
—
Power off
Power off
Table 4-8. Wi-Fi Power consumption characteristics(1)(2)(3)
Power Mode
Active
Description
Consumption
unit
Wi-Fi Tx 802.11b, CCK 1Mbps, Pout = +18dBm(4)
338
mA
Wi-Fi Tx 802.11b, CCK 11Mbps, Pout = +17dBm(4)
323
mA
327
mA
Wi-Fi Tx 802.11g, OFDM 6Mbps, Pout =
+18dBm(4)
47
GD32W515xx Datasheet
Power Mode
Description
Consumption
unit
289
mA
297
mA
272
mA
280
mA
267
mA
Wi-Fi Rx 802.11b, CCK 1Mbps, -90dBm(5)
101
mA
Wi-Fi Rx 802.11b, CCK 11Mbps, -80Bm(5)
102
mA
Wi-Fi Rx 802.11g, OFDM 6Mbps, -80dBm(5)
120
mA
Wi-Fi Rx 802.11g, OFDM 54Mbps,
-70dBm(5)
126
mA
Wi-Fi Rx 802.11n, HT 20M MCS0,
-75dBm(5)
120
mA
Wi-Fi Rx 802.11n, HT 20M MCS7,
-65dBm(5)
126
mA
Wi-Fi Rx 802.11n, HT 40M MCS0,
-72dBm(5)
124
mA
Wi-Fi Rx 802.11n, HT 40M MCS7,
-62dBm(5)
129
mA
56.5
mA
1.5
mA
0.75
mA
5.4
μA
—
mA
Wi-Fi Tx 802.11g, OFDM 54Mbps, Pout =
+15dBm(4)
Wi-Fi Tx 802.11n, HT 20M MCS0, Pout =
+16dBm(4)
Wi-Fi Tx 802.11n, HT 20M MCS7, Pout =
+13dBm(4)
Wi-Fi Tx 802.11n, HT 40M MCS0, Pout =
+14dBm(4)
Wi-Fi Tx 802.11n, HT 40M MCS7, Pout =
+12dBm(4)
Wi-Fi Sleep
MCU in Run
DTIM=1
Mild Sleep
DTIM=3
Hibernation
MCU in Standby
Shutdown
(1)
(2)
(3)
(4)
(5)
(6)
(7)
mode(6)
mode(7)
—
Below data are measured at antenna port of GD Wi-Fi Demo board.
Unless otherwise specified, all values given for TA condition and test result is mean value.
DC Power = 3.3 V, HXTAL = 40 MHz, System clock = 180 MHz.
Continuous Tx, Duty cycle = 100%.
Rx Packet Length = 1024 Bytes.
VDD = VDDA = 3.3 V, HXTAL = 40 MHz, System clock = 180 MHz, all peripherals enabled, except Wi-Fi.
VDD = VDDA = 3.3 V, LXTAL off, IRC32K on, RTC on.
Table 4-9. Power consumption characteristics (2)(3)(4)(5)(6)
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 180 MHz, All peripherals
—
56.5
—
mA
—
29.7
—
mA
—
52.9
—
mA
—
27.8
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
IDD+IDDA
Supply current
(Run mode)
System clock = 180 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 168 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 168 MHz, All peripherals
48
GD32W515xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
—
38.4
—
mA
—
20.5
—
mA
—
34.8
—
mA
—
18.6
—
mA
—
31.2
—
mA
—
16.8
—
mA
—
24
—
mA
—
13.2
—
mA
—
16.6
—
mA
—
9.5
—
mA
—
13
—
mA
—
7.7
—
mA
—
9.5
—
mA
—
5.8
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 120 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 25 MHz, PLL off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 25 MHz, PLL off, All
49
GD32W515xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
peripherals disabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 16 MHz, PLL off, All peripherals
—
7.8
—
mA
—
4.8
—
mA
—
5.5
—
mA
—
3.6
—
mA
—
4.4
—
mA
—
3.1
—
mA
—
3.8
—
mA
—
2.8
—
mA
—
43.1
—
mA
—
16.1
—
mA
—
40.3
—
mA
—
15.1
—
mA
—
29
—
mA
—
11
—
mA
enabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 16 MHz, PLL off, All peripherals
disabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 8 MHz, PLL off, All peripherals
enabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 8 MHz, PLL off, All peripherals
disabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 4 MHz, PLL off, All peripherals
enabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 4 MHz, PLL off, All peripherals
disabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 2 MHz, PLL off, All peripherals
enabled
VDD = VDDA = 3.3 V, use IRC16M, System
clock = 2 MHz, PLL off, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 180 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 180 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
Supply current
(Sleep mode)
System Clock = 168 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 168 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 120 MHz, CPU clock off,
50
GD32W515xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
—
26.2
—
mA
—
9.9
—
mA
—
23.4
—
mA
—
8.9
—
mA
—
17.7
—
mA
—
6.9
—
mA
—
12.1
—
mA
—
4.9
—
mA
—
9.3
—
mA
—
3.8
—
mA
—
6.4
—
mA
—
2.7
—
mA
—
5.3
—
mA
—
2.4
—
mA
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 25 MHz, PLL off, CPU
clock off, All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 25 MHz, PLL off, CPU
clock off, All peripherals disabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 16 MHz, PLL off, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 16 MHz, PLL off, CPU clock off, All
51
GD32W515xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
peripherals disabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 8 MHz, PLL off, CPU clock off, All
—
3.6
—
mA
—
1.7
—
mA
—
2.7
—
mA
—
1.4
—
mA
—
2.3
—
mA
—
1.3
—
mA
—
379.3
—
μA
—
325
—
μA
—
229.7
—
μA
—
200.8
—
μA
—
129
—
μA
—
5.75
—
μA
—
5.55
—
μA
—
5.25
—
μA
peripherals enabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 8 MHz, PLL off, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 4 MHz, PLL off, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 4 MHz, PLL off, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 2 MHz, PLL off, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, use IRC16M, System
Clock = 2 MHz, PLL off, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, LDO in normal power
and normal driver mode, IRC32K off, RTC
off, All GPIOs analog mode
VDD = VDDA = 3.3 V, LDO in low power and
normal driver mode, IRC32K off, RTC off,
All GPIOs analog mode
Supply current
(Deep-Sleep
mode)
VDD = VDDA = 3.3 V, LDO in normal power
and low driver mode, IRC32K off, RTC off,
All GPIOs analog mode
VDD = VDDA = 3.3 V, LDO in low power and
low driver mode, IRC32K off, RTC off, All
GPIOs analog mode
VDD = VDDA = 3.3 V, LDO in low power and
low driver mode, IRC32K off, RTC off, All
GPIOs analog mode, Wi-Fi、SRAM1、
SRAM2、SRAM3 sleep
VDD = VDDA = 3.3 V, LXTAL off, IRC32K on,
RTC on
Supply current VDD = VDDA = 3.3 V, LXTAL off, IRC32K on,
(Standby mode)
RTC off
VDD = VDDA = 3.3 V, LXTAL off, IRC32K off,
RTC off
52
GD32W515xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
VDD off, VDDA off, VBAT = 3.63V, LXTAL on
with external crystal, RTC on, LXTAL
—
1.98
—
μA
—
1.88
—
μA
—
1.77
—
μA
—
1.43
—
μA
—
1.57
—
μA
—
1.48
—
μA
—
1.37
—
μA
—
1.17
—
μA
—
1.16
—
μA
—
1.08
—
μA
—
0.97
—
μA
—
0.82
—
μA
—
1.03
—
μA
—
0.94
—
μA
Highest driving
VDD off, VDDA off, VBAT = 3.3V, LXTAL on
with external crystal, RTC on, LXTAL
Highest driving
VDD off, VDDA off, VBAT = 2.7V, LXTAL on
with external crystal, RTC on, LXTAL
Highest driving
VDD off, VDDA off, VBAT = 1.62V, LXTAL on
with external crystal, RTC on, LXTAL
Highest driving
VDD off, VDDA off, VBAT = 3.63V, LXTAL on
with external crystal, RTC on, LXTAL
Higher driving
VDD off, VDDA off, VBAT = 3.3V, LXTAL on
with external crystal, RTC on, LXTAL
Higher driving
VDD off, VDDA off, VBAT = 2.7V, LXTAL on
Battery supply
IBAT
current (Backup
mode)
with external crystal, RTC on, LXTAL
Higher driving
VDD off, VDDA off, VBAT = 1.62V, LXTAL on
with external crystal, RTC on, LXTAL
Higher driving
VDD off, VDDA off, VBAT = 3.63V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.3V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 2.7V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 1.62V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.63V, LXTAL on
with external crystal, RTC on, LXTAL
Lower driving
VDD off, VDDA off, VBAT = 3.3V, LXTAL on
with external crystal, RTC on, LXTAL
Lower driving
53
GD32W515xx Datasheet
Symbol
Parameter
Min Typ(1)
Conditions
Max
Unit
VDD off, VDDA off, VBAT = 2.7V, LXTAL on
with external crystal, RTC on, LXTAL
—
0.83
—
μA
—
0.68
—
μA
Lower driving
VDD off, VDDA off, VBAT = 1.62V, LXTAL on
with external crystal, RTC on, LXTAL
Lower driving
(1)
(2)
(3)
(4)
(5)
(6)
4.4.
Based on characterization, not tested in production.
Unless otherwise specified, all values given for TA condition and test result is mean value.
When System Clock is greater than 16 MHz, a crystal 25 MHz is used, and the HXTAL bypass function
is closed, using PLL.
When analog peripheral blocks such as ADCs, HXTAL, LXTAL, IRC16M, or IRC32K are ON, an additional
power consumption should be considered.
With large margin, it will be adjusted according to the mass production data.
When Wi-Fi power off.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result
is given in Table 4-10. EMS characteristics, based on the EMS levels and classes
compliant with IEC 61000 series standard.
Table 4-10. EMS characteristics (1)
Symbol
Parameter
Conditions
Level/Class
VDD = VDDA = AVDD33 = 3.3 V,
VESD
Voltage applied to all device pins to
TA = 25 °C, Wi-Fi on, QFN56,
induce a functional disturbance
fHCLK = 180 MHz
2A
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
induce a functional disturbance through
100 pF on VDD and GND
(1)
4.5.
VDD = VDDA = AVDD33 = 3.3 V,
TA = 25 °C, Wi-Fi on, QFN56,
4A
fHCLK = 180 MHz
conforms to IEC 61000-4-4
Based on characterization, not tested in production.
Power supply supervisor characteristics
Table 4-11. Power supply supervisor characteristics
Symbol
VLVD(1)
Parameter
Conditions
Min
Typ
Max
Unit
LVDT[2:0] = 000, rising edge
—
2.21
—
V
Low Voltage Detector
LVDT[2:0] = 000, falling edge
—
2.11
—
V
Threshold
LVDT[2:0] = 001, rising edge
—
2.37
—
V
LVDT[2:0] = 001, falling edge
—
2.25
—
V
54
GD32W515xx Datasheet
Symbol
VVLVD(1)
VLVDhyst(2)
VPOR(1)
VPDR(1)
VDDA Low Voltage
Detector Threshold
LVD hysteresis
Conditions
Min
Typ
Max
Unit
LVDT[2:0] = 010, rising edge
—
2.51
—
V
LVDT[2:0] = 010, falling edge
—
2.39
—
V
LVDT[2:0] = 011, rising edge
—
2.65
—
V
LVDT[2:0] = 011, falling edge
—
2.54
—
V
LVDT[2:0] = 100, rising edge
—
2.80
—
V
LVDT[2:0] = 100, falling edge
—
2.68
—
V
LVDT[2:0] = 101, rising edge
—
2.94
—
V
LVDT[2:0] = 101, falling edge
—
2.83
—
V
LVDT[2:0] = 110, rising edge
—
3.08
—
V
LVDT[2:0] = 110, falling edge
—
2.98
—
V
LVDT[2:0] = 111, rising edge
—
3.23
—
V
LVDT[2:0] = 111, falling edge
—
3.13
—
V
—
—
2.36
—
V
—
—
100
—
mV
—
1.55
—
V
—
1.51
—
V
Power on reset
threshold
Power down reset
threshold
—
VPDRhyst(2)
PDR hysteresis
—
40
—
mV
tRSTTEMPO(2)
Reset temporization
—
2.45
—
ms
(1)
(2)
4.6.
Parameter
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical
sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample.
Static latch-up (LU) test is based on the two measurement methods.
55
GD32W515xx Datasheet
Table 4-12. ESD characteristics
Symbol
Parameter
Electrostatic discharge
VESD(HBM)
VESD(CDM)
(1)
(2)
(1)
voltage (human body model)
Electrostatic discharge
voltage (charge device model)
Conditions
Min
Typ
Max
Unit
—
—
2000
V
—
—
500
V
Min
Typ
Max
Unit
—
—
±200
mA
—
—
5.4
V
TA = 25 °C;
ESDA/JEDEC JS-0012017
TA = 25 °C;
ESDA/JEDEC JS-0022018
Based on characterization, not tested in production.
There is space for adjustment, it will be tested soon.
Table 4-13. Static latch-up characteristics (1)
Symbol
Parameter
Conditions
I-test
LU
TA = 25 °C; JESD78E
Vsupply over voltage
4.7.
(1)
Based on characterization, not tested in production.
(2)
There is space for adjustment, it will be tested soon.
External clock characteristics
Table 4-14. High speed external clock (HXTAL) generated from a crystal / ceramic
characteristics
Symbol
fHXTAL
(1)
CHXTAL
(1)
(2)
(2)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency Range
—
19.2
40
52
MHz
Crystal load Capacitance
—
9
10
12
pF
ESR(2)
Equivalent Series Resistance
—
—
—
70
Ω
f_tol(2)
Frequency tolerance
-20
—
20
ppm
tSUHXTAL(1)
Crystal startup time
—
1.2
—
ms
Initial and over
temperature
VDD = 3.3 V, TA = 25 °C,
fHXTAL = 40 MHz
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-15. High speed external user clock characteristics (HXTAL in bypass
mode)
Symbol
Parameter
Conditions
Min
fHXTAL_ext(1)
Frequency Range
—
—
40
—
MHz
VHXTAL(2)
OSCIN Input Voltage
—
0.7
—
3.3
V
Duty cycle
—
45
50
55
%
@1kHz, fHXTAL = 40 MHz
—
—
-125 dBc/Hz
@10kHz fHXTAL = 40 MHz
—
—
-138 dBc/Hz
@100kHz fHXTAL = 40 MHz
—
—
-143 dBc/Hz
-20
—
Ducy(HXTAL)
PN(2)
f_tol(2)
(2)
Phase Noise
Frequency tolerance Initial and over temperature
Typ Max
20
Unit
ppm
56
GD32W515xx Datasheet
(1)
(2)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-16. Low speed external clock (LXTAL) generated from a crystal / ceramic
characteristics
fLXTAL
(1)
Parameter
Conditions
Min
Typ
Max Unit
Crystal or ceramic frequency
VDD = 3.3 V
—
32.768
—
kHz
—
—
15
—
pF
Lower driving capability
—
4.5
—
—
6.5
—
Recommended matching
CLXTAL
(2)(3)
capacitance on OSC32IN
and OSC32OUT
Medium low driving
gm(2)
Oscillator transconductance
capability
Medium high driving
capability
Higher driving capability
VDD = VDDA = 3.3 V,
Lower driving capability
VDD = VDDA = 3.3 V, Medium
IDDLXTAL
(1)
Crystal or ceramic operating
low driving capability
current
VDD = VDDA = 3.3 V, Medium
high driving capability
VDD = VDDA = 3.3 V, Higher
driving capability
tSULXTAL(1)(4)
(1)
(2)
(3)
(4)
Crystal or ceramic startup
time
VDD = 3.3 V
μA/V
—
13
—
—
19
—
—
0.8
—
—
0.94
—
μA
—
1.34
—
—
1.74
—
—
2
—
s
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on
OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or
ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance.
tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz
oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer.
Table 4-17. Low speed external user clock characteristics (LXTAL in bypass
57
GD32W515xx Datasheet
mode)
Symbol
Parameter
External clock source or
fLXTAL_ext(1)
oscillator frequency
4.8.
voltage
Typ
Max
Unit
VDD = 3.3 V
—
32.768
1000
kHz
0.7*VDD
—
—
VDD = 3.3 V
OSC32IN input pin low level
(2)
V
voltage
—
—
0.3*VDD
tH/L(LXTAL)(2)
OSC32IN high or low time
—
450
—
—
tR/F(LXTAL)(2)
OSC32IN rise or fall time
—
—
—
50
CIN(2)
OSC32IN input capacitance
—
—
5
—
pF
Duty cycle
—
30
—
70
%
Ducy(LXTAL)
(1)
(2)
Min
OSC32IN input pin high level
VLXTALH(2)
VLXTALL
Conditions
(2)
ns
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Internal clock characteristics
Table 4-18. High speed internal clock (IRC16M) characteristics
Symbol
fIRC16M
Parameter
High Speed Internal Oscillator
(IRC16 M) frequency
Conditions
Min
VDD = VDDA = 3.3 V
—
2.7 V ≤ VDD = VDDA ≤ 3.63 V,
IRC16 M oscillator Frequency
TA = -40 °C ~ +85
accuracy, Factory-trimmed
VDD = VDDA = 3.3 V,
ACCIRC16M
accuracy, User trimming step(1)
IDDAIRC16M(1)
tSUIRC16M(1)
(1)
(2)
IRC16 M oscillator duty cycle
IRC16 M oscillator operating
current
IRC16 M oscillator startup time
16
-1.6 to
1.3
—
MHz
—
%
-1
—
1
%
—
—
0.5
—
%
VDD = VDDA = 3.3 V
45
—
55
%
VDD = VDDA = 3.3 V
—
80
—
μA
VDD = VDDA = 3.3 V
—
1.5
—
μs
TA = 25°C
IRC16 M oscillator Frequency
DucyIRC16M(2)
—
°C(1)
Typ Max Unit
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-19. Low speed internal clock (IRC32K) characteristics
Symbol
Parameter
Low Speed Internal
fIRC32K(1)
oscillator (IRC32K)
frequency
IDDAIRC32K(2)
tSUIRC32K(2)
IRC32K oscillator
operating current
IRC32K oscillator startup
time
Conditions
Min
Typ
Max
Unit
—
32
—
kHz
VDD = VDDA = 3.3 V
—
0.4
—
μA
VDD = VDDA = 3.3 V
—
40
—
μs
VDD = VDDA = 3.3 V,
TA = -40 °C ~ +85 °C
58
GD32W515xx Datasheet
(1)
(2)
4.9.
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
PLL characteristics
Table 4-20. PLL characteristics
Symbol
fPLLIN
(1)
fPLLOUT
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
1
—
2
MHz
PLL output clock frequency
—
—
—
200
MHz
fVCO(2)
PLL VCO output clock frequency
—
—
—
400
MHz
tLOCK(2)
PLL lock time
—
—
—
300
μs
IDDA(2)
Current consumption on VDDA
VCO freq = 400 MHz
—
2
—
mA
—
30
—
(2)
Cycle to cycle Jitter
JitterPLL(3)
(rms)
Cycle to cycle Jitter
VCO freq = 360 MHz
(peak to peak)
(1)
(2)
(3)
ps
—
210
—
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Value given with main PLL running.
Table 4-21. PLLDIG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLIN(1)
PLL input clock frequency
—
19.2
40
52
MHz
fPLLOUT(2)
PLL output clock frequency
—
—
—
480
MHz
—
—
960
—
MHz
fVCO(2)
(1)
(2)
PLL VCO output clock
frequency
tLOCK(2)
PLL lock time
—
—
—
50
μs
IDDA(2)
Current consumption
—
—
3.5
—
mA
JitterPLL
Absolute RMS Jitter
XTAL freq = 40 MHz
—
6.5
—
ps
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-22. PLLI2S characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
2
—
16
MHz
fVCO(2)
PLL VCO output clock frequency
—
—
—
550
MHz
tLOCK(2)
PLL lock time
—
—
—
300
μs
IDDA(2)
Current consumption on VDDA
VCO freq = 550 MHz
—
1.5
—
mA
JitterPLL(3)
Cycle to cycle rms Jitter
System clock
—
40
—
ps
fPLLIN
(1)
(2)
(3)
(1)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Value given with main PLL running.
59
GD32W515xx Datasheet
4.10.
Memory characteristics
Table 4-23. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TA = -40 °C ~ +85 °C
100
—
—
kcycles
Data retention time
—
—
20
—
years
word programming time
TA = -40 °C ~ +105 °C
—
47.5
106
μs
TA = -40 °C ~ +105 °C
—
45
300
ms
TA = -40 °C ~ +105 °C
—
6
20
s
Number of guaranteed
PECYC(1)
program /erase cycles
before failure(Endurance)
tRET
(1)
tPROG
(2)
tERASE(2)
tMERASE(2)
(1)
(2)
(3)
4.11.
Page(3)
erase time
Mass erase time
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
4KB.
NRST pin characteristics
Table 4-24. NRST pin characteristics
Symbol
VIL(NRST)
(1)
VIH(NRST)
(1)
Vhyst(1)
Parameter
Conditions
NRST Input low level voltage
NRST Input high level voltage
Min
Typ
Max
-0.5
—
0.35 VDD
—
VDD + 0.5
VDD = VDDA = 2.7 V 0.65 VDD
Unit
V
Schmidt trigger Voltage hysteresis
—
250
—
(1)
NRST Input low level voltage
-0.5
—
0.35 VDD
VIH(NRST)(1)
NRST Input high level voltage
—
VDD + 0.5
Vhyst(1)
Schmidt trigger Voltage hysteresis
—
280
—
VIL(NRST)(1)
NRST Input low level voltage
-0.5
—
0.35 VDD
VIH(NRST)(1)
NRST Input high level voltage
—
VDD + 0.5
Vhyst(1)
Schmidt trigger Voltage hysteresis
—
300
—
mV
Rpu(2)
Pull-up equivalent resistor
—
40
—
kΩ
VIL(NRST)
(1)
(2)
VDD = VDDA = 3.3 V 0.65 VDD
VDD = VDDA = 3.63 V 0.65 VDD
—
mV
V
mV
V
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
60
GD32W515xx Datasheet
Figure 4-2. Recommended external NRST pin circuit(1)
VDD
VDD
External reset circuit
10 kΩ
RPU
NRST
K
100 nF
GND
(1)
4.12.
Unless the voltage on NRST pin go below VIL(NRST) level, the device would not generate a reliable reset.
GPIO characteristics
Table 4-25. I/O port DC characteristics (1)(3)
Symbol
Parameter
Standard IO Low
VIL
level input voltage
5V-tolerant IO Low
level input voltage
Standard IO Low
VIH
level input voltage
5V-tolerant IO Low
level input voltage
VOL
Low level output
(IO_speed = 166
voltage for an IO Pin
MHz)
(IIO = +8 mA)
VOL
Low level output
(IO_speed = 166
voltage for an IO Pin
MHz)
(IIO = +20 mA)
VOH
High level output
(IO_speed = 166
voltage for an IO Pin
MHz)
(IIO = +8 mA)
VOH
High level output
(IO_speed = 166
voltage for an IO Pin
MHz)
(IIO = +20 mA)
Conditions
Min
Typ
Max
Unit
1.62 V ≤ VDD ≤ 3.63 V
—
—
0.35 VDD
V
1.62 V ≤ VDD ≤ 3.63 V
—
—
0.35 VDD
V
1.62 V ≤ VDD ≤ 3.63 V 0.65 VDD
—
—
V
1.62 V ≤ VDD ≤ 3.63 V 0.65 VDD
—
—
V
V
VDD = 1.62V
—
0.142
—
VDD = 2.7V
—
0.1
—
VDD = 3.3 V
—
0.1
—
VDD = 3.63V
—
0.1
—
VDD = 1.62V
—
0.427
—
VDD = 2.7V
—
0.2
—
VDD = 3.3 V
—
0.2
—
VDD = 3.63V
—
0.2
—
VDD = 1.62V
—
1.406
—
VDD = 2.7V
—
2.6
—
VDD = 3.3 V
—
3.2
—
VDD = 3.63V
—
3.5
—
VDD = 1.62V
—
1.265
—
VDD = 2.7V
—
2.3
—
VDD = 3.3 V
—
3.0
—
VDD = 3.63V
—
3.3
—
V
V
V
V
V
V
V
61
GD32W515xx Datasheet
Symbol
VOL
(IO_speed = 25 MHz)
VOL
(IO_speed = 25 MHz)
VOH
(IO_speed = 25 MHz)
VOH
(IO_speed = 25 MHz)
VOL
(IO_speed = 10 MHz)
VOL
(IO_speed = 10 MHz)
VOH
(IO_speed = 10 MHz)
VOH
(IO_speed = 10 MHz)
VOL
(IO_speed = 2 MHz)
Parameter
Conditions
Min
Typ
Max
Unit
VDD = 1.62V
—
0.204
—
V
VDD = 2.7V
—
0.1
—
VDD = 3.3 V
—
0.1
—
VDD = 3.63V
—
0.1
—
VDD = 1.62V
—
1.477
—
VDD = 2.7V
—
0.3
—
VDD = 3.3 V
—
0.3
—
VDD = 3.63V
—
0.3
—
VDD = 1.62V
—
1.297
—
VDD = 2.7V
—
2.5
—
VDD = 3.3 V
—
3.1
—
VDD = 3.63V
—
3.4
—
VDD = 1.62V
—
1.125
—
VDD = 2.7V
—
2.2
—
VDD = 3.3 V
—
2.9
—
VDD = 3.63V
—
3.2
—
VDD = 1.62V
—
0.403
—
VDD = 2.7V
—
0.2
—
VDD = 3.3 V
—
0.2
—
VDD = 3.63V
—
0.2
—
VDD = 1.62V
—
1.381
—
VDD = 2.7V
—
0.5
—
VDD = 3.3 V
—
0.4
—
VDD = 3.63V
—
0.4
—
VDD = 1.62V
—
1.073
—
VDD = 2.7V
—
2.4
—
VDD = 3.3 V
—
3.1
—
VDD = 3.63V
—
3.4
—
VDD = 1.62V
—
0.927
—
VDD = 2.7V
—
2.1
—
VDD = 3.3 V
—
2.8
—
VDD = 3.63V
—
3.1
—
VDD = 1.62V
—
0.160
—
VDD = 2.7V
—
0.1
—
VDD = 3.3 V
—
0.1
—
VDD = 3.63V
—
0.1
—
VDD = 1.62V
—
0.359
—
Low level output
VDD = 2.7V
—
0.4
—
voltage for an IO Pin
VDD = 3.3 V
—
0.4
—
Low level output
voltage for an IO Pin
(IIO = +8 mA)
Low level output
voltage for an IO Pin
(IIO = +20 mA)
High level output
voltage for an IO Pin
(IIO = +8 mA)
High level output
voltage for an IO Pin
(IIO = +20 mA)
Low level output
voltage for an IO Pin
(IIO = +8 mA)
Low level output
voltage for an IO Pin
(IIO = +16 mA)
High level output
voltage for an IO Pin
(IIO = +8 mA)
High level output
voltage for an IO Pin
(IIO = +16 mA)
Low level output
voltage for an IO Pin
(IIO = +1 mA)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Low level output
voltage for an IO Pin
VOL
(IO_speed = 2 MHz)
V
(IIO = +2 mA)
V
62
GD32W515xx Datasheet
Symbol
VOH
(IO_speed = 2 MHz)
Parameter
Conditions
Min
Typ
Max
(IIO = +4 mA)
VDD = 3.63V
—
0.4
—
VDD = 1.62V
—
1.375
—
VDD = 2.7V
—
2.6
—
VDD = 3.3 V
—
3.2
—
VDD = 3.63V
—
3.5
—
VDD = 1.62V
—
1.130
—
High level output
voltage for an IO Pin
(IIO = +1 mA)
Unit
V
V
High level output
voltage for an IO Pin
VOH
(IIO = +2 mA)
(IO_speed = 2 MHz)
High level output
VDD = 2.7V
—
2.2
—
voltage for an IO Pin
VDD = 3.3 V
—
2.9
—
(IIO = +4 mA)
VDD = 3.63V
—
3.2
—
All pins
—
—
40
—
PU
—
—
10
—
All pins
—
—
40
—
PU
—
—
10
—
Internal
RPU
(2)
Internal
RPD
V
kΩ
pull-up
resistor
(2)
V
pull-down
resistor
kΩ
(1) Based on characterization, not tested in production.
(2) Guaranteed by design, not tested in production.
(3) All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which
can only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz
when they are in output mode (maximum load: 30 pF).
Table 4-26. I/O port AC characteristics (1)(2)
GPIOx_MDy[1:0] bit value(3)
Parameter
GPIOx_CTL->MDy[1:0]=10
Maximum
(IO_Speed = 2 MHz)
frequency(4)
GPIOx_CTL->MDy[1:0] = 01
Maximum
(IO_Speed = 10 MHz)
frequency(4)
GPIOx_CTL->MDy[1:0]=11
Maximum
(IO_Speed = 25 MHz)
frequency(4)
GPIOx_CTL->MDy[1:0]=11(IO_S
peed = 166 MHz)
(1)
(2)
(3)
(4)
Maximum
frequency(4)
Conditions
Typ
1.62 V ≤ VDD ≤ 3.63 V , CL = 10pF
5
1.62 V ≤ VDD ≤ 3.63 V , CL = 30pF
4
1.62 V ≤ VDD ≤ 3.63 V , CL = 50pF
4
1.62 V ≤ VDD ≤ 3.63 V , CL = 10pF
25
1.62 V ≤ VDD ≤ 3.63 V , CL = 30pF
23
1.62 V ≤ VDD ≤ 3.63 V , CL = 50pF
22
1.62 V ≤ VDD ≤ 3.63 V , CL = 10pF
86
1.62 V ≤ VDD ≤ 3.63 V , CL = 30pF
61
1.62 V ≤ VDD ≤ 3.63 V, CL = 50pF
53
1.62 V ≤ VDD ≤ 3.63 V, CL = 10pF
180
1.62 V ≤ VDD ≤ 3.63 V , CL = 30pF
155
1.62 V ≤ VDD ≤ 3.63 V , CL = 50pF
133
Unit
MHz
MHz
MHz
MHz
Based on characterization, not tested in production.
Unless otherwise specified, all test results given for TA = 25 ℃.
The I/O speed is configured using the GPIOx_OSPD0->OSPDy [1:0] bits. Refer to the GD32W515xx user
manual which is selected to set the GPIO port output speed.
The maximum frequency is defined in Figure 4-3, and maximum frequency cannot exceed 100 MHz.
63
GD32W515xx Datasheet
Figure 4-3. I/O port AC characteristics definition
90%
90%
50%
50%
10%
EXTERNAL
OUTPUT
ON 50pF
10%
tf(IO)out
tr(IO)out
T
If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved.
The duty cycle is (45%-55%) when loaded by 50 pF.
4.13.
ADC characteristics
Table 4-27. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.7
3.3
3.6
V
VIN(1)
ADC input voltage range
—
0
—
VDDA
V
fADC(1)
ADC clock
—
0.1
—
35
MHz
fS(1)
Sampling rate
12-bit
0.007
—
2.5
MSPS
Analog input voltage
9 external; 3 internal
0
—
VDDA
V
External input impedance
See Equation 1
—
—
440.7
kΩ
—
—
—
0.5
kΩ
—
—
3.2
pF
(1)
VAIN
RAIN(2)
RADC(2)
Input sampling switch
resistance
CADC(2)
ts(2)
Input sampling
No pin / pad capacitance
capacitance
included
Sampling time
fADC = 35 MHz
0.04
—
13.7
μs
12-bit
—
14
—
1 / fADC
—
—
—
1
μs
Total conversion
tCONV(2)
time(including sampling
time)
tSU(2)
(1)
(2)
Startup time
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Equation 1: RAIN max formula R AIN <
Ts
fADC *CADC *ln(2N+2 )
-R ADC
The formula above (Equation 1) is used to determine the maximum external impedance allowed
for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-28. ADC RAIN max for fADC = 35 MHz (1)
Ts(cycles)
ts(μs)
RAINmax(kΩ)
1.5
0.04
0.88
14.5
0.41
12.84
27.5
0.79
24.80
64
GD32W515xx Datasheet
(1)
Ts(cycles)
ts(μs)
RAINmax(kΩ)
55.5
1.59
50.57
83.5
2.39
76.33
111.5
3.19
102.1
143.5
4.10
131.5
479.5
13.7
440.7
Based on characterization, not tested in production.
Table 4-29. ADC dynamic accuracy at f ADC = 35 MHz (1)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC = 35 MHz,
—
10.6
—
bits
SNDR
Signal-to-noise and distortion ratio
VDDA = 3.3 V,
—
65.7
—
SNR
Signal-to-noise ratio
Input Frequency = 20
—
66.5
—
—
-72
—
kHz,
THD
(1)
Total harmonic distortion
Temperature = 25℃
dB
Based on characterization, not tested in production.
Table 4-30. ADC static accuracy at fADC = 35 MHz
Symbol
Parameter
Offset
Offset error
DNL
Differential linearity error
INL
Integral linearity error
(1)
4.14.
Test conditions
Typ(1) Max
fADC = 35 MHz,
VDDA = 3.3 V
±1
—
±1
—
±2
—
Unit
LSB
Based on characterization, not tested in production.
Temperature sensor characteristics
Table 4-31. Temperature sensor characteristics (1)
Symbol
Parameter
Min
Typ
Max
Unit
TL
VSENSE linearity with temperature
—
±1
—
℃
Avg_Slope
Average slope
—
4.3
—
mV/℃
V25
Voltage at 25 °C
—
1.42
—
V
Startup time
—
8
—
μs
ADC sampling time when reading the temperature
—
13.7
—
μs
tSTART
tS_temp
(1)
(2)
(2)
Based on characterization, not tested in production.
Shortest sampling time can be determined in the application by multiple iterations.
65
GD32W515xx Datasheet
4.15.
I2C characteristics
Table 4-32. I2C characteristics (1)(2)(3)
Standard
Symbol
tSCL(H)
Parameter
SCL clock high
time
Conditions
mode
Fast mode
Fast mode
plus
Unit
Min
Max
Min
Max
Min
Max
—
4.0
—
0.6
—
0.2
—
μs
tSCL(L)
SCL clock low time
—
4.7
—
1.3
—
0.5
—
μs
tsu(SDA)
SDA setup time
—
250
—
100
—
50
—
ns
—
0(3)
3450
0
900
0
450
ns
—
—
1000
—
300
—
120
ns
—
—
300
3(4)(5)
300
3(4)(6)
120
ns
—
4.0
—
0.6
—
0.26
—
μs
—
4.7
—
0.6
—
0.26
—
μs
—
4.0
—
0.6
—
0.26
—
μs
—
4.7
—
1.3
—
0.5
—
μs
th(SDA)
tr(SDA/SCL)
tf(SDA/SCL)
th(STA)
SDA data hold time
SDA and SCL rise
time
SDA and SCL fall
time
Start condition hold
time
Repeated Start
ts(STA)
condition
setup time
ts(STO)
Stop condition
setup time
Stop to Start
tbuff
condition time (bus
free)
(1)
(2)
(3)
(4)
(5)
(6)
Guaranteed by design, not tested in production.
To ensure the standard mode I2C frequency, fPCLK1 must be at least 2 MHz. To ensure the fast mode I2C
frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode plus I2C frequency, f PCLK1 must be at
least a multiple of 10 MHz.
The external device should provide a data hold time of 300 ns at least in order to bridge the undefined
region of the falling edge of SCL.
Based on characterization, not tested in production.
In the condition of I2C frequency = 400 kHz, IO_Speed = 50 MHz and Pull-up resistor = 1 kΩ.
In the condition of I2C frequency = 1 MHz, IO_Speed = 50 MHz and Pull-up resistor = 1 kΩ.
66
GD32W515xx Datasheet
Figure 4-4. I2C bus timing diagram
tsu(STA)
SDA
70%
30%
tf(SDA)
tr(SDA)
tSCL(H)
th(STA)
SCL
tbuff
th(SDA)
tsu(SDA)
70%
30%
tSCL(L)
4.16.
tr(SCL)
tf(SCL)
tsu(STO)
SPI characteristics
Table 4-33. Standard SPI characteristics
Symbol
Parameter
fSCK
SCK clock frequency
tsck(H)
SCK clock high time
tsck (L)
SCK clock low time
(1)
Conditions
VDD = VDDA = 3.3 V
Min
Typ
Max
Unit
—
—
22.5
MHz
—
22.22
—
ns
—
22.22
—
ns
—
—
7
ns
2
—
—
ns
0
—
—
ns
0
—
—
ns
2
—
—
ns
—
6
—
ns
—
9
—
ns
—
9
—
ns
0
—
—
ns
1
—
—
ns
SPI master mode
tV(MO)
Data output valid time
tSU(MI)
Data input setup time
tH(MI)
Data input hold time
VDD = VDDA = 3.3 V
SPI slave mode
(1)
tSU(NSS)
NSS enable setup time
tH(NSS)
NSS enable hold time
tA(SO)
Data output access time
tDIS(SO)
Data output disable time
tV(SO)
Data output valid time
tSU(SI)
Data input setup time
tH(SI)
Data input hold time
VDD = VDDA = 3.3 V,
fPCLK = 90 MHz
VDD = VDDA = 3.3 V
Based on characterization, not tested in production.
67
GD32W515xx Datasheet
Figure 4-5. SPI timing diagram - master mode
tSCK
SCK (CKPH=0 CKPL=0)
SCK (CKPH=0 CKPL=1)
SCK (CKPH=1 CKPL=0)
tSCK(H)
tSCK(L)
SCK (CKPH=1 CKPL=1)
tSU(MI)
MISO
D[0]
LF=1,FF16=0
D[7]
tH(MI)
D[0]
MOSI
D[7]
tH(MO)
tV(MO)
Figure 4-6. SPI timing diagram - slave mode
NSS
tSCK
tSU(NSS)
SCK (CKPH=0 CKPL=0)
tSCK(H)
SCK (CKPH=0 CKPL=1)
tSCK(L)
tH(NSS)
tH(SO)
tDIS(SO)
tV(SO)
tA(SO)
MISO
D[0]
D[7]
tSU(SI)
D[0]
MOSI
D[7]
tH(SI)
4.17.
I2S characteristics
Table 4-34. I2S characteristics (1)
Symbol
Parameter
fCK
Clock frequency
Conditions
Master mode (data: 32 bits,
Audio frequency = 96 kHz)
Min
Typ
Max
Unit
—
6.25
—
MHz
68
GD32W515xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Slave mode
—
—
12.5
—
81
—
ns
—
81
—
ns
tH
Clock high time
tL
Clock low time
tV(WS)
WS valid time
Master mode
—
3
—
ns
tH(WS)
WS hold time
Master mode
—
3
—
ns
tSU(WS)
WS setup time
Slave mode
0
—
—
ns
tH(WS)
WS hold time
Slave mode
2
—
—
ns
Slave mode
—
50
—
%
Ducy(SCK)
fCK = 6.25 MHz
I2S slave input clock duty
cycle
tSU(SD_MR)
Data input setup time
Master mode
2
—
—
ns
tSU(SD_SR)
Data input setup time
Slave mode
0
—
—
ns
Master receiver
0
—
—
ns
Slave receiver
1
—
—
ns
—
—
9
ns
3
—
—
ns
—
—
9
ns
0
—
—
ns
tH(SD_MR)
Data input hold time
tH(SD_SR)
tV(SD_ST)
Data output valid time
tH(SD_ST)
Data output hold time
tV(SD_MT)
Data output valid time
tH(SD_MT)
Data output hold time
(1)
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
Based on characterization, not tested in production.
Figure 4-7. I2S timing diagram - master mode
tCK
CPOL=0
tL
CPOL=1
tV(WS)
tH
tH(WS)
WS output
tV(SD_MT)
SD transmit
SD receive
tH(SD_MT)
D[0]
D[0]
tSU(SD_MR)
tH(SD_MR)
69
GD32W515xx Datasheet
Figure 4-8. I2S timing diagram - slave mode
tCK
CPOL=0
tL
CPOL=1
tH
tH(WS)
WS input
tSU(WS)
tH(SD_ST)
tV(SD_ST)
SD transmit
D[0]
SD receive
D[0]
tSU(SD_SR)
tH(SD_SR)
4.18.
USART characteristics
Table 4-35. USART characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 45 MHz
—
—
22.5
MHz
tSCK(H)
SCK clock high time
fPCLKx = 45 MHz
22.22
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 45 MHz
22.22
—
—
ns
(1)
Guaranteed by design, not tested in production.
70
GD32W515xx Datasheet
4.19.
SDIO characteristics
Table 4-36. SDIO characteristics (1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP(3)
Clock frequency in data transfer mode
—
0
—
48
MHz
tW(CKL)(3)
Clock low time
fpp = 48 MHz
10.5
11
—
ns
(3)
Clock high time
fpp = 48 MHz
9.5
10
—
ns
tW(CKH)
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU(4)
Input setup time HS
fpp = 48 MHz
4
—
—
ns
tIH(4)
Input hold time HS
fpp = 48 MHz
3
—
—
ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV(3)
Output valid time HS
fpp = 48 MHz
—
—
13.8
ns
tOH(3)
Output hold time HS
fpp = 48 MHz
12
—
—
ns
CMD, D inputs (referenced to CK) in SD default mode
tISUD(4)
Input setup time SD
fpp = 24 MHz
3
—
—
ns
tIHD(4)
Input hold time SD
fpp = 24 MHz
3
—
—
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD(3)
Output valid default time SD
fpp = 24 MHz
—
2.4
2.8
ns
tOHD(3)
Output hold default time SD
fpp = 24 MHz
0.8
—
—
ns
(1)
(2)
(3)
(4)
4.20.
CLK timing is measured at 50% of VDD.
Capacitive load CL = 30 pF.
Based on characterization, not tested in production.
Guaranteed by design, not tested in production
USBFS characteristics
Table 4-37. USBFS start up time
Symbol
Parameter
Max
Unit
tSTARTUP(1)
USBFS startup time
1
μs
(1)
Guaranteed by design, not tested in production.
71
GD32W515xx Datasheet
Table 4-38. USBFS DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
USBFS operating voltage
—
3
—
3.6
VDI Differential input sensitivity
—
0.2
—
—
Includes VDI range
0.8
—
2.5
—
1.3
—
2.0
VDD
Input
levels(1)
VCM
Differential common mode
range
Single ended receiver
VSE
threshold
Max Unit
V
Output VOL
Static output level low
RL of 1.0 kΩ to 3.6 V
—
0.002
0.3
levels (2)
Static output level high
RL of 15 kΩ to GND
2.8
3.48
3.6
17
19.02
24
0.65
—
2.0
1.5
1.589
2.1
0.25
—
0.55
VOH
PB13,
PB12(USBFS_DM/DP)
RPD(2)
VIN = VDD
PB14(USBFS_VBUS)
PB13,
PB12(USBFS_DM/DP)
RPU(2)
VIN = GND
PB14(USBFS_VBUS)
(1)
(2)
V
kΩ
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Table 4-39. USBFS full speed-electrical characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tR
Rise time
CL = 50 pF
4
—
20
ns
tF
Fall time
CL = 50 pF
4
—
20
ns
tRFM
Rise / fall time matching
tR / tF
90
—
110
%
vCRS
Output signal crossover voltage
—
1.3
—
2.0
V
(1)
Guaranteed by design, not tested in production.
Figure 4-9. USBFS timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
VCRS
VSS
tf
4.21.
tr
TIMER characteristics
Table 4-40. TIMER characteristics (1)
Symbol
Parameter
tres
Timer resolution time
fEXT
RES
Conditions
Min
Max
Unit
—
1
—
tCK_TIMERx
fCK_TIMERx = 180 MHz
5.56
—
ns
Timer external clock
—
0
2*fCK_TIMERx
MHz
frequency
fCK_TIMERx = 180 MHz
0
360
MHz
Timer resolution
TIMERx except
—
16
bit
72
GD32W515xx Datasheet
Symbol
Parameter
Conditions
Min
Max
Unit
TIMER1& TIMER2
—
32
—
1
65536
tCK_TIMERx
364
μs
(TIMER1& TIMER2)
16-bit counter clock period
when internal clock is
tCOUNTER
fCK_TIMERx = 180 MHz 0.0056
selected
—
1
fCK_TIMERx = 180 MHz
—
Maximum possible count
—
—
(32-bit)
fCK_TIMERx = 180 MHz
—
32-bit counter clock period
when internal clock is
selected
tMAX_COUNT
(1)
4.22.
65536x65536 tCK_TIMERx
23.9
s
65536x65536 tCK_TIMERx
23.9
s
Guaranteed by design, not tested in production.
WDGT characteristics
Table 4-41. FWDGT min/max timeout period at 32 kHz (IRC32K) (1)
Min timeout
Max timeout
RLD[11:0] =0x000
RLD[11:0] = 0xFFF
000
0.03125
511.90625
1/8
001
0.03125
1023.78125
1/16
010
0.03125
2047.53125
1/32
011
0.03125
4095.03125
1/64
100
0.03125
8190.03125
1/128
101
0.03125
16380.03125
1/256
110 or 111
0.03125
32760.03125
Prescaler divider
PSC[2:0] bits
1/4
(1)
Unit
ms
Guaranteed by design, not tested in production.
Table 4-42. WWDGT min-max timeout value at 45 MHz (fPCLK1) (1)
PSC[2:0]
1/1
00
91.02
1/2
01
182.04
1/4
10
364.09
1/8
11
728.18
(1)
4.23.
Min timeout value
Prescaler divider
CNT[6:0] = 0x40
Max timeout value
Unit
CNT[6:0] = 0x7F
Unit
5.83
11.65
μs
ms
23.30
46.60
Guaranteed by design, not tested in production.
HPDF Characteristics
Table 4-43. HPDF characteristics (1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHPDFCLK
HPDF clock
—
—
fAPB2
fSYSCLK
MHz
73
GD32W515xx Datasheet
Symbol
Parameter
fCKIN
Input clock
(1 / TCKIN)
frequency
fCKOUT
Output clock
frequency
Conditions
Min
Typ
Max
Unit
20
SPI mode(SITYP[1:0]=01)
—
—
(fHPDFCLK /
4)
—
—
—
20
—
30
50
75
Output clock
DutyCKOUT
frequency duty
%
cycle
twh(CKIN)
Input clock high and
twl(CKIN)
low time
tSU
Data input setup
time
SPI mode(SITYP[1:0]=01),
External clock
mode(SPICKSS[1:0]=0)
TCKIN / 2- TCKIN /
0.5
2
—
ns
SPI mode(SITYP[1:0]=01),
External clock
1
—
—
1
—
—
mode(SPICKSS[1:0]=0)
SPI mode(SITYP[1:0]=01),
th
Data input hold time
External clock
mode(SPICKSS[1:0]=0)
Manchester data
TManchester
period(recovered
clock period)
(1)
(2)
Manchester
mode(SITYP[1:0]=10 or 11),
Internal clock
mode(SPICKSS[1:0]≠0)
(CKOUT
DIV+1)*T
HPDFCLK
(2*CKOU
—
TDIV)*TH
PDFCLK
Guaranteed by design, not tested in production.
Output speed is set to OSPEEDRy[1:0]=10；Capacitive load C = 30 pF；Measurement points are done
at COMS levels: 0.5*VDD.
74
GD32W515xx Datasheet
4.24.
Serial / Quad Parallel Interface (SQPI) Characteristics
Table 4-44. SQPI characteristics
Symbol
Parameter
Min
Typ
Max
Unit
CLK period
11.0(4)
—
—
ns
CLK high level duty for even clock divided
45
50
55
CLK high level duty for odd clock divided
45
—
71
tKHKL(1)(3)
CLK rise or fall time
—
2.0
—
ns
tCPH(2)
CE# high between subsequent burst operations
22.2
—
—
ns
tCEM(2)
CE# low pulse width
88.8
—
—
ns
tCSP(2)
CE# setup time to CLK rising edge
5.5
—
177.7
ns
tCHD(2)
CE# hold time from CLK rising edge
5.5
—
177.7
ns
tSP(2)
Setup time to active CLK edge
5.5
—
177.7
ns
tHD(2)
Hold time from active CLK edge
5.5
—
177.7
ns
CE# rise to data output high-Z
—
0
—
ns
CLK fall to data output valid delay
—
0
—
ns
Data hold time from CLK falling edge
—
0
—
ns
tCLK(2)
tCD(2)
tHZ
(2)
tACLK(2)
(2)
tKOH
(1)
(2)
(3)
(4)
4.25.
%
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Output driven mode is 50 MHz. Measured from 10% to 90% of VDD.
This is designed minimal period. The operating minimal clock period is 22.2 ns (45 MHz = 180 MHz / 4).
Wi-Fi Radio characteristics
Below data are measured at antenna port of GD Wi-Fi Demo board.
Table 4-45. Transmitter power characteristics (1)(2)
Parameter
Tx Power
(1)
(2)
Rate
Typ
11b
21
11g
18.3
11n, BW20M
17.3
11n, BW40M
17.3
Unit
dBm
Tx Power level is Limited by 802.11 Mask & EVM spec.
Based on characterization, not tested in production.
Table 4-46. Receiver sensitivity characteristics (1)
Parameter
Rx Sensitivity
Rate
Typ
11b,1Mbps
-97.6
11b,2Mbps
-94.4
11b,5.5Mbps
-92.1
11b,11Mbps
-87.6
11g,6Mbps
-94.3
11g,9Mbps
-92.5
Unit
dBm
75
GD32W515xx Datasheet
Parameter
(1)
Rate
Typ
11g,12Mbps
-91.0
11g,18Mbps
-89.1
11g,24Mbps
-84.6
11g,36Mbps
-82.4
11g,48Mbps
-77.0
11g,54Mbps
-76.3
11n,HT20,MCS0
-94.0
11n,HT20,MCS1
-90.3
11n,HT20,MCS2
-88.5
11n,HT20,MCS3
-84.4
11n,HT20,MCS4
-82.0
11n,HT20,MCS5
-76.6
11n,HT20,MCS6
-75.6
11n,HT20,MCS7
-74.2
11n,HT40,MCS0
-89.6
11n,HT40,MCS1
-85.4
11n,HT40,MCS2
-83.5
11n,HT40,MCS3
-80.3
11n,HT40,MCS4
-77.9
11n,HT40,MCS5
-72.7
11n,HT40,MCS6
-71.8
11n,HT40,MCS7
-70.7
Unit
Based on characterization, not tested in production.
Table 4-47. Rx Maximum Input Level (1)(2)
Parameter
Rx Maximum Level Input
(1)
(2)
Rate
Typ
11b,1Mbps
>8.5(1)
11b,11Mbps
>8.5(1)
11g,6Mbps
>8.5(1)
11g,54Mbps
4.6
11n,HT20,MCS0
>8.5(1)
11n,HT20,MCS7
3.7
11n,HT40,MCS0
5.2
11n,HT40,MCS7
3.7
Unit
dBm
IQxel VSG max TX power = 10 dBm, cable loss = 1.5 dB => max input power = 8.5 dBm.
Based on characterization, not tested in production.
76
GD32W515xx Datasheet
Table 4-48. Adjacent Channel Rejection
(1)(4)
Typ
Parameter
Rate
Interference pattern
by
Adjacent Channel
Rejection
4.26.
IQxel(2)
In-house
interference
pattern(3)
11b, 11Mbps
47.4
48
11g, 6Mbps
34.6
46
11g, 54Mbps
15.0
25
11n, HT20,MCS0
31.8
45
11n,HT20,MCS7
12.3
20
11n,HT40,MCS0
17.1
32
11n,HT40,MCS7
8.6
16
(1)
(2)
(3)
ACR result depends on interference source.
Waveform generated by LitePoint IQxel series instrument, gap = SIFS
Waveform generated by GD32W515xx baseband, gap = SIFS
(4)
Based on characterization, not tested in production.
Unit
dB
Parameter conditions
Unless otherwise specified, all values given for V DD = VDDA = AVDD33_ANA = AVDD33_PA =
AVDD33_CLK = 3.3 V, TA = 25 ℃.
77
GD32W515xx Datasheet
5.
Package information
5.1.
QFN56 package outline dimensions
Figure 5-1. QFN56 package outline
D2
L
D
h
56
1
56
PIN 1#
Laser Mark
1
2
E2
e
b
Nd
TOP VIEW
K
Ne
E
h
2
EXPOSED THERMAL
PAD ZONE
c
A1
A
BOTTOM VIEW
SIDE VIEW
Table 5-1. QFN56 package dimensions
Symbol
Min
Typ
Max
A
0.70
0.75
0.80
A1
—
0.02
0.05
b
0.15
0.20
0.25
c
0.18
0.20
0.25
D
6.90
7.00
7.10
D2
5.10
5.20
5.30
E
6.90
7.00
7.10
E2
5.10
5.20
5.30
e
—
0.40
—
h
0.30
0.35
0.40
K
0.20
—
—
L
0.35
0.40
0.45
Nd
—
5.20
—
Ne
—
5.20
—
(Original dimensions are in millimeters)
78
GD32W515xx Datasheet
Figure 5-2. QFN56 recommended footprint
7.70
43
56
6.10
1
5.45
7.70
5.15
0.25
42
5.15
14
28
15
29
0.80
0.40
(Original dimensions are in millimeters)
79
GD32W515xx Datasheet
QFN36 package outline dimensions
Figure 5-3. QFN36 package outline
D
b
K
b1
36
L
36
PIN 1#
Laser Mark
1
h
1
2
2
Ne
E
E2
h
D2
e
Nd
EXPOSED THERMAL
PAD ZONE
BOTTOM VIEW
A1
A
TOP VIEW
c
5.2.
SIDE VIEW
Table 5-2. QFN36 package dimensions
Symbol
Min
Typ
Max
A
0.70
0.75
0.80
A1
0
0.02
0.05
b
0.15
0.20
0.25
b1
—
0.14
—
c
—
0.203
—
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
e
—
0.40
—
h
0.30
0.35
0.40
K
—
0.35
—
L
0.35
0.40
0.45
Nd
—
3.20
—
Ne
—
3.20
—
(Original dimensions are in millimeters)
80
GD32W515xx Datasheet
Figure 5-4. QFN36 recommended footprint
5.70
36
28
4.10
1
3.45
5.70
3.45
0.25
27
3.45
9
18
10
19
0.80
0.40
(Original dimensions are in millimeters)
81
GD32W515xx Datasheet
5.3.
Thermal characteristics
Thermal resistance is used to characterize the thermal performance of the package
device, which is represented by the Greek letter “θ”. For semiconductor devices, thermal
resistance represents the steady-state temperature rise of the chip junction due to the
heat dissipated on the chip surface.
θJA: Thermal resistance, junction-to-ambient.
θJB: Thermal resistance, junction-to-board.
θJC: Thermal resistance, junction-to-case.
ᴪJB: Thermal characterization parameter, junction-to-board.
ᴪJT: Thermal characterization parameter, junction-to-top center.
θJA =(TJ -TA )/PD
(5-1)
θJB =(TJ -TB )/PD
(5-2)
θJC =(TJ -TC )/PD
(5-3)
Where, TJ = Junction temperature.
TA = Ambient temperature
TB = Board temperature
TC = Case temperature which is monitoring on package surface
PD = Total power dissipation
θJA represents the resistance of the heat flows from the heating junction to ambient air. It
is an indicator of package heat dissipation capability. Lower θJA can be considerate as
better overall thermal performance. θJA is generally used to estimate junction temperature.
θJB is used to measure the heat flow resistance between the chip surface and the PCB
board.
θJC represents the thermal resistance between the chip surface and the package top case.
θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other
heat dissipation methods outside the device package).
Table 5-3. Package thermal characteristics(1)
Symbol
Condition
θJA
Natural convection, 2S2P PCB
θJB
Cold plate, 2S2P PCB
θJC
Cold plate, 2S2P PCB
Package
Value
QFN56
38.32
QFN36
42.58
QFN56
17.23
QFN36
12.22
QFN56
13.28
QFN36
16.76
Unit
°C/W
°C/W
°C/W
82
GD32W515xx Datasheet
Symbol
Condition
ᴪJB
Natural convection, 2S2P PCB
ᴪJT
Natural convection, 2S2P PCB
(1)
Package
Value
QFN56
17.48
QFN36
12.81
QFN56
2.90
QFN36
0.69
Unit
°C/W
°C/W
Thermal characteristics are based on simulation, and meet JEDEC specification.
83
GD32W515xx Datasheet
6.
Ordering information
Table 6-1. Part ordering code for GD32W515xx devices
Ordering code
Flash (KB)
Package
Package type
GD32W515PIQ6
2048
QFN56
Green
GD32W515P0Q6
0
QFN56
Green
GD32W515TIQ6
2048
QFN36
Green
GD32W515TGQ6
1024
QFN36
Green
Temperature
operating range
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
84
GD32W515xx Datasheet
7.
Revision history
Table 7-1. Revision history
Revision No.
Description
Date
1.0
Initial Release
Nov.23, 2021
1.
Update the I2C characteristics in Table 7-2.
2.
Change the 16-bit general timers from five to four in
chapter 3.15.
3.
1.1
Delete TRACED0~3 in chapter 2.6, refers to Pin
definitions.
4.
Update the I/O port DC characteristics in Table 7-3.
5.
Change the title of chapter 3.2 from Embedded memory
Jul.12, 2022
to On-chip memory.
6.
Add the pin definitions of USARTx_DE.
85
GD32W515xx Datasheet
Important Notice
This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including
any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property
laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The Company reserves all rights under
such laws and treaties and does not grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. The names and brands of third party referred thereto (if any) are the property of their respective owner and referred to for
identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product, including, but not
limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company does not assume any
liability arising out of the application or use of any Product described in this document. Any information provided in this document
is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test
the functionality and safety of any application made of this information and any resulting product. Except for customized products
which has been expressly identified in the applicable agreement, the Products are designed, developed, and/or manufactured
for ordinary business, industrial, personal, and/or household applications only. The Products are not designed, intended, or
authorized for use as components in systems designed or intended for the operation of weapons, weapons systems, nuclear
installations, atomic energy control instruments, combustion control instruments, airplane or spaceship instruments,
transportation instruments, traffic signal instruments, life-support devices or systems, other medical devices or systems (including
resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the
failure of the device or Product could cause personal injury, death, property or environmental damage ("Unintended Uses").
Customers shall take any and all actions to ensure using and selling the Products in accordance with the applicable laws and
regulations. The Company is not liable, in whole or in part, and customers shall and hereby do release the Company as well as
it’s suppliers and/or distributors from any claim, damage, or other liability arising from or related to all Unintended Uses of the
Products. Customers shall indemnify and hold the Company as well as it’s suppliers and/or distributors harmless from and against
all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any
Unintended Uses of the Products.
Information in this document is provided solely in connection with the Products. The Company reserves the right to make changes,
corrections, modifications or improvements to this document and Products and services described herein at any time, without
notice.
© 2022 GigaDevice – All rights reserved
86
工商网监
湘ICP备2023018690号
