16 Mbit (x8/x16) Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
GLS36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash
FEATURES:
• Organized as 1M x16 or 2M x8
• Dual Bank Architecture for Concurrent
Read/Write Operation
– 16 Mbit Bottom Sector Protection
- GLS36VF1601G: 4 Mbit + 12 Mbit
– 16 Mbit Top Sector Protection
- GLS36VF1602G: 12 Mbit + 4 Mbit
• Single 2.7-3.6V for Read and Write Operations
• Superior Reliability
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
• Hardware Sector Protection/WP# Input Pin
– Protects the 4 outermost sectors (8 KWord)
in the smaller bank by driving WP# low and
unprotects by driving WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
array data
• Byte# Pin
– Selects 8-bit or 16-bit mode
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Chip-Erase Capability
• Block-Erase Capability
– Uniform 32 KWord blocks
• Erase-Suspend / Erase-Resume Capabilities
• Security ID Feature
– Greenliant: 128 bits
– User: 256 Byte
• Fast Read Access Time
– 70 ns
• Latched Address and Data
• Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• Conforms to Common Flash Memory Interface (CFI)
• JEDEC Standards
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
– 56-ball LFBGA (8mm x 10mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The GLS36VF1601G and GLS36VF1602G are 1M x16 or
2M x8 CMOS Concurrent Read/Write Flash Memory manufactured with high performance SuperFlash memory technology. The split-gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability compared with alternate approaches. The devices write (Program or Erase) with a 2.7-3.6V power supply and conform
to JEDEC standard pinouts for x8/x16 memories.
Featuring high performance Program, the GLS36VF160xG
provide a typical Program time of 7 µsec and use Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inadvertent write, the devices have on-chip hardware and Soft-
©2010 Greenliant Systems, Ltd.
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the
GLS36VF160xG significantly improve performance and
reliability, while lowering power consumption. These
devices inherently use less energy during Erase and Program than alternative flash technologies, because the total
energy consumed is a function of the applied voltage, current, and time of application. For any given voltage range,
www.greenliant.com
S71342-03-000
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
the SuperFlash technology uses less current to program
and has a shorter erase time; therefore, the total energy
consumed during any Erase or Program operation is less
than alternative flash technologies.
TABLE 1: Concurrent Read/Write State
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Bank 2
Read
No Operation
Write
Note: For the purposes of this table, write means to perform Blockor Sector-Erase or Program operations as applicable to the
appropriate bank.
The Read operation of the GLS36VF160xG is controlled
by CE# and OE#, both of which have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The
data bus is in a high impedance state when either CE# or
OE# is high. Refer to Figure 9, the Read cycle timing diagram, for further details.
To meet high-density, surface-mount requirements, the
GLS36VF1601G and GLS36VF1602G devices are offered
in 48-ball TFBGA, 48-lead TSOP, and 56-ball LFBGA
packages. See Figures 6, 7, and 8 for pin assignments.
Device Operation
Program Operation
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, ensure that the sector which is
being programmed is fully erased.
The Program operation is accomplished in three steps:
1. Initiate Software Data Protection using the threebyte load sequence.
Auto Low Power Mode
These devices also have the Auto Lower Power mode
which puts them in a near-standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the typical IDD active Read current to 4 µA.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
2. Load address and data.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. Initiate the internal Program operation after the rising edge of the fourth WE# or CE#, whichever
occurs first. The Program operation, once initiated, will be completed typically within 7 µs.
Concurrent Read/Write Operation
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank. See Table 1 below
for more information.
See Figures 10 and 11 for WE# and CE# controlled Program operation timing diagrams and Figure 25 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks.
Any commands issued during an internal Program operation are ignored.
TABLE 1: Concurrent Read/Write State
Bank 1
Bank 2
Read
No Operation
Read
Write
Write
Read
Write
No Operation
©2010 Greenliant Systems, Ltd.
Bank 1
No Operation
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Sector-Erase/Block-Erase Operation
Erase-Suspend/Erase-Resume Operations
The Sector- or Block- Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The GLS36VF160xG offer both Sector-Erase and
Block-Erase operations.
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read or programmed into any sector or block that is not
engaged in an Erase operation. The operation is executed
by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters
read mode no more than 10 µs after the Erase-Suspend
command had been issued. (TES maximum latency equals
10 µs.) Valid data can be read from any sector or block that
is not suspended from an Erase operation. Reading at
address location within erase-suspended sectors/blocks
will output DQ2 toggling and DQ6 at ‘1’. While in EraseSuspend mode, a Program operation is allowed except for
the sector or block selected for Erase-Suspend.
The sector architecture is based on a uniform sector size of
2 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erase
command (50H) and sector address (SA) in the last bus
cycle.
The Block-Erase mode is based on a uniform block size of
32 KWord. Block-Erase is initiated by executing a six-byte
command sequence with Block-Erase command (30H) and
block address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (50H or 30H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse.
To resume a suspended Sector-Erase or Block-Erase
operation, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte
command sequence with Erase Resume command (30H)
at any address in the one-byte sequence.
Any commands issued during the Sector- or Block-Erase
operation are ignored except Erase-Suspend and EraseResume. See Figures 15 and 16 for timing waveforms.
Write Operation Status Detection
To optimize the system Write cycle time, the
GLS36VF160xG provide two software means to detect the
completion of a Write (Program or Erase) cycle The software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
Chip-Erase Operation
The GLS36VF1601G and GLS36VF1602G provide a
Chip-Erase operation, which erases the entire memory
array to the ‘1’ state. This operation is useful when the
entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid Read is Toggle Bit or Data# Polling. Any commands issued during the Chip-Erase operation are ignored. See Table 6 for the command sequence,
Figure 14 for timing diagram, and Figure 29 for the flowchart. When WP# is low, any attempt to Chip-Erase will be
ignored.
©2010 Greenliant Systems, Ltd.
The actual completion of the nonvolatile write is asynchronous with the system. Therefore, Data# Polling or
Toggle Bit maybe be read concurrent with the completion
of the write cycle. If this occurs, the system may possibly
get an incorrect result from the status detection process.
For example, valid data may appear to conflict with either
DQ7 or DQ6. To prevent false results, upon detection of
failures, the software routine should loop to read the
accessed location an additional two times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the failure is valid.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Ready/Busy# (RY/BY#)
Toggle Bits (DQ6 and DQ2)
The GLS36VF160xG include a Ready/Busy# (RY/BY#)
output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to VDD via an external
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling, and the device is then ready for the next
operation. For Sector-, Block-, or Chip-Erase, the toggle bit
(DQ6) is valid after the rising edge of sixth WE# (or CE#)
pulse. DQ6 will be set to ‘1’ if a Read operation is attempted
on an Erase-Suspended Sector or Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector or block is being actively erased or erase-suspended. Table 2 shows detailed bit status information. The
Toggle Bit (DQ2) is valid after the rising edge of the last
WE# (or CE#) pulse of Write operation. See Figure 13 for
Toggle Bit timing diagram and Figure 26 for a flowchart.
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (VIH) the device is in x16 data configuration: all
data I/0 pins DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic ‘0’, the device is in x8 data configuration -- only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The remaining data pins DQ8DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
TABLE 2: Write Operation Status
Status
Data# Polling (DQ7)
EraseSuspend
Mode
When the GLS36VF160xG are in an internal Program
operation, any attempt to read DQ7 will produce the complement of true data. Once the Program operation is completed, DQ7 will produce valid data.
During internal Erase operation, any attempt to read DQ7
will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid
after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 12 for Data# Polling (DQ7) timing
diagram and Figure 26 for a flowchart.
©2010 Greenliant Systems, Ltd.
DQ7
DQ6
DQ2
RY/BY#
DQ7#
Toggle
No Toggle
0
Standard
Erase
0
Toggle
Toggle
0
Read From
Erase
Suspended
Sector/Block
1
1
Toggle
1
Read From
Non-Erase
Suspended
Sector/Block
Data
Data
Data
1
Program
DQ7#
Toggle
N/A
Normal
Standard
Operation Program
0
T2.1 1342
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation status. If the address is pointing to a different bank (not busy),
the device will output array data.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Data Protection
These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes.
The GLS36VF160xG provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
All Program operations require the inclusion of the threebyte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations. SDP for Erase operations is similar to Program, but a six-byte load sequence is
required for Erase operations.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
During SDP command sequence, invalid commands will
abort the device to read mode within TRC. The contents of
DQ15-DQ8 can be VIL or VIH, but no other value, during any
SDP command sequence.
Hardware Block Protection
Common Flash Memory Interface (CFI)
The GLS36VF1601G and GLS36VF1602G provide hardware block protection which protects the outermost 8
KWord in the smaller bank. The block is protected when
WP# is held low. See Figures 2, 3, 4, and 5 for Block-Protection location.
These devices contain Common Flash Memory Interface
(CFI) information that describes the characteristics of the
device. In order to enter the CFI Query mode, the system
must write a three-byte sequence, using the CFI Query
command, to address BKx555H in the last byte sequence.
The system can also use the one-byte sequence with
address BKx55H and Data Bus 98H to enter this mode.
See Figure 18 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 7
through 9.
Block protection is disabled by driving WP# high. This
allows data to be erased or programmed into the protected
sectors. WP# must be held high prior to issuing the Write
command and remain stable until after the entire Write
operation has completed. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Hardware Reset (RST#)
Security ID
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate
and return to Read mode (see). When no internal Program/
Erase operation is in progress, a minimum period of TRHR
is required after RST# is driven high before a valid Read
can take place. See Figures 22 and 21 for more information.
The GLS36VF160xG offer a 136-word Security ID space.
The Secure ID space is divided into two segments — one
128-bit, factory-programmed, segment and one 256-Byte,
user programmed segment. The first segment is programmed and locked at Greenliant and contains a 128 bit
Unique ID which uniquely identifies the device. The user
segment is left un-programmed for the customer to program
as desired.
The interrupted Erase or Program operation must be re-initiated after the device resumes normal operation mode to
ensure data integrity.
The user segment of the Security ID can be programmed
using the Security ID Program command. End-of-Write status is checked by reading the toggle bits. Data# Polling is
not used for Security ID End-of-Write detection.
Software Data Protection (SDP)
The GLS36VF160xG devices implement the JEDEC
approved Software Data Protection (SDP) scheme for all
data alteration operations, such as Program and Erase.
©2010 Greenliant Systems, Ltd.
Once the programming is complete, lock the Sec ID by
issuing the User Sec ID Program Lock-Out command.
Locking the Sec ID disables any corruption of this space.
Note that regardless of whether or not the Sec ID is locked,
the Sec ID segments can not be erased.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
The Secure ID space can be queried by executing a threebyte command sequence with Query Sec ID command
(88H) at address 555H in the last byte sequence. See Figure 20 for timing diagram. To exit this mode, the Exit Sec ID
command should be executed. Refer to Table 6 for more
details.
TABLE 3: Product Identification
Manufacturer’s ID
Address
Data
BK0000H
00BFH
BK0001H
7343H
BK0001H
7344H
Device ID
GLS36VF1601G
GLS36VF1602G
Product Identification
T3.0 1342
Note: BK = Bank Address (A19-A18)
The Product Identification mode identifies the devices as
GLS36VF1601G or GLS36VF1602G and the manufacturer as Greenliant. For details, see Table 3 for software
operation, Figure 17 for the Software ID Entry and Read
timing diagram, and Figure 27 for the Software ID Entry
command sequence flowchart.
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. The exit is
accomplished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
causes the device to behave abnormally. Please note that
the Software ID Exit/CFI Exit command is ignored during an
internal Program or Erase operation. See Table 6 for the
software command code, Figure 19 for timing waveform
and Figure 28 for a flowchart.
The addresses A19 and A18 indicate a bank address.
When the addressed bank is switched to Product Identification mode, it is possible to read another address from the
same bank without issuing a new Software ID Entry command.
Address
Buffers
Memory
Address
SuperFlash Memory
12 Mbit Bank
BYTE#
SuperFlash Memory
4 Mbit Bank
(8 KWord Sector Protection)
RST#
CE#
WP#
Control
Logic
I/O Buffers
WE#
DQ15/A-1 - DQ0
OE#
RY/BY#
1342 B01.0
FIGURE 1: Functional Block Diagram
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Bank 2
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Bank 1
8 KWord Sector Protection
(4-2 KWord Sectors)
FFFFFH
F8000H
F7FFFH
F0000H
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
07FFFH
02000H
01FFFH
00000H
Block 1
Block 0
1342 F01.0
Note: The address input range in x16 mode (BYTE#=VIH) is A19-
FIGURE 2: GLS36VF1601G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Bank 2
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Bank 1
16 KByte Sector Protection
(4-4 KByte Sectors)
1FFFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
004000H
003FFFH
000000H
Block 1
Block 0
1342 F02.0
Note: The address input range in x8 mode (BYTE#=VIL)
FIGURE 3: GLS36VF1601G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Top Block Protection; 32 KWord Blocks; 2 KWord Sectors
8 KWord Block Protection
(4 - 2 KWord Sectors)
Block 31
Block 30
Block 29
Block 28
Block 27
Bank 2
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Bank 1
FFFFFH
FE000H
FDFFFH
F8000H
F7FFFH
F0000H
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
07FFFH
00000H
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
1342 F03.0
Note: The address input range in x16 mode (BYTE#=VIH) is
FIGURE 4: GLS36VF1602G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Top Block Protection; 64 KByte Blocks; 4 KByte Sectors
16 KByte Block Protection
(4 - 4 KByte Sectors)
Block 31
Block 30
Block 29
Block 28
Block 27
Bank 2
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Bank 1
1FFFFFH
1FC000H
1FBFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
000000H
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
Note: The address input range in x8 mode (BYTE#=VIL) is
1342 F04.0
FIGURE 5: GLS36VF1602G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
TOP VIEW (balls facing down)
6
5
A13 A12 A14 A15 A16 BYTE#
A9
A8
NOTE*
VSS
A10 A11 DQ7 DQ14 DQ13 DQ6
WE# RST# NC
A19 DQ5 DQ12 VDD DQ4
RY/BY# WP# A18
NC DQ2 DQ10 DQ11 DQ3
3
1342 48-tfbga P1.0
4
2
1
DQ0 DQ8 DQ9 DQ1
A7
A17
A6
A5
A3
A4
A2
A1
A0
A
B
C
D
E
CE# OE# VSS
F
G
H
Note* = DQ15/A-1
FIGURE 6: Pin Assignments for 48-ball TFBGA (6mm x 8mm)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1342 48-tsop P02.0
FIGURE 7: Pin Assignments for 48-lead TSOP (12mm x 20mm)
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
TOP VIEW (balls facing down)
8
7
6
5
4
A15
NC
NC
A16 BYTE# VSS
A11
A12
A13
A14
NC DQ15/A-1 DQ7 DQ14
A8
A19
A9
A10
DQ6 DQ13 DQ12 DQ5
WE#
NC
NC
DQ4
WP# RST# RY/BY#
NC
NC
DQ3
VDD DQ11
NC
NC
A18
A17
DQ1
DQ9
DQ10 DQ2
A7
A6
A5
A4
VSS
OE#
DQ0
A3
A2
A1
A0
CE#
NC
B
C
D
E
F
2
DQ8
1
A
G
1342 56-lfbga P1.0
3
H
FIGURE 8: Pin Assignments for 56-lead LFBGA (8mm x 10mm)
TABLE 4: Pin Description
Symbol
Name
A19-A0
Address Inputs
Functions
To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A19-A11 address lines will select the sector. During Block-Erase A19-A15 address
lines will select the block.
DQ14-DQ0 Data Input/Output
To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# or CE# is high.
DQ15/A-1
DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)
A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)
Data Input/Output
and LBS Address
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers
WE#
Write Enable
To control the Write operations
RST#
Hardware Reset
To reset and return the device to Read mode
RY/BY#
Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
WP#
Write Protect
To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or
Program operation.
BYTE#
Word/Byte Configuration To select 8-bit or 16-bit mode.
VDD
Power Supply
VSS
Ground
NC
No Connection
To provide 2.7-3.6V power supply voltage
Unconnected pins
T4.0 1342
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
TABLE 5: Operation Modes Selection
DQ15-DQ8
Mode1
CE#
OE#
WE#
DQ7-DQ0
BYTE# = VIH
BYTE# = VIL
Address
Read
VIL
VIL
VIH
DOUT
DOUT
DQ14-DQ8 = High Z
AIN
Program
VIL
VIH
VIL
DIN
DIN
DQ15 = A-1
AIN
Erase
VIL
VIH
VIL
X2
X
High Z
Sector or Block
address,
555H for Chip-Erase
VIHC
X
X
High Z
High Z
High Z
X
X
VIL
X
High Z / DOUT
High Z / DOUT
High Z
X
X
X
VIH
High Z / DOUT
High Z / DOUT
High Z
X
VIL
VIL
VIH
Manufacturer’s ID
(BFH)
Manufacturer’s ID
(00H)
High Z
See Table 6
Device ID3
Device ID3
High Z
Standby
Write Inhibit
Product
Identification
Software
Mode
T5.2 1342
1. RST# = VIH for all described operation modes
2. X can be VIL or VIH, but no other value.
3. Device ID =
GLS36VF1601G = 7343H,
GLS36VF1602G = 7344H
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
TABLE 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
Addr1
Data2
2nd Bus
Write Cycle
Addr1
Data2
3rd Bus
Write Cycle
Addr1
4th Bus
Write Cycle
Data2
Addr1
Data2
Data
AAH
Program
555H
AAH
2AAH
55H
555H
A0H
WA3
Sector-Erase
555H
AAH
2AAH
55H
555H
80H
555H
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data2
Addr1
Data2
2AAH
55H
SAX4
50H
4
30H
10H
Block-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
BAX
Chip-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
Erase-Suspend
XXXXH
B0H
Erase-Resume
XXXXH
30H
Query Sec
ID5
555H
AAH
2AAH
55H
555H
88H
User Security ID
Program
555H
AAH
2AAH
55H
555H
A5H
SIWA6
Data
User Security ID
Program Lock-out7
555H
AAH
2AAH
55H
555H
85H
XXH
0000H
Software ID Entry8
555H
AAH
2AAH
55H
BKX9
555H
90H
CFI Query Entry
555H
AAH
2AAH
55H
BKX9
555H
98H
CFI Query Entry
BKX9
55H
98H
Software ID Exit/
CFI Exit/
Sec ID Exit10,11
555H
AAH
2AAH
55H
555H
F0H
Software ID Exit/
CFI Exit/
Sec ID Exit10,11
XXH
F0H
T6.0 1342
1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.
When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word/byte address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. For GLS36VF1601G,
Greenliant ID is read with A3 = 0 (Address range = 00000H to 00007H),
User ID is read with A3 = 1 (Address range = = 00008H to 00087H).
Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
For GLS36VF1602G,
Greenliant ID is read with A3 = 0 (Address range = C0000H to C0007H),
User ID is read with A3 = 1 (Address range = = C0008H to C0087H).
Lock Status is read with A7-A0 = C00FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. SIWA = User Security ID Program word/byte address
For GLS36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.
For GLS36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.
All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.
7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH).
8. The device does not remain in Software Product Identification mode if powered down.
9. A19 and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode
With A17-A1 = 0;Greenliant Manufacturer’s ID = 00BFH, is read with A0 = 0
GLS36VF1601G Device ID = 7343H, is read with A0 = 1
GLS36VF1602G Device ID = 7344H, is read with A0 = 1
10. Both Software ID Exit operations are equivalent
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the
User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
For GLS36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.
For GLS36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.
TABLE 7: CFI Query Identification String1
Address
x16 Mode
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Address
x8 Mode
20H
22H
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H
Data2
0051H
0052H
0059H
0002H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Description
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T7.0 1342
1. Refer to CFI publication 100 for more details.
2. In x8 mode, only the lower byte of data is output.
TABLE 8: System Interface Information
Address
x16 Mode
Address
x8 Mode
Data1
Description
1BH
36H
0027H
VDD Min (Program/Erase)
1CH
38H
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
3AH
0000H
VPP min (00H = no VPP pin)
1EH
3CH
0000H
VPP max (00H = no VPP pin)
1FH
3EH
0004H
Typical time out for Program 2N µs (24 = 16 µs)
20H
40H
0000H
Typical time out for min size buffer program 2N µs (00H = not supported)
21H
42H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H
44H
0006H
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
23H
46H
0001H
Maximum time out for Program 2N times typical (21 x 24 = 32 µs)
24H
48H
0000H
Maximum time out for buffer program 2N times typical
25H
4AH
0001H
Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H
4CH
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T8.0 1342
1. In x8 mode, only the lower byte of data is output.
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
TABLE 9: Device Geometry Information
Address
x16 Mode
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Address
x8 Mode
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H
Data1
0015H
0002H
0000H
0000H
0000H
0002H
00FFH
0001H
0010H
0000H
001FH
0000H
0000H
0001H
Description
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0002H = x8/x16 asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FFH = 512)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.1 1342
1. In x8 mode, only the lower byte of data is output.
©2010 Greenliant Systems, Ltd.
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16 Mbit Concurrent SuperFlash
GLS36VF1601G / GLS36VF1602G
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (
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