EM78P301N
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.2
ELAN MICROELECTRONICS CORP.
March 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
st
No. 12, Innovation 1 Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Hong Kong:
USA:
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre 95
How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
Elan Information
Technology Group
(U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
6F, Ke Yuan Building
No. 5 Bibo Road
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
General Description ................................................................................................ 1
2
Features ................................................................................................................... 1
3
Pin Assignment ....................................................................................................... 2
4
Pin Description ........................................................................................................ 3
5
Block Diagram ......................................................................................................... 5
6
Functional Description ............................................................................................ 6
6.1
Operational Registers ....................................................................................... 6
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.1.15
6.1.16
6.1.17
6.1.18
6.1.19
6.1.20
6.1.21
6.1.22
6.1.23
6.1.24
6.1.25
6.1.25
6.2
R0 (Indirect Address Register) ........................................................................... 6
R1 (Time Clock/Counter) .................................................................................... 6
R2 (Program Counter) and Stack ........................................................................ 6
6.1.3.1 Data Memory Configuration ................................................................. 8
R3 (Status Register) ............................................................................................ 9
R4 (RAM Select Register) ................................................................................... 9
Bank 0 R5 ~ R7 (Port 5 ~ Port 7) ........................................................................ 9
Bank 0 R8 (AISR: ADC Input Select Register) ................................................. 10
Bank 0 R9 (ADCON: ADC Control Register) .................................................... 12
Bank 0 RA (ADOC: ADC Offset Calibration Register) ...................................... 13
Bank 0 RB (ADDATA: Converted Value of ADC) .............................................. 14
Bank 0 RC (ADDATA1H: Converted Value of ADC) ......................................... 14
Bank 0 RD (ADDATA1L: Converted Value of ADC) .......................................... 15
Bank 0 RE (Interrupt Status 2 and Wake-up Control Register) ........................ 15
Bank 0 RF (Interrupt Status 2 Register) ............................................................ 16
Bank 1 R5 (TBHP: Table Point Register for Instruction TBRD) ........................ 17
Bank 1 R6 (TBLP: Table Point Register for Instruction TBRD) ......................... 17
Bank 1 R7 (PWMCON: PWM Control Register) ............................................... 17
Bank 1 R8 (TMRCON: Timer Control Register) ................................................ 18
Bank 1 R9 (PRD1: PWM 1 Time Period) .......................................................... 18
Bank 1 RA (PRD2: PWM 2 Time Period) .......................................................... 19
Bank 1 RB (DT1: PWM 1 Duty Cycle) .............................................................. 19
Bank 1 RC (DT2:PWM 2 Duty Cycle) ............................................................... 19
Bank 1 RD (High Byte of PWM 1 and PWM 2 Period and Duty Cycle) ............ 19
Bank 1 RE (LVD Interrupt and Wake-up Register) ........................................... 19
Bank 1 RF (System Control Register)............................................................... 20
R10 ~ R3F ......................................................................................................... 24
Special Purpose Registers .............................................................................. 24
6.2.1
6.2.2
6.2.3
A (Accumulator)................................................................................................. 24
CONT (Control Register)................................................................................... 24
IOC50 ~ IOC70 (I/O Port Control Register) ...................................................... 25
Product Specification (V1.2) 03.10.2016
iii
Contents
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
6.2.15
6.2.16
6.3
6.4
TCC/WDT and Prescaler ................................................................................ 31
I/O Ports ......................................................................................................... 32
6.4.1
6.5
Usage of Port 5 Input Change Wake-up/Interrupt Function .............................. 35
Reset and Wake-up ........................................................................................ 35
6.5.1
6.5.2
Reset and Wake-up Operation.......................................................................... 35
6.5.1.1 Wake-up and Interrupt Modes Operation Summary .......................... 39
6.5.1.2 Register Initial Values after Reset ...................................................... 41
6.5.1.3 Controller Reset Block Diagram ......................................................... 46
T and P Status under the Status Register ......................................................... 46
6.6
Interrupt .......................................................................................................... 47
6.7
Analog-to-Digital Converter (ADC) .................................................................. 49
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.8
ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) ............................... 50
6.7.1.1 Bank 0 R8 (AISR: ADC Input Select Register) .................................. 50
6.7.1.2 Bank 0 R9 (ADCON: ADC Control Register) ..................................... 51
6.7.1.3 RA (ADOC: AD Offset Calibration Register) ...................................... 52
6.7.1.4 Bank 1 RF (IRC Switch Register) ...................................................... 53
ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) ............... 53
ADC Sampling Time .......................................................................................... 54
AD Conversion Time ......................................................................................... 54
ADC Operation during Sleep Mode .................................................................. 55
Programming Process/Considerations ............................................................. 55
6.7.6.1 Programming Process ....................................................................... 55
6.7.6.2 Sample Demo Programs .................................................................... 56
Dual Sets of PWM (Pulse Width Modulation) .................................................. 58
6.8.1
6.8.2
6.8.3
6.8.4
iv
IOC80 (High Byte of Timers 1 and 2) ................................................................ 25
IOC90 (TMR1: PWM 1 Timer)........................................................................... 25
IOCA0 (TMR2: PWM 2 Timer) .......................................................................... 25
IOCB0 (Pull-down Control Register) ................................................................. 26
IOCC0 (Open-drain Control Register)............................................................... 26
IOCD0 (Pull-high Control Register)................................................................... 27
IOCE0 (WDT Control Register and Interrupt Mask Register 2) ........................ 27
IOCF0 (Interrupt Mask Register) ....................................................................... 28
IOC51 (High Sink Control Register 1) ............................................................... 29
IOC61 (High Sink Control Register 2) ............................................................... 29
IOC71 (High Driver Control Register 1) ............................................................ 30
IOC81 (High Driver Control Register 2) ............................................................ 30
IOCF1 (Pull-high Control Register) ................................................................... 31
Overview ........................................................................................................... 58
Increment Timer Counter (TMRX: TMR1 or TMR2) .......................................... 59
PWM Time Period (TMRX: TMR1 or TMR2) ..................................................... 59
PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2) .................................. 60
Product Specification (V1.2) 03.10.2016
Contents
6.8.5
6.9
PWM Programming Process/Steps................................................................... 60
Timer/Counter ................................................................................................. 60
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
Overview ........................................................................................................... 60
Functional Description ...................................................................................... 61
Programming the Related Registers ................................................................. 61
Timer Programming Process/Steps .................................................................. 62
PWM Cascade Mode ........................................................................................ 62
6.11 Oscillator......................................................................................................... 63
6.11.1
6.11.2
6.11.3
6.11.4
Oscillator Modes ............................................................................................... 63
Crystal Oscillator/Ceramic Resonators (Crystal) .............................................. 64
External RC Oscillator Mode ............................................................................. 67
Internal RC Oscillator Mode .............................................................................. 68
6.12 Power-on Considerations ................................................................................ 68
6.12.1 Programmable WDT Time-out Period ............................................................... 68
6.12.2 External Power-on Reset Circuit ....................................................................... 69
6.12.3 Residual Voltage Protection .............................................................................. 69
6.13 Code Option ................................................................................................... 70
6.13.1 Code Option Register (Word 0) ........................................................................ 70
6.13.2 Code Option Register (Word 1) ........................................................................ 72
6.13.3 Customer ID Register (Word 2) ........................................................................ 73
6.14 Low Voltage Detector/Low Voltage Reset ....................................................... 74
6.14.1 Low Voltage Reset ............................................................................................ 74
6.14.2 Low Voltage Detector ........................................................................................ 75
6.14.2.1 Bank 1 RE (LVD Interrupt and Wake-up Register) ............................ 75
6.14.2.2 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register) ......... 76
6.14.3 Programming Process ...................................................................................... 77
6.15 Instruction Set ................................................................................................. 78
7
Absolute Maximum Ratings .................................................................................. 80
8
DC Electrical Characteristics ................................................................................ 80
8.1
AD Converter Characteristics.......................................................................... 82
8.4
VREF 2V/3V/4V Characteristics ...................................................................... 83
9
AC Electrical Characteristics ................................................................................ 84
10
Timing Diagrams ................................................................................................... 85
Product Specification (V1.2) 03.10.2016
v
Contents
APPENDIX
A
Package Type ......................................................................................................... 86
B
Ordering and Manufacture Information ............................................................... 87
C
Packaging Configuration ...................................................................................... 89
C.1 EM78P301ND14 ............................................................................................. 89
C.2 EM78P301NSO14 .......................................................................................... 90
C.3 EM78P301NMS10 .......................................................................................... 91
C
Quality Assurance and Reliability ........................................................................ 92
C.1 Address Trap Detect ....................................................................................... 92
Specification Revision History
Doc. Version
Revision Description
Date
0.9
Preliminary version
2012/12/12
1.0
Initial version
2012/12/17
1. Modified the description about the resolution of PWM in the
Features section.
2. Modified the description about the resolution of PWM in Bank 1
R7 Control Register.
1.1
3. Modified the description about the resolution of PWM and PWM
Output Timing Figure in Section 6.8.1.
2015/02/17
4. Modified the description about the resolution of PWM, Cascade
Mode table and Functional Block Diagram of PWM Figure in
Section 6.9.5.
5. Deleted Section 6.8.5.
1. Modified the package type in Section 2 Features
2. Added User Application Note
3. Modified Appendix B “Ordering and Manufacturing Information”
1.2
2016/03/10
4. Modified the pin description of P70.
5. Modified Section 6.7.4 ADC Conversion Time.
6. Modified Section 6.8.2 Increment Timer Counter.
vi
Product Specification (V1.2) 03.10.2016
Contents
User Application Note
(Before using this chip, take a look at the following description note, it includes important messages.)
1.
We strongly recommend that you have to place external pull-down or pull-high resistor on P70 no
matter what the pin function is (except Crystal Mode). The purpose of this is to prevent P70 from
floating.
2.
The PWM output will not be set, if the duty cycle is “0”.
3.
The internal TCC will stop running when in sleep mode. However, during AD conversion, when
TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is enabled, the TCC will keep
on running.
4.
During ADC conversion, do not perform output instruction to maintain precision for all of the pins.
In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins during
AD conversion
5.
The noise rejection function is turned off in the LXT2 and sleep mode
Product Specification (V1.2) 03.10.2016
vii
Contents
viii
Product Specification (V1.2) 03.10.2016
EM78P301N
8-Bit Microcontroller with OTP ROM
1
General Description
EM78P301N is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS
technology. The device has an on-chip 1K13-bit Electrical One Time Programmable Read Only Memory
(OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Three Code
option bits are also available to meet user’s requirements.
With enhanced OTP-ROM features, the EM78P301N provides a convenient way of developing and verifying
user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates,
using development and programming tools. Users can avail of the ELAN Writer to easily program their
development code.
2
Features
CPU configuration
1K13 bits on-chip ROM
808 bits on-chip registers (SRAM)
8-level stacks for subroutine nesting
Less than 1.5 mA at 5V/4 MHz
Typically 15 A, at 3V/32kHz
Typically 2 A, during sleep mode
I/O port configuration
3 bidirectional I/O ports: P5, P6, P7
12 I/O pins
Wake-up port : P5
8 programmable pull-down I/O pins (P50~P57)
10 programmable pull-high I/O pins (P50~P57,
P60, P67)
2 programmable open-drain I/O pins (P60, P67)
8 programmable high-sink current I/O pins
(P50~P57, P60, P67)
External interrupt : P60
Operating voltage range:
2.1V~5.5V at 0C~70C (commercial)
2.3V~5.5V at -40C~85C (industrial)
Operating frequency range (based on 2 clocks):
Crystal mode: DC ~ 16 MHz, 4.5V
DC ~ 8 MHz, 3V; DC ~ 4 MHz, 2.1V
ERC mode: DC ~ 2 MHz, 2.1V
IRC mode
Oscillation mode: 16 MHz, 4 MHz, 1 MHz, 8 MHz
Nine available interrupts
TCC overflow interrupt
Input-port status changed interrupt (wake up
from sleep mode)
External interrupt
ADC completion interrupt
Low voltage detect (LVD) interrupt
PWM 1~2 period match interrupt
PWM 1~2 duty match interrupt
Special Features
Programmable free running Watchdog Timer
(4.5ms : 18ms)
Power saving Sleep mode
Power-on voltage detector available
High EFT immunity (better performance at
4 MHz or below)
Package Type:
Drift Rate
Internal
RC Freq.
4 MHz
16 MHz
8 MHz
1 MHz
Temp.
(-40~85°C)
Voltage
±2%
±2%
±2%
±2%
±1% *(2.1~5.5V)
±1% *(4.5~5.5V)
±1% *(3.0~5.5V)
±1% *(2.1~5.5V)
Process Total
±2%
±2%
±2%
±2%
±5%
±5%
±5%
±5%
* Operating voltage range
All the four main frequencies can be trimmed by
programming with six calibrated bits in the
ICE300N Simulator. The OTP is auto trimmed by
ELAN Writer.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
Fast set-up time requires only 0.8ms (VDD: 5V
Crystal: 4 MHz, C1/C2: 15pF) in XT mode and
10s in IRC mode (VDD: 5V, IRC: 4 MHz)
Peripheral configuration
8-bit real time clock/counter (TCC) with
selective signal sources, trigger edges, and
overflow interrupt
4 programmable Level Voltage Detector
(LVD) : 4.5V, 4.0V, 3.3V, 2.2V
Power-on reset and three programmable level
voltage reset
POR: 1.8V (Default), LVR: 4.0, 3.5, 2.7V
8-bit multi-channel Analog-to-Digital Converter
with 12-bit resolution in Vref mode
Two Pulse Width Modulation (PWM) with
8/10-bit resolution
10-pin MSOP 118mil : EM78P301NMS10
14-pin DIP 300mil
: EM78P301ND14
14-pin SOP 150mil
: EM78P301NSO14
Note: These are Green products that do not contain
hazardous substances.
1
EM78P301N
8-Bit Microcontroller with OTP ROM
3
Pin Assignment
1
P54/TCC/VREF
2
3
4
P52/ADC2
5
P50/ADC0
6
VSS
7
14
P60//INT
13
P67/ADC4/PWM1
12
P51/ADC1/PWM2
11
P71//RESET
10
P70/ADC5/OSCI/RCOUT
9
P55/ADC6/OSCO/ERCin
8
VDD
Figure 3-1 EM78P301ND14/SO14
2
P57/ADC7
1
P53/ADC3
2
P52/ADC2
3
P50/ADC0
4
VSS
5
EM78P301N10Pin
P57/ADC7
P53/ADC3
EM78P301N-14Pin
P56
10
P51/ADC1/PWM2
9
P71//RESET
8
P70/ADC5/OSCI/RCOUT
7
P55/ADC6/OSCO/ERCin
6
VDD
Figure 3-2 EM78P301NMS10
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
4
Pin Description
Name
Input
Type
Output
Type
P50
ST
CMOS
ADC0
AN
P51
ST
CMOS
ADC1
AN
ADC Input 1
PWM2
CMOS
PWM2 output
P52
ST
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
ADC2
AN
P53
ST
CMOS
ADC3
AN
P54
ST
CMOS
TCC
ST
Real Time Clock/Counter clock input
VREF
AN
ADC external voltage reference
P55
ST
CMOS
ADC6
AN
OSCO
ERCin
AN
P56
ST
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
P57
ST
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
ADC7
ST
Function
P50
P51
P52
P53
P54
P55
P56
XTAL
P57
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
Description
Bidirectional I/O pin with programmable
pull-down, pull-high and pin change
wake-up.
ADC Input 0
Bidirectional I/O pin with programmable
pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
ADC Input 2
Bidirectional I/O pin with programmable
pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
ADC Input 3
Bidirectional I/O pin with programmable
pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
Bidirectional I/O pin with programmable
pull-down, pull-high and pin change
wake-up.
ADC Input 6
Clock output of crystal/ resonator oscillator
External RC input pin
ADC Input 7
3
EM78P301N
8-Bit Microcontroller with OTP ROM
Name
Function
Input
Output
Type
Type
ST
CMOS
Description
Bidirectional I/O pin with programmable
P60
P60//INT
open-drain, pull-high, high-driver and high
sink.
/INT
ST
External interrupt pin
Bidirectional I/O pins with programmable
P67
ST
CMOS
sink.
P67/ADC4/PWM1
P70/ADC5/OSCI/
open-drain, pull-high, high-driver and high
ADC4
AN
ADC Input 4
PWM1
CMOS
PWM1 output
P70
P70
ADC5
AN
OSCI
XTAL
Bidirectional I/O pin
Remark: Off-chip pull-down or pull-high
ADC Input 5
Remark: Off-chip pull-down or pull-high
Clock input of crystal/ resonator oscillator
RCOUT
Clock output of internal RC oscillator
ROCUT
CMOS
Clock output of external RC oscillator
(open-drain)
Remark: Off-chip pull-down or pull-high
P71
ST
CMOS
/RESET
ST
P71
Bidirectional I/O pin (open-drain)
System reset pin
(should be external pull-high)
VDD
VDD
Power
Power
VSS
VSS
Power
Ground
Legend: ST: Schmitt Trigger input
AN: analog pin
XTAL: oscillation pin for crystal/resonator
CMOS: CMOS output
NOTE
It is strongly recommended that user has to place external pull-down or pull-high
resistor on P70 no matter what the pin function is (except Crystal Mode ).
The purpose of this is to prevent P70 from floating.
4
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
5
Block Diagram
P70
P71
ROM
PC
Instruction
Register
8-level stack
(13 bit)
Ext.
OSC.
Int.
RC
Ext.
RC
Oscillation
Generation
Start-up
timer
WDT
Reset
Instruction
Decoder
PWM2
PWM1
P6
TCC
Mux
P60
PWM2
PWM1
TCC
ALU
R4
P67
LVD
RAM
P5
ACC
R3 (Status
Reg.)
P50
P51
P52
P53
P54
P55
P56
P57
Interrupt
control
register
LVR
Interrupt
circuit
ADC
Ext INT
Ain0~7
Figure 5-1 EM78P301N Block Diagram
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
5
EM78P301N
8-Bit Microcontroller with OTP ROM
6
Functional Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect address pointer.
Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM
Select Register (R4).
6.1.2 R1 (Time Clock/Counter)
Incremented by an external signal edge which is defined by the TE bit (CONT-5)
through the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
The TCC prescaler counter is assigned to TCC
The contents of the CONT register is cleared whenever –
a value is written to the TCC register
a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of the CONT register)
there’s power-on reset, /RESET, or WDT time out reset
6.1.3 R2 (Program Counter) and Stack
PC
A9
A7
~
A0
Reset vector
0000h
External interrupt
0003h
Port 5 pin change
0006h
TCC overflow interrupt
0009h
AD conversion complete interrupt
000Ch
000Fh
PWM1 Period Match interrupt
0012h
PWM2 Period Match interrupt
0015h
PWM1 Duty Match interrupt
0018h
PWM2 Duty Match interrupt
001Bh
001Eh
Low Voltage Detector interrupt
0021h
User Memory Space
CALL
LCALL
RET
RETL
Store ACC, R3, R4
RETI
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
On-chip Program Memory
03FFh
Figure 6-1 Program Counter Organization
6
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
R2 and hardware stacks are 10-bit wide. The structure is depicted in the table
under Section 6.1.3.1 Data Memory Configuration.
The configuration structure generates 1K13 bits on-chip ROM addresses to the
relative programming instruction codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a reset condition occurs.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to jump to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and PC+1 are pushed onto the
stack. Thus, the subroutine entry address can be located anywhere within a page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top of the stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.
Any instruction (except “ADD R2, A”) that is written to R2 (e.g., "MOV R2, A", "BC
R2, 6", etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain
unchanged.
All instructions are single instruction cycle (fclk/2) except “LCALL” and “LJMP”
instructions. The “LCALL” and “LJMP” instructions need two instruction cycles.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
7
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.3.1
Data Memory Configuration
Register
Bank 0
Register
Bank 1
IOC
Page 0
IOC
Page 1
Address
00
R0 (Indirect Addressing
Register)
01
R1 (Timer Clock Counter)
02
R2 (Program Counter)
03
R3 (Status Register)
04
R4 (RSR, Bank select)
05
R5 (Port 5 I/O data)
R5 (TBHP: Table Point
Register)
IOC50 (Port 5 I/O control)
IOC51 (HSCR1: High Sink
Control Register 1)
06
R6 (Port 6 I/O data)
R6 (TBLP: Table Point
Register)
IOC60 (Port 6 I/O control)
IOC61 (HSCR2: High Sink
Control Register 2)
07
R7 (Port 7 I/O data)
R7 (PWMCON: PWM
Control Register)
IOC70 (Port 7 I/O control)
IOC71 (HDCR1: High Driver
Control Register1)
08
R8 (ADC Input Select
Register)
R8 (TMRCON: Timer Control
Register)
IOC80 (High byte of
Timers 1 and 2)
IOC81 (HDCR2: High Driver
Control Register 2)
09
R9 (ADC Control
Register)
R9 (PRD1: PWM1 Time
Period)
IOC90 (TMR1: PWM1 Timer)
IOC91 (Reserved)
0A
RA (ADC Offset
Calibration Register)
RA (PRD2: PWM2 Time
Period)
IOCA0 (TMR2: PWM2 Timer)
IOCA1 (Reserved)
0B
RB (Converted value
AD11~AD4 of ADC)
RB (DT1: PMW1 Duty Cycle)
IOCB0 (Pull-down Control
Register)
IOCB1 (Reserved)
0C
RC (Converted value
AD11~AD8 of ADC)
RC (DT2: PMW2 Duty Cycle)
IOCC0 (Open-drain Control
Register)
IOCC1 (Reserved)
0D
RD (Converted value
AD7~AD0 of ADC)
RD (High Byte of PWM1 &
PWM2 Period and Duty
Cycle)
IOCD0 (Pull-high Control
Register)
IOCD1 (Reserved)
0E
RE (Interrupt Status 2 and
Wake-up Control Register 1)
RE (LVD Control and
Wake-up Control Register 2)
IOCE0 (WDT Control Register IOCE1 (Reserved)
and Interrupt Mask Register 2)
0F
RF (Interrupt Status
Register 1)
RF (Mode Select and IRC
Switch Register)
IOCF0 (Interrupt Mask
Register 1)
10
:
1F
16-Byte Common Register
20
:
3F
Bank 0
32x8
IOCF1 (Pull-high Control
Register)
Bank 1
32x8
Figure 6-2 Data Memory Configuration
8
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
IOCS
T
P
Z
DC
C
Bit 7 (RST): Bit of reset type
Set to “1” if wake-up from sleep on pin change or AD conversion
completed. Set to “0” if wake-up from other reset types.
Bit 6 (IOCS): Select the Segment of IO control register
0: Segment 0 (IOC50 ~ IOCF0) selected
1: Segment 1 (IOC51 ~ IOCC1) selected
Bit 5: Not used, set “0” at all the time.
Bit 4 (T): Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during
power on, and reset to “0” by WDT time-out (for more details, see Section
6.5.2, The T and P Status under Status Register).
Bit 3 (P): Power-down bit. Set to “1” during power-on or by a "WDTC" command and
reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P Status
under Status Register for more details).
Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7 (SBANK): Special Register 0x05~0x0F bank selection bit.
Bit 6 (BANK): Used to select Bank 0 or Bank 1 of the register
Bits 5 ~ 0: Used to select a register (Address: 00~0F, 10~3F) in indirect addressing
mode.
See the table under Section 6.1.3.1 Data Memory Configuration.
6.1.6 Bank 0 R5 ~ R7 (Port 5 ~ Port 7)
R5 and P60 and P67, P70 and P71 are I/O registers.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
9
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.7 Bank 0 R8 (AISR: ADC Input Select Register)
The AISR register individually defines the I/O Port as analog input or as digital I/O.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bit 7 (ADE7): AD converter enable bit of P57 pin
0: Disable ADC7, P57 functions as I/O pin
1: Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P55 pin
0: Disable ADC6, P55 functions as I/O pin
1: Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P70 pin
0: Disable ADC5, P70 functions as I/O pin
1: Enable ADC5 to function as analog input pin
Bit 4 (ADE4): AD converter enable bit of P67 pin
0: Disable ADC4, P67 functions as I/O pin
1: Enable ADC4 to function as analog input pin
Bit 3 (ADE3): AD converter enable bit of P53 pin
0: Disable ADC3, P53 functions as I/O pin
1: Enable ADC3 to function as analog input pin
Bit 2 (ADE2): AD converter enable bit of P52 pin
0: Disable ADC2, P52 functions as I/O pin
1: Enable ADC2 to function as analog input pin
Bit 1 (ADE1): AD converter enable bit of P51 pin
0: Disable ADC1, P51 functions as I/O pin
1: Enable ADC1 to function as analog input pin
Bit 0 (ADE0): AD converter enable bit of P50 pin
0: Disable ADC0, P50 functions as I/O pin
1: Enable ADC0 to function as analog input pin
10
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
NOTE
The P55/ADC6/OSCO/ERCin pin cannot be applied to OSCO and ADC6 at the same
time. If P55/ADC6/OSCO/ERCin functions as OSCO oscillator input pin, then ADE6
bit for R8 must be ”0” and ADIS2~0 do not select “110”. The P55/ADC6/OSCO/ERCin
pin priority is as follows
:
P55/ADC6/OSCO/ERCin Pin Priority
High
Medium
Low
OSCO
ADC6
P55
The P70/ADC5/OSCI/RCOUT pin cannot be applied to OSCI and ADC5 at the same
time. If P70/ADC5/OSCI/RCOUT acts as OSCI oscillator input pin, then ADE5 bit for R8
must be ”0” and ADIS2~0 do not select “101”. The P70/ADC5/OSCI/RCOUT pin priority
is as follows:
P70/ADC5/OSCI/RCOUT Pin Priority
High
Medium
Low
OSCI/RCOUT
ADC5
P70
The P67/ADC4/PWM1 pin cannot be applied to PWM1 and ADC4 at the same time.
If P67/ADC4/PWM1 functions as ADC4 analog input pin, then the P67/ADC4/PWM1
pin priority is as follows:
P67/ADC4/PWM1 Pin Priority
High
Medium
Low
ADC4
PWM1
P67
The P51/ADC1/PWM2 pin cannot be applied to PWM2 and ADC1 at the same time.
If P51/ADC1/PWM2 functions as ADC1 analog input pin, then the P51/ADC1/PWM2
pin priority is as follows:
P51/ADC1/PWM2 Pin Priority
High
Medium
Low
ADC1
PWM2
P51
The P50/ADC0 pin cannot be applied to ADC0 at the same time.
If P50/ADC0 functions as ADC0 analog input pin, then the P50/ADC0 pin priority is as
follows:
P50/ADC0 Pin Priority
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
High
Low
ADC0
P50
11
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.8 Bank 0 R9 (ADCON: ADC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Bit 7 (VREFS): The input source of Vref of the ADC
0: The Vref of the ADC is connected to Vdd (default value), and the
VREF/TCC/P54 pin carries out the function of P54 (default)
1: The Vref of the ADC is connected to VREF/TCC/P54
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If
P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 “TS” must
be “0”.
The VREF/TCC/P54 Pin Priority is as follows:
P54/TCC/VREF Pin Priority
High
Medium
Low
VREF
TCC
P54
Bit 6 and Bit 5 (CKR1 and CKR0): ADC Clock Rate Select
00 = 1 : 16 (default value)
01 = 1 : 4
10 = 1 : 64
11 = 1 : 1
Bit 4 (ADRUN): ADC starts to RUN
0: on completion of the conversion Reset by hardware. This bit cannot
be reset through software (default)
1: an A/D conversion is started. This bit can be set by software
Bit 3 (ADPD): ADC Power
0: ADC is in power down mode (default)
1: ADC is operating normally
12
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select
ADICS
ADIS2
ADIS1
ADIS0
Analog Input Select
0
0
0
0
ADIN0/P50
0
0
0
1
ADIN1/P51
0
0
1
0
ADIN2/P52
0
0
1
1
ADIN3/P53
0
1
0
0
ADIN4/P67
0
1
0
1
ADIN5/P70
0
1
1
0
ADIN6/P55
0
1
1
1
ADIN7/P57
1
0
X
X
OPOUT
1
1
X
X
Internal 1/4 VDD
These bits can only be changed when the ADIF bit and the ADRUN bit are both low.
See Section 6.1.13, RE (Interrupt Status 2 and Wake-up Control Register).
6.1.9 Bank 0 RA (ADOC: ADC Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
VREF1
VREF0
ADICS
Bit 7 (CALI): Calibration enable bit for ADC offset
0: Disable Calibration (default)
1: Enable Calibration
Bit 6 (SIGN): Polarity bit of the offset voltage
0: Negative voltage (default)
1: Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2]
VOF[1]
VOF[0]
EM78P301N
0
0
0
0LSB
0
0
1
2LSB
0
1
0
4LSB
0
1
1
6LSB
1
0
0
8LSB
1
0
1
10LSB
1
1
0
12LSB
1
1
1
14LSB
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
13
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 2 ~ Bit 1 (VREF1 ~ VREF0): ADC internal reference voltage source
VREF1
VREF0
ADC Internal Reference Voltage
0
0
VDD (default)
0
1
4.0V ± 1%
1
0
3.0V ± 1%
1
1
2.0V ± 1%
NOTE
If VREF [1:0]=00, the internal reference will not turn on. If VREF[1:0]≠ 00, the
internal reference will turn on automatically. Moreover, the power of the internal
reference is irrelevant to ADC.
When using internal voltage reference, users need to wait for at least 50 µs when
doing it for the first time to enable and stabilize the voltage reference.
Un-stabilized reference makes conversion result inaccurate. After that, users
only need to wait for at least 6μs whenever switching the voltage reference.
Bit 0 (ADICS): ADC Internal Channel Select (select ADC internal 1/4 VDD or OP
output pin connected to ADC input)
0: Disable (default)
1: Enable
6.1.10 Bank 0 RB (ADDATA: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
When AD conversion is completed, the result is loaded into the ADDATA. The ADRUN
bit is cleared and the ADIF is set. See Section 6.1.13, Bank 0 RE (Interrupt Status 2
and Wake-up Control Register).
RB is read only.
6.1.11 Bank 0 RC (ADDATA1H: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
“0”
“0”
AD11
AD10
AD9
AD8
When AD conversion is completed, the result is loaded into the ADDATA1H. The
ADRUN bit is cleared and the ADIF is set. See Section 6.1.13, Bank 0 RE (Interrupt
Status 2 and Wake-up Control Register).
RC is read only.
14
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.12 Bank 0 RD (ADDATA1L: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared and the ADIF is set. See Section 6.1.13, RE (Interrupt Status 2
and Wake-up Control Register).
RD is read only
6.1.13 Bank 0 RE (Interrupt Status 2 and Wake-up Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
ADWE
ICWE
LVDWE
Note: 1. RE can be cleared by instruction but cannot be set.
2. IOCE0 is the interrupt mask register.
3. Reading RE will result to “Logic AND” of the RE and IOCE0.
Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin
voltage is lower than LVD voltage interrupt level (selected by LVD1 and
LVD0), this bit will be cleared.
0: Low voltage is detected
1: Low voltage is not detected or LVD function is disabled (default)
Bit 6 (LVDIF): Low Voltage Detector Interrupt flag
LVDIF is reset to “0” by software.
Bit 5 (ADIF): Interrupt flag for analog to digital conversion. Set when AD conversion is
completed. Reset by software.
0: no interrupt occurs (default)
1: interrupt request
Bit 4: Not used. Set “0” at all the time.
Bit 3 (ADWE): ADC wake-up enable bit
0: Disable ADC wake-up (default)
1: Enable ADC wake-up
When AD Conversion enters sleep/idle mode, this bit must be set to
“Enable”.
Bit 2: Not used. Set “0” at all the time.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
15
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 1 (ICWE): Port 5 input change to wake-up status enable bit
0: Disable Port 5 input change to wake-up status (default)
1: Enable Port 5 input change to wake-up status
When Port 5 change enters sleep/idle mode, this bit must be set to
“Enable”.
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit
0: Disable Low Voltage Detect wake-up (default)
1: Enable Low Voltage Detect wake-up
When the Low Voltage Detect is used to enter an interrupt vector or to
wake-up the IC from sleep/idle with Low Voltage Detect running, the
LVDWE bit must be set to “Enable”.
6.1.14 Bank 0 RF (Interrupt Status 2 Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
DT2IF
DT1IF
PWM2IF
PWM1IF
EXIF
ICIF
TCIF
Note: 1. “1” means there is interrupt request, “0”
2. RF can be cleared by instruction but cannot be set.
3. IOCF0 is the interrupt mask register.
4. Reading RF will result to “Logic AND” of the RF and IOCF0
Bit 7: Not used. Set “0” at all the time.
Bit 6 (DT2IF): PWM2 Duty Interrupt flag. Set when PWM 2 Duty Match. Reset by
software.
Bit 5 (DT1IF): PWM 1 Duty Interrupt flag. Set when PWM 1 Duty Match. Reset by
software.
Bit 4 (PWM2IF): PWM 2 Period Interrupt flag. Set when PWM 2 period match. Reset
by software.
Bit 3 (PWM1IF): PWM1 Period Interrupt flag. Set when PWM1 period match. Reset
by software.
Bit 2 (EXIF): External interrupt flag. Set by falling edge on /INT pin. Reset by software.
Bit 1 (ICIF): Port 5 input status change interrupt flag. Set when Port 5 input changes.
Reset by software.
Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by
software.
16
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.15 Bank 1 R5 (TBHP: Table Point Register for Instruction
TBRD)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MLB
-
-
-
-
-
RBit9
RBit8
Bit 7 (MLB): Chooses the MSB or LSB machine code to move into the register.
The machine code is pointed by TBLP and TBHP register.
Bit 6 ~ Bit 2: Not used. Set to “0” at all time.
Bit 1 ~ Bit 0: Most two significant bits for program code address
6.1.16 Bank 1 R6 (TBLP: Table Point Register for Instruction
TBRD)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBit7
RBit6
RBit5
RBit4
RBit3
RBit2
RBit1
RBit0
Bit 7 ~ Bit 0: These are the least 8 significant bits of address for program code.
6.1.17 Bank 1 R7 (PWMCON: PWM Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
“0”
“0”
“0”
PWMCAS
PWM2E
PWM1E
Bit 7~ Bit 3: Not used bit. Read as “0” all the time
Bit 2 (PWMCAS): PWM Cascade Mode
0: Two Independent 8/10-bit PWM functions (default value)
1: 16/20-bit PWM Mode (Cascaded from two 8/10-bit ones)
Bit 1 (PWM2E): PWM2 enable bit
0: PWM2 is off (default value), and its related pin carries out the P51
function.
1: PWM2 is on, and its related pin is automatically set to output.
Bit 0 (PWM1E): PWM1 enable bit
0: PWM1 is off (default value), and its related pin carries out the P67
function.
1: PWM1 is on, and its related pin is automatically set to output.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
17
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.18 Bank 1 R8 (TMRCON: Timer Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T2EN
T1EN
T2P2
T2P1
T2P0
T1P2
T1P1
T1P0
Bit 7 (T2EN): TMR2 enable bit
0: TMR2 is off (default value)
1: TMR2 is on
Bit 6 (T1EN): TMR1 enable bit
0: TMR1 is off (default value)
1: TMR1 is on
Bit 5 ~ Bit 3 (T2P2 ~ T2P0): TMR2 clock prescaler option bits
T2P2
T2P1
T2P0
Prescale
0
0
0
1:1 (default)
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 2 ~ Bit 0 (T1P2 ~ T1P0): TMR1 clock prescale option bits
T1P2
T1P1
T1P0
Prescale
0
0
0
1:1 (default)
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
6.1.19 Bank 1 R9 (PRD1: PWM 1 Time Period)
The content of Bank 1-R9 is the time period (time base) of PWM1. The frequency of
PWM1 is the reverse of the period.
18
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.1.20 Bank 1 RA (PRD2: PWM 2 Time Period)
The content of Bank 1-RA is the time period (time base) of PWM 2. The frequency of
PWM 2 is the reverse of the period.
6.1.21 Bank 1 RB (DT1: PWM 1 Duty Cycle)
A specified value keeps the output of PWM 1 to remain high until the value matches
with TMR 1.
6.1.22 Bank 1 RC (DT2: PWM 2 Duty Cycle)
A specified value keeps the output of PWM 2 to remain high until the value matches
with TMR2.
6.1.23 Bank 1 RD (High Byte of PWM 1 and PWM 2 Period and Duty
Cycle)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DT2[9]
DT2[8]
DT1[9]
DT1[8]
PRD2[9]
PRD2[8]
PRD1[9]
PRD1[8]
Bits 7~6 (DT2 [9~8]): The content of Bank 1 RD is the high byte of PWM 2 duty.
Bits 5~4 (DT1 [9~8]): The content of Bank 1 RD is the high byte of PWM 1 duty.
Bits 3~2 (PRD2 [9~8]): The content of Bank 1 RD is the high byte of PWM 2 period.
Bits 1~0 (PRD1 [9~8]): The content of Bank 1 RD is the high byte of PWM 1 period.
6.1.24 Bank 1 RE (LVD Interrupt and Wake-up Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
LVDEN
LVD1
LVD0
-
-
-
EXWE
Bit 7 (LVDIE): Low voltage detector interrupt enable bit
0: Disable the low voltage detector interrupt (default)
1: Enable the low voltage detector interrupt
NOTE
When the detected low level voltage is used to enter an interrupt vector or enter
the next instruction, the LVDIE bit must be set to “Enable”.
Bit 6 (LVDEN): Low voltage detector enable bit
0: Disable the Low voltage detector function (default)
1: Enable the Low voltage detector function
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
19
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 5 ~ Bit 4: Low voltage detector level bits
LVDEN
LVD1, LVD0
1
11 (default)
1
10
1
LVD Voltage Interrupt Level
/LVD
Vdd 2.2V
0
Vdd > 2.2V
1
Vdd 3.3V
0
Vdd > 3.3V
1
Vdd 4.0V
0
Vdd > 4.0V
1
Vdd 4.5V
0
Vdd > 4.5V
1
N/A
1
01
1
00
0
NOTE
IF Vdd has crossover at LVD voltage in interrupt level as VDD varies, LVD interrupt
will occur.
Bit 3 ~ Bit 1: Not used. Set to “0” at all time.
Bit 0 (EXWE): External /INT wake-up enable bit
0: Disable External /INT pin wake-up (default)
1: Enable External /INT pin wake-up
6.1.25 Bank 1 RF (System Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TIMERSC
CPUS
IDLE
SHS1
SHS0
RCM1
RCM0
Bit 7: not used, fixed to "0" all the time.
Bit 6 (TIMERSC): TCC, PWM1, PWM2 clock source select.
0: Fs is used as Fc
1: Fm is used as Fc (default)
Bit 5 (CPUS): CPU Oscillator Source Select
0: Fs : sub frequency for WDT internal RC time base is 16kHz
1: Fm : main oscillator (Fm) (default)
When CPUS=0, the CPU oscillator selects the sub-oscillator and the
main oscillator is stopped.
20
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 4 (IDLE): Idle Mode Enable Bit.
From SLEP instruction, this bit will determine as to which mode to
activate.
0: IDLE = ‘0’ + SLEP instruction sleep mode (default)
1: IDLE = ‘1’ + SLEP instruction idle mode
CPU Operation Mode
RESET
Normal Mode
fm:oscillation
fs: oscillation
Wake up
wake up
CPU: using fm
IDLE="0"
+SLEP
Sleep Mode
Wake up
fm:stop
fs: stop
CPU: stop
CPUS="0"
CPUS="1"
Green Mode
IDLE="1"
+SLEP
IDLE="1
"+SLEP
fm:stop
fs: oscillation
IDLE="0"
+ SLEP
CPU: using fs
Idle Mode
fm:stop
fs: oscillation
wake up
CPU: stop
Figure 6-3 CPU Operation Mode Diagram
Oscillator
(Normal Mode Source)
CPU Mode Status
Sleep/Idle → Normal
Crystal
1M ~ 16 MHz
ERC
2 MHz
Green → Normal
1M, 4M, 8M, 16 MHz
0.5 ms ~ 2 ms
510 CLK
510 CLK
Sleep/Idle → Green
< 100 µs
8 CLK
Sleep/Idle → Normal
< 5 µs
8 CLK
Sleep/Idle → Normal
IRC
Oscillator Stable
Count from
1
2
Time (S)
Normal/Green (CLK)
Green → Normal
Sleep/Idle → Green
< 2 µs
8 CLK
< 100 µs
NOTE
1
■ The oscillator stable time depends on the oscillator characteristics.
2
■ After the oscillator has stabilized, the CPU will count 510/8 CLK in Normal/Green
mode and continue to work in Normal/Green mode.
Ex 1 : The 4 MHz IRC wakes-up from Sleep mode to Normal mode,
the total wake-up time is 2 µs + 8 CLK @ 4 MHz.
Ex 2 : The 4 MHz IRC wakes-up from Sleep mode to Green mode,
the total wake-up time is 100 µs + 8 CLK @ 16kHz.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
21
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 3 ~ Bit 2 (SHS1 ~ SHS0): Sample and Hold Timing Select
(Recommend at least 4μs, TAD: Period of ADC Operating Clock).
SHS1
SHS0
Sample and Hold Timing(TAD)
0
0
2 x TAD
0
1
4 x TAD
1
0
8 x TAD
1
1
12 x TAD (default)
Bits 1 ~ 0 (RCM1 ~ RCM0): IRC mode select bits.
RCM 1
RCM 0
Frequency (MHz)
1
1
4
1
0
16
0
1
8
0
0
1
Bank 1 RF will be enabled.
Writer Trim IRC
4 MHz
16 MHz
8 MHz
1 MHz
Bank 1 RF
Frequency
Operating Voltage
Range
Stable Time
RCM1
RCM0
1
1
4 MHz ± 2%
2.1V ~ 5.5V
< 5 µs
1
0
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
0
1
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
0
0
1MHz ± 10%
2.1V ~ 5.5V
< 24 µs
1
1
4 MHz ± 10%
2.1V ~ 5.5V
< 6 µs
1
0
16 MHz ± 2%
4.5V ~ 5.5V
< 1.25 µs
0
1
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
0
0
1MHz ± 10%
2.1V ~ 5.5V
< 24 µs
1
1
4 MHz ± 10%
2.1V ~ 5.5V
< 6 µs
1
0
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
0
1
8 MHz ± 2%
3.0V ~ 5.5V
< 2.5 µs
0
0
1MHz ± 10%
2.1V ~ 5.5V
< 24 µs
1
1
4 MHz ± 10%
2.1V ~ 5.5V
< 6 µs
1
0
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
0
1
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
0
0
1MHz ± 2%
2.1V ~ 5.5V
< 20 µs
NOTE
■ The initial values of Bank 1 RF will be kept the same as Word 1.
■ If user changes the IRC frequency from A-frequency to B-frequency, the MCU needs
to wait for some time for it to work. The waiting time corresponds to the B-frequency.
22
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
For Example:
st
1 step When user selects the 4 MHz at the Writer, the initial values of Bank 1 RF
would be “11”, the same as the value of Word 1 which is “11”.
If the MCU is free-running, it will work at 4 MHz ± 2%. Refer to the table below.
Writer Trim IRC
Bank 1 RF
Frequency
Operating Voltage
Range
Stable
Time
1
4 MHz ± 2%
2.1V ~ 5.5V
< 5 µs
1
0
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
0
1
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
0
0
1 MHz ± 10%
2.1V ~ 5.5V
< 24 µs
RCM1
RCM0
1
4 MHz
nd
2 step If it is desired to set Bank 1 RF = “10” while the MCU is working at 4 MHz
± 2%, the MCU needs to hold for 1.5 µs, then it will continue to work at 16 MHz
± 10%.
Bank 1 RF
Writer Trim IRC
Frequency
Operating Voltage
Range
Stable
Time
RCM1
RCM0
1
1
4 MHz ± 2%
2.1V ~ 5.5V
< 5 µs
1
0
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
0
1
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
0
0
1 MHz ± 10%
2.1V ~ 5.5V
< 24 µs
4 MHz
rd
3 step If it is desired to set Bank 1 RF = “00” while the MCU is working at 16
MHz ± 10%, the MCU needs to hold for 24 µs, then it will continue to work at
1 MHz ± 10%.
Bank 1 RF
Writer Trim IRC
Frequency
Operating Voltage
Range
Stable
Time
1
4 MHz ± 2%
2.1V ~ 5.5V
< 5 µs
1
0
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
0
1
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
0
0
1 MHz ± 10%
2.1V ~ 5.5V
< 24 µs
RCM1
RCM0
1
4 MHz
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
23
EM78P301N
8-Bit Microcontroller with OTP ROM
th
4 step If it is desired to set Bank 1 RF = “11” while the MCU is working at 1 MHz
± 10%, the MCU needs to hold for 5 µs, then it will continue to work at 4 MHz ±
2%.
Writer Trim IRC
Bank 1 RF
Frequency
Operating Voltage
Range
Stable
Time
RCM1
RCM0
1
1
4 MHz ± 2%
2.1V ~ 5.5V
< 5 µs
1
0
16 MHz ± 10%
4.5V ~ 5.5V
< 1.5 µs
0
1
8 MHz ± 10%
3.0V ~ 5.5V
< 3 µs
0
0
1 MHz ± 10%
2.1V ~ 5.5V
< 24 µs
4 MHz
6.1.25 R10 ~ R3F
All of these are 8-bit general-purpose registers.
6.2 Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Note: The CONT register is both readable and writable.
Bit 6 is read only.
Bit 7 (INTE): INT signal edge
0: Interrupt occurs at the rising edge of the INT pin
1: Interrupt occurs at the falling edge of the INT pin
Bit 6 (INT): Interrupt Enable flag
0: Masked by DISI or hardware interrupt
1: Enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS): TCC signal source
0: Internal instruction cycle clock. If P54 is used as I/O pin
1: Transition on the TCC pin
Bit 4 (TE): TCC signal edge
0: Increment if the transition from low to high takes place on the TCC pin
1: Increment if the transition from high to low takes place on the TCC pin.
24
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 3 (PSTE): Prescaler enable bit for TCC
0: Prescaler disable bit. TCC rate is 1:1.
1: Prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Note: Tcc Time-out period [1/FT x prescaler x (256 Tcc cnt) x 1
Where FT = Fm or Fs, determined by Bank 1 RF TIMERSC bit.
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
"0" defines the relative I/O pin as output
"1" sets the relative I/O pin into high impedance
6.2.4 IOC80 (High Byte of Timers 1 and 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR2[9]
TMR2[8]
-
-
-
-
TMR1[9]
TMR1[8]
Note: Bits 7~6 and 1~0 of the IOC80 register are both readable and writable.
Bits 7~ 6 (TMR2[9], TMR2[8]): the most significant bits of PWM2 timer
Bits 5~2: set to “0” all the time.
Bits 1~ 0 (TMR1[9], TMR1[8]): the most significant bits of timer of PWM1
The content of IOC80 is read-only.
6.2.5 IOC90 (TMR1: PWM 1 Timer)
6.2.6 IOCA0 (TMR2: PWM 2 Timer)
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
25
EM78P301N
8-Bit Microcontroller with OTP ROM
6.2.7 IOCB0 (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
The IOCB0 register is both readable and writable.
Bit 7 (/PD57): Control bit used to enable internal pull-down of the P57 pin.
0: Enable internal pull-down
1: Disable internal pull-down (default)
Bit 6 (/PD56): Control bit used to enable internal pull-down of the P56 pin.
Bit 5 (/PD55): Control bit used to enable internal pull-down of the P55 pin.
Bit 4 (/PD54): Control bit used to enable internal pull-down of the P54 pin.
Bit 3 (/PD53): Control bit used to enable internal pull-down of the P53 pin.
Bit 2 (/PD52): Control bit used to enable internal pull-down of the P52 pin.
Bit 1 (/PD51): Control bit used to enable internal pull-down of the P51 pin.
Bit 0 (/PD50): Control bit used to enable internal pull-down of the P50 pin.
6.2.8 IOCC0 (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
-
-
-
-
-
-
OD60
The IOCC0 register is both readable and writable.
Bit 7 (OD67): Control bit used to enable open-drain output of the P67 pin.
0: Disable open-drain output
1: Enable open-drain output
Bits 6~1: Not used
Bit 0 (OD60): Control bit used to enable open-drain output of the P60 pin.
26
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.2.9 IOCD0 (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
The IOCD0 register is both readable and writable.
Bit 7 (/PH57): Control bit used to enable internal pull-high of the P57 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH56): Control bit used to enable internal pull-high of the P56 pin.
Bit 5 (/PH55): Control bit used to enable internal pull-high of the P55 pin.
Bit 4 (/PH54): Control bit used to enable internal pull-high of the P54 pin.
Bit 3 (/PH53): Control bit used to enable internal pull-high of the P53 pin.
Bit 2 (/PH52): Control bit used to enable internal pull-high of the P52 pin.
Bit 1 (/PH51): Control bit used to enable internal pull-high of the P51 pin.
Bit 0 (/PH50): Control bit used to enable internal pull-high of the P50 pin.
6.2.10 IOCE0 (WDT Control Register and Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
ADIE
CMPIE
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE): Control bit used to enable Watchdog Timer
0: Disable WDT (default)
1: Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS): Control bit used to define the function of the P60 (/INT) pin
0: P60, bidirectional I/O pin
1: /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC60) must be set to "1".
NOTE
■ When EIS is "0", the path of /INT is masked. When EIS is "1", the status of the /INT
pin can also be read by way of reading Port 6 (R6). Refer to Figure 6-5 (I/O Port and
I/O Control Register Circuit for P60 (/INT)) under Section 6.4 (I/O Ports).
■ EIS is both readable and writable.
Bit 5 (ADIE): ADIF interrupt enable bit
0: disable ADIF interrupt
1: enable ADIF interrupt
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
27
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 4 (CMPIE): CMPIF interrupt enable bit
0: Disable CMPIF interrupt
1: Enable CMPIF interrupt
Bit 3 (PSWE): Prescaler enable bit for WDT
0: Prescaler disable bit, WDT rate is 1:1
1: Prescaler enable bit, WDT rate is set at Bit 2 ~ Bit 0
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2
PSW1
PSW0
WDT Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
6.2.11 IOCF0 (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
DT2IE
DT1IE
PWM2IE
PWM1IE
EXIE
ICIE
TCIE
Note: The IOCF0 register is both readable and writable.
Individual interrupt is enabled by setting to “1” its associated control bit in the IOCF0 and
in IOCEO Bits 4 and 5.
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
Refer to Figure 6-7 Interrupt Input Circuit under Section 6 Interrupt.
Bit 7: Not used. Set “0” at all the time.
Bit 6 (DT2IE): DT2IE interrupt enable bit
0: Disable DT2IF interrupt
1: Enable DT2IF interrupt
Bit 5 (DT1IE): DT1IE interrupt enable bit
0: Disable DT1IF interrupt
1: Enable DT1IF interrupt
Bit 4 (PWM2IE): PWM2IE interrupt enable bit
0: Disable PWM2IF interrupt
1: Enable PWM2IF interrupt
Bit 3 (PWM1IE): PWM1IE interrupt enable bit
0: Disable PWM1IF interrupt
1: Enable PWM1IF interrupt
28
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 2 (EXIE): EXIF interrupt enable bit
0: Disable EXIF interrupt
1: Enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: Disable ICIF interrupt
1: Enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit.
0: Disable TCIF interrupt
1: Enable TCIF interrupt
6.2.12 IOC51 (High Sink Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HS57
HS56
HS55
HS54
HS53
HS52
HS51
HS50
Bit 7 (HS57): Output High Sink current Select for P57.
Bit 6 (HS56): Output High Sink current Select for P56.
Bit 5 (HS55): Output High Sink current Select for P55
Bit 4 (HS54): Output High Sink current Select for P54.
Bit 3 (HS53): Output High Sink current Select for P53.
Bit 2 (HS52): Output High Sink current Select for P52.
Bit 1 (HS51): Output High Sink current Select for P51.
Bit 0 (HS50): Output High Sink current Select for P50
HSxx
VDD = 5V, Sink Current
0
12 mA (in 0.1VDD)
1
25 mA (in 0.1VDD)
6.2.13 IOC61 (High Sink Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HS67
-
-
-
-
-
-
HS60
Bit 7 (HS67): Output High Sink current Select for P67.
Bits 6~1: Not used. Set “0” all the time
Bit 0 (HS60): Output High Sink current Select for P60.
HSxx
VDD = 5V, Sink Current
0
12 mA (in 0.1VDD)
1
25 mA (in 0.1VDD)
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
29
EM78P301N
8-Bit Microcontroller with OTP ROM
6.2.14 IOC71 (High Driver Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HD57
HD56
HD55
HD54
HD53
HD52
HD51
HD50
Bit 7 (HD57): Output High Driver current Select for P57.
Bit 6 (HD56): Output High Driver current Select for P56.
Bit 5 (HD55): Output High Driver current Select for P55.
Bit 4 (HD54): Output High Driver current Select for P54.
Bit 3 (HD53): Output High Driver current Select for P53.
Bit 2 (HD52): Output High Driver current Select for P52.
Bit 1 (HD51): Output High Driver current Select for P51.
Bit 0 (HD50): Output High Driver current Select for P50.
HDxx
VDD = 5V, Driver Current
0
6 mA (in 0.9VDD)
1
18 mA (in 0.9VDD)
6.2.15 IOC81 (High Driver Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HD67
-
-
-
-
-
-
HD60
Bit 7 (HD67): Output High Driver current Select for P67.
Bits 6~1: Not used
Bit 0 (HD60): Output High Driver current Select for P60.
30
HDxx
VDD = 5V, Driver Current
0
6 mA (in 0.9VDD)
1
18 mA (in 0.9VDD)
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.2.16 IOCF1 (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
-
-
-
-
-
-
/PH60
Note: The IOCD0 register is both readable and writable.
Bit 7 (/PH67): Control bit used to enable pull-high of the P67 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bits 6~1: Not used.
Bit 0 (/PH60): Control bit used to enable internal pull-high of the P60 pin.
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT
respectively. The PST2 ~ PST0 bits of the CONT register are used to determine the
ratio of the TCC prescaler, and the PSW2 ~ PSW0 bits of the IOCE0 register are used
to determine the prescaler of WDT. The prescaler counter is cleared by the instructions
each time such instructions are written into TCC. The WDT and prescaler will be
cleared by the “WDTC” and “SLEP” instructions. Figure 6-3 depicts the block diagram
of TCC/WDT.
TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock
(Fm/Fs) or external signal input (edge selectable from the TCC pin). If TCC signal
source is from the internal clock, TCC will be incremented by 1 at every instruction
cycle (without prescaler). If TCC signal source is from an external clock, the TCC will
be incremented by 1 at every falling edge or rising edge of the TCC pin. The TCC pin
input time length (kept at High or Low level) must be greater than Fm clock or Fs clock,
determine by Bank 1 RF CPUS bit.
NOTE
The internal TCC will stop running when in sleep mode. However, during AD
conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is
enabled, the TCC will keep on running.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
31
EM78P301N
8-Bit Microcontroller with OTP ROM
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or in sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal mode
through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10
IOCE0 (WDT Control and Interrupt Mask Registers 2). With no prescaler, the WDT
1
2
time-out period is approximately 18ms or 4.5ms .
Fs
Fm
MUX
0
TCC Pin
1
8-Bit Counter
Data Bus
MUX
8 to 1 MUX
TE (CONT)
TCC (R1)
Prescaler
TS (CONT)
WDT
TCC overflow
interrupt
PST2~0
(CONT)
8-Bit counter
8 to 1 MUX
Prescaler
WDTE
(IOCE0)
PSW2~0
(IOCE0)
WDT Time out
Figure 6-3 TCC and WDT Block Diagram
6.4 I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5
is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain
output set through software. Port 5 features an input status changed interrupt (or
wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O
control register (IOC50 ~ IOC70). The I/O registers and I/O control registers are both
readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are
illustrated in Figures 6-4, 6-5, 6-6, and 6-7.
1
VDD=5V, WDT time-out period = 16.5ms ± 30% at 25°C
VDD=3V, WDT time-out period = 18ms ± 30% at 25°C
2
VDD=5V, WDT time-out period = 4.2ms ± 30% at 25°C
VDD=3V, WDT time-out period = 4.5ms ± 30% at 25°C
32
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
PCRD
Q
PORT
P
R
D
_
CLK
Q
C
L
Q
P
R
PCWR
IOD
D
_
CLK
Q
C
L
PDWR
PDRD
0
1
M
U
X
Note: Pull-high and Open-drain are not shown in the figure.
Figure 6-4 I/O Port and I/O Control Register Circuit for Port 6 and Port 7
PCRD
P
Q R D
_ CLK
Q C
L
Q P
R D
_ CLK
Q C
L
PORT
Bit 6 of IOCE0
P
R Q
CLK _
C Q
L
D
PCWR
IOD
PDWR
0
1
M
U
X
PDRD
INT
Note: Pull-high and Open-drain are not shown in the figure.
Figure 6-5 I/O Port and I/O Control Register Circuit for P60 (/INT)
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
33
EM78P301N
8-Bit Microcontroller with OTP ROM
PCRD
Q
P
R
D
_
CLK
Q
C
L
PCWR
P50 ~ P57
Q
PORT
0
P
R
IOD
D
_
CLK
Q
C
L
PDWR
M
U
X
1
PDRD
TI n
D
P
R
CLK
C
L
Q
_
Q
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-6 I/O Port and I/O Control Register Circuit for Ports 50~57
IOCF.1
RF.1
TI 0
TI 1
….
TI 8
Figure 6-7 Port 5 Block Diagram with Input Change Interrupt/Wake-up
34
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function
(1) Wake-up
(2) Wake-up and Interrupt
(a) Before Sleep
(a) Before Sleep
1. Disable WDT
1. Disable WDT
2. Read I/O Port 5 (MOV R5,R5)
2. Read I/O Port 5 (MOV R5,R5)
3. Execute "ENI" or "DISI"
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set RE ICWE =1)
4. Enable wake-up bit (Set RE
ICWE =1)
5. Execute "SLEP" instruction
5. Enable interrupt (Set IOCF ICIE =1)
(b) After wake-up
6. Execute "SLEP" instruction
Next instruction
(b) After wake-up
1. IF "ENI" Interrupt Vector (006H)
2. IF "DISI" Next instruction
(3) Interrupt
(a) Before Port 5 pin change
1. Read I/O Port 5 (MOV R5,R5)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set IOCF ICIE =1)
(b) After Port 5 pin changed (interrupt)
1. IF "ENI" Interrupt Vector (006H)
2. IF "DISI" Next instruction
6.5 Reset and Wake-up
6.5.1 Reset and Wake-up Operation
A reset is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
3
The device is kept in reset condition for a period of approximately 18ms (except in LXT
mode) after the reset is detected. When in LXT2 mode, the reset time is 500 ms. Two
3
4
choices (18ms or 4.5ms ) are available for WDT-time out period. Once a reset occurs,
the following functions are performed (the initial Address is 000h):
The oscillator continues running, or will be started (if in sleep mode).
The Program Counter (R2) is set to all "0".
3
VDD=5V, Setup time period = 16.5 ms ± 30% at 25°C
VDD=3V, Setup time period = 18 ms ± 30% at 25°C.
4
VDD=5V, Setup time period = 4.2 ms ± 30%. at 25°C
VDD=3V, Setup time period = 4.5 ms ± 30% at 25°C.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
35
EM78P301N
8-Bit Microcontroller with OTP ROM
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog Timer and prescaler are cleared
When power is switched on, the upper three bits of R3 is cleared
The IOCB0 register bits are set to all "1"
The IOCC0 register bits are set to all "0"
The IOCD0 register bits are set to all "1"
Bits 7, 5, and 4 of the IOCE0 register are cleared
Bits 5 and 4 of the RE register are cleared
RF and IOCF0 registers are cleared
Executing the “SLEP” instruction will assert the sleep (power down) mode (when
IDLE=”0”.). While entering into sleep mode, the Oscillator, TCC, TMR1 and TMR2 are
stopped. The WDT (if enabled) is cleared but keeps on running.
During AD conversion, when “SLEP” instruction is set; the Oscillator, TCC, TMR1 and
TMR2 keep on running. The WDT (if enabled) is cleared but keeps on running.
The controller can be awakened by:
Case 1 External reset input on /RESET pin
Case 2 WDT time-out (if enabled)
Case 3 Port 5 input status changes (if ICWE is enabled)
Case 4 AD conversion completed (if ADWE is enabled)
Case 5 Low Voltage Detector (if LVDWE is enabled)
The first two cases (1 and 2) will cause the EM78P301N to reset. The T and P flags of
R3 can be used to determine the source of the reset (wake-up). Cases 3, 4 and 5 are
considered the continuation of program execution and the global interrupt ("ENI" or
"DISI" being executed) determines whether or not the controller branches to the
interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will
begin to execute from Address 0x06 (Case 3), 0x0C (Case 4) and 021 (Case 5) after
wake-up. If DISI is executed before SLEP, the execution will restart from the instruction
next to SLEP after wake-up.
36
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Only one of Cases 2 to 5 can be enabled before entering into sleep mode. That is:
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78P301N can be awakened only with Case 1 or Case 2. Refer to the
section on Interrupt (Section 6.6) for further details.
Case [b] If Port 5 Input Status Change is used to wake up the EM78P301N and the
ICWE bit of the RE register is enabled before SLEP, and WDT must be
disabled. Hence, the EM78P301N can be awakened only with Case 3.
Wake-up time is dependent on the oscillator mode. In RC mode, wake-up
time is 10 s (for stable oscillators). In XT (4 MHz) mode, wake-up time is
800 s (for stable oscillators), and in LXT2 mode, Wake-up time is 2~3s.
Case [c] If AD conversion completed is used to wake-up the EM78P301N and ADWE
bit of RE register is enabled before SLEP, WDT must be disabled by
software. Hence, the EM78P301N can be awakened only with Case 4. The
wake-up time is 16 TAD (ADC clock period).
Case[d] If Low voltage detector is used to wake-up the EM78P301N and the LVDWE
bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled by
software. Hence, the EM78P301N can be awakened only with Case 5.
Wake-up time is dependent on the oscillator mode.
If Port 5 Input Status Change Interrupt is used to wake up the EM78P301N (as in Case
[b] above), the following instructions must be executed before SLEP:
BC
R3, 6
; Select Segment 0
MOV
A, @00xx1110b
; Select WDT prescaler and Disable WDT
IOW
IOCE0
; Clear WDT and prescaler
WDTC
MOV
R5, R5
; Read Port 5
; Enable (or disable) global interrupt
ENI (or DISI)
MOV
A, @xxxxxx1xb
MOV
RE
MOV
A, @xxxxxx1xb
IOW
IOCF0
SLEP
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
; Enable Port 5 input change wake-up bit
; Enable Port 5 input change interrupt
; Sleep
37
EM78P301N
8-Bit Microcontroller with OTP ROM
Similarly, if the Comparator Interrupt is used to wake up the EM78P301N (as in
Case [c]), the following instructions must be executed before SLEP:
BC
R3, 6
; Select Segment 0
MOV
A, @xxx10XXXb
; Select a comparator and P64 functions
; as CO pin
IOW
IOC80
MOV
A, @00x11110b
IOW
IOCE0
WDTC
; Clear WDT and prescaler
ENI (or DISI)
; Enable (or disable) global interrupt
MOV
A, @xxx0x1xxb
MOV
RE
SLEP
38
; Select WDT prescaler and Disable WDT,
; and enable comparator output status
; change interrupt
; Enable comparator output status
; change wake-up bit
; Sleep
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.5.1.1 Wake-up and Interrupt Modes Operation Summary
The controller can be awakened from sleep mode and idle mode. The wake-up signals
are listed as follows.
Wake-up
Signal
Condition
Signal
EXWE = 0
EXIE = 0
EXWE = 0
EXIE = 1
Sleep Mode
DISI
ENI
Wake-up is invalid
Wake-up is invalid
Idle Mode
DISI
ENI
Wake-up is invalid
Wake-up is invalid
External
Green Mode
Normal Mode
DISI
DISI
ENI
Interrupt is invalid
ENI
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake up
Wake up
+
+
Interrupt is invalid
Interrupt is invalid
Next Instruction
Next Instruction
Wake up Wake up Wake up Wake up
Interrupt
Interrupt
EXWE = 1
+
+
+
+
Next
+
Next
+
EXIE = 1
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
ICWE = 0
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
ICIE = 0
Interrupt
Interrupt
ICWE = 0
Next
+
Next
+
Wake-up is invalid
Wake-up is invalid
ICIE = 1
Instruction Interrupt Instruction Interrupt
Vector
Vector
Port 5
Wake up
Wake up
Pin change ICWE = 1
+
+
Interrupt is invalid
Interrupt is invalid
ICIE = 0
Next Instruction
Next Instruction
Wake up Wake up Wake up Wake up
Interrupt
Interrupt
ICWE = 1
+
+
+
+
Next
+
Next
+
ICIE = 1
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
INT
EXWE = 1,
EXIE = 0
TCIE = 0
TCC
Overflow
Wake-up is invalid
TCIE = 1
ADWE = 0
ADIE = 0
AD
Conversion
complete
Wake-up is invalid
ADWE = 0
ADIE = 1
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Wake up Wake up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake up
Wake up
+
+
Interrupt is invalid
Interrupt is invalid
Next Instruction
Next Instruction
Wake up Wake up Wake up Wake up
Interrupt
Interrupt
ADWE = 1,
+
+
+
+
Next
+
Next
+
ADIE = 1
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
ADWE = 1
ADIE = 0
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
39
EM78P301N
8-Bit Microcontroller with OTP ROM
Wake-up
Signal
PWM1
Condition
Signal
PWM2
ENI
PWM1IE=1
PWM2IE=0
Wake-up is invalid
DT1IE = 0
Interrupt
DT1IE = 1
DT2IE = 0
Interrupt
ENI
DT2IE = 1
LVDWE = 0
Wake-up is invalid
LVDIE = 0
DISI
ENI
Interrupt is invalid
Normal Mode
DISI
ENI
Interrupt is invalid
Interrupt is invalid
Interrupt is invalid
Wake up Wake up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Interrupt is invalid
Interrupt is invalid
Wake up Wake up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Wake-up is invalid
Wake-up is invalid
Green Mode
Wake up Wake up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Wake-up is invalid
Wake-up is invalid
PWM2 Duty
DISI
Wake-up is invalid
PWM2IE=1
PWM1 Duty
Idle Mode
Wake-up is invalid
Wake-up is invalid
period
interrupt
DISI
PWM1IE=0
Period
Interrupt
Sleep Mode
Interrupt is invalid
Interrupt is invalid
Wake up Wake up
Interrupt
Interrupt
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid.
Interrupt
Interrupt
Next
+
Next
+
Wake-up is invalid
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake up
Wake up
+
+
Interrupt is invalid. Interrupt is invalid.
Next Instruction
Next Instruction
Wake up Wake up Wake up Wake up
Interrupt
Interrupt
+
+
+
+
Next
+
Next
+
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
LVDWE = 0
Wake-up is invalid
LVDIE = 1
Low Voltage
Detector
LVWE = 1
LVDIE = 0
LVDWE = 1
LVDIE = 1
WDT
Timeout
Low voltage
Reset
40
WDTE = 1
Wake up + Reset
Wake up + Reset
Reset
Reset
Wake up + Reset
Wake up + Reset
Reset
Reset
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.5.1.2
Address
Name
Register Initial Values after Reset
Summary of Registers Initialized Values
Reset Type
Bit Name
N/A
IOC50
IOC60
IOC70
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C57
C56
C55
C54
C53
C52
C51
C50
–
–
–
–
–
–
–
–
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
C67
C60
Type
–
–
–
–
–
–
–
–
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
Bit Name
N/A
Bit 6
Type
Wake-up from Pin
Change
Bit Name
N/A
Bit 7
C71
C70
Power-on
0
0
0
0
0
0
1
1
/RESET and WDT
0
0
0
0
0
0
1
1
P
P
P
P
P
P
0
0
0
0
0
0
Wake-up from Pin
P
P
Change
Bit Name
TMR2[9] TMR2[8]
Power-on
0
0
N/A
IOC80
/RESET and WDT
Wake-up from Pin
Change
Bit Name
N/A
Power-on
IOCB0
(PDCR) /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
N/A
IOCC0
(ODCR) /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
N/A
N/A
IOCD0
(PHCR) /RESET and WDT
Wake-up from Pin
Change
Bit Name
IOCE0
Power-on
(WDTCR
/RESET and WDT
and
IMR2) Wake-up from Pin
Change
TMR1[9] TMR1[8]
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
OD67
OD60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
WDTE
EIS
ADIE
CMPIE
PSWE
PSW2
PSW1
PSW0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
41
EM78P301N
8-Bit Microcontroller with OTP ROM
Address
N/A
N/A
N/A
Name
IOCF0
(IMR)
Reset Type
Bit 7
Bit 6
Bit 5
Bit Name
Power-on
DT2IE
DT1IE
0
0
0
0
0
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
0
0
0
0
P
P
P
HS57
HS56
0
0
0
IOC51
(HSCR1) /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
IOC61
(HSCR2) /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
N/A
N/A
N/A
IOC71
(HDCR1) /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
IOC81
(HDCR2) /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
IOCF1
(PHCR) /RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
N/A
000
001
CONT
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
Bit 3
Bit 2
Bit 1
Bit 0
EXIE
ICIE
TCIE
0
0
0
0
0
0
0
P
P
P
P
P
HS55
HS54
HS53
HS52
HS51
HS50
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
HS67
HS60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
HD57
HD56
HD55
HD54
HD53
HD52
HD51
HD50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
HD67
HD60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
/PH67
/PH60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
0
0
P
P
P
P
P
P
P
P
PWM2IE PWM1IE
–
–
–
–
–
–
–
–
U
U
U
U
U
U
U
U
R0 (IAR) /RESET and WDT
Wake-up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
–
–
–
–
–
–
–
–
Power-on
R1 (TCC) /RESET and WDT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
42
Bit 4
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Address
002
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
–
–
–
–
–
–
–
–
Power-on
R2 (PC) /RESET and WDT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
003
004
005
006
007
008
009
00A
Jump to Address 0x06 or continue to execute next instruction
Bit Name
RST
IOCS
-
T
P
Z
DC
C
Power-on
0
0
0
1
1
U
U
U
R3 (SR) /RESET and WDT
0
0
0
t
t
P
P
P
Wake-up from Pin
Change
1
P
P
t
t
P
P
P
Bit Name
SBANK
BS0
–
–
–
–
–
–
Power-on
0
0
U
U
U
U
U
U
R4 (RSR) /RESET and WDT
0
0
P
P
P
P
P
P
Wake-up from Pin
Change
0
P
P
P
P
P
P
P
Bit Name
P57
P56
P55
P54
P53
P52
P51
P50
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P67
P60
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
P71
P70
Power-on
0
0
0
0
0
0
1
1
/RESET and WDT
0
0
0
0
0
0
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
0
0
0
0
P
P
P
P
Bit Name
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
0
P
P
Bit Name
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
VREF1
VREF0
ADICS
Bank 0 Power-on
RA
/RESET and WDT
(ADOC) Wake-up from Pin
Change
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bank 0
R5
Bank 0
R6
Bank 0
R7
Bank 0
R8
(AISR)
Bank 0
R9
/RESET and WDT
(ADCON) Wake-up from Pin
Change
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
43
EM78P301N
8-Bit Microcontroller with OTP ROM
Addr.
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
Power-on
Bank 0
/RESET and
RB
WDT
(ADDATA)
Wake-up from
Pin Change
Bit Name
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
AD11
AD10
AD9
AD8
Power-on
Bank 0
/RESET and
RC
WDT
(ADDATA1H)
Wake-up from
Pin Change
Bit Name
0
0
0
0
U
U
U
U
0
0
0
0
U
U
U
U
P
P
P
P
P
P
P
P
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
/LVD
LVDIF
ADIF
-
ADWE
-
ICWE
LVDWE
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
DT2IF
DT1IF
EXIF
ICIF
TCIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
MLB
RBit9
RBit8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
RBit7
RBit6
RBit5
RBit4
RBit3
RBit2
RBit1
RBit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
00B
00C
00D
00E
00F
005
006
007
44
Power-on
Bank 0
/RESET and
RD
WDT
(ADDATA1L)
Wake-up from
Pin Change
Bit Name
Bank 0
Power-on
RE
/RESET and
(ISR2
WDT
and
Wake-up from
WUCR)
Pin Change
Bit Name
Power-on
Bank 0
/RESET and
RF
WDT
(ISR2)
Wake-up from
Pin Change
Bit Name
Power-on
Bank 1
/RESET and
R5
WDT
(TBHP)
Wake-up from
Pin Change
Bit Name
Power-on
Bank 1
/RESET and
R6
WDT
(TBLP)
Wake-up from
Pin Change
Bit Name
Power-on
Bank 1
/RESET and
R7
WDT
(PWMCON)
Wake-up from
Pin Change
PWM2IF PWM1IF
PWMCAS PWM2E PWM1E
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Address
008
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
T2EN
T1EN
T2P2
T2P1
T2P0
T1P2
T1P1
T1P0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bank 1
R8
/RESET and WDT
(TMRCON)
Wake-up from Pin
Change
Bit Name
009
Bank 1
R9
(PRD1)
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
00A
00B
00C
00D
00E
00F
0x10
~
0x3F
Bank 1
RA
(PRD2)
Bank 1
RB
(DT1)
Bank 1
RC
(DT2)
PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0]
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
Power-on
/RESET and WDT
Bank 1
RF
(SCR)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
DT1[6]
DT1[5]
DT1[4]
DT1[3]
DT1[2]
DT1[1]
DT1[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
DT2[6]
DT2[5]
DT2[4]
DT2[3]
DT2[2]
DT2[1]
DT2[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
Wake-up from Pin
P
Change
DT1[7]
Bit Name
0
Power-on
0
/RESET and WDT
Wake-up from Pin
P
Change
DT2[7]
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
P
Change
DT2[9]
Bit Name
Bank 1 Power-on
RD
(DT and /RESET and WDT
PRD HB) Wake-up from Pin
Change
Bank 1
RE
(LVDCR
and
WUCR)
0
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
/RESET and WDT
Wake-up from Pin
Change
Bit Name
Power-on
R10~R3F /RESET and WDT
Wake-up from Pin
Change
DT2[8]
DT1[9]
DT1[8]
0
0
0
0
PRD2[9] PRD2[8] PRD1[9] PRD1[8]
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
LVDIE
LVDEN
LVD1
LVD0
EXWE
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
P
P
P
P
P
P
P
P
-
TIMERSC
CPUS
IDLE
SHS1
SHS0
RCM1
RCM0
0
1
1
0
1
1
Word 1
0
1
1
0
1
1
Word 1
P
P
P
P
P
P
P
P
–
–
–
–
–
–
–
–
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Legend: “” = not used
“u” = unknown or don’t care
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
“P” = previous value before reset
“t” = check “Reset Type” Table in Section 6.5.2
45
EM78P301N
8-Bit Microcontroller with OTP ROM
6.5.1.3
Controller Reset Block Diagram
VDD
D
Oscillator
Q
CLK
CLK
CLR
Power-on Reset
Voltage
Detector
ENWDTB
WDT Timeout
Reset
Setup time
WDT
/RESET
Figure 6-8 Controller Reset Block Diagram
6.5.2 T and P Status under the Status Register
A reset condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
The values of T and P as listed in the table below, are used to check how the processor
wakes up.
Reset Type
RST
T
P
Power-on
0
1
1
/RESET during Operating mode
0
*P
*P
/RESET wake-up during Sleep mode
0
1
0
LVR during Operating mode
0
*P
*P
LVR wake-up during Sleep mode
0
1
0
WDT during Operating mode
0
0
1
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
1
0
1
0
0
*P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event
RST
T
P
Power-on
0
1
1
WDTC instruction
*P
1
1
WDT time-out
0
0
*P
SLEP instruction
*P
1
0
Wake-up on pin changed during Sleep mode
1
1
0
*P: Previous value before reset
46
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.6 Interrupt
The EM78P301N has nine interrupts enumerated below:
1. PWM 1~2 period match and duty cycle match overflow interrupt
2. Port 5 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin]
4. Analog to Digital conversion completed
5. Low voltage detector Interrupt
Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV
R5, R5") is necessary. Each Port 5 pin will have this feature if its status changes. The
Port 5 Input Status Change Interrupt will wake up the EM78P301N from sleep mode if it
is enabled prior to going into sleep mode by executing SLEP instruction. When wake
up occurs, the controller will continue to execute program in-line if the global interrupt is
disabled. If enabled, the global interrupt will branch out to the Interrupt Vector 006H.
External interrupt equipped with digital noise rejection circuit (input pulse less than
system clock time) is eliminated as noise. However, under Low Crystal oscillator
(LXT2) mode the noise rejection circuit will be disabled. Edge selection is possible with
INTE of CONT. When an interrupt is generated by the External interrupt (when
enabled), the next instruction will be fetched from Address 003H. Refer to Word 1
Bits 9 and 8, Section 6.14.2, Code Option Register (Word 1) for digital noise rejection
definition.
RF and RE are the interrupt status registers that record the interrupt requests in the
relative flags/bits. IOCF0 and IOCE0 are Interrupt mask registers. The global interrupt
is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
When interrupt mask bits is “Enable”, the flag in the Interrupt Status Register (RF) is set
regardless of the ENI execution. Note that the result of RF will be the logic AND of RF
and IOCF0 (refer to figure below). The RETI instruction ends the interrupt routine and
enables the global interrupt (the ENI execution).
When an interrupt is generated by the Timer clock/counter (when enabled), the next
instruction will be fetched from Address 009, 012, 015, 018 and 01BH (PWM 1~2
period match and duty match respectively).
When an interrupt generated by the AD conversion is completed (if enabled), the next
instruction will be fetched from Address 00CH.
When an interrupt is generated by the Low Voltage Detect (when enabled), the next
instruction will be fetched from Address 021H (Low Voltage Detector interrupt).
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
47
EM78P301N
8-Bit Microcontroller with OTP ROM
Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and
R4 will be replaced by the new interrupt. After an interrupt service routine is completed,
the ACC, R3, and R4 registers are restored.
VDD
D
Oscillator
Q
CLK
CLK
CLR
Power-On Reset
Low Voltage Reset
Setup time
WDTE
WDT
WDT Timeout
Reset
/RESET
Interrupt sources
ACC
Interrupt
occurs
Stack ACC
ENI/DISI
R3
RETI
Stack R3
Stack R4
R4
Figure 6-9 Interrupt Back-up Diagram
In EM78P301N, each individual interrupt source has its own interrupt vector as
depicted in the table below.
Interrupt Vector
Interrupt Status
Priority *
003H
External interrupt
2
006H
Port 5 pin change
3
009H
TCC overflow interrupt
4
00CH
AD conversion complete interrupt
5
012H
PWM1 period match interrupt
6
015H
PWM2 period match interrupt
7
018H
PWM1 duty match interrupt
8
01BH
PWM2 duty match interrupt
9
021H
Low Voltage Detector interrupt
1
Note: *Priority: 1 = highest ; 9 = lowest priority
48
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.7 Analog-to-Digital Converter (ADC)
The analog-to-digital circuitry consists of an 8-bit analog multiplexer; three control
registers (AISR/R8, ADCON/R9, and ADOC/RA), three data registers (ADDATA/RB,
ADDATA1H/RC, and ADDATA1L/RD) and an ADC with 12-bit resolution as shown in
the functional block diagram below. The analog reference voltage (Vref) and the
analog ground are connected via separate input pins. Connecting to an external VREF
is more accurate than connecting to an internal VDD.
The ADC module utilizes successive approximation to convert the unknown analog
signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and
ADDATA1L. Input channels are selected by the analog input multiplexer via the
ADCON register Bits ADIS2, ADIS1 and ADIS0.
OPOUT
VDD
VREFP
16 to 1 Analog switch
1/4 VDD PowerDet.
AD7
ADC
(Successive Approximation)
Power Down
Start to Convert
Fsub
Fmain/4
Fmain/1
4 to 1
MUX
Fmain/16
AD0
Fmain/64
7-0
AISR
2~0
ADCON
6
ADCON
5
4
ISR
4
11 10 9 8 7 6 5 4 3 2 1 0
IMR
ADDATA1H
ADDATA1L
4
3
1 0
ADCON
DATA BUS
Figure 6-10 Analog-to-Digital Conversion Functional Block Diagram
This is a 12-bit successive approximation register analog to digital converter (SAR
ADC). There are two reference voltages for SAR ADC. The positive reference voltage
can select internal AVDD, internal voltage sources or external input pin by setting the
VREFP and VPIS[1:0] bits in ADCR2. Connecting to external positive reference
voltage provides more accuracy than using internal AVDD.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
49
EM78P301N
8-Bit Microcontroller with OTP ROM
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)
6.7.1.1
Bank 0 R8 (AISR: ADC Input Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
The AISR register individually defines the P5, P6 and P7 pins as analog inputs or as
digital I/O.
Bit 7 (ADE7): AD converter enable bit of P57 pin
0: Disable ADC7, P57 functions as I/O pin
1: Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P55 pin
0: Disable ADC6, P55 functions as I/O pin
1: Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P70 pin
0: Disable ADC5, P70 functions as I/O pin
1: Enable ADC5 to function as analog input pin
Bit 4 (ADE4): AD converter enable bit of P67 pin
0: Disable ADC4, P67 functions as I/O pin
1: Enable ADC4 to function as analog input pin
Bit 3 (ADE3): AD converter enable bit of P53 pin
0: Disable ADC3, P53 functions as I/O pin
1: Enable ADC3 to function as analog input pin
Bit 2 (ADE2): AD converter enable bit of P52 pin
0: Disable ADC2, P52 functions as I/O pin
1: Enable ADC2 to function as analog input pin
Bit 1 (ADE1): AD converter enable bit of P51 pin
0: Disable ADC1, P51 acts as I/O pin
1: Enable ADC1 acts as analog input pin
Bit 0 (ADE0): AD converter enable bit of P50 pin
0: Disable ADC0, P50 functions as I/O pin
1: Enable ADC0 to function as analog input pin
50
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.7.1.2
Bank 0 R9 (ADCON: ADC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
The ADCON register controls the operation of the AD conversion and determines
which pin should be currently active.
Bit 7 (VREFS): The input source of the ADC Vref
0: The ADC Vref is connected to Vdd (default value), and the
VREF/TCC/P54 pin carries out the P54 function
1: The ADC Vref is connected to VREF/TCC/P54
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If
P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 (TS) must be “0”.
The P54/TCC/VREF pin priority is as follows:
P54/TCC/VREF Pin Priority
High
Medium
Low
VREF
TCC
P54
Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The prescaler of ADC oscillator clock rate
00 = 1: 16 (default value)
01 = 1: 4
10 = 1: 64
11 = 1: 1
System
Mode
Normal
Mode
Green
Mode
CKR[1:0]
Operating Clock
of ADC (FAD = 1 / TAD)
Max. FMain
(VDD = 2.5V ~ 3V)
Max. FMain
(VDD = 3V ~ 5.5V)
00
(default)
FOSC /16
4 MHz
16 MHz
01
FOSC /4
1 MHz
4 MHz
10
FOSC /64
16 MHz
11
FOSC /1
1 MHz
xx
16k/128kHz
16k/128kHz
Bit 4 (ADRUN): ADC starts to RUN
0: Reset upon completion of the conversion. This bit cannot be reset
though software.
1: AD conversion is started. This bit can be set by software.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
51
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 3 (ADPD): ADC Power-down mode
0: Switch off the resistor reference to conserve power even while the
CPU is operating
1: ADC is operating
Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select
ADICS
ADIS2
ADIS1
ADIS0
Analog Input Select
0
0
0
0
ADIN0/P50
0
0
0
1
ADIN1/P51
0
0
1
0
ADIN2/P52
0
0
1
1
ADIN3/P53
0
1
0
0
ADIN4/P67
0
1
0
1
ADIN5/P70
0
1
1
0
ADIN6/P55
0
1
1
1
ADIN7/P57
1
0
X
X
OPOUT
1
1
x
x
Internal, 1/4 VDD
These bits can only be changed when the ADIF bit and the ADRUN bit are both Low.
6.7.1.3
RA (ADOC: AD Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
VREF1
VREF0
ADICS
Bit 7 (CALI): Calibration enable bit for ADC offset
0: disable Calibration
1: enable Calibration
Bit 6 (SIGN): Polarity bit of offset voltage
0: Negative voltage
1: Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
52
VOF[2]
VOF[1]
VOF[0]
EM78P301N
0
0
0
0
0
1
0LSB
2LSB
0
1
0
4LSB
0
1
1
6LSB
1
0
0
8LSB
1
0
1
10LSB
1
1
0
12LSB
1
1
1
14LSB
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 2 ~ Bit 1: ADC internal reference voltage source.
VREF1
VREF0
ADC Internal Reference Voltage
0
0
VDD
0
1
4.0V ± 1%
1
0
3.0V ± 1%
1
1
2.0V ± 1%
Bit 0 (ADICS): ADC Internal Channel Select (select ADC internal 1/4 VDD or OP
output pin connects to ADC input)
0: disable
1: enable
NOTE
1. If VREF [1:0]=00, internal reference will not turn on. If VREF[1:0]≠ 00, internal
reference will turn on automatically. Moreover, the power of internal reference is
irrelevant to ADC.
2. When using internal voltage reference, users need to wait for at least 50µs when it
is the first time to enable and stabilize the voltage reference. Un-stabilized
reference makes conversion result inaccurate. After that, users only need to wait
for at least 6μs whenever switching voltage references.
6.7.1.4
Bank 1 RF (IRC Switch Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TIMERSC
CPUS
IDLE
SHS1
SHS0
RCM1
RCM0
Bits 3 ~ 2 (SHS1 ~ SHS0): Select AD sample and hold Timing Select. (Recommend at
least 4 s, TAD: Period of ADC Operating Clock)
SHS1
SHS0
ADC Sample and Hold (TAD)
0
0
2 x TAD
0
1
4 x TAD
1
0
8 x TAD
1
1
12 x TAD (default)
6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC,
ADDATA1L/RD)
When AD conversion is completed, the result is loaded into the ADDATA1H and
ADDATA1L. The ADIF is set if ADIE is enabled.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
53
EM78P301N
8-Bit Microcontroller with OTP ROM
6.7.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation AD converter are
dependent on the properties of the ADC. The source impedance and the internal
sampling impedance directly affect the time required to charge the sample and hold
capacitor. The application program controls the length of the sample time to meet the
specified accuracy. The maximum recommended impedance for the analog source is
10 k at VDD = 5V. After the analog input channel is selected; this acquisition time
must be done before AD conversion can be started.
6.7.4 AD Conversion Time
CKR[2:0] select the conversion time (TAD). This allows the MCU to run at maximum
frequency without sacrificing the accuracy of the AD conversion. The following tables
show the relationship between TAD and the maximum operating frequencies. The TAD
is 0.5 µs for 3V~5.5V and TAD is 2 µs for 2.5V~3V.
VDD = 3V ~ 5.5V (TAD is 1 µs)
System
Mode
Normal
Mode
Green Mode
CKR[1:0]
Operating Clock
of ADC
(FAD = 1 / TAD)
Max. FMain
Conversion Time
of One Word
(VDD = 3V ~ 5.5V)
(SHS[1:0] = 10*)
00
FMain / 16
16 MHz
20 s
01
FMain / 4
4 MHz
20 s
10
FMain / 64
-
-
11
FMain / 1
1 MHz
20 s
xx
FSub
128 kHz
157 s
* Conversion Time = Sample and Hold (SHS [1:0]=10, 8 TAD) + 12 Bit Conversion Time
(12 TAD) + Delay Time between setting ADSTART bit and starting first TAD.
VDD = 2.5V ~ 3V (TAD is 4 µs)
System
Mode
Normal
Mode
Green Mode
Operating Clock
of ADC
(FAD = 1 / TAD)
Max. FMain
Conversion Time
of One Word
(VDD = 2.5V ~ 3V)
(SHS[1:0] = 10*)
00
FMain / 16
4 MHz
82 s
01
FMain / 4
1 MHz
82 s
10
FMain / 64
-
-
11
FMain / 1
xx
-
CKR[1:0]
128 kHz
157 s
* Conversion Time = Sample and Hold (SHS [1:0]=10, 8 TAD) + 12 Bit Conversion Time
(12 TAD) + Delay Time between setting ADSTART bit and starting first TAD (0.5 TAD).
54
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
NOTE
Pin not used as an analog input can be used as regular input or output pin.
During conversion, do not perform output instruction to maintain precision for all of
the pins.
6.7.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during sleep mode. As the SLEP instruction is
executed, all the MCU operations will stop except for the Oscillator, TCC, PWM1,
PMW2 and AD conversion.
The AD Conversion is considered completed as determined by:
1. The ADRUN bit of the R9 register is cleared to “0”.
2. The ADIF bit of the Bank 0 RE register is set to “1”.
3. The ADWE bit of the Bank 0 RE register is set to “1”. Wakes up from ADC
conversion (where it remains in operation during sleep mode).
4. Wake up and execution of the next instruction if the ADIE bit of the IOCE0 is enabled
and the “DISI” instruction is executed.
5. Wake up and enters into Interrupt vector (Address 0x00C) if the ADIE bit of the
IOCE0 is enabled and the “ENI” instruction is executed.
6. Enters into an Interrupt vector (Address 0x00C) if the ADIE bit of the IOCE0 is
enabled and the “ENI” instruction is executed.
The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the
conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise,
the AD conversion will be shut off, no matter what the status of the ADPD bit is.
6.7.6 Programming Process/Considerations
6.7.6.1
Programming Process
Follow these steps to obtain data from the ADC:
1. Write to the eight bits (ADE7: ADE0) on the R8 (AISR) register to define the
characteristics of R5 (digital I/O, analog channels, or voltage reference pin)
2. Write to the R9/ADCON register to configure the AD module:
a) Select the ADC input channel (ADIS2 : ADIS0)
b) Define the AD conversion clock rate (CKR1 : CKR0)
c) Select the VREFS input source of the ADC
d) Set the ADPD bit to 1 to begin sampling
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(This specification is subject to change without prior notice)
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EM78P301N
8-Bit Microcontroller with OTP ROM
3. Set the ADWE bit, if the wake-up function is employed
4. Set the ADIE bit, if the interrupt function is employed
5. Write “ENI” instruction, if the interrupt function is employed
6. Set the ADRUN bit to 1
7. Write “SLEP” instruction or Polling.
8. Wait for wake-up or for the ADRUN bit to be cleared to “0” , interrupt flag (ADIF) is
set to “1”, or ADC interrupt occurs.
9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the
ADC input channel changes at this time, the ADDATA, ADDATA1H, and
ADDATA1L values can be cleared to ‘0’.
10. Clear the interrupt flag bit (ADIF).
11. For next conversion, go to Step 1 or Step 2 as required. At least two Tct is required
before the next acquisition starts.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on the I/O
pins during AD conversion.
6.7.6.2
Sample Demo Programs
R_0 == 0
PSW == 3
PORT5 == 5
PORT6 == 6
RE== 0XE
; Indirect addressing register
; Status register
; Interrupt status register
B. Define a Control Register
IOC50 == 0X5
IOC60 == 0X6
IOCE0== 0XE
C_INT== 0XF
;
;
;
;
Control Register of Port 5
Control Register of Port 6
Interrupt Mask Register 2
Interrupt Mask Register
C. ADC Control Register
ADDATA == 0xB
ADDATA1H == 0xC
ADDATA1L == 0xD
AISR == 0x08
ADCON == 0x9
56
;
;
;
;
;
;
The contents are the results of ADC[11:4]
The contents are the results of ADC[11:8]
The contents are the results of ADC[7:0]
ADC input select register
7
6
5
4
3
2
1
0
VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
D. Define Bits in ADCON
ADRUN == 0x4
ADPD == 0x3
; ADC is executed as the bit is set
; Power Mode of ADC
E. Program Starts
ORG 0
JMP INITIAL
; Initial address
ORG 0x0C
; Interrupt vector
JMP CLRRE
;
;(User program section)
;
CLRRE:
MOV A,RE
AND A, @0BXX0XXXXX ; To clear the ADIF bit, “X” by application
MOV RE,A
BS ADCON, ADRUN
; To start to execute the next AD conversion
; if necessary
RETI
INITIAL:
MOV A,@0B00000001
; To define P50 as an analog input
MOV AISR,A
MOV A,@0B00001000
; To select P50 as an analog input channel, and
; AD power on
MOV ADCON,A
; To define P50 as an input pin and set the
; clock rate at fosc/16
En_ADC:
MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others
; are dependent on applications
IOW PORT5
MOV A, @0BXXXX1XXX ;
;
MOV RE,A
MOV A, @0BXX1XXXXX ;
;
IOW IOCE0
ENI
;
BS ADCON, ADRUN
Enable the ADWE wake-up function of ADC, “X”
by application
Enable the ADIE interrupt function of ADC,
“X” by application
Enable the interrupt function
; Start to run the ADC
; If the interrupt function is employed, the following three lines
; may be ignored
;If Sleep:
SLEP
;
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(This specification is subject to change without prior notice)
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EM78P301N
8-Bit Microcontroller with OTP ROM
; (User program section)
;
or
;If Polling:
POLLING:
JBC ADCON, ADRUN
JMP POLLING
; To check the ADRUN bit continuously;
; ADRUN bit will be reset as the AD conversion
; is completed
;
; (User program section)
6.8 Dual Sets of PWM (Pulse Width Modulation)
6.8.1 Overview
In PWM mode, PWM1 and PWM2 pins produce 8/10-bit resolution PWM output (see.
the functional block diagram below). A PWM output consists of a time period and a
duty cycle, and it keeps the output high. The baud rate of PWM is the inverse of the
time period. Figure 6-13 PWM Output Timing depicts the relation between a time
period and a duty cycle.
DT1H
+
DT1L
Fosc
1:1
1:2
1:4
1:8
1:16
1:64
1:128
1:256
latch
DL2H + DL2L
PWM1IF
Duty Cycle
Match
Comparator
MUX
R Q
TMR1H + TMR1L
T1P2 T1P1 T1P0 T1EN
Data
Bus
T2P2 T2P1 T2P0 T2EN
S
reset
BANK1 R7[0]
Comparator
Period
Match
PRD1H
+
PRD1L
DT2H
+
DT2L
Data
Bus
DL2H + DL2L
latch
Comparator
PWM2IF
Duty Cycle
Match
PWM2
Fosc
1:1
1:2
1:4
1:8
1:16
1:64
1:128
1:256
PWM1
TMR2H + TMR2L
MUX
R Q
reset
Comparator
PRD1H
+
PRD1L
S
BANK1 R7 [1]
Period
Match
Figure 6-12 PWM System Block Diagram
58
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Period
PRD1H+PRD1L = TMR1H+TMR1L
Duty Cycle
DT1H+DT1L = TMR1H+TMR1L
Figure 6-13 PWM Output Timing
6.8.2 Increment Timer Counter (TMRX: TMR1 or TMR2)
TMRX are 8-bit clock counters with programmable prescalers. They are designed for the
PWM module as baud rate clock generators. If employed, they can be turned off for
power saving by setting the T1EN bit [Bank 1-R8] or T2EN bit [Bank 1-R8] to “0”.
TMR1 and TMR2 are internal designs and can be read only
6.8.3 PWM Time Period (TMRX: TMR1 or TMR2)
PWM Time Period (PRDX: PRD1 or PRD2). The PWM time period is defined by writing
to the PRDX register. When TMRX is equal to PRDX, the following events occur on the
next increment cycle:
1) TMR is cleared
2) The PWMX pin is set to “1”
3) The PWMX duty cycle is latched from DT1/DT2 to DL1/DL2
NOTE
The PWM output will not be set, if the duty cycle is “0”.
4) The PWMXIF pin is set to “1”
The following formula describes how to calculate the PWM time period:
1
Period PRDX 1
TMRX prescale value
FOSC
Example:
PRDX=49; Fosc=4 MHz; TMRX (0, 0, 0) = 1:1,
then
1
Period 49 1
1 12.5 µS
4M
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
59
EM78P301N
8-Bit Microcontroller with OTP ROM
6.8.4 PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2)
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX
to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared.
DTX can be loaded anytime. However, it cannot be latched into DLX until the current
value of DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
1
TMRX prescale value
Duty Cycle DTX
F
OSC
Example:
DTX=10; Fosc=4 MHz; TMRX (0, 0, 0) = 1:1,
then
1
Duty Cycle 10
1 2.5
4M
µS
6.8.5 PWM Programming Process/Steps
1. Load PRDX with the PWM time period.
2. Load DTX with the PWM Duty Cycle.
3. Enable the interrupt function by writing to the IOCF0, if required.
4. Set PWMX pin to be output by writing a desired value to Bank 1-R7.
5. Load a desired value to Bank 1-R7 or Bank 1-R8 with TMRX prescaler value and
enable both PWMx and TMRX.
6.9 Timer/Counter
6.9.1 Overview
Timer 1 (TMR1) and Timer 2 (TMR2) (TMRX) are 8-bit clock counters with
programmable prescalers. They are designed for the PWM module as baud rate clock
generators. TMRX can be read only. The Timer 1 and Timer 2 will stop running when
sleep mode occurs with AD conversion not running. However, if AD conversion is
running when sleep mode occurs, Timer 1 and Timer 2 will keep on running.
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Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.9.2 Functional Description
Fosc
1:1
1:2
1:4
1:8
1:16
1:64
1:128
1:256
To TMR1IF(PWM1IF)
MUX
reset
TMR1
Period
Match
Comparator
T1P2 T1P1 T1P0 T1EN
PRD1
Data Bus
Data Bus
PRD2
T2P2 T2P1 T2P0 T2EN
Comparator
TMR2
Fosc 1:1
1:2
1:4
1:8
1:16
1:64
1:128
1:256
Period
Match
reset
MUX
To TMR2IF(PWM2IF)
Figure 6-14 Timer Block Diagram
Where:
Fosc: Input clock
Prescaler (T1P2, T1P1 and T1P0 / T2P2, T2P1 and T2P0): The Options 1:1, 1:2, 1:4,
1:8, 1:16, 1:64, 1:128, and 1:256 are defined by TMRX. These are cleared when any
type of reset occurs.
TMR1 and TMR2: Timer X register. TMRX is increased until it matches with PRDX,
and then is reset to “0” (default value).
PRDX (PRD1, PRD2): PWM time period register
Comparator X (Comparator 1 and Comparator 2): Reset TMRX while a match
occurs. The TMRXIF (PWMXIF) flag is set at the same time.
6.9.3 Programming the Related Registers
When defining TMRX, refer to the operation of its related registers as shown in the
following table. It must be noted that the PWMX bits must be disabled if their related
TMRXs are utilized. That is, Bit 7 ~ Bit 3 of the PWMCON register must be set to “0”.
Related Control Registers of TMR1 and TMR2
Addr.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x07
PWMCON/R7
”0”
“0”
“0”
“0”
“0”
0x08
TMRCON/R8
T2EN T1EN T2P2 T2P1 T2P0
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
Bit 2
Bit 1
Bit 0
PWMCAS PWM2E PWM1E
T1P2
T1P1
T1P0
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EM78P301N
8-Bit Microcontroller with OTP ROM
6.9.4 Timer Programming Process/Steps
1. Load PRDX with the Timer duration
2. Enable interrupt function by writing IOCF0, if required
3. Load a desired value for the TMRX prescaler, enable TMRX and disable PWM
6.9.5 PWM Cascade Mode
The PWM Cascade Mode merges two 8/10-bit PWM function to one 16/20-bit. In this
Mode, the necessary parameters are redefined as shown on the table below:
Parameter
16/20-bit PWM
DT (Duty)
PRD(Period)
TMR (Timer)
MSB(19/15~10/8)
DT2H+DT2L
PRD2H+PRD2L
TMR2H+TMR2L
LSB (9/7~0)
DT1H+DT1L
PRD1H+PRD1L
TMR1H+TMR2H
The prescaler of this 16/20-bit PWM uses the prescaler of the TMR1, the MSB of TMR
is counted when LSB carry and the PWM1IF bit/PWM1 Pin are redefined as the
PWMIF bit/PWM pin for this one.
latch
DL
Fosc
To PWMIF
(PWM1IF)
DT
1:1
1:2
1:4
1:8
1:16
1:64
1:128
1:256
MUX
16/20-bit Comparator
Duty Cycle
Match
R
PWM
(PWM1)
Q
TMR
reset
S
BANK 1 R7 [2]
16/20-bit Comparator
T1P2 T1P1 T1P0 T1EN
Period
Match
PRD
Data Bus
Data Bus
Figure 6-14 Functional Block Diagram of 16/20-bit PWM (merged from two 8/10 bits)
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Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.11 Oscillator
6.11.1 Oscillator Modes
The EM78P301N can be operated in six different oscillator modes, such as Crystal
Oscillator Mode (XT), High Crystal Oscillator Mode 1 (HXT1), High Crystal Oscillator
Mode 2 (HXT2), Low Crystal Oscillator Mode 1 (LXT1), Low Crystal Oscillator Mode 2
(LXT2), External RC Oscillator Mode (ERC), and RC Oscillator Mode with Internal RC
Oscillator Mode (IRC). User can select one of the six modes by programming the
OSC3, OSC2, OCS1, and OSC0 in the Code Option register.
The Oscillator modes defined by OSC3, OSC2, OCS1, and OSC0 are described below.
Oscillator Modes
OSC2
OSC1
OSC0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
1
1
ERC (External RC oscillator mode);
P55/ERCin acts as ERCin
P70/RCOUT acts as P70
1
ERC (External RC oscillator mode);
P55/ERCin acts as ERCin
P70/RCOUT acts as RCOUT
2
IRC (Internal RC oscillator mode);
P55/ERCin acts as P55
P70/RCOUT acts as P70
(Default)
2
IRC (Internal RC oscillator mode);
P55/ERCin acts as P55
P70//RCOUT acts as RCOUT
3
LXT1 (Frequency range of XT, mode is 100kHz ~ 1 MHz)
3
HXT1 (Frequency range of XT mode is 12 MHz ~ 16 MHz)
3
LXT2 (Frequency range of XT mode is 32.768kHz)
3
HXT2 (Frequency range of XT mode is 6 MHz ~ 12 MHz)
3
XT (Frequency range of XT mode is 1 MHz ~ 6 MHz)
1
2
3
In ERC mode, ERCin is used as oscillator pin. RCOUT/P70 is defined by Code Option Word 1
Bit 4 ~ Bit 1.
In IRC mode, P55 is normal I/O pin. RCOUT/P70 is defined by Code Option Word 1 Bit 4~Bit 1.
In LXT1, LXT2, HXT1, HXT2 and XT modes; OSCI and OSCO are used as oscillator pins.
These pins cannot and should not be defined as normal I/O pins.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
63
EM78P301N
8-Bit Microcontroller with OTP ROM
The maximum operating frequency limit of the crystal/resonator at different VDD are as
follows:
Conditions
Two clocks
VDD
Max. Freq. (MHz)
2.1V
4
3.0V
8
4.5V
16
6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P301N can be driven by an external clock signal through the OSCI pin as
illustrated below.
OSCI
OSCO
Figure 6-17 External Clock Input Circuit
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure 6-18 below depicts such a circuit.
The same applies to the HXT1 mode, HTX2 mode, LXT1 mode, LXT2 and XT mode.
C1
OSCI
Crystal
OSCO
RS
C2
Figure 6-18 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each
resonator has its own attribute, user should refer to the resonator specifications for the
appropriate values of C1 and C2. RS, a serial resistor, maybe required for AT strip cut
crystal or low frequency mode. Figure 6-21 is a PCB layout suggestion. When the
system works in Crystal mode (16 MHz), a 10 K is connected between OSCI
and OSCO.
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Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type
Frequency Mode
Frequency
LXT1
(100 K ~ 1 MHz)
Ceramic Resonators
XT
(1 M ~ 6 MHz)
LXT2 (32.768kHz)
LXT1
(100 K ~ 1 MHz)
Crystal Oscillator
XT
(1~6 MHz)
HXT2
(6~12 MHz)
HXT1
(12~20 MHz)
C1 (pF)
C2 (pF)
100kHz
200kHz
60 pF
60 pF
60 pF
60 pF
455kHz
1 MHz
40 pF
30 pF
40 pF
30 pF
1.0 MHz
2.0 MHz
30 pF
30 pF
30 pF
30 pF
4.0 MHz
20 pF
20 pF
32.768kHz
40 pF
40 pF
100kHz
200kHz
60 pF
60 pF
60 pF
60 pF
455kHz
1 MHz
40 pF
30 pF
40 pF
30 pF
1.0 MHz
2.0 MHz
30 pF
30 pF
30 pF
30 pF
4.0 MHz
6.0 MHz
20 pF
30 pF
20 pF
30 pF
6.0 MHz
8.0 MHz
30 pF
20 pF
30 pF
20 pF
12.0 MHz
12.0 MHz
30 pF
30 pF
30 pF
30 pF
16.0 MHz
20 pF
20 pF
Circuit diagrams for Serial and Parallel Modes Crystal/Resonator:
330
330
C
OSCI
7404
7404
7404
Crystal
Figure 6-19 Serial Mode Crystal/Resonator Circuit Diagram
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
65
EM78P301N
8-Bit Microcontroller with OTP ROM
7404
4.7K
10K
Vdd
OSCI
10K
7404
Crystal
C1
10K
C2
Figure 6-20 Parallel Mode Crystal/Resonator Circuit Diagram
Figure 6-21 Parallel Mode Crystal/Resonator Circuit Diagram
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Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.11.3 External RC Oscillator Mode
For some applications that do not
require precise timing calculation, the
RC oscillator (Figure 6-22) could offer
an effective cost savings.
Nevertheless, it should be noted that
the frequency of the RC oscillator is
influenced by the supply voltage, the
values of the resistor (Rext), the
capacitor (Cext), and even by the
operation temperature. Moreover, the
frequency also changes slightly from
one chip to another due to the
manufacturing process variation.
Vcc
Rext
ERCin
Cext
Figure 6-22 External RC Oscillator Mode
Circuit
In order to maintain a stable system frequency, the values of the Cext should be not
lesser than 20 pF, and the value of Rext should not be greater than 1 M. If the
frequency cannot be kept within this range, the frequency can be affected easily by
noise, humidity, and leakage.
The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 K, the oscillator will become
unstable because the NMOS cannot correctly discharge the capacitance current.
Based on the above reasons, it must be kept in mind that all the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the PCB layout have certain effects on the system frequency.
The RC Oscillator frequencies:
Cext
20 pF
100 pF
300 pF
Rext
Average Fosc 5V, 25C
Average Fosc 3V, 25C
3.3k
2.064 MHz
1.901 MHz
5.1k
1.403 MHz
1.316 MHz
10k
750.0kHz
719.0kHz
100k
81.45kHz
81.33kHz
3.3k
647.0kHz
615.0kHz
5.1k
430.8kHz
414.3kHz
10k
225.8kHz
219.8kHz
100k
23.88kHz
23.96kHz
3.3k
256.6kHz
245.3kHz
5.1k
169.5kHz
163.0kHz
10k
88.53kHz
86.14kHz
100k
9.283kHz
9.255kHz
1
Note: : Measured based on DIP packages.
2
: The values are for design reference only.
3
: The frequency drift is 30%
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
67
EM78P301N
8-Bit Microcontroller with OTP ROM
6.11.4 Internal RC Oscillator Mode
The EM78P301N offers a versatile internal RC mode with default frequency value of
4 MHz. Internal RC oscillator mode has other frequencies (16 MHz, 1 MHz, and
8 MHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below
describes the EM78P301N internal RC drift with voltage, temperature, and process
variations.
Internal RC Drift Rate (Ta=25°C, VDD=5V, VSS=0V)
Drift Rate
Internal
RC
Frequency
Temperature
(-40°C ~+85°C)
4 MHz
±2%
16 MHz
±2%
8 MHz
±2%
1 MHz
±2%
Voltage
(2.1V~5.5V)
Process
Total
±2%
±5%
±2%
±5%
±2%
±5%
±2%
±5%
±1%
*(2.1~5.5V)
±1%
*(4.5~5.5V)
±1%
*(3.0~5.5V)
±1%
*(2.1~5.5V)
* Operating voltage range
Note: Theoretical values are for reference only. Actual values may vary depending on the actual
process.
6.12 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply
stabilizes in steady state. The EM78P301N POR voltage range is 1.8V ~ 1.9V. Under
customer application, when power is switched OFF, Vdd must drop below 1.8V and
remains at OFF state for 10s before power can be switched ON again. Subsequently,
the EM78P301N will reset and work normally. The extra external reset circuit will work
well if Vdd rises fast enough (50ms or less). However, under critical applications, extra
devices are still required to assist in solving power-on problems.
6.12.1 Programmable WDT Time-out Period
5
The Option word (WDTPS) is used to define the WDT time-out period (18ms or
6
4.5ms ). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic
resonators, the lower the operation frequency is, the longer is the required set-up time.
68
5
VDD=5V, WDT time-out period = 16.5ms ± 30% at 25°C.
VDD=3V, WDT time-out period = 18ms ± 30% at 25°C.
6
VDD=5V, WDT time-out period = 4.2ms ± 30% at 25°C.
VDD=3V, WDT time-out period = 4.5ms ± 30% at 25°C.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.12.2 External Power-on Reset Circuit
The circuits shown in the
VDD
following figure implement
an external RC to produce a
/RESET
R
D
reset pulse. The pulse
width (time constant) should
Rin
be kept long enough to
C
allow the Vdd to reach the
minimum operating voltage.
This circuit is used when the
Figure 6-23 External Power-on Reset Circuit
power supply has a slow
power rise time.
Because the current leakage from the /RESET pin is about 5 A, it is recommended
that R should not be greater than 40KΩ. This way, the voltage at Pin /RESET is held
below 0.2V. The diode (D) functions as a short circuit at power-down. The “C”
capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high
current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
6.12.3 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but residual voltage
remains. The residual voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Figure 6-24 and Figure 6-25 show how to
create a protection circuit against residual voltage.
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Figure 6-24 Residual Voltage Protection Circuit 1
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
69
EM78P301N
8-Bit Microcontroller with OTP ROM
VDD
VDD
R1
Q1
/RESET
R2
R3
Figure 6-25 Residual Voltage Protection Circuit 2
6.13 Code Option
EM78P301N has three Code Option Words and one Customer ID word that are not part
of the normal program memory.
Word 0
Word 1
Word 2
Word 3
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit12 ~ Bit 0
Bit12 ~ Bit 0
6.13.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12
Bit 11
Bit 10
Mne
P70_HD
PWMS
WK_CLK
monic
/HS
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
CLKS
LVR1
LVR0 RESETEN ENWDT NRHL
1
8-bit Disable 8 clock
High
High
High
Disable Disable 32/fc
0
10-bit Enable 32 clock
Low
Low
Low
Enable
Enable
8/fc
Bit 3
Bit 2 ~ 0
NRE
Protect
Enable Disable
Disable Enable
Bit 12 (PWMS): PWM Bit Select.
0: 10-bit PWM function
1: 8-bit PWM function (Default)
Bit 11 (P70_HD/HS):
0: Enable
1: Disable (default)
Bit 10 (WK_CLK): Selecting 8 or 32 clocks wake up from sleep and idle mode (only
IRC mode)
0: IRC stable time + 32 clocks
1: IRC stable time + 8 clocks (default)
70
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 9 (CLKS): Instruction period option bit
0: Two oscillator periods
1: Four oscillator periods (default)
Bits 8 ~ 7 (LVR1 ~ LVR0): Low Voltage Reset Enable bits
LVR1, LVR0
VDD Reset Level
11
VDD Release Level
NA (Power-on Reset) (Default)
10
2.7V
2.9V
01
3.5V
3.7V
00
4.0V
4.2V
Bit 6 (RESETEN): RESET/P71 Pin Select Bit
0: P71 set to /RESET pin
1: P71 is general purpose input pin or open-drain for output Port
(default)
Bit 5 (ENWDT): Watchdog timer enable bit
0: Enable
1: Disable (default)
Bit 4 (NRHL): Noise rejection high/low pulses define bit. The INT pin is falling or rising
edge trigger.
0: Pulses equal to 8/fc is regarded as signal
1: Pulses equal to 32/fc is regarded as signal (default)
NOTE
The noise rejection function is turned off in the LXT2 and sleep mode.
Bit 3 (NRE): Noise Rejection Enable
0: Disable noise rejection
1: Enable noise rejection (default), but in Low Crystal oscillator (LXT)
mode, the noise rejection circuit is always disabled.
Bits 2 ~ 0 (Protect): Protect Bit
Protect Bits
Protect
0
Enable
1
Disable (default)
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
71
EM78P301N
8-Bit Microcontroller with OTP ROM
6.13.2 Code Option Register (Word 1)
Word 1
Bit
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCM1 RCM0 OSC3 OSC2 OSC1 OSC0
Bit 0
Mnemonic
C5
C4
C3
C2
C1
C0
RCOUT
1
High
High
High
High
High
High
High
High
High
High
High
High System_clk
0
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Open_
drain
Bits 12 ~ 7 (C5 ~ C0): Calibrator of internal RC mode C5~C0 must be set to “1” only
(auto-calibration).
Bit 6 ~ 5 (RCM1 ~ RCM0): RC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
1
1
4 (Default)
1
0
16
0
1
8
0
0
1
Bits 4 ~ 1 (OSC3 ~ OSC0): Oscillator Modes Selection bits
Oscillator Modes
OSC3 OSC2
OSC1 OSC0
1
ERC (External RC oscillator mode);
P55/ERCin acts as ERCin
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
1
P70/RCOUT acts as P70
1
ERC (External RC oscillator mode);
P55/ERCin acts as ERCin
P70/RCOUT acts as RCOUT
2
IRC (Internal RC oscillator mode);
P55/ERCin acts as P55
P70/RCOUT acts as P70 (default)
2
IRC (Internal RC oscillator mode);
P55/ERCin acts as P55
P70/RCOUT acts as RCOUT
3
LXT1 (Frequency range of XT, mode is 100kHz ~ 1 MHz)
3
HXT1 (Frequency range of XT mode is 12 MHz ~ 16 MHz)
3
LXT2 (Frequency range of XT mode is 32.768kHz)
3
HXT2 (Frequency range of XT mode is 6MHz ~ 12 MHz)
3
XT (Frequency range of XT mode is 1 MHz ~ 6 MHz)
1
In ERC mode, ERCin is used as oscillator pin. RCOUT/P70 is defined by code option Word 1
Bit 4 ~ Bit 1.
2
In IRC mode, P55 is normal I/O pin. RCOUT/P70 is defined by Code Option Word 1 Bit 4~Bit 1.
3
72
In LXT1, LXT2, HXT1, HXT2 and XT modes; OSCI and OSCO are used as oscillator pins.
These pins cannot and should not be defined as normal I/O pins.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Bit 0 (RCOUT): Instruction clock output enable bit in IRC or ERC mode.
0: RCOUT pin output instruction clock with open drain.
1: RCOUT pin output instruction clock (default)
6.13.3 Customer ID Register (Word 2)
Word 2
Bit
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
–
–
–
SFS
–
–
–
HLP
–
WDTPS
–
–
–
1
–
–
–
16kHz
–
–
–
High
–
18ms
–
–
–
0
–
–
–
128kHz
–
–
–
Low
–
4.5ms
–
–
–
Bit 12: Not used (reserved). This bit is set to “1” all the time.
Bit 11: Not used, (reserved). This bit is set to “0” all the time.
Bit 10: Not used, (reserved). This bit is set to “1” all the time.
Bit 9 (SFS): Sub-oscillator select for GREEN mode and TCC, PWM1, PWM2 clock
source (Non-include WDT time-out and free run setup-up time)
0: 128kHz
1: 16kHz (default)
Bit 8: Not used, (reserved). This bit is set to “0” all the time.
Bit 7: Not used (reserved). This bit is set to “1” all the time.
Bit 6: Not used (reserved). This bit is set to “1” all the time.
Bit 5 (HLP): Power consumption selection
0: Low power consumption mode, applies to operating frequency at
400kHz or below 400kHz
1: High power consumption mode, applies to operating frequency above
400kHz (default)
(User selects LXT1 or LXT2 in crystal mode, HLP function automatically selects
low)
Bit 4: Not used, (reserved). This bit is set to “1” all the time.
Bit 3 (WDTPS): WDT Time-out Period
WDTPS
Watchdog Timer*
1
18 ms (Default)
0
4.5 ms
*Theoretical values, for reference only.
Bits 2 ~ 0: Not used, (reserved). This bit is set to “1” all the time.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
73
EM78P301N
8-Bit Microcontroller with OTP ROM
6.13.4 Customer ID Register (Word 3)
Word 3
Bit
Bit 12 Bit 11 Bit 10
Mnem
ID12
onic
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID13
ID2
ID1
ID0
1
High
High
High
High
High
High
High
High
High
High
High
High
High
0
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Bits 12 ~ 0: Customer’s ID code
6.14 Low Voltage Detector/Low Voltage Reset
The Low Voltage Reset (LVR) and the Low Voltage Detector (LVD) are designed for
unstable power situation, such as external power noise interference or in EMS test
condition.
When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level
(VRESET) and remains at 10s, a system reset will occur and the system will remain in
reset status. The system will remain at reset status until Vdd voltage rises above Vdd
release level. Refer to Figure 6-26 LVD/LVR Waveform.
If Vdd drops below the low voltage detector level, /LVD (Bit 7 of RE) is cleared to “0’ to
show a low voltage signal when LVD is enabled. This signal can be used for low
voltage detection.
6.14.1 Low Voltage Reset
LVR property is set at Bits 8 and 7 of Code Option Word 0. Detailed operation mode is
as follows:
Word 0
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2~Bit 0
PWMS
P70_H
WK_CLK CLKS
D/HS
LVR1
LVR0 RESETEN ENWDT NRHL
NRE
Protect
Bits 8~7 (LVR1 ~ LVR0): Low Voltage Reset Enable bits.
LVR1, LVR0
VDD Reset Level
11
74
VDD Release Level
NA (Power-on Reset)
10
2.7V
2.9V
01
3.5V
3.7V
00
4.0V
4.2V
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.14.2 Low Voltage Detector
LVD property is set and Register detailed operation mode is as follows:
6.14.2.1 Bank 1 RE (LVD Interrupt and Wake-up Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
LVDEN
LVD1
LVD0
-
-
-
EXWE
NOTE
■ Bank 1 RE< 6 > register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the Bank 1 RE
< 7 > to "1."
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Figure 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (LVDIE): Low voltage Detector interrupt enable bit.
0: Disable Low voltage Detector interrupt
1: Enable Low voltage Detector interrupt
When the detected low level voltage state is used to enter an interrupt
vector or enter next instruction, the LVDIE bit must be set to “Enable“.
Bit 6 (LVDEN): Low Voltage Detector Enable bit
0: Disable Low voltage detector
1: Enable Low voltage detector
Bits 5 ~ 4 (LVD1 ~ LVD0): Low Voltage Detector level bits.
LVDEN
LVD1, LVD0
1
11
1
1
1
0
LVD voltage Interrupt Level
/LVD
Vdd ≤ 2.2V
0
Vdd > 2.2V
1
Vdd ≤ 3.3V
0
Vdd > 3.3V
1
Vdd ≤ 4.0V
0
Vdd > 4.0V
1
Vdd ≤ 4.5V
0
Vdd > 4.5V
1
NA
0
10
01
00
××
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
75
EM78P301N
8-Bit Microcontroller with OTP ROM
6.14.2.2 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
ADWE
ICWE
LVDWE
NOTE
■ Bank 0 RE < 6, 5, 4 > can be cleared by instruction but cannot be set.
■ Bank 1 RE and IOCE0 is the interrupt mask register.
■ Reading Bank 0 RE will result to "logic AND" of Bank 1 RE and IOCE0.
Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin
voltage is lower than LVD voltage interrupt level (selected by LVD1 and
LVD0), this bit will be cleared.
0: Low voltage is detected.
1: Low voltage is not detected or LVD function is disabled.
Bit 6 (LVDIF): Low Voltage Detector Interrupt flag
LVDIF is reset to “0” by software or hardware.
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit.
0: Disable Low Voltage Detect wake-up.
1: Enable Low Voltage Detect wake-up.
When the Low Voltage Detect is used to enter an interrupt vector or to
wake up the IC from Sleep/Idle with Low Voltage Detect running, the
LVDWE bit must be set to “Enable“.
76
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
6.14.3 Programming Process
Follow these steps to obtain data from the LVD:
1. Write to the two bits (LVD1: LVD0) on the LVDCR register to define the LVD level.
2. Set the LVDWE bit, if the wake-up function is employed.
3. Set the LVDIE bit, if the interrupt function is employed.
4. Write “ENI” instruction, if the interrupt function is employed.
5. Set LVDEN bit to 1
6. Write “SLEP” instruction or Polling /LVD bit.
7. Clear the low voltage detector interrupt flag bit (LVDIF) when Low Voltage Detector
interrupt occurred.
The LVD module uses the internal circuit. When LVDEN (Bit 6 of Bank 1-RE) is set to
“1”, the LVD module is enabled.
When LVDWE (Bit 0 of RE) is set to “1”, the LVD module will continue to operate during
sleep/idle mode. If Vdd drops slowly and crosses the detect point (VLVD), the LVDIF
(Bit 6 of RE) will be set to “1”, the /LVD (Bit 7 of RE) will be cleared to “0”, and the
system will wake up from Sleep/Idle mode. When a system reset occurs, the LVDIF will
be cleared.
When Vdd remains above VLVD, LVDIF is kept at “0” and /LVD is kept at “1”. When
Vdd drops below VLVD, LVDIF is set to “1” and /LVD is kept at “0”. If the ENI instruction
is executed, LVDIF will be set to “1”, and the next instruction will branch to interrupt
Vector 021H. The LVDIF is cleared to “0” by software. Refer to Figure 6-26 below.
LVDIF is cleared by
software
Vdd
VLVD
VRESET
LVDIF
Internal
Reset
18ms
LVR Voltage drop
Vdd < Vreset not longer than 10us, the system still keeps on operating
System occur reset
Figure 6-26 LVD/LVR Waveform
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
77
EM78P301N
8-Bit Microcontroller with OTP ROM
6.15 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator time periods), unless the program
counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of
arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.).
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same instruction
can operate on I/O registers.
The following symbols are used in the Instruction Set table:
Convention:
R = Register designator that specifies which one of the registers (including operation and general
purpose registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects
the operation.
k = 8 or 10-bit constant or literal value
Mnemonic
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
78
Operation
Status Affected
No Operation
Decimal Adjust A
A CONT
0 WDT, Stop oscillator
0 WDT
A IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC,
Enable Interrupt
CONT A
IOCR A
AR
0A
0R
R-A A
R-A R
R-1 A
R-1 R
A VR A
A VR R
None
C
None
T, P
T, P
1
None
None
None
None
None
None
1
None
None
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
Mnemonic
Operation
A&RA
A&RR
ARA
ARR
A+RA
A+RR
RA
RR
/R A
/R R
R+1 A
R+1 R
R-1 A, skip if zero
R-1 R, skip if zero
R(n) A(n-1), R(0) C, C A(7)
R(n) R(n-1), R(0) C,
RRC R
C R(7)
R(n) A(n+1), R(7) C,
RLCA R
C A(0)
R(n) R(n+1), R(7) C,
RLC R
C R(0)
R(0-3) A(4-7),
SWAPA R
R(4-7) A(0-3)
SWAP R R(0-3) R(4-7)
JZA R
R+1 A, skip if zero
JZ R
R+1 R, skip if zero
BC R,b
0 R(b)
BS R,b
1 R(b)
JBC R,b
if R(b)=0, skip
JBS R,b
if R(b)=1, skip
CALL k
PC+1 [SP], (Page, k) PC
JMP k
(Page, k) PC
MOV A,k k A
OR A,k
AkA
AND A,k A & k A
XOR A,k A k A
RETL k
k A, [Top of Stack] PC
SUB A,k
k-A A
BANK k
k R4(6)
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
RRCA R
Status Affected
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
None
None
None
2
None
3
None
None
None
None
None
None
Z
Z
Z
None
Z, C, DC
None
LCALL k
PC+1[SP], kPC
None
LJMP k
kPC
None
If Bank1 R5.7=0, machine code(7~0) R
TBRD R
Else Bank1 R5.7=1, machine code(12~8)
None
R(4~0), R(7~5)=(0,0,0)
Note: 1 This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only.
2
3
This instruction is not recommended for RF operation.
This instruction cannot operate under RF.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
79
EM78P301N
8-Bit Microcontroller with OTP ROM
7
Absolute Maximum Ratings
Items
8
Rating
Temperature under bias
-40C
to
85C
Storage temperature
-65C
to
150C
Input voltage
Vss-0.3V
to
Vdd+0.5V
Output voltage
Vss-0.3V
to
Vdd+0.5V
Working Voltage
2.1V
to
5.5V
Working Frequency
DC
to
16 MHz
DC Electrical Characteristics
Ta= 25C, VDD= 5.0V, VSS= 0V
Symbol
80
Parameter
Condition
Min.
Typ.
Max.
Unit
32.768k
4
16
MHz
760
950
1140
kHz
FXT
Crystal: VDD to 5V
Two cycles with two clocks
ERC
ERC: VDD to 5V
R: 5.1K, C: 100 pF
VIH1
Input High Voltage
(Schmitt Trigger)
Ports 5, 6, 7
0.7VDD
VDD+0.3
V
VIL1
Input Low Voltage
(Schmitt Trigger)
Ports 5, 6, 7
-0.3V
0.3VDD
V
VIHT1
Input High Threshold
Voltage (Schmitt Trigger)
/RESET
1.8
V
VILT1
Input Low Threshold
Voltage (Schmitt Trigger)
/RESET
1.1
V
VIHT2
Input High Threshold
Voltage (Schmitt Trigger)
TCC,INT
0.7VDD
VDD+0.3
V
VILT2
Input Low Threshold
Voltage (Schmitt Trigger)
TCC,INT
-0.3V
0.3VDD
V
IOH1
Output High Voltage
(Ports 5, 6, 7)
-6
IOH2
Output High Voltage
(Ports 51~54, 56~57,
60, 67)
IOL1
Output Low Voltage
(Ports 5, 6, 7)
IOL2
Output Low Voltage
(Ports 51~54, 56~57,
60, 67)
VOH = 0.9VDD
mA
-18
12
25
VOL = 0.1VDD
mA
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
(Continuation)
Symbol
Parameter
Condition
LVR1
Low voltage reset level
LVR2
Low voltage reset level
Min.
Typ.
Max.
Unit
Ta= 25C
2.41
2.7
2.99
V
Ta= -40~85C
2.14
2.7
3.25
V
Ta= 25C
3.1
3.5
3.92
V
Ta= -40~85C
2.73
3.5
4.25
V
Ta= 25C
3.56
4.0
4.43
V
Ta= -40~85C
3.16
4.0
4.81
V
LVR3
Low voltage reset level
IPH
Pull-high current
Pull-high active, input pin at VSS
70
A
IPL
Pull-low current
Pull-low active, input pin at Vdd
40
A
ISB1
Power down current
All input and I/O pins at VDD,
output pin floating, WDT disabled
1.0
2.0
A
ISB2
Power down current
All input and I/O pins at VDD,
output pin floating, WDT enabled
10
A
ICC1
Operating supply current
at two clocks (VDD = 3V)
/RESET= 'High', Fosc=32.768kHz
(Crystal type, CLKS="0"),
Output pin floating, WDT disabled
15
20
A
ICC2
Operating supply current
at two clocks (VDD = 3V)
/RESET= 'High', Fosc=32.768kHz
(Crystal type,CLKS="0"), output
pin floating, WDT enabled
15
25
A
ICC3
Operating supply current
at two clocks
/RESET= 'High', Fosc=4 MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
1.5
1.7
mA
ICC4
Operating supply current
at two clocks
/RESET= 'High', Fosc=10 MHz
(Crystal type, CLKS="0"),
Output pin floating, WDT enabled
2.8
3.0
mA
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.
2. Data under Minimum, Typical, and Maximum (Min., Typ., and Max.) columns are based on
hypothetical results at 25C. These data are for design reference only.
Internal RC Electrical Characteristics (Ta=25C, VDD=5V, VSS=0V)
Internal RC
Drift Rate
Temperature
Voltage
Min.
Typ.
Max.
4 MHz
25C
5V
3.92 MHz
4 MHz
4.08 MHz
16 MHz
25C
5V
15.68 MHz
16 MHz
16.32 MHz
1 MHz
25C
5V
0.98 MHz
1 MHz
1.02 MHz
8 MHz
25C
5V
7.84 MHz
8 MHz
8.16 MHz
Internal RC Electrical Characteristics (Ta=-40 ~ 85C, VDD=2.1~5.5V, VSS=0V)
Internal RC
Drift Rate
Temperature
Voltage
Min.
Typ.
Max.
4 MHz
-40C ~85C
2.1V~5.5V
3.80 MHz
4 MHz
4.20 MHz
16 MHz
-40C ~85C
2.1V~5.5V
15.2 MHz
16 MHz
16.8 MHz
1 MHz
-40C ~85C
2.1V~5.5V
0.95 MHz
1 MHz
1.05 MHz
8 MHz
-40C ~85C
2.1V~5.5V
7.60 MHz
8 MHz
8.40 MHz
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
81
EM78P301N
8-Bit Microcontroller with OTP ROM
8.1 AD Converter Characteristics
Vdd=5V, Vss=0V, Ta= 25°C
Symbol
VAREF
Parameter
VASS
Analog reference
voltage
VAI
Analog input voltage
Ivdd
IAI1
Analog supply current
Ivref
Ivdd
IAI2
Analog supply current
IVref
Min. Typ. Max. Unit
2.5
Vdd
V
Vss
Vss
V
VASS
VAREF
V
VAREF=VDD=5.0V,
*1
VASS=0.0V, FS =100kHz,
*1
FIN =1kHz
(VREF is internal VDD)
1400
µA
10
µA
VAREF=VDD=5.0V,
*1
VASS=0.0V, FS =100kHz,
*1
FIN =1kHz
(VREF is external VREF pin)
900
µA
500
µA
12
Bits
VAREF - VASS 2.5V
RN
Resolution
INL
Integral Nonlinearity
VAREF=VDD=5.0V
*1
VASS=0.0V, FS =100kHz,
*1
FIN =1kHz
±4
LSB
DNL
Differential nonlinear
error
VAREF=VDD=5.0V
*1
VASS=0.0V, FS =100kHz,
*1
FIN =1kHz
±1
LSB
FSE
Full scale error
VAREF=VDD=5.0V
*1
VASS=0.0V, FS =100kHz
±8
LSB
OE
Offset error
VAREF= Vdd=5.0V
*1
VASS=0.0V, FS =100kHz
±4
LSB
ZAI
External impedance of
ADC input channel.
10
KΩ
VDD=3~5.5V, VASS = 0.0V,
*1
FIN =1kHz
0.5
µs
VDD=2.5~3V, VASS = 0.0V,
*1
FIN =1kHz
2
µs
VDD=3~5.5V,
VASS = 0.0V, Ta=25°C
4
µs
VDD=2.5~3V,
VASS = 0.0V, Ta=25°C
16
µs
TAD
Tsh
82
Condition
Period of ADC clock
Sample and Hold Time
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
(Continuation)
Symbol
TCN
Parameter
AD conversion time
(Include S/H Time)
Condition
VDD=2.5~5.5V,
VASS = 0.0V
TADD1
AD delay time between
setting “ADRUN” and
starting 1st TAD
PSRR
VAREF= 2.5V,
Power Supply Rejection
VAREF=2.5V, VASS=0V,
Ratio
*1
*1
VIN =0V~2.5V, FS =25kHz
V1/4VDD
Accuracy for 1/4 VDD
VDD=2.5~5.5V, VASS=0.0V
Min. Typ. Max. Unit
14
24
TAD
0.5
TAD
2
LSB
±3
%
Note:
* FS is Sample Rate or conversion rate. FIN is frequency of input test sine wave
1. The parameters are theoretical values and have not been tested. Such parameters are
for design reference only.
2. There is no current consumption when ADC is off other than minor leakage current.
3. AD conversion result will not decrease when an increase of input voltage and no
missing code.
4. These parameters are subject to change without further notice.
8.2 VREF 2V/3V/4V Characteristics
Vdd = 5.0V, Vss=0V, Ta= -40 to 85°C
Symbol
Parameter
Condition
Min. Typ. Max. Unit
VDD
Power Supply
–
2.1
5.5
V
IVDD
DC Supply Current
No load
250
µA
Vref
Accuracy for Vref
2V, 3V, 4V
±1
1.75
%
Warn up
Time ready for voltage
time
reference
30
50
µs
V
VDD=VDDmin - 5.5V,
Cload = 19.2pf
Rload=15.36K
VDDmin
Minimum
Power Supply
Vref
+
0.2*
*VDDmin : can work at (Vref+0.1V), but will have a poor PSRR.
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
83
EM78P301N
8-Bit Microcontroller with OTP ROM
9
AC Electrical Characteristics
Ta=25C, VDD=5V 5%, VSS=0V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Dclk
Input CLK duty cycle
–
45
50
55
%
Tins
Instruction cycle time
(CLKS="0")
Crystal type
125
–
DC
ns
Tpor
Delay Time after
Power-On-Reset release
FSS0=1
(16kHz)
–
16 30%
–
ms
–
WSTO +
510/Fm
–
s
Delay time after
/Reset, WDT, and LVR
release
Crystal type
–
WSTO + 8/Fs
–
s
–
WSTO + 8/Fm
–
s
–
WSTO + 8/Fs
–
s
Trstrl
IRC type
Trsth1
Hold Time after /RESET
pin reset
–
–
1 s
–
–
Trsth2
Hold Time after LVR
pin reset
–
–
1 s
–
–
Twdt
Watchdog timer time-out
FSS0=1 (16kHz)
–
16 30%
–
ms
Tset
Input pin setup time
–
–
0
–
ns
Thold
Input pin hold time
–
15
20
25
ns
Tdelay
Output pin delay time
Cload=20 pF
Rload=1M
–
20
–
ns
Note: 1. WSTO: The waiting time of Start-to-Oscillation
2. These parameters are hypothetical (not tested) and are provided for design reference
only.
3. Data under minimum, typical, and maximum (Min., Typ. and Max.) columns are based
on hypothetical results at 25C. These data are for design reference use only.
*. Tpor and Twdt are 16+/- 30% ms at FSS0=1(16kHz), Ta=-40~85C, and
VDD=2.1~5.5V
84
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V
0.75 VDD
0.75 VDD
TEST POINTS
0.25VDD
0.25VDD
GND+0.5V
Note: AC Testing: Input is driven at VDD-0.5V for logic “1”, and GND+0.5V for Logic “0”
Timing measurements are made at 0.75V for logic “1”, and 0.25VDD for Logic “0”
Figure 10-1a AC Test Input/Output Waveform Timing Diagram
Reset Timing (CLK = "0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
Figure 10-1b Reset Timing Diagram
TCC Input Timing (CLKS = "0")
ins
CLK
TCC
tcc
Figure 10-1c TCC Input Timing Diagram
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
85
EM78P301N
8-Bit Microcontroller with OTP ROM
APPENDIX
A
Package Type
OTP MCU
Package Type
Pin Count
Package Size
MSOP
10
118 mil
EM78P301ND14
DIP
14
300 mil
EM78P301NSO14
SOP
14
150 mil
EM78P301NMS10
These are Green products and comply with RoHS specifications.
Part No.
Electroplate type
Pure Tin
Ingredient (%)
Sn: 100%
Melting point (°C)
86
EM78P301NxJ
232°C
Electrical resistivity (µ-cm)
11.4
Hardness (hv)
8~10
Elongation (%)
>50%
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
B
Ordering and Manufacturing Information
EM78P301NSO14J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
D: DIP
SO: SOP
MS: MSOP
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P301ND14J
is EM78P301N with OTP program memory product,
in 14-pin DIP 300mil package with RoHS complied
IC Mark
‧‧‧‧‧‧‧
EM78Paaaa
1041 bbbbbb
‧‧‧‧‧‧‧
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
Elan Product Number
Batch Number
Manufacture Date
“YYWW”
YY is year and WW is week
87
EM78P301N
8-Bit Microcontroller with OTP ROM
Ordering Code
EM78P301NS14J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Elan IC Product Number
88
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
C
Packaging Configuration
C.1
EM78P301ND14
Min.
Symbol
D
14
E1
8
C
E
eB
1
A
7
θ
Normal
Max.
4.318
A
A1
A2
c
D
E
E1
eB
B
B1
L
e
θ
0.381
3.175
0.203
18.796
6.174
7.366
8.409
0.356
1.143
3.048
0
3.302
3.429
0.254 0.356
19.050 19.304
6.401
6.628
7.696
8.025
9.017
9.625
0.457 0.559
1.524 1.778
3.302 3.556
2.540 (TYP)
15
A1
A2
L
B
e
B1
TITLE:
PDIP-14 L 300 MIL PACKAGE OUTLINE
DIMENSION
File:
D14
Edtion : A
Unit : mm
Scale: Free
Material:
Sheet: 1 of 1
Figure C-1 EM78P301N 14-pin PDIP Package Type
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
89
EM78P301N
8-Bit Microcontroller with OTP ROM
C.2
EM78P301NSO14
E
Symbol
A
A1
b
c
E
H
D
L
e
θ
H
Min
1.350
0.100
0.330
0.190
3.800
5.800
8.550
0.600
Normal
Max
1.750
0.250
0.510
0.250
4.000
6.200
8.750
1.270
1.27(TYP)
0
8
e
b
c
D
A2
A
TITLE:
SOP-14L(150MIL) PACKAGE OUTLINE
DIMENSION
File :
NSO14
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-2 EM78P301N 14-pin SOP Package Type
90
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
EM78P301N
8-Bit Microcontroller with OTP ROM
C.3
EM78P301NMS10
Figure B-9 EM78P301N 10-pin MSOP Package Type
Figure C-9 EM78P301N 10-pin MSOP Package Type
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
91
EM78P301N
8-Bit Microcontroller with OTP ROM
D
Quality Assurance and Reliability
Test Category
Solderability
Test Conditions
Remarks
Solder temperature=245 5C, for 5 seconds up to the
stopper using a rosin-type flux
Step 1: TCT, 65C (15 min.)~150C (15 min.), 10 cycles
Step 2: Bake at 125C, TD (durance) = 24 hrs
Step 3: Soak at 30C /60% , TD (durance) = 192 hrs
For SMD IC (such as
SOP, QFP, SOJ, etc)
Step 4: IR flow 3 cycles
Pre-condition
(Pkg thickness 2. 5 mm or
3
Pkg volume 350 mm 225 5C)
(Pkg thickness 2.5 mm or
3
Pkg volume 350 mm 240 5C )
Temperature cycle test
-65 (15 min.)~150C (15 min.), 200 cycles
Pressure cooker test
TA = 121C, RH = 100%, pressure = 2 atm,
TD (durance) = 96 hrs
High temperature /
High humidity test
TA=85C , RH = 85% , TD (durance) = 168 , 500 hrs
High-temperature
storage life
TA=150C, TD (durance) = 500, 1000 hrs
High-temperature
operating life
TA=125C, VCC = Max. operating voltage,
TD (durance) = 168, 500, 1000 hrs
Latch-up
TA=25C, VCC = Max. operating voltage, 800mA/40V
ESD (HBM)
TA=25°C, ≥ | ± 4KV |
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (MM)
TA=25°C, ≥ | ± 400V |
VDD-VSS(+),VDD_VSS
(-) mode
D.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise-caused address error is detected, the MCU will repeat execution of the
program until the noise is eliminated. The MCU will then continue to execute the next
program.
92
Product Specification (V1.2) 03.10.2016
(This specification is subject to change without prior notice)
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