ES8156

ES8156 High Performance Stereo Audio DAC FEATURES • • • • • • • • • • • • • High performance and low power multibit delta-sigma audio DAC 110 dB signal to noise ratio, -80 dB THD+N 24-bit, 8 to 96 kHz sampling frequency Integrated headphone driver with capless option Differential output for higher SNR and CMRR I2S/PCM master or slave serial data port 256/384Fs, USB 12/24 MHz and other non standard audio system clocks I2C interface 7-band fully adjustable EQ Dynamic range compression Playback signal feedback Pop and click noise suppression 1.8V to 3.3V operation APPLICATIONS • • • • Headphone Speaker TV Portable audio devices ORDERING INFORMATION ES8156 -40°C ~ +85°C QFN-20 1 Everest Semiconductor Confidential ES8156 1. BLOCK DIAGRAM CDATA CCLK CE IC Audio Data 2 EQ DRC Stereo DAC HP Driver LOUTP/LOUTN ROUTP/ROUTN Analog Reference Power Supply VRP VMID HPCOM DVDD PVDD DGND AVDD AGND Revision 3.0 MCLK SCLK LRCK SDIN SDOUT Clock Mgr 2 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Everest Semiconductor Confidential ES8156 2. PIN OUT AND DESCRIPTION AVDD VRP VMID CE SDOUT 16 17 18 19 20 CDATA CCLK MCLK DVDD PVDD 1 2 3 4 5 15 14 13 12 11 ES8156 LOUTP LOUTN AGND ROUTN ROUTP 10 9 8 7 6 HPCOM LRCK SDIN SCLK DGND Pin Name Pin number 1, 2, 19 3 7 8 9 20 15, 14 11, 12 I/O, I, I I I/O I I/O O O O HPCOM 10 Analog PVDD DVDD, DGND AVDD, AGND VMID VRP 5 4, 6 16, 13 18 17 Analog Analog Analog Analog Analog CDATA, CCLK, CE MCLK SCLK SDIN LRCK SDOUT LOUTP, LOUTN ROUTP, ROUTN Revision 3.0 Input or Output Pin Description I2C clock, data, address Master clock Serial data bit clock/DMIC bit clock DAC serial data input Serial data left and right channel frame clock Playback signal feedback Left channel differential analog output Right channel differential analog output Virtual ground for capless headphone (Only available in software mode) Power supply for the digital input and output Digital power supply Analog power supply Filtering capacitor connection Filtering capacitor connection 3 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Everest Semiconductor Confidential ES8156 3. TYPICAL APPLICATION CIRCUIT 0R GND(SYS) AGND In the layout, chip is treated as a analog device AGND VA * 1uF AGND AGND AGND3 7 9 20 8 MCU/DSP 2 1 19 16 AGND PGND 6 DVDD PVDD VMID 1uF 4 5 VRP 0.1uF * * VD VP AGND AVDD 17 18 ** 13 21 1uF 1uF DGND LOUTP MCLK SCLK LRCK SDOUT SDIN LOUTN ES8156 ROUTN ROUTP CCLK CDATA CE 15 1uF 14 1uF 12 1uF 11 1uF LOUTP LOUTN ROUTN ROUTP 10 HPCOM For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible Additional paralle capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help * 0R GND(SYS) AGND In the layout, chip is treated as a analog device AGND VA * 1uF AGND AGND DGND AGND3 7 9 20 8 MCLK SCLK LRCK SDOUT SDIN MCU/DSP 2 1 19 CCLK CDATA CE ES8156 16 AVDD 6 AGND PGND DVDD PVDD * * VMID VD VP 1uF 4 5 VRP 17 18 ** 0.1uF 13 21 1uF 1uF AGND LOUTN ROUTN 14 12 LOUTP 15 ROUTP HPCOM 11 10 4 3 5 2 1 Capless headphone For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible Additional paralle capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help * Revision 3.0 4 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Everest Semiconductor Confidential ES8156 0R GND(SYS) AGND In the layout, chip is treated as a analog device AGND VA * 1uF AGND AGND DGND AGND3 7 9 20 8 MCLK SCLK LRCK SDOUT SDIN MCU/DSP 2 1 19 CCLK CDATA CE ES8156 16 AVDD 6 AGND PGND DVDD PVDD * * VMID VD VP 1uF 4 5 VRP 17 18 ** 0.1uF 13 21 1uF 1uF AGND LOUTN HPCOM ROUTN 14 10 12 LOUTP 15 ROUTP 11 4 22uF 33R 3 5 22uF 33R 2 AGND 1 headphone with DC blocking cap For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible Additional paralle capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help * Revision 3.0 5 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Everest Semiconductor Confidential ES8156 4. HARDWARE MODE The device works either in hardware mode (HW mode) or software mode (I2C mode). The default is hardware mode. Software mode is enabled by setting bit 2 of configuration register 0x02. In HW mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously derived from the system clock with some specific rates. The device can auto detect MCLK/LRCK ratio according to Table 1. The device only supports the MCLK/LRCK ratios listed in Table 1. The SCLK/LRCK ratio is normally 64. Table 1 Slave Mode Sampling Frequencies and MCLK/LRCK Ratio Speed Mode Single Speed Sampling Frequency 8kHz – 50kHz MCLK/LRCK Ratio 32, 64, 96, 128, 192, 256, 384, 512, 640, 768, 1024, 1152, 1280, 1536 5. CLOCK MODES AND SAMPLING FREQUENCIES In software mode, the device supports standard audio clocks (32Fs, 64F, 128Fs, 256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (16 MHz, 25 MHz, 26 MHz, etc). According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 6. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the CDATA low. The transfer rate of this interface can be up to 400 kbps. Revision 3.0 6 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Everest Semiconductor Confidential ES8156 A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 0001 00x, where x equals CE. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 2 and Table 3. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 2 Write Data to Register in I2C Interface Mode start Chip Address 0001 00 CE R/W 0 ACK Chip Addr CDATA Register Address RAM Write ACK bit 1 to 7 Reg Addr ACK ACK bit 1 to 8 Data to be written DATA Write Data ACK ACK bit 1 to 8 CCLK START STOP Figure 1a I2C Write Timing Table 3 Read Data from Register in I2C Interface Mode Start Start Chip Address 0001 00 CE Chip Address 0001 00 CE R/W 0 R/W 1 Chip Addr Reg Addr CDATA bit 1 to 7 Write ACK ACK ACK ACK bit 1 to 8 Register Address RAM Data to be read Data Chip Addr bit 1 to 7 Read ACK ACK NACK Stop Read Data NO ACK bit 1 to 8 CCLK START START STOP Figure 1b I2C Read Timing Revision 3.0 7 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Stop Everest Semiconductor Confidential ES8156 7. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the input or output through LRCK, SCLK and SDIN or SDOUT pins. These formats are I2S, left justified, right justified and DSP/PCM. SDIN is sampled by the device on the rising edge of SCLK. SDOUT is out on the falling edge of SCLK. The relationship of SDATA (SDIN or SDOUT), SCLK and LRCK with these formats are shown through Figure 2a to Figure 2d. 1 SCLK 1 SCLK L Channel LRCK R Channel SCLK SDATA MSB LSB LSB MSB Figure 2a I2S Serial Audio Data Format LRCK L Channel R Channel SCLK SDATA LSB MSB MSB LSB Figure 2b Left Justified Serial Audio Data Format 1 SCLK LRCK R Channel L Channel SCLK SDATA MSB LSB MSB LSB Figure 2c DSP/PCM Mode A Serial Audio Data Format LRCK R Channel L Channel SCLK SDATA MSB LSB MSB LSB Figure 2d DSP/PCM Mode B Serial Audio Data Format Revision 3.0 8 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Everest Semiconductor Confidential ES8156 8. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Analog Input Voltage Range Digital Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V AGND-0.3V DGND-0.3V -40°C -65°C MAX +3.6V +3.6V AVDD+0.3V PVDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER DVDD PVDD AVDD MIN 1.6 1.6 1.7 TYP 3.3 3.3 3.3 MAX 3.6 3.6 3.6 UNIT V V V DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, MCLK/LRCK=256. PARAMETER DAC Performance Signal to Noise ratio (A-weigh) THD+N Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Output Full Scale Output Level MIN TYP MAX UNIT 100 -85 110 -80 115 -78 ±5 dB dB % 0.4535 Fs Fs dB dB 0 0.5465 ±0.05 53 0 0.5833 0.4167 ±0.005 56 AVDD/3.3 Fs Fs dB dB Vrms DC CHARACTERISTICS PARAMETER Normal Operation Mode DVDD=1.8V, PVDD=1.8V, AVDD=3.3V Revision 3.0 MIN TYP MAX 19 9 Latest datasheet: www.everest-semi.com or info@everest-semi.com UNIT mW July 2019 Everest Semiconductor Confidential Power Down Mode DVDD=1.8V, PVDD=1.8V, AVDD=3.3V Digital Voltage Level Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage ES8156 0 0.7*PVDD PVDD 0 uA V V V V 0.5 I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE) PARAMETER CCLK Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition CDATA Hold Time from CCLK Falling CDATA Setup time to CCLK Rising Rise Time of CCLK Fall Time CCLK Symbol FCCLK TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN 4.7/1.3 4.0/0.6 4.7/1.3 4.0/0.6 4.7/0.6 0.25/0.1 MAX 100/400 3.45/0.9 1.0/0.3 1.0/0.3 UNIT KHz us us us us us us us us us Figure 3 I2C Timing Revision 3.0 10 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Everest Semiconductor Confidential ES8156 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER Symbol MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle (Note 2) SCLK frequency SCLK pulse width low TSLKL SCLK Pulse width high TSCLKH SCLK falling to LRCK edge (master mode only) TSLR LRCK edge to SCLK rising (slave mode only) TLSR SCLK falling to SDOUT valid VDDD=3.3V T VDDD=1.8V SDO LRCK edge to SDOUT valid (Note 3) VDDD=3.3V T VDDD=1.8V LDO SDIN valid to SCLK rising setup time TSDIS SCLK rising to SDIN hold time TSDIH Note 2: one SCLK period of high time in DSP/PCM modes. MIN 40 40 16 16 10 10 10 MAX 49.2 60 200 60 26 10 16 39 11 25 UNIT MHz % KHz % MHz ns ns ns ns ns ns ns ns Note 3: only apply to MSB of Left Justified or DSP/PCM mode B. LRCK TSLR TSCLKH TLSR TSCLKL SCLK TSDO TLDO SDOUT TSDIS TSDIH SDIN Figure 4 Serial Audio Port Timing Revision 3.0 11 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2019 Revision 3.0 Confidential 12 Latest datasheet: www.everest-semi.com or info@everest-semi.com 9. PACKAGE Everest Semiconductor July 2019 ES8156