ES8311

ES8311 FEATURES Low Power Mono Audio CODEC DAC • • System • • • • High performance and low power multibit delta-sigma audio ADC and DAC I2S/PCM master or slave serial data port 256/384Fs, USB 12/24 MHz and other non standard audio system clocks I2C interface • • • 24-bit, 8 to 96 kHz sampling frequency 110 dB signal to noise ratio, -80 dB THD+N One pair of analog output with headphone driver and differential output option Dynamic range compression Pop and click noise suppression ADC Low Power • • • • • • • • • • 24-bit, 8 to 96 kHz sampling frequency 100 dB signal to noise ratio, -93 dB THD+N One pair of analog input with differential input option Low noise pre-amplifier Noise reduction filters Auto level control (ALC) and noise gate Support analog and digital microphone 1.8V to 3.3V operation 14 mW playback and record Low standby current APPLICATIONS • • • • • • • • Automotive Phone Toy 2-way radio Dash cam IP Camera DVR, NVR Surveillance ORDERING INFORMATION ES8311 -40°C ~ +105°C QFN-20 1 Everest Semiconductor Confidential ES8311 1. BLOCK DIAGRAM PGA DSDIN ASDOUT SCLK LRCK IC 2 Mono ADC ADC ALC DAC DRC Noise Filter 2 I S/PCM Mono DAC Analog Reference Power Supply ADCVREF DACVREF VMID DVDD PVDD DGND AVDD AGND Revision 5.0 CDATA CCLK CE MIC1N MCLK MIC1P Clock Mgr HP Driver OUTP OUTN 2 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 2. PIN OUT AND DESCRIPTION VMID MIC1N MIC1P/DMIC_SDA CDATA CE 16 17 18 19 20 CCLK MCLK PVDD DVDD DGND 1 2 3 4 5 15 14 13 12 11 ES8311 ADCVREF DACVREF OUTN OUTP AVDD 10 9 8 7 6 AGND DSDIN LRCK ASDOUT SCLK/DMIC_SCL Pin Name Pin number Input or Output CCLK, CDATA, CE MCLK SCLK/DMIC_SCL LRCK ASDOUT DSDIN MIC1P/DMIC_SDA MIC1N OUTP, OUTN PVDD DVDD, DGND AVDD, AGND VMID ADCVREF, DACVREF 1, 19, 20 2 6 8 7 9 18 17 12, 13 3 4, 5 11, 10 16 15, 14 I, I/O, I I I/O I/O O I I2C clock, data, address Master clock Serial data bit clock/DMIC bit clock Serial data left and right channel frame clock ADC serial data output DAC serial data input I Mic input O Analog Analog Analog Analog Analog Differential analog output Power supply for the digital input and output Digital power supply Analog power supply Filtering capacitor connection Filtering capacitor connection Revision 5.0 Pin Description 3 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 3. TYPICAL APPLICATION CIRCUIT 0R GND(SYS) AGND In the layout, chip is treated as a analog device AGND VA * 1uF AGND AGND MCU/DSP AGND2 6 8 7 9 1 19 20 DGND 11 AVDD MIC1P/DMIC_SDA MCLK SCLK/DMIC_SCL LRCK ES8311 ASDOUT DSDIN CCLK CDATA CE AGND PGND 15 16 VMID 5 DVDD PVDD ADCVREF * * VD VP 0.1uF 4 3 DACVREF 14 *** 0.1uF 10 21 1uF 1uF 1uF MIC1N OUTN OUTP AGND 18 1uF 17 1uF 13 1uF 12 1uF MIC1P MIC1N OUTN OUTP For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible Additional paralle capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help * Revision 5.0 4 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 4. CLOCK MODES AND SAMPLING FREQUENCIES The device supports standard audio clocks (64F, 128Fs, 256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (16 MHz, 25 MHz, 26 MHz, etc). According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 5. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the CDATA low. The transfer rate of this interface can be up to 400 kbps. A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 0011 00x, where x equals CE. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode start Chip Address 0011 00 CE Revision 5.0 R/W 0 ACK Register Address RAM ACK Data to be written DATA ACK 5 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Stop Everest Semiconductor Confidential Chip Addr CDATA Write ACK bit 1 to 7 Reg Addr ES8311 ACK bit 1 to 8 Write Data ACK bit 1 to 8 CCLK START STOP Figure 1a I2C Write Timing Table 2 Read Data from Register in I2C Interface Mode Start Start Chip Address 0011 00 CE Chip Address 0011 00 CE R/W 0 R/W 1 Chip Addr Reg Addr CDATA bit 1 to 7 Write ACK ACK ACK ACK bit 1 to 8 Register Address RAM Data to be read Data Chip Addr bit 1 to 7 Read ACK ACK NACK Stop Read Data NO ACK bit 1 to 8 CCLK START START STOP Figure 1b I2C Read Timing Revision 5.0 6 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 6. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the input of the DAC or output from the ADC through LRCK, SCLK and DSDIN or ASDOUT pins. These formats are I2S, left justified, right justified and DSP/PCM. DAC input DSDIN is sampled by the device on the rising edge of SCLK. ADC data is out at ASDOUT on the falling edge of SCLK. The relationship of SDATA (DSIN/ASDOUT), SCLK and LRCK with these formats are shown through Figure 2a to Figure 2d. 1 SCLK 1 SCLK L Channel LRCK R Channel SCLK SDATA MSB LSB LSB MSB Figure 2a I2S Serial Audio Data Format LRCK L Channel R Channel SCLK SDATA LSB MSB MSB LSB Figure 2b Left Justified Serial Audio Data Format 1 SCLK LRCK R Channel L Channel SCLK SDATA MSB LSB MSB LSB Figure 2c DSP/PCM Mode A Serial Audio Data Format LRCK R Channel L Channel SCLK SDATA MSB LSB MSB LSB Figure 2d DSP/PCM Mode B Serial Audio Data Format Revision 5.0 7 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 7. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Analog Input Voltage Range Digital Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V AGND-0.3V DGND-0.3V -40°C -65°C MAX +3.6V +3.6V AVDD+0.3V PVDD+0.3V +105°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER DVDD PVDD AVDD MIN 1.6 1.6 1.7 TYP 3.3 3.3 3.3 MAX 3.6 3.6 3.6 UNIT V V V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) THD+N Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance MIN TYP MAX UNIT 95 -95 100 -93 102 -85 ±5 dB dB % 0.4535 Fs Fs dB dB 0 0.5465 ±0.05 70 0 0.5833 0.4167 ±0.005 70 AVDD/3.3 6 Fs Fs dB dB Vrms KΩ DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, MCLK/LRCK=256. Revision 5.0 8 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential PARAMETER DAC Performance Signal to Noise ratio (A-weigh) THD+N Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Output Full Scale Output Level ES8311 MIN TYP MAX UNIT 100 -85 110 -80 115 -75 ±5 dB dB % 0.4535 Fs Fs dB dB 0 0.5465 ±0.05 53 0 0.5833 0.4167 Fs Fs dB dB ±0.005 56 AVDD/3.3 Vrms DC CHARACTERISTICS PARAMETER Normal Operation Mode DVDD=1.8V, PVDD=1.8V, AVDD=3.3V Power Down Mode DVDD=1.8V, PVDD=1.8V, AVDD=3.3V Digital Voltage Level Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage MIN TYP MAX UNIT 8 mA 0 uA 0.7*PVDD V V V V 0.5 PVDD 0 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid Revision 5.0 Symbol MIN 40 40 TSCLKL TSCLKH TSLR TSDO 15 15 –10 11 MAX 51.2 60 200 60 26 10 UNIT MHz % KHz % MHz ns ns ns ns 9 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 Figure 3 Serial Audio Port Timing I2C SWITCHING SPECIFICATIONS PARAMETER CCLK Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition CDATA Hold Time from CCLK Falling CDATA Setup time to CCLK Rising Rise Time of CCLK Fall Time CCLK Symbol FCCLK TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN 1.3 0.6 1.3 0.4 0.6 100 MAX 400 900 300 300 UNIT KHz us us us us us ns ns ns ns Figure 4 I2C Timing Revision 5.0 10 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 8. PACKAGE Revision 5.0 11 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8311 9. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Revision 5.0 12 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com