HYM1381

HYM1380/1381 Serial Real Time Clock/Calendar Features ■ Provides year, month, day, weekday, hours, minutes and seconds based on 32.768 kHz ■ Single–byte or multiple–byte (burst mode) data transfer for read or write of clock ■ 8–pin DIP for HYM1380, 8–pin SOP package for quartz crystal ■ Serial I/O transmission: Simple 3–wire interface ■ Clock registers store BCD format ■ 2.0–5.5 volt full operation HYM1381 ■ Maximum input serial clock: 500kHz at VCC =2V， 2MHz at VCC =5V ■ Uses less than 400nA at 2.0 volts ■ TTL–compatible (VDD = 5V) Applications ■ Cash Register ■ Mobile Telephones ■ Security Access Controller, Door Controller ■ Public Phone Bill Meter, Smart Card Payphone ■ Time Recorder ■ IC Water-Flow Meter, IC Gas Meter General Description The HYM1380/HYM1381 is a serial timekeeper IC which provides seconds, minutes, hours, day, date, month, and year information. It communicates with a microprocessor via a simple serial interface. The end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. The clock operates in either the 24–hour or 12–hour format with an AM/PM indicator. Interfacing the HYM1380/HYM1381 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK (Serial clock). Data can be transferred to and from the clock 1 byte at a time or in a burst mode. The HYM1380/HYM1381 is designed to operate on very low power. Ordering Information Part Temp Range Pin-Package HYM1380 0°C to +70°C 8 DIP HYM1381 0°C to +70°C 8 SOP Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com - 1 - 1380/1381 Block Diagram and Pin Description Block Diagram Vcc X2 X1 + 5V Divider Da ta b us Minute Hour Day Week Month Year ROM command Ad d re ss b u s decoder Shift Register I/O SCLK RST GND Pin Assignment HYM1380 —8DIP, HYM1381 —8SOP Pin Description Pin No. Symbol Description 1 NC No Connection 2 X1 Connections for a standard 32.768kHz quartz crystal 3 X2 Connections for a standard 32.768kHz quartz crystal 4 GND Ground 5 RST The reset signal must be asserted high during a read or a write, 6 I/O The I/O pin is the bi-directional data pin for the 3-wire interface 7 SCLK 8 VCC The SCLK pin is used to synchronize data movement on the serial interface Power Supply Pin Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com -2- 1380/1381 Absolute Maximum Rating Parameter Symbol Value Unit VCC －0.3～5.5 V Operating Temperature TA 0～70 ℃ Storage Temperature TS -50～+125 ℃ Soldering Temperature TH 260（10 Sec） ℃ Supply Voltage Note: These stress ratings only. Stress exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification. not implied and prolonged to extreme conditions may affect device reliability. Electrical Characteristics DC Electrical Characteristics (TA=25℃, VCC = 2.0 to 5.5V, Unless otherwise noted.) Test Condition Parameter Symbol Min Typical Max Unit Supply Voltage Vcc 2 － 5.5 V Standby Current ISTB － － 100 nA － － 100 nA Operating Current Icc 0.7 1.0 μA 0.7 1.2 μA Logic 1 Intput VIH 5V － 2 － － V Logic 0 Intput VIL 5V － － － 0.8 V System Frequency fosc 5V 32.768KHz － 32.768 － KHz CLK Frequency fSCLK － － 0.5 MHz － － 2 MHz VDD Condition － － 2V － 5V 2V 5V 2V 5V No Load － AC Electrical Characteristics (TA=25℃, VCC = 2.0 to 5.5V, Unless otherwise noted.) Parameter Symbol CLK to RST Hold tcch RST Inactive Time tcwh RST to I/O High Z tcdz SCLK to I/O High Z tccz Data to CLK Setup tdc CLK to Data Hold tcdh CLK to Data Delay tcdd Test Condition Min VCC=2.0V 240 VCC=5V 60 VCC=2.0V 4 VCC=5V 1 Max ns ns VCC=2.0V 280 VCC=5V 70 VCC=2.0V 280 VCC=5V 70 VCC=2.0V 200 VCC=5V 50 VCC=2.0V 280 VCC=5V 70 VCC=2.0V Unit ns ns ns ns 800 Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com ns -3- 1380/1381 VCC=5V CLK Low Time tcl CLK High Time tch CLK Frequency tclk CLK Rise and Fall tr，tf RST to CLK Setup tCC 200 VCC=2.0V 1000 VCC=5V 250 VCC=2.0V 1000 VCC=5V 250 VCC=2.0V VCC=5V ns ns 0.5 DC 2.0 VCC=2.0V 2000 VCC=5V 500 VCC=2.0V 4 VCC=5V 1 MHz ns µs Timing Diagram: Read Data Transfer Timing Diagram: Write Data Transfer Application Information Command Byte For each data transfer, a command byte is initiated to specify which register is accessed. This is to determine whether a read or write is operated and whether a single byte or burst mode transfer is to occur. The command byte is shown in Table 1. Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com -4- 1380/1381 Table 1 Address/ Command Byte 1 0 0 0 A2 A1 A0 R/W The MSB (Bit 7) must be logic 1. If it is 0, writes to the HYM1380/1381 will be disabled. A2-A0 (Bits 1 through 3) specify the designated registers to be input or output, and the R/W (bit 0) specifies a write operation if logic 0 or read operation if logic 1. The command byte is always input starting with the LSB (bit 0). Clock/Calendar The clock/calendar is contained in seven write/read registers. Data contained in the clock/ calendar registers is in binary coded decimal format (BCD). The registers and data format summary is shown in Table 2. Table 2 Registers Address/Definition Register Definition Register Range Name Data D7 Seconds 00-59 CH Minutes 00-59 0 10MIN Hours 01-12 12/ 0 AP HR 00-23 24 0 10 HR Date 01-31 0 0 Month 01-12 0 Day 01-07 0 Year 00-99 10 YEAR Control WP D6 D5 D4 D3 1 0 0 0 A2 A1 A0 R/W 1 0 0 0 0 0 0 1/0 MIN 1 0 0 0 0 0 1 1/0 HOUR 1 0 0 0 0 1 0 1/0 10DATE DATE 1 0 0 0 0 1 1 1/0 0 0 10M MONTH 1 0 0 0 1 0 0 1/0 0 0 0 DAY 1 0 0 0 1 0 1 1/0 YEAR 1 0 0 0 1 1 0 1/0 1 0 0 0 1 1 1 1/0 10SEC 0 0 D2 The command byte D1 D0 SEC 0 0 0 0 0 Data Transfer To initiate any transfer of data, RST is taken high and the command word is loaded into the shift register providing both address and command information. Data is serially input on the rising edge of the SCLK. The first 8 bits specify which of 8 bytes will be accessed, whether a read or write cycle will take place, and whether a byte or burst mode transfer is to occur. After the first eight clock cycles have loaded the command word into the shift register, additional clocks will output data for a read or input data for a write. All data is serially input on the rising edge of SCLK and outputs on the falling edge of SCLK. The data transfer summary is shown in Figure 1. Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com -5- 1380/1381 Figure 1 Data Transfer Summary In writing a data byte with HYM1380/1381, following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. In reading a data on the register of HYM1380/1381, following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as RST remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri–stated upon each rising edge of SCLK. Data is output starting with bit 0. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the I/O pin goes to a high impedance state. Data transfer is illustrated in Table 2. Burst Mode The command byte of burst mode is shown in Table 3. Table 3 The command byte of burst mode 1 0 1 1 1 1 1 R/W In the clock/calendar burst mode, the first eight clock/calendar registers can be consecutively read or written starting with bit 0 of address 0, and the R/W (bit 0) specifies a write operation if logic 0 or read operation if logic 1. Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com -6- 1380/1381 Clock Halt Flag and Write-Protect Bit Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock oscillator is stopped, when this bit is written to logic 0, the clock will start. The WP bit (bit 7) of the control register is the write-protect bit. Before any write operation to the clock, bit 7 must be 0. When bit7 is set to logic 0, the write protect bit prevents a write operation to any other register. The initial power on state is not defined. The first seven bits (bits 0 – 6) are forced to 0 and will always read a 0 when read. AM-PM/12-24 Mode Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10-hour bit (20 – 23 hours). Crystal Selection A 32.768 kHz crystal can be directly connected to the HYM1380/1381 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6pF. The selection of C1,C2 Part HYM1380/HYM1381 Crystal Error Vaule ± 10ppm 5pF 10~20ppm 8pF Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com -7- 1380/1381 Typical Applications Circuit Package Information Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com -8- 1380/1381 Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com -9-