CWR-500(Qfn)

CWR500® Datasheet Qi Compliant 5W Wireless Power Receiver IC General Description CWR500 can deliver up to 5W as a highly-integrated single-chip wireless medium power receiver IC. As wireless power transfer systems are getting more popular, they require more fast charging and high efficiency solution. The CWR500 wireless power receiver IC is compliant with WPC 1.2.4 standard and supports the 5W baseband power profile (BPP). The CWR500 power receiver integrates a synchronous rectifier, a low drop-out regulator, and communication controllers which use Amplitude Shift Keying (ASK). The chip also supports the Foreign Object Detection (FOD) extension in WPC 1.2.4. For achieving chip stability, protection tools are implemented, such as over-current-protection, over-voltage-protection, thermal shutdown, and under voltage lock-out (UVLO). Configurable analog blocks can be used independently and co-operated with the control and communication unit. Features Overview          Single-chip dual mode 5W receiver for WPC 1.2.4 compliance Support 5W baseline power profile (BPP) FOD extension supports Integrated Synchronous Rectifier Receiver. - Support Output Power up to 5W. - High Rectifier Efficiency up to 95%. - High System Efficiency up to 90%. Programmable Dynamic Rectifier Voltage Control. Integrated Programmable Linear Regulator. - Output voltage range of 4.5~5.5V with 0.5V control step. - Output current limit up to 1A. Bi-directional channel communication - ASK modulation for PRx to PTx 24-bit Power Calculation support Received Power Calculation for FOD function - 12-bit ADC for voltage/current measurement. - Adaptive Coil Power loss/offset compensation.         Programmable Temperature Control. Charger Complete and Enable control inputs End of Power Transfer (EPT) Packet management. Over Current Limit Over Voltage Protection Thermal Shutdown QFN 40-pin 6mm x 6mm, 0.5mm pitch 384-bit One-Time-Programmable Device Applications - WPC Compliant Receivers. Cell phones and smart phones. Digital Cameras. Power Banks. Wireless Power Embedded Batteries Bluetooth Headsets Portable Media Players Other Hand-held Device Datasheet (REV. 1.0) Information furnished by CELFRAS is believed to be accurate and reliable. However, no responsibility is assumed by CELFRAS for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of CELFRAS. World Wide Web Site: www.celfras.com Revised 2018-07-01 CWR500 Qi Compliant 5W Wireless Power Receiver IC 1. Description for Implementation Figure 1. CWR500 Block Diagram 1.1 Overview A wireless power charging system is composed of transmitter and receiver. In general, wireless power transmitter will transfer AC power using a power amplifier through a TX inductor coil. Then wireless power receiver will receive AC power through an RX inductor coil which is strongly coupled with the TX coil. In receiver part, rectifier will change the AC power to DC power and LDO will transfer the DC power to battery charger. Figure1 shows the block diagram of CWR500 wireless charging receiver IC. CWR500 receiver will support power transfer up to 5W and it is compliant with WPC 1.2.4 standard. It consists of rectifier, main LDO, internal LDOs, ADC, digital controller and etc. 1.2 Rectifier CWR500 employs a synchronous active rectifier in order to improve AC to DC power conversion efficiency. The rectifier power conversion efficiency is very important because it has a large influence on overall CELFRAS Semiconductor, Inc. -2- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC receiver efficiency. The rectifier in CWR500 will support full-wave, half-wave and passive mode according to the transferred power level. When the power transfer is started initially, the rectifier will operate in passive mode and supply the system power to overall received IC. 1.3 Main LDO Main LDO regulator will transfer DC power from rectifier output to battery charger. LDO in CWR500 is designed to transfer power up to 5W and its output voltage level can be changed by user. The LDO power transistor is designed to minimize its on-resistance because the LDO drop-out voltage is directly related to overall system efficiency. Especially, in case of large power transfer, the LDO drop-out voltage (VRECTVOUT) should be controlled as small as possible. 1.4 ASK Modulator CWR500 power receiver communicates with the power transmitter by ASK modulator. The ASK modulator make up the WPC standard 2kHz bi-phase signal by switching the capacitors between COMM1/2 and AC1/AC2. Switching the capacitance at AC1/AC2 nodes will change the impedance of transmitter coil. As a result, amplitude modulation is built up. 1.5 ADC CWR500 power receiver employs 12-bit SAR ADC because it has low power, small area characteristics and moderate speed performance. ADC monitors important internal voltages and currents and gives the system information to the digital controller. 1.6 Protection CWR500 power receiver employs various protection schemes in order to prevent system damage. When the VRECT voltage is too high, the OVP (Over Voltage Protection) function will turn on the clamp path or send the EPT (End Power Transfer) packet to the transmitter. When the main LDO current is too large, the OCL (Over Current Limit) function will limit the output current. When the temperature inside or outside the chip is too high, the OTP (Over Temperature Protection) function will send the EPT packet to transmitter or shutdown the receiver system. 1.7 Digital Controller Digital controller in CWR500 controls all the analog blocks and entire system to perform power transfer operation according to the wireless power transfer standard, that is, WPC 1.2.4. It also supports I2C interface to communicate with external host. CELFRAS Semiconductor, Inc. -3- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC 2. Pin-out and description CWR500 Figure 3. CWR500 Pin Configuration (QFN 40-pin 6mm x 6mm, 0.5mm pitch) 2.1 Pin Description (QFN 40-pin 6mm x 6mm, 0.5mm pitch) Pin Number Name Type 1 COMM1 O 28 COMM2 O 2 CHG_DONE I Active-high input from the external battery charger to terminate power transfer. 3 VDD_5V O Internal 5V LDO output pin for capacitor connection. 4 DIG_TEST O Digital test output pin. 5 ANA_TEST O Analog test output pin. CELFRAS Semiconductor, Inc. Description High voltage open drain output for ASK modulation. -4- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC 6,20,21,25 26,39 AVSS Analog ground pin. 7,8 VOUT O Main LDO output pin for delivering power to the battery charger. 9 BOOST1 O 24 BOOST2 O Bootstrap capacitor connection pin for driving the high-side FETs of synchronous rectifier. 10,11 AC1 I 22,23 AC2 I 12,13,18,19 PGND 14,15,16,17 VRECT O Internal synchronous rectifier output for capacitor connection. 27 CLAMP O High voltage open drain output for analog linear over-voltage protection. 29 EXT_TS I External temperature sensor input. Connect this pin to external NTC thermistor. If not used, connect this pin to VDD_DIG. 30 SDA I/O 31 DIG3 I 32 VDD_DIG I/O 33 SCL I I2C clock input for internal register access. 34 DIG2 I Scan enable for scan test mode. 35 VPP I 8V high voltage power for OTP programming. During the normal operation, connect this pin to VDD_DIG. 36 DIG1 I Enable scan test mode. 37 ENB I Active-low enable pin for the entire chip. 38 FOD I FOD offset setting pin. Connect a resistor between this pin and GND. 40 ILIM I Output current or over-current limit level programming pin. CELFRAS Semiconductor, Inc. AC power input of synchronous rectifier. Power ground for synchronous rectifier. I2C data input/output for internal register access. Scan clock for scan test mode. Internal 3V LDO output for digital block and etc. -5- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC 3. Application Guide Figure 4. CWR500 Typical Application Diagram 3.1 Receiver Coil and Resonant Capacitors The receiver coil design is related to the overall system application. The coil inductance, shape and material can be chosen according to your applications. The recommended receiver coil inductance for dual mode operation is between 5uH to 10uH. Series and parallel resonant capacitors CS and CP are set according to WPC specification. The capacitance of the resonant capacitors can be calculated by the following equations. CS = CP = 1 L′S ⅹ(2πfS )2 1 LS ⅹ(2πfD )2 − 1 CS In these equations, fS and fD are the dual resonant frequencies which cover the power transfer frequency range. For example, fS can be set to 100kHz and fD can be set to 1000kHz, respectively. L’S is coil self inductance when placed on the transmitter, and LS is the self inductance when placed away from the transmitter. CELFRAS Semiconductor, Inc. -6- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC 3.2 Boost and Communication Capacitors As shown in Figure 4, two external bootstrap capacitors CBOOST1 and CBOOST2 are needed to drive the highside FETs of synchronous rectifier. Bootstrap capacitors should have voltage rating of more than 25V and their recommended capacitances are 15nF. In order to communicate with transmitter, external capacitors should be connected between high voltage open drain output and AC1/AC2 input. CWR500 will be switching COMM1/COMM2 output in WPC mode. Typical recommended capacitance values are CCOMM1=CCOMM2=22nF. 3.3 Output Regulating Capacitors As shown in Figure 4, rectifier output VRECT and internal LDOs’ output VOUT, VDD_5V, VDD_DIG should be connected to external capacitor for voltage regulation. Typical recommended capacitance values are CVRECT=20uF, CVOUT=3.3uF, CVDD_5V=1uF, CVDD_DIG=1uF, respectively. 3.4 Clamp Resistor When the VRECT voltage is too high, the OVP (Over Voltage Protection) function will turn on the clamp path or send the EPT (End Power Transfer) packet to the transmitter. The clamp path uses high voltage open drain output for analog linear OVP. The recommended resistance value of RCLAMP is between 5Ω to 20Ω according to the transfer power level of application. 3.5 Current Limit and FOD Setting Resistors When the main LDO current is too large, the OCL (Over Current Limit) function will limit the output current. The current limit level can be adjusted by external resistors and it is calculated as follows, ILIM = 45000 45000 = R ILIM R IL1 + R IL2 In this equation, the RILIM is the total resistance from the ILIM pin to ground, that is, RIL1 + RIL2 as shown in Figure 4. It is recommended to use the resistors of good tolerance less than 1%, because the current estimation in wireless power receiver is very important. CWR500 adds an FOD offset proportional to output power level when it sends the received power packet to transmitter. The amount of the added FOD offset can be adjusted by the ratio of RIL1 to (RIL1 + RIL2). 3.6 External Temperature Sensor When the temperature inside or outside the chip is too high, the OTP (Over Temperature Protection) function will send the EPT packet to transmitter or shutdown the receiver system. In order to sense the temperature outside chip, connect EXT_TS pin to external NTC (Negative temperature Coefficient) thermistor as shown in Figure 4. The NTC thermistor should be placed close to the heat emission device. The EXT_TS voltage VEXT_TS can be calculated as follows, VEXT_TS (R NTC + R TS1 ) × R TS3 (R NTC + R TS1 ) + R TS3 = VDD_DIGⅹ (R NTC + R TS1 ) × R TS3 + R TS2 (R NTC + R TS1 ) + R TS3 In this equation, VDD_DIG is 3V from the internal LDO. CWR500 compares VEXT_TS with internal reference voltages VTS_HOT and VTS_COLD. If VEXT_TSVTS_COLD, it means external temperature is too low and CWR500 also sends the EPT packet to transmitter. Remind that VEXT_TS is negative slope curve vs temperature. The internal reference voltages VTS_HOT and VTS_COLD are fixed values as follows, Internal TS Reference Threshold Voltage [V] Hysteresis [mV] VTS_HOT 0.315 20 VTS_COLD 0.980 80 Recommended NTC resistance range is from hundreds of Ω to hundreds of kΩ vs temperature. After choosing the appropriate NTC thermistor, you can design RTS1, RTS2 and RTS3 according to your thermal protection specification. Table 1 shows an EXT_TS thermal protection design example. Temp [℃] VDD_DIG [V] RNTC [kΩ] RTS1 [kΩ] RTS2 [kΩ] RTS3 [kΩ] VEXT_TS [V] -40 3.0 188.5 3.9 47 68 1.550 -30 3.0 111.3 3.9 47 68 1.429 -20 3.0 67.8 3.9 47 68 1.278 -10 3.0 42.5 3.9 47 68 1.109 0 3.0 27.3 3.9 47 68 0.938 10 3.0 18.0 3.9 47 68 0.782 20 3.0 12.1 3.9 47 68 0.648 30 3.0 8.31 3.9 47 68 0.541 40 3.0 5.83 3.9 47 68 0.460 50 3.0 4.16 3.9 47 68 0.399 60 3.0 3.02 3.9 47 68 0.354 70 3.0 2.23 3.9 47 68 0.321 80 3.0 1.67 3.9 47 68 0.296 90 3.0 1.27 3.9 47 68 0.278 100 3.0 0.98 3.9 47 68 0.265 110 3.0 0.76 3.9 47 68 0.255 120 3.0 0.60 3.9 47 68 0.247 Status VEXT_TS > VTS_COLD Send EPT packet VTS_HOT < VEXT_TS < VTS_COLD Normal charging operation VEXT_TS < VTS_HOT Send EPT packet Table 1. EXT_TS Thermal Protection Design Example In this example, the hot temperature threshold TTS_HOT and the cold temperature threshold TTS_COLD are designed to be 80℃ and -10℃ respectively. You can change the hot and cold temperature threshold according to your application by changing the related resistors. 3.7 PCB Layout Guide  Keep the trace resistance as low as possible on large current nets as shown in Table 2.  Resonant capacitors CS and CP need to be as close to the device as possible. CELFRAS Semiconductor, Inc. -8- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC  Clamp, boost and communication capacitors (CCLAMP, CBOOST1, CBOOST2, CCOMM1, CCOMM2) need to be as close to the device as possible.  Output regulating capacitors CVRECT and CVOUT need to be as close to the device as possible. Net (Ball) Type Maximum Current [A] AC1, AC2 AC 1 VRECT AC 1 VOUT DC 1 PGND AC 1 COMM1, COMM2 AC 0.5 CLAMP AC 1 Table 2. Large Current Nets CELFRAS Semiconductor, Inc. -9- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC 4. Package Outline Figure 6. QFN 40-pin Package Outline, 6.0mm x 6.0mm, 0.5mm pitch CELFRAS Semiconductor, Inc. -10- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC 5. Electrical Characteristics 5.1 5.2 5.3 Absolute Maximum Rating PIN Parameter Rating Unit AC1, AC2, COMM1, COMM2, VRECT, CLAMP Voltage -0.3 to 20 V BOOST1, BOOST2 Voltage -0.3 to 26 V VOUT Voltage -0.3 to 15 V VPP Voltage -0.3 to 8 V VDD_5V, VDD_DIG, ENB, CHG_DONE ILIM, FOD, EXT_TS, SCL, SDA Voltage -0.3 to 6 V PGND Voltage -0.3 to 0.3 V AC1, AC2, VRECT, VOUT, CLAMP, PGND Current 2 A COMM1, COMM2 Current 1 A Recommended Operating Condition Symbol Description Min. VRECT Rectifier voltage range 4 IOUT Typ. Max. Unit 10 V Main LDO output current 1 A ICOMM COMM1, COMM2 sink current 500 mA TJ Junction temperature -30 125 ℃ TA Ambient temperature -30 85 ℃ Max. Unit Device Characteristics Symbol Description Conditions Min. Typ. Synchronous Active Rectifier VIN_RECT AC1, AC2 input voltage range 4.0 10 V fIN_RECT AC1, AC2 input frequency range 80 500 kHz Eff_RECT AC to DC power conversion efficiency VUVLO VUVLO_HYS 92 Under voltage lockout VRECT: 0V to 4V 3.2 Under voltage lockout hysteresis VRECT: 4V to 0V 400 % 3.3 V mV Main LDO VIN_MLDO Main LDO input voltage range CELFRAS Semiconductor, Inc. 4.0 -11- 10 V CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC VOUT_MLDO VOUT_MLDO_STEP Main LDO output voltage range Register programmable VRECT>5V 4.5 Main LDO output voltage control step IOUT_MLDO Main LDO output current range PSRR_MLDO Main LDO power supply rejection ratio 5.0 5.5 0.5 V 1.3 CVOUT=3.3uF DC to 100MHz 20 V A dB Internal LDO VOUT_VDD_5V Internal VDD_5V LDO output voltage range VRECT>5V 5 V VOUT_VDD_DIG Internal VDD_DIG LDO output voltage range VRECT>3V 3 V Internal BGR output voltage Register programmable VRECT>3V 1.22 V Internal oscillator frequency Register programmable VRECT>3V 15 MHz ADC resolution VRECT>3V 12 bit fOSC=15MHz 217 kSa/s BGR VBGR Oscillator fOSC ADC NADC fSAMPLE ADC sampling rate NCH_ADC ADC channel 7 Protection IOCL IOCL_HYS TOTP IOUT over current limit protection Programmable by RILIM RILIM=24kΩ IOUT: 0A to 2A 1.875 A OCL hysteresis IOUT: 2A to 0A 50 mA Over temperature protection Thermal shutdown temperature Temperature: 150 ℃ 20 ℃ 30℃ to 160℃ Temperature: TOTP_HYS OTP hysteresis VTS_HOT EXT_TS hot temperature protection threshold voltage VEXT_TS: 0V to 0.5V 0.315 V VTS_HOT hysteresis VEXT_TS: 0.5V to 0V 20 mV EXT_TS cold temperature protection threshold voltage VEXT_TS: 0.5V to 1.5V 0.980 V VTS_COLD hysteresis VEXT_TS: 1.5V to 0.5V 80 mV VTS_HOT_HYS VTS_COLD VTS_COLD_HYS CELFRAS Semiconductor, Inc. 160℃ to 30℃ -12- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC 6. I2C Signal Timing Figure 7. Timing Diagram for I2C interface Symbol Description Conditions VIL_SDA Input low threshold level SDA VPULLUP=VDD_DIG=3V VIH_SDA Input high threshold level SDA VPULLUP=VDD_DIG=3V VIL_SCL Input low threshold level SCL VPULLUP=VDD_DIG=3V VIH_SCL Input high threshold level SCL VPULLUP=VDD_DIG=3V Min. Typ. Max. Unit 0.7 V 2.3 V 0.7 2.3 V V fSCL SCL clock frequency 400 kHz tLOW SCL clock low time 1.3 us tHIGH SCL clock high time 0.6 us tr Rise time of both SDA and SCL 0.3 us tf Fall time of both SDA and SCL 0.3 us tSU,STA Setup time for START condition 0.6 us tHD,STA Hold time for START condition 0.6 us tSU,DAT Data setup time 0.1 us tHD,DAT Data hold time tSU,STO Setup time for STOP condition 0.6 us Bus free time between STOP and START condition 1.3 us tBF 0.9 us Table 3. I2C Characteristics CELFRAS Semiconductor, Inc. -13- CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC Revision History Date Version No. 2018/07/01 1.0 Description Preliminary Release Ordering Information Part Number Package Shipping Carrier CWR500 QFN 40 Tray CELFRAS Semiconductor, Inc. -14- Description VOUT=5V(BPP) CWR500 Datasheet (Rev 1.0) CWR500 Qi Compliant 5W Wireless Power Receiver IC Contact US  Headquarters CELFRAS Semiconductor Inc. 江西联智集成电路有限公司 59 Chuangxin No.1 Road, Nanchang Hi-tech Development Zone, Nanchang, Jiangxi, P.R.CHINA, Zip:330000  International CELFRAS Design Center Inc. 7F, 225-14, Pangyoyeok-ro, Bundang-gu, Seongnam-si, Gyeonggi-do, 13494, Korea Tel. +82-70-4055-6466 Fax +82-31-707-8825  Contact Website Technical Support cts@celfras.com, june_yoo@celfras.com Sales Contact marketing@celfras.com Copyright © 2018 CELFRAS., Inc. All rights reserved. CELFRAS., Inc. CELFRAS Semiconductor, Inc. -15- CWR500 Datasheet (Rev 1.0)