CWR500® Datasheet
Qi Compliant 5W Wireless Power Receiver IC
General Description
CWR500 can deliver up to 5W as a highly-integrated single-chip wireless medium power receiver IC. As wireless
power transfer systems are getting more popular, they require more fast charging and high efficiency solution.
The CWR500 wireless power receiver IC is compliant with WPC 1.2.4 standard and supports the 5W baseband
power profile (BPP) . The CWR500 power receiver integrates a synchronous rectifier, a low drop-out regulator,
and communication controllers which use Amplitude Shift Keying (ASK) . The chip also supports the Foreign
Object Detection (FOD) extension in WPC 1.2.4. For achieving chip stability, protection tools are implemented,
such as over-current-protection, over-voltage-protection, thermal shutdown, and under voltage lock-out (UVLO).
Configurable analog blocks can be used independently and co-operated with the control and communication unit.
Features Overview
Single-chip dual mode 5W receiver for WPC
1.2.4 compliance
Support 5W baseline power profile (BPP)
FOD extension supports
Integrated Synchronous Rectifier Receiver.
-
Support Output Power up to 5W.
-
High Rectifier Efficiency up to 95%.
-
High System Efficiency up to 90%.
- Topology Auto Selection operation.
Programmable Dynamic Rectifier Voltage Cont
rol.
Integrated Programmable Linear Regulator.
-
Output voltage range of 4.5~5.5V with 0.5V
control step.
- Adaptive Coil Power loss/offset compensation.
Programmable Temperature Control.
Charger Complete and Enable control inputs
End of Power Transfer (EPT) Packet manage
ment.
Over Current Limit
Over Voltage Protection
Thermal Shutdown
WLCSP 50B 2.64mm x 3.94mm, 0.4mm pitch
384-bit One-Time-Programmable Device
Applications
-
WPC Compliant Receivers.
-
Cell phones and smart phones.
- Output current limit up to 1A.
Bi-directional channel communication
-
Digital Cameras.
-
Power Banks.
- ASK modulation for PRx to PTx
24-bit Power Calculation support
Received Power Calculation for FOD function
-
Wireless Power Embedded Batteries
-
Bluetooth Headsets
-
Portable Media Players
-
Other Hand-held Device
-
12-bit ADC for voltage/current measuremen
t.
1. Description for Implementation
Datasheet (REV. 1.0)
Information furnished by CELFRAS is believed to be accurate and
reliable. However, no responsibility is assumed by CELFRAS for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of CELFRAS.
World Wide Web Site: TBD
Revised 2017-12-28
CWR500
Qi Compliant 5W Wireless Power Receiver IC
Figure 1. CWR500 Block Diagram
1.1
Overview
A wireless power charging system is composed of transmitter and receiver. In general, wireless power
transmitter will transfer AC power using a power amplifier through a TX inductor coil. Then wireless power
receiver will receive AC power through an RX inductor coil which is strongly coupled with the TX coil. In
receiver part, rectifier will change the AC power to DC power and LDO will transfer the DC power to battery
charger.
Figure1 shows the block diagram of CWR500 wireless charging receiver IC. CWR500 receiver will support
power transfer up to 5W and it is compliant with WPC1.2.4 standards. It consists of rectifier, main LDO,
internal LDOs, ADC, digital controller and etc.
1.2
Rectifier
CWR500 employs a synchronous active rectifier in order to improve AC to DC power conversion efficiency.
The rectifier power conversion efficiency is very important because it has a large influence on overall
receiver efficiency. The rectifier in CWR500 will support full-wave, half-wave and passive mode according to
the transferred power level. When the power transfer is started initially, the rectifier will operate in passive
mode and supply the system power to overall receive IC.
1.3
Main LDO
CELFRAS Semiconductor, Inc.
-2-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
Main LDO regulator will transfer DC power from rectifier output to battery charger. LDO in CWR1000 is
designed to transfer power up to 5W and its output voltage level can be changed by user. The LDO power
transistor is designed to minimize its on-resistance because the LDO drop-out voltage is directly related to
overall system efficiency. Especially, in case of large power transfer, the LDO drop-out voltage (VRECT-VOUT)
should be controlled as small as possible.
1.4
ASK Modulator
CWR1000 power receiver communicates with the power transmitter by ASK modulator. The ASK modulator
make up the WPC standard 2kHz bi-phase signal by switching the capacitors between COMM1/2 and AC1/AC2.
Switching the capacitance at AC1/AC2 nodes will change the impedance of transmitter coil. As a result,
amplitude modulation is built up.
1.5
ADC
CWR1000 power receiver employs 12-bit SAR ADC because it has low power, small area characteristics and
moderate speed performance. ADC monitors important internal voltages and currents and gives the system
information to the digital controller.
1.6
Protection
CWR500 power receiver employs various protection schemes in order to prevent system damage. When
the VRECT voltage is too high, the OVP (Over Voltage Protection) function will turn on the clamp path or
send the EPT (End Power Transfer) packet to the transmitter. When the main LDO current is too large, the
OCL (Over Current Limit) function will limit the output current. When the temperature inside or outside the
chip is too high, the OTP (Over Temperature Protection) function will send the EPT packet to transmitter or
shutdown the receiver system.
1.7
Digital Controller
Digital controller in CWR500 controls all the analog blocks and entire system to perform power transfer
operation according to the wireless power transfer standard, that is, WPC 1.2.4. It also supports I2C
interface to communicate with external host.
CELFRAS Semiconductor, Inc.
-3-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
2. Pin-out and description
Figure 2. CWR500 Pin Configuration (WLCSP 50B 2.64mm x 3.94mm, 0.4mm pitch)
2.1
Pin Description (WLCSP 50B 2.64mm x 3.94mm, 0.4mm pitch)
Pin Number
Name
Type
A1
CMA
O
A6
CMB
O
A2
EXT_TS
I
External temperature sensor input. Connect this pin to external NTC
thermistor. If not used, connect this pin to VDD_DIG.
A3
VDD_DIG
P
Internal 3V LDO output for digital block and etc. 1uF capacitor connect to GND.
Not for external use
A4
VPP
I
8V high voltage power for OTP programming. During the normal operation,
connect this pin to VDD_DIG.
A5
FOD
I
FOD offset setting pin. Connect a resistor between this pin and GND.
B1
COMM1
O
B6
COMM2
O
High voltage open drain output for ASK modulation. Connect 47nF capacitor
from AC1/AC2 to COMM1/COMM2 separately
B2
SDA
I/O
CELFRAS Semiconductor, Inc.
Description
NC
I2C data input/output for internal register access.
-4-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
B3
SCL
I
I2C clock input for internal register access.
B4
DIG1
I
Enable scan test mode. Connect to GND directly in normal application.
B5
ILIM
I
Output current or over-current limit level programming pin.
C1,D2,D5,D6
AVSS
P
Analog ground pin.
C2
DIG3
I
Scan clock for scan test mode. Connect to GND directly in normal application.
C3
DIG2
I
Scan enable for scan test mode. Connect to GND directly in normal application.
C4
ENB
I
Active-low enable pin for the entire chip.
C5
CHG_DONE
I
Active-high input from the external battery charger to terminate power
transfer.
C6
VDD_5V
P
Internal 5V LDO output pin for 1uF capacitor connection. Not for external use
D1
CLAMP
O
High voltage open drain output for analog linear over-voltage protection.
D3
DIG_TEST
O
Digital test output pin. Floating for normal application
D4
ANA_TEST
O
Analog test output pin. Floating for normal application
VOUT
P
Main LDO output pin for delivering power to the battery charger. 3.3uF
capacitor connect to GND.
VRECT
P
Internal synchronous rectifier output for 20uF capacitor connection.
G1
BOOST1
O
G6
BOOST2
O
Bootstrap capacitor connection pin for driving the high-side FETs of
synchronous rectifier. Connect 100nF capacitor to AC1/AC2 separately
H1,H2,H3
AC1
I
H4,H5,H6
AC2
I
PGND
P
E1,E6,F2,F3
F4,F5
F1,F6,G2,G3
G4,G5
J1,J2,J3,J4
J5,J6
CELFRAS Semiconductor, Inc.
AC power input of synchronous rectifier.
Power ground for synchronous rectifier.
-5-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
Application Guide
Figure 4. CWR500 Typical Application Diagram
2.2
Receiver Coil and Resonant Capacitors
The receiver coil design is related to the overall system application. The coil inductance, shape and
material can be chosen according to the applications. The recommended receiver coil inductance for dual
mode operation is between 5uH to 10uH. Series and parallel resonant capacitors CS and Cd are set according
to WPC specification. The capacitance of the resonant capacitors can be calculated by the following
equations.
CS =
Cd =
1
L'S ⅹ 2πfS
1
LS ⅹ 2πfD
2
2
−
1
CS
In these equations, fS and fD are the dual resonant frequencies which cover the power transfer frequency
range. Follow WPC Qi 1.2.4 specifications, fS is set to 100 kHz and fD is set to 1000kHz, respectively. L’S is
coil self-inductance when placed on the transmitter, and LS is the self-inductance when placed away from
the transmitter.
2.3
Boost and Communication Capacitors
As shown in Figure 4, two external bootstrap capacitors CBOOST1 and CBOOST2 are needed to drive the highside FETs of synchronous rectifier. Bootstrap capacitors should have voltage rating of more than 25V and
their recommended capacitances are 100nF.
CELFRAS Semiconductor, Inc.
-6-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
In order to communicate with transmitter, external capacitors should be connected between high voltage
open drain output and AC1/AC2 input. CWR500 will be switching COMM1/COMM2 output in WPC mode.
Typical recommended capacitance values are CCOMM1=CCOMM2=47nF.
2.4
Output Regulating Capacitors
As shown in Figure 4, rectifier output VRECT and internal LDOs’ output VOUT, VDD_5V, VDD_DIG should be
connected to external capacitor for voltage regulation. Typical recommended capacitance values are
CVRECT=20uF, CVOUT=3.3uF, CVDD_5V=1uF, CVDD_DIG=1uF, respectively.
2.5
Clamp Resistor
When the VRECT voltage is too high, the OVP (Over Voltage Protection) function will turn on the clamp
path or send the EPT (End Power Transfer) packet to the transmitter. The clamp path uses high voltage open
drain output for analog linear OVP. The recommended resistance value of RCLAMP is between 10Ω to 50Ω
according to the transfer power level of application.
2.6
Current Limit and FOD Setting Resistors
When the main LDO current is too large, the OCL (Over Current Limit) function will limit the output
current. The current limit level can be adjusted by external resistors and it is calculated as follows,
ILIM =
45000
45000
=
RILIM
RIL1 + RIL2
In this equation, the RILIM is the total resistance from the ILIM pin to ground, that is, RIL1 + RIL2 as shown in
Figure 4. It is recommended to use the resistors of good tolerance less than 1%, because the current
estimation in wireless power receiver is very important.
CWR500 adds an FOD offset proportional to output power level when it sends the received power packet
to transmitter. The amount of the added FOD offset can be adjusted by the ratio of RIL1 to (RIL1 + RIL2).
2.7
External Temperature Sensor
When the temperature inside or outside the chip is too high, the OTP (Over Temperature Protection)
function will send the EPT packet to transmitter or shutdown the receiver system. In order to sense the
temperature outside chip, connect EXT_TS pin to external NTC (Negative temperature Coefficient)
thermistor as shown in Figure 4. The NTC thermistor should be placed close to the heat emission device.
The EXT_TS voltage VEXT_TS can be calculated as follows,
VEXT_TS
RNTC + RTS1 × RTS3
RNTC + RTS1 + RTS3
= VDD_DIGⅹ
RNTC + RTS1 × RTS3
+ RTS2
RNTC + RTS1 + RTS3
In this equation, VDD_DIG is 3V from the internal LDO.
CWR1000 compares VEXT_TS with internal reference voltages VTS_HOT and VTS_COLD. If VEXT_TSVTS_COLD, it means external temperature is too low and CWR500 also sends the EPT
packet (value=0x03) to transmitter. Remind that VEXT_TS is negative slope curve vs temperature.
The internal reference voltages VTS_HOT and VTS_COLD are fixed values as follows,
Internal TS Reference
Threshold Voltage [V]
Hysteresis [mV]
VTS_HOT
0.315
20
CELFRAS Semiconductor, Inc.
-7-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
VTS_COLD
0.980
80
Recommended NTC resistance range is from hundreds of Ω to hundreds of kΩ vs temperature. After
choosing the appropriate NTC thermistor, you can design RTS1, RTS2 and RTS3 according to your thermal
protection specification. Table 1 shows an EXT_TS thermal protection design example.
Temp
VDD_DIG
[V]
RNTC
RTS1
RTS2
RTS3
[℃]
[kΩ]
[kΩ]
[kΩ]
[kΩ]
VEXT_TS
[V]
-40
3.0
188.5
3.9
47
68
1.550
-30
3.0
111.3
3.9
47
68
1.429
-20
3.0
67.8
3.9
47
68
1.278
-10
3.0
42.5
3.9
47
68
1.109
0
3.0
27.3
3.9
47
68
0.938
10
3.0
18.0
3.9
47
68
0.782
20
3.0
12.1
3.9
47
68
0.648
30
3.0
8.31
3.9
47
68
0.541
40
3.0
5.83
3.9
47
68
0.460
50
3.0
4.16
3.9
47
68
0.399
60
3.0
3.02
3.9
47
68
0.354
70
3.0
2.23
3.9
47
68
0.321
80
3.0
1.67
3.9
47
68
0.296
90
3.0
1.27
3.9
47
68
0.278
100
3.0
0.98
3.9
47
68
0.265
110
3.0
0.76
3.9
47
68
0.255
120
3.0
0.60
3.9
47
68
0.247
Status
VEXT_TS > VTS_COLD
Send EPT packet
VTS_HOT < VEXT_TS < VTS_COLD
Normal charging operation
VEXT_TS < VTS_HOT
Send EPT packet
Table 1. EXT_TS Thermal Protection Design Example
In this example, the hot temperature threshold TTS_HOT and the cold temperature threshold TTS_COLD are
designed to be 80℃ and -10℃ respectively. You can change the hot and cold temperature threshold
according to your application by changing the related resistors.
2.8
CHG_DOWN
When CHG_DOWN is from low to high, CWR500 send “charging complete” EPT (0x01) to TX to inform TX
that battery is charging complete.
2.9
ENB
When applying logic high to ENB, CWR500 is suspended and IC leakage current will be smaller than 10uA.
When ENB is logic low level, CWR500 is enabled for wireless charging.
2.10
PCB Layout Guide
Keep the trace resistance as low as possible on large current nets as shown in Table 2.
CELFRAS Semiconductor, Inc.
-8-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
Resonant capacitors CS and Cd need to be as close to the device as possible.
Clamp, boost and communication capacitors (CCLAMP, CBOOST1, CBOOST2, CCOMM1, CCOMM2, CCMA and CCMB) need to
be as close to the device as possible.
Output regulating capacitors CVRECT and CVOUT need to be as close to the device as possible.
LDO capacitors C
Net (Ball)
Type
Maximum Current [A]
AC1, AC2
AC
1.5
VRECT
AC
1.5
VOUT
DC
1.5
PGND
AC
1.5
COMM1, COMM2, CMA, CMB
AC
1
CLAMP
AC
1.5
Table 2. Large Current Nets
2.11
Register Map
7bit Address: 0x24H.
Register
index
(hex)
27h
2Eh
2Fh
41h
42h
5Ch
5Dh
5Eh
62h
63h
64h
68h
69h
Bit Number
B7
B6
B5
B4
B3
SET_VOUT_EXTENDED[3:0]
COLD_UTP[1:0]
OCL_ON_
PEN_PROT
MASK
B2
B1
B0
SET_VOUT_BASE_LINE[3:0]
OVP[1:0]
HOT_OTP[1:0]
OTP_COLD_
TSD_OUT_ OVP_OU OTP_HOT
RELEASE_TIME[1:0]
MASK
T_MASK
_ MASK
MASK
REF_Q_FACTOR
PTC_GUARANTEED_PWR
ADC_CODE
Reserved
ADC_OUT[11:8]
ADC_OUT[7:0]
8bit RP
24bit RP[15:8]
24bit RP[7:0]
POWER_CLASS
GUARANTEED_POWER_VALUE
Reserved
POTENTIAL_POWER_VALUE
CELFRAS Semiconductor, Inc.
TSD[1:0]
-9-
W/R
W/R
W/R
W/R
W/R
R
W/R
R
R
R
R
R
R
R
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
DETAILED REGISTER INFORMATION
REG
27H
REG
Bit
REG
2FH
Type
Default
Description
7
VOUT_EPP[3]
R/W
1
6
VOUT_EPP[2]
R/W
0
5
VOUT_EPP[1]
R/W
0
4
VOUT_EPP[0]
R/W
1
3
VOUT_BPP[3]
R/W
0
Setup bits of VOUT voltage for base line profile
2
VOUT_BPP[2]
R/W
0
Offset: 4.5 V, Range 4.5 V – 9.5 V; Unit=0.5V
1
VOUT_BPP[1]
R/W
0
Default: 5 V (0001).
0
VOUT_BPP[0]
R/W
1
Normal case, VOUT=5V in BPP mode
Type
Default
Bit
Field
7
COLD_UTP[1]
R/W
1
6
COLD_UTP[0]
R/W
0
5
2EH
Field
4
TSD[1]
R/W
TSD[0]
R/W
Default:
Description
00
1.163V / 1.073V (Detection / Release)
01
1.069V / 0.984V (Detection / Release)
10
0.980V / 0.898V (Detection / Release)
11
0.894V / 0.820V (Detection / Release)
00
130 ℃ / 110 ℃ (Die OTP Detection / Releas
e)
01
140 ℃ / 120 ℃ (Die OTP Detection / Releas
e)
10
150 ℃ / 130 ℃ (Die OTP Detection / Releas
e)
11
160 ℃ / 140 ℃ (Die OTP Detection / Releas
e)
00
14.0 V / 12.5 V (Detection / Release)
01
14.5 V / 13.0 V (Detection / Release)
10
15.0 V / 13.5 V (Detection / Release)
11
15.5 V / 14.0 V (Detection / Release)
0
OVP[1]
R/W
1
2
OVP[0]
R/W
0
1
HOT_OTP[1]
R/W
1
0
HOT_OTP[0]
R/W
0
Type
Default
Field
Offset: 4.5 V, Range 4.5 V – 9.5 V; Unit=0.5V
1
3
Bit
Setup bits of VOUT voltage for extended profile ,
00
0.339V / 0.367V (Detection / Release)
01
0.326V / 0.351V (Detection / Release)
10
0.314V / 0.335V (Detection / Release)
11
0.306V / 0.322V (Detection / Release)
Description
0:disable protection function,
1:enable protection function
7
PEN_PROT
R/W
1
6
OCL_ON_MASK
R/W
1
5
RELEASE_TIME[1]
R/W
0
RELEASE_TIME[0]
R/W
3
TSD_OUT_MASK
R/W
1
0: No mask; 1: mask
Initially all signals are masked and release masks
after a time delay. 00:No release; 01: Release after
5s; 10: Release after 10s;
11:Release after
20s;
0: No mask; 1: mask
2
OVP_OUT_MASK
R/W
1
0: No mask; 1: mask
1
OTP_HOT_MASK
R/W
1
0: No mask; 1: mask
4
CELFRAS Semiconductor, Inc.
0
-10-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
0
REG
41H
REG
Bit
Default
6
REF_Q_FACTOR[6]
R/W
0
5
REF_Q_FACTOR[5]
R/W
0
4
REF_Q_FACTOR[4]
R/W
1
3
REF_Q_FACTOR[3]
R/W
0
2
REF_Q_FACTOR[2]
R/W
1
1
REF_Q_FACTOR[1]
R/W
0
0
REF_Q_FACTOR[0]
R/W
0
Type
Default
Bit
Field
7
Reserved
-
-
6
Reserved
-
-
R
0
R
0
R
1
R
0
R
1
R
0
Bit
PTC_GUARANTEED_PO
WER[5]
PTC_GUARANTEED_PO
WER[4]
PTC_GUARANTEED_PO
WER[3]
PTC_GUARANTEED_PO
WER[2]
PTC_GUARANTEED_PO
WER[1]
PTC_GUARANTEED_PO
WER[0]
Field
Type
Default
7
Reserved
-
-
6
Reserved
-
-
5
-
-
4
Reserved
Reserved
-
-
3
ADC_CODE[3]
R/W
0
2
ADC_CODE[2]
R/W
0
1
ADC_CODE[1]
R/W
0
0
ADC_CODE[0]
R/W
0
Bit
Field
Type
Default
7
Reserved
-
-
6
Reserved
-
-
5
Reserved
-
-
4
Reserved
-
-
3
ADC_OUT[11]
R
0
3
0
5DH
Type
0
1
REG
0: No mask; 1: mask
R/W
2
5CH
Field
1
REF_Q_FACTOR[7]
4
REG
R/W
7
5
42H
OTP_COLD_MASK
CELFRAS Semiconductor, Inc.
-11-
Description
Quality factor reference value
Description
Reserved
Guaranteed Power Value in Power Transfer
Contract. Unit=0.5W
Description
Reserved
The related ADC_OUT value is loaded to
Reg: 0x5D and Reg 0x5E.
4'b0000:VRECT; 4’0001:VOUT
4’b0010:IOUT;
4’b0011:ILIM
4’b0100:FOD;
4’b0101：EXT_TS
4’b0110:VCTAT
Description
Reserved
ADC value with Reg 5EH according to
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
REG
5EH
REG
62H
REG
63H
REG
64H
2
ADC_OUT[10]
R
0
1
ADC_OUT[9]
R
0
0
ADC_OUT[8]
R
0
ADC_CODE register select ADC channel
ADC MSB 4bits
Bit
Field
Type
Default
7
ADC_OUT[7]
R
0
6
ADC_OUT[6]
R
0
5
ADC_OUT[5]
R
0
4
ADC_OUT[4]
R
0
3
ADC_OUT[3]
R
0
2
ADC_OUT[2]
R
0
1
ADC_OUT[1]
R
0
0
ADC_OUT[0]
R
0
Bit
Field
Type
Default
7
8bit RP[7]
R
0
6
8bit RP[6]
R
0
5
8bit RP[5]
R
0
4
8bit RP[4]
R
0
3
8bit RP[3]
R
0
2
8bit RP[2]
R
0
1
8bit RP[1]
R
0
0
8bit RP[0]
R
0
Bit
Field
Type
Default
7
24bit RP[15]
R
0
6
24bit RP[14]
R
0
5
24bit RP[13]
R
0
4
24bit RP[12]
R
0
3
24bit RP[11]
R
0
2
24bit RP[10]
R
0
1
24bit RP[9]
R
0
0
24bit RP[8]
R
0
Bit
Field
Type
Default
7
24bit RP[7]
R
0
6
24bit RP[6]
R
0
5
24bit RP[5]
R
0
4
24bit RP[4]
R
0
3
24bit RP[3]
R
0
CELFRAS Semiconductor, Inc.
-12-
Description
ADC value with Reg5DH according to
ADC_COUD register select ADC
channel ADC LSB 8bits
Description
8bits Receiver Power Package ValueBPP only
Description
24bits Receiver Power Package Value
High 8bits-EPP
only
Description
24bits Receiver Power Package Value
Low 8bits-EPP
only
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
REG
68H
REG
69H
2
24bit RP[2]
R
0
1
24bit RP[1]
R
0
0
24bit RP[0]
R
0
Bit
Field
Type
Default
7
TX POWER CLASS[1]
R
0
6
TX POWER CLASS[0]
R
0
5
TX_GUARANTEED_POWER[5]
R
0
4
TX_GUARANTEED_POWER[4]
R
0
3
TX_GUARANTEED_POWER[3]
R
0
2
TX_GUARANTEED_POWER[2]
R
0
1
TX_GUARANTEED_POWER[1]
R
0
0
TX_GUARANTEED_POWER[0]
R
0
Bit
Field
Type
Default
7
Reserved
-
-
6
Reserved
-
-
5
TX_POTENTIAL_POWER[5]
R
0
4
TX_POTENTIAL_POWER[4]
R
0
3
TX_POTENTIAL_POWER[3]
R
0
2
TX_POTENTIAL_POWER[2]
R
0
1
TX_POTENTIAL_POWER[1]
R
0
0
TX_POTENTIAL_POWER[0]
R
0
CELFRAS Semiconductor, Inc.
-13-
Description
TX Power Class Value by FSK
TX Guaranteed Power Value by
FSK
Description
Reserved
TX Potential Power Value by FSK
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
3. Package Outline
Figure 5. WLCSP 50B Package Outline, 2.64mm x 3.94mm, 0.4mm pitch
CELFRAS Semiconductor, Inc.
-14-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
4. Electrical Characteristics
4.1
4.2
4.3
Absolute Maximum Rating
PIN
Parameter
Rating
Unit
AC1, AC2, COMM1, COMM2, CMA, CMB
VRECT, CLAMP
Voltage
-0.3 to 20
V
BOOST1, BOOST2
Voltage
-0.3 to 26
V
VOUT
Voltage
-0.3 to 9.5
V
VPP
Voltage
-0.3 to 8
V
VDD_5V, VDD_DIG, ENB, CHG_DONE
ILIM, FOD, EXT_TS, SCL, SDA
Voltage
-0.3 to 6
V
PGND
Voltage
-0.3 to 0.3
V
AC1, AC2, VRECT, VOUT, CLAMP, PGND
Current
1.5
A
COMM1, COMM2, CMA, CMB
RMS Current
1
A
Recommended Operating Condition
Symbol
Description
Min.
VRECT
Rectifier voltage range
4
IOUT
Typ.
Max.
Unit
15
V
Main LDO output current
1.5
A
ICOMM
COMM1, COMM2 sink current
500
mA
ICM
CMA, CMB sink current
500
mA
TJ
Junction temperature
-30
125
℃
TA
Ambient temperature
-30
85
℃
Thermal Information
CWR500 WLCSP 50B 2.
64mm x 3.94mm
Parameters
UNITS
Junction-to-ambient thermal resistance
℃/W
Junction-to-case thermal resistance
℃/W
Junction-to-board thermal resistance
℃/W
Junction temperature，TJ
℃
Ambient operation temperature
℃
Storage temperature，Tstg
℃
Lead soldering temperature，TL(10s)
℃
CELFRAS Semiconductor, Inc.
-15-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
4.4
ESD
Test Model
RATINGS
UNITS
HBM: all pins
CDM: all pins
4.5
V
V
ELECTRICAL Characteristics
Unless otherwise specified: TA = -20°C to 70°C. Typical values are for TA = 25°C
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
Synchronous Active Rectifier
VIN_RECT
AC1, AC2 input voltage range
4.0
20
V
fIN_RECT
AC1, AC2 input frequency range
80
500
kHz
Eff_RECT
AC to DC power conversion efficiency
VUVLO
VUVLO_HYS
92
Under voltage lockout
VRECT: 0V to 4V
3.2
Under voltage lockout hysteresis
VRECT: 4V to 0V
400
%
3.3
V
mV
Main LDO
VIN_MLDO
VOUT_MLDO
VOUT_MLDO_STEP
Main LDO input voltage range
Main LDO output voltage range
Register programmable
VRECT>5V
4.0
15
V
4.5
12
V
Main LDO output voltage control step
0.5
IOUT_MLDO
Main LDO output current range
PSRR_MLDO
Main LDO power supply rejection ratio
V
1.7
CVOUT=3.3uF
DC to 100MHz
20
A
dB
Internal LDO
VOUT_VDD_5V
VOUT_VDD_DIG
Internal VDD_5V LDO output voltage
range
Internal VDD_DIG LDO output voltage
range
VRECT>5V,
CVDD_5V=1uF,
External load3V,
CVDD_DIG=1uF
External load3V
1.22
V
Internal oscillator frequency
Register programmable
VRECT>3V
15
MHz
ADC resolution
VRECT>3V
12
bit
fOSC=15MHz
217
kSa/s
Oscillator
fOSC
ADC
NADC
fSAMPLE
ADC sampling rate
NCH_ADC
ADC channel
7
ENB/CHG_DOWN
VIH
ENB/CHG_DOWN input threshold high
CELFRAS Semiconductor, Inc.
1.5
-16-
V
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
VIL
ENB/CHG_DOWN input threshold low
0.5
V
15.2
V
Protection
VOVP
VOVP_HYS
IOCL
IOCL_HYS
TOTP
VRECT over voltage protection
Register programmable
VRECT: 5V to 16V
OVP hysteresis
VRECT: 16V to 5V
IOUT over current limit protection
Programmable by RILIM
IOUT: 0A to 2A
OCL hysteresis
IOUT: 2A to 0A
Over temperature protection
Thermal shutdown temperature
Temperature:
14.8
RILIM=24kΩ
30℃ to 160℃
Temperature:
15
1.5
V
1.875
A
50
mA
150
℃
20
℃
TOTP_HYS
OTP hysteresis
VTS_HOT
EXT_TS hot temperature protection
threshold voltage
VEXT_TS: 0V to 0.5V
0.315
V
VTS_HOT hysteresis
VEXT_TS: 0.5V to 0V
20
mV
EXT_TS cold temperature protection
threshold voltage
VEXT_TS: 0.5V to 1.5V
0.980
V
VTS_COLD hysteresis
VEXT_TS: 1.5V to 0.5V
80
mV
VTS_HOT_HYS
VTS_COLD
VTS_COLD_HYS
160℃ to 30℃
5. I2C Signal Timing
Figure 7. Timing Diagram for I2C interface
Symbol
Description
Conditions
VIL_SDA
Input low threshold level SDA
VPULLUP=VDD_DIG=3V
VIH_SDA
Input high threshold level SDA
VPULLUP=VDD_DIG=3V
VIL_SCL
Input low threshold level SCL
VPULLUP=VDD_DIG=3V
VIH_SCL
Input high threshold level SCL
VPULLUP=VDD_DIG=3V
Min.
Typ.
Max.
Unit
0.7
V
2.3
V
0.7
2.3
V
V
fSCL
SCL clock frequency
tLOW
SCL clock low time
1.3
us
tHIGH
SCL clock high time
0.6
us
tr
400
Rise time of both SDA and SCL
CELFRAS Semiconductor, Inc.
0.3
-17-
kHz
us
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
tf
Fall time of both SDA and SCL
0.3
us
tSU,STA
Setup time for START condition
0.6
us
tHD,STA
Hold time for START condition
0.6
us
tSU,DAT
Data setup time
0.1
us
tHD,DAT
Data hold time
tSU,STO
Setup time for STOP condition
0.6
us
Bus free time between STOP and START
condition
1.3
us
tBF
0.9
us
Table 3. I2C Characteristics
CELFRAS Semiconductor, Inc.
-18-
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
Revision History
Date
Version No.
2017/07/27
1.0
Description
Preliminary Release
Ordering Information
Part
Number
CWR500-W5
CWR500-W9
CWR500-WC
Shipping
Carrier
Package Type
WLCSP 50, 2.6
4mm x 3.94m
m
WLCSP 50, 2.6
4mm x 3.94m
m
WLCSP 50, 2.6
4mm x 3.94m
m
Tape and Reel
Eco
Plan
Package
Qty
Green
(RoHS&noSb/Br)
MSL Peak Temp
Description
Level-1-260C-UNLIM
VOUT=5V(BPP),
5V(EPP)
Tape and Reel
Green
(RoHS& no Sb/Br)
Level-1-260C-UNLIM
VOUT=5V(BPP),
9V(EPP)
Tape and Reel
Green
(RoHS& no Sb/Br)
Level-1-260C-UNLIM
VOUT=5V(BPP),
12V(EPP)
CELFRAS Semiconductor, Inc.
-19-
Device M
arking
CWR500 Datasheet (Rev 1.0)
CWR500
Qi Compliant 5W Wireless Power Receiver IC
Contact US
Headquarters
CELFRAS Semiconductor Inc. 江西联智集成电路有限公司
59 Chuangxin No.1 Road, Nanchang Hi-tech Development Zone, Nanchang, Jiangxi, P.R.CHINA, Zip:33000
0
International
CELFRAS Design Center Inc.
7F, 225-14, Pangyoyeok-ro, Bundang-gu, Seongnam-si, Gyeonggi-do, 13494, Korea
Tel. +82-70-4055-6466
Fax +82-31-707-8825
Contact
Website
Technical Support
cts@celfras.com, ken_zhang@celfras.com
Sales Contact
marketing@celfras.com
Copyright © 2018 CELFRAS., Inc. All rights reserved.
CELFRAS., Inc.
CELFRAS Semiconductor, Inc.
-20-
CWR500 Datasheet (Rev 1.0)
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