HX24LC32B/64B
Features
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Wide Voltage Operation
- VCC = 1.8V to 5.5V
Operating Ambient Temperature: -40℃ to +85℃
Internally Organized:
- HX24LC32B, 4096 X 8 (32K bits)
- HX24LC64B, 8192 X 8 (64K bits)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
Write Protect Pin for Hardware Data Protection
32-byte Page (32K, 64K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
Die Sales: Wafer Form, Waffle Pack
ORDERING INFORMATION
DEVICE
Package Type
MARKING
Packing
Packing Qty
HX24LC32BPG
DIP8
24LC32
TUBE
2000/box
HX24LC64BPG
DIP8
24LC64
TUBE
2000/box
HX24LC32BDRG
SOP8
24LC32
REEL
4000/reel
HX24LC64BDRG
SOP8
24LC64
REEL
4000/reel
HX24LC32BMMRG
MSOP8
24LC32
REEL
3000/reel
HX24LC64BMMRG
MSOP8
24LC64
REEL
3000/reel
General Description
The HX24LC32B / 64B provides 32,768/65,536 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device is optimized
for use in many industrial and commercial applications where low-power and low-voltage operations
are essential. The HX24LC32B / 64B is available in space-saving 8-lead DIP, 8-lead SOP, and
8-lead MSOP packages and is accessed via a two-wire serial interface.
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Pin Configuration
DIP8/SOP8/MSOP8
Pin Descriptions
Table 1: Pin Configuration
Pi
Pin Designation
A0 - A2
SDA
SCL
WP
GND
VCC
Type
I
I/O & Open-drain
I
I
P
P
Name and Functions
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
N
Block Diagram
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Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs
that are hard wired for the HX24LC32B / 64B . Eight 32K/64K devices may be addressed on a single
bus system (device addressing is discussed in detail under the Device Addressing section).
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
WRITE PROTECT (WP): The HX24LC32B / 64B has a Write Protect pin that provides hardware
data protection. The Write Protect pin allows normal read/write operations when connected to ground
(GND). When the Write Protect pin is connected
to VCC, the write protection feature is enabled and operates as shown in the following Table 2.
Table 2: Write Protect
WP Pin Status
At VCC
At GND
Part of the Array Protected
HX24LC32B
Full (32K) Array
HX24LC64B
Full (64K) Array
Normal Read/Write Operations
Memory Organization
HX24LC32B , 32K SERIAL EEPROM: Internally organized with 128 pages of 32 bytes each, the 32K
requires an 12-bit data word address for random word addressing.
HX24LC64B, 64K SERIAL EEPROM: Internally organized with 256 pages of 32 bytes each, the 64K
requires a 13-bit data word address for random word address
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 5). Data
changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see to Figure 2 on page 5).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on
page 5).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM
in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This
happens during the ninth clock cycle.
STANDBY MODE: Th e HX24LC32B / 64B
features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations
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MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part
can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
l
Figure 1: Data Validity
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Figure 2: Start and Stop Definition
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Figure 3: Output Acknowledge
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Device Addressing
The 32K and 64K EEPROM devices all require an 8-bit device address word following a start
condition to enable the chip for a read or write operation (see to Figure 4 on page 7).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant
bits as shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 32K/64K EEPROM. These 3 bits
must compare to their corresponding hardwired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated
if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the
chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word address following the device address
word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0"
and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will
output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence
with a stop condition. At this time the EEPROM enters an internally timed write cycle, t WR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond
until the write is complete (see Figure 5 on page 7).
PAGE WRITE: The 32K/64K EEPROM is capable of a 32-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of
the first data word, the microcontroller can transmit up to 31 (32K, 64K) more data words. The
EEPROM will respond with a "0" after each data word received. The microcontroller must terminate
the page write sequence with a stop condition (see Figure 6 on page 8).
The data word address lower five (32K, 64K) bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the following
byte is placed at the beginning of the same page. If more than 32 (32K, 64K) data words are
transmitted to the EEPROM, the data word address will "roll over" and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM
inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition
followed by the device address word. The read/write bit is representative of the operation desired.
Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read
or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to "1". There are three read operations: current address read,
random address read and sequential read.
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CURRENT ADDRESS READ: The internal data word address counter maintains the last address
accessed during the last read or write operation, incremented by one. This address stays valid between
operations as long as the chip power is maintained. The address "roll over" during read is from the last
byte of the last memory page to the first byte of the first page. The address "roll over" during write is
from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond
with an input "0" but does generate a following stop condition (see Figure 7 on page 8).
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word
address. Once the device address word and data word address are clocked in and acknowledged by the
EEPROM, the microcontroller must generate another start condition. The microcontroller now
initiates a current address read by sending a device address with the read/write select bit high. The
EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller
does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random
address read. After the microcontroller receives a data word, it responds with an acknowledge. As
long as the EEPROM receives an acknowledge, it will continue to increment the data word address
and serially clock out sequential data words. When the memory address limit is reached, the data word
address will "roll over" and the sequential read will continue. The sequential read operation is
terminated when the microcontroller does not respond with a "0" but does generate a following stop
condition (see Figure 9 on page 9).
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Figure 4: Device Address
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Figure 5: Byte Write
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l
Figure 6: Page Write
l
Figure 7: Current Address Read
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Figure 8: Random Read
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Figure 9: Sequential Read
Electrical Characteristics
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Absolute Maximum Stress Ratings
DC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V
Operating Ambient Temperature . . . . . -40℃ to +85 ℃
Input / Output Voltage . . . . . . . .GND-0.3V to V CC+0.3V
Storage Temperature . . . . . . . . . . . . -65℃ to +150℃
l Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this
device. These are stress ratings only. Functional operation of this device at these or any other
conditions above those indicated in the operational sections of this specification is not implied or
intended. Exposure to the absolute maximum rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.8V to +5.5V
(unless otherwise noted)
Parameter
Supply Voltage
Supply Current Vcc=5.0V
Supply Current Vcc=5.0V
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Level
Input High Level
Output Low Level Vcc=5.0V
Output Low Level Vcc=3.0V
Output Low Level Vcc=1.8V
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Symbol
Vcc
Icc1
Icc2
ISB
ILI
ILO
V IL
VIH
VOL3
VOL2
VOL1
Typ.
0.4
2.0
0.05
-
Min.
1.8
-0.6
Vcc×0.7
-
8
Max.
5.5
1.0
3.0
2.0
3.0
3.0
Vcc×0.3
Vcc + 0.5
0.4
0.4
0.2
Unit
V
mA
mA
uA
uA
uA
V
V
V
V
V
Condition
Read @100KHz
Write @100KHz
Vin=Vcc or GND
Vin=Vcc or GND
Vout=Vcc or GND
IOL=3.0mA
IOL=2.1mA
IOL=0.15mA
2022 MAR
HX24LC32B/64B
Pin Capacitance
Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.8V
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Symbol
C I/O
C IN
Min.
-
Typ.
-
Max.
8
6
Unit
pF
pF
Condition
VI/O = 0V
VIN = 0V
AC Electrical Characteristics
Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.8V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
fSCL
tLOW
tHIGH
tI
tAA
Min.
1.2
0.6
0.05
1.8-volt
Typ.
-
Max.
400
50
0.9
Min.
0.6
0.4
0.05
5.0-volt
Typ.
-
Max.
1000
40
0.55
tBUF
1.2
-
-
0.5
-
-
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
0.6
0.6
0
100
0.6
50
-
-
0.3
300
5
0.25
0.25
0
100
0.25
50
-
-
0.3
100
5
Endurance
1M
-
-
-
-
-
Parameter
Symbol
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
5.0V, 25℃, Byte Mode
Units
KHz
us
us
us
us
us
us
us
us
ns
us
ns
us
ns
ms
Write
Cycles
Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall time: ≤50 ns
Input and output timing reference voltages: 0.5 VCC
The value of RL should be concerned according to the actual loading on the user's system.
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Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
l
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
Note
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.
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PACKAGE
SOP8
Dimensions In Millimeters
Symbol
Min
Max
Symbol
Min
Max
A
1.225
1.570
D
A1
Q
B
a
C
b
C1
DIP8
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A
A2
MSOP8
D
E
E1
A1
e
b
©
L
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Important statement:
Shenzhen Hanschip semiconductor co.,ltd. reserves the right to
change the products and services provided without notice. Customers
should obtain the latest relevant information before ordering, and
verify the timeliness and accuracy of this information.
Customers are responsible for complying with safety standards and
taking safety measures when using our products for system design
and machine manufacturing to avoid potential risks that may result in
personal injury or property damage.
Our products are not licensed for applications in life support, military,
aerospace, etc., so we do not bear the consequences of the
application of these products in these fields.
Our documentation is only permitted to be copied without any
tampering with the content, so we do not accept any responsibility or
liability for the altered documents.
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