PN: DS35X1GAXXX
DS35X1GAXXX
3.3V/1.8V x1/x2/x4 1G-bit SPI NAND FLASH
Rev.03 (Feb 20, 2020) 1
PN: DS35X1GAXXX
Catalog
Revision History ......................................................................................................................................................... 5
FEATURES .................................................................................................................................................................. 6
Part Numbering System ............................................................................................................................................. 7
1 SUMMARY DESCRIPTION ......................................................................................................................................... 8
1.1 Product List ....................................................................................................................................................... 9
1.2 Pin description ................................................................................................................................................ 10
1.3 Functional block diagram ................................................................................................................................. 11
1.4 Address Map ................................................................................................................................................... 11
1.5 Command Set ................................................................................................................................................. 12
2 BUS OPERATION .................................................................................................................................................... 13
2.1 SPI Mode. ....................................................................................................................................................... 13
2.2 CS# ................................................................................................................................................................. 13
2.3 SI/SIO0 ........................................................................................................................................................... 13
2.4 SO/SIO1 .......................................................................................................................................................... 13
2.5 WP#/SIO2 ....................................................................................................................................................... 13
2.6 HOLD#/SIO3 .................................................................................................................................................... 14
3 DEVICE OPERATION ............................................................................................................................................... 15
3.1 Write Operations. ............................................................................................................................................ 15
3.2 Feature Operations ......................................................................................................................................... 15
3.3 Read Operations.............................................................................................................................................. 17
3.4 Read ID. .......................................................................................................................................................... 21
3.5 Parameter Page. .............................................................................................................................................. 23
3.6 UniqueID Page. ............................................................................................................................................... 24
3.7 Program Operations. ....................................................................................................................................... 24
3.8 BLOCK ERASE .................................................................................................................................................. 30
3.9 Block Lock Feature. .......................................................................................................................................... 31
3.10 OTP Feature. ................................................................................................................................................. 32
3.11 Status Register .............................................................................................................................................. 33
3.12 ECC Protection .............................................................................................................................................. 34
4 Device Parameters ................................................................................................................................................ 35
5 Bad Block Management ......................................................................................................................................... 39
6 Supported Packages .............................................................................................................................................. 42
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Figure Content
Figure 1.1 Logic Diagram ................................................................................................................................................................ 9
Figure 1.3 Address Map ............................................................................................................................................................... 11
Figure 1.2 Block Description......................................................................................................................................................... 11
Figure 2.1 SPI Modes Timing ........................................................................................................................................................ 13
Figure 3.1 Write Enable................................................................................................................................................................ 15
Figure 3.2 Write Disable ............................................................................................................................................................... 15
Figure 3.3 Get Features(0Fh) ....................................................................................................................................................... 16
Figure 3.4 Set Features(1Fh) ........................................................................................................................................................ 16
Figure 3.5 Page Read (13h) .......................................................................................................................................................... 18
Figure 3.6 Random Data Read (03h or 0Bh) ................................................................................................................................. 19
Figure 3.7 Read From Cache x2 .................................................................................................................................................... 20
Figure 3.8 Read From Cache x4 .................................................................................................................................................... 21
Figure 3.9 Read ID (9Fh) ............................................................................................................................................................... 22
Figure 3.10 Program Load (02h)................................................................................................................................................... 25
Figure 3.11 Program Load x4 (32h) .............................................................................................................................................. 26
Figure 3.12 Program Excute (10h) ................................................................................................................................................ 27
Figure 3.13 Program Load Random Data (84h) ............................................................................................................................ 28
Figure 3.14 Program Load Random Data x4 (34h) ....................................................................................................................... 29
Figure 3.15 Block Erase ................................................................................................................................................................ 30
Figure 4.1 Serial Input Timing ...................................................................................................................................................... 38
Figure 4.2 Serial Output Timing ................................................................................................................................................... 38
Figure 4.3 Hold Timing ................................................................................................................................................................. 38
Figure 4.4 WP# Setup/Hold Timing When BPRWD=1 .................................................................................................................. 39
Figure 4.5 Power on Sequence..................................................................................................................................................... 39
Figure 5.1 Bad Block Management Flowchart ............................................................................................................................. 40
Figure 5.2 Bad Block Replacement ............................................................................................................................................... 41
Figure 6.1 Pin Configuration......................................................................................................................................................... 42
Figure 6.2 WSON (8*6mm) .......................................................................................................................................................... 43
Figure 6.3 SOP16 .......................................................................................................................................................................... 44
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PN: DS35X1GAXXX
Table Content
Table 1.1 Signal Name .................................................................................................................................................................... 9
Table 1.2 Pin Description ............................................................................................................................................................. 10
Table 1.3 Command Set ............................................................................................................................................................... 12
Table 3.1 Status Register Coding.................................................................................................................................................. 16
Table 3.2 Read ID for Supported Configurations ......................................................................................................................... 22
Table 3.3 Parameter Page Data ................................................................................................................................................... 24
Table 3.4 Definition of Protectiong Bits ....................................................................................................................................... 31
Table 3.5 OTP States .................................................................................................................................................................... 32
Table 3.6 Status Register Bit Descriptions ................................................................................................................................... 33
Table 3.7 The Distribution of ECC Segment and Spare Area ........................................................................................................ 34
Table 4.1 Valid Blocks Number .................................................................................................................................................... 35
Table 4.2 Absolute Maximum Ratings ......................................................................................................................................... 35
Table 4.3 DC and Operating Characteristics................................................................................................................................. 35
Table 4.4 AC Test Conditions ....................................................................................................................................................... 36
Table 4.5 Ping Capacitance (TA=25C,f=1.0MHz) .......................................................................................................................... 36
Table 4.6 Read/Program/Erase Characteristics ........................................................................................................................... 36
Table 4.7 AC Timing Characteristics ............................................................................................................................................. 37
Table 5.1 Block Failure ................................................................................................................................................................. 41
Rev.03 (Feb 20, 2020) 4
PN: DS35X1GAXXX
Documents title
1Gbit SPI NAND FLASH
Revision History
Revision
No.
0.0
0.1
0.2
0.3
History
Initial Draft
Change voltage definition from 3.0V to 3.3V
Modify catalog page number
Update 1.8V max frequency to 104Mhz
Draft date
Remark
Aug 29, 2018
Dec 7, 2018
Jul 5, 2019
Feb 20，2020
preliminary
Rev.03 (Feb 20, 2020) 5
PN: DS35X1GAXXX
FEATURES
■ Serial Peripheral Interface
－ Mode 0 and Mode 3
■ Standard, Dual, Quad SPI
－ Standard SPI: SCLK, CS#, SI, SO
－ Dual SPI: SCLK, CS#, SIO0, SIO1
－ Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
■ SUPPLY VOLTAGE
－ VCC = 1.8/3.3 Volt core supply voltage for
Program, Erase and Read operations
■ PAGE READ / PROGRAM
－ (2048+64 spare) byte
－ Random access:
25us (w/o ECC), 70us(w/ ECC)
－ Serial access:
104MHz (1.8V /3.3V)
－ Page program time: 300us (Typ)
■ MEMORY CELL ARRAY
－ (2K + 64) bytes x 64 pages x 1024 blocks
■ ELECTRONIC SIGNATURE
－ Manufacturer Code
－ Device Code
■ STATUS REGISTER
■ HARDWARE DATA PROTECTION
－ Enable/Disable protection with WP# Pin
－ Top or Bottom, Block selection combination
■ DATA RETENTION
－ Max cycling: 100K Program / Erase cycles
－ Data retention: 10 Years (4bit/512byte ECC)
－ Internal ECC can be enabled (4bit ECC)
－ Block zero is a valid block and will be valid for at
least 1K program-erase cycles with ECC
■ FAST BLOCK ERASE
－ Block size: (128K + 4K) bytes
－ Block erase time: 2ms (Typ)
Rev.03 (Feb 20, 2020) 6
PN: DS35X1GAXXX
Part Numbering System
DS XX X XXX -X X X
Dosilicon
Memory
Packing Type
R: Tape and Reel
Blank: Tray
Product Family
35: SPI NAND
Organization
Q: 3.3V, Quad SPI x1/x2/x4
M: 1.8V, Quad SPI x1/x2/x4
Device Depth
Package Type
Generation
Temperature
12: 512Mb
1G: 1Gb
2G: 2Gb
4G: 4Gb
A: 1st
B: 2nd
C: 3rd
A: SOP16 300mil
B: WSON 8x6mm
C: Commercial (0°C~70°C)
E: Extended (-25°C~85°C)
I: Industrial (-40°C~85°C)
Rev.03 (Feb 20, 2020) 7
PN: DS35X1GAXXX
1 SUMMARY DESCRIPTION
DS35X1GAXXX is a 128Mx8bit with spare 4Mx8 bit capacity.
The device is offered in 3.3/1.8 Vcc Power Supply, and with SPI interface.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while
old data is erased.
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells. Program operation allows the 2112-byte page writing in typical 300us and an erase operation can be
performed in typical 2 ms on a 128K-byte block.
Data in the page can be read out at 10ns cycle time per word. The on-chip Program/Erase Controller automates
all program and erase functions including pulse repetition, where required, and internal verification and
margining of data.
An internal 4-bit ECC logic is implemented in the chip, which is enabled by default. The internal ECC can be
disabled or enabled again by command. When the internal 4-bit ECC logic is disabled, the host side needs to
handle the 4-bit ECC by host micro controller.
The serial peripheral interface (SPI) provides NAND Flash with a cost-effective non-volatile memory storage
solution in systems where pin count must be kept to a minimum. It is also an alternative to SPI-NOR, offering
superior write performance and cost per bit over SPI-NOR.
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PN: DS35X1GAXXX
1.1 Product List
PART NUMBER
DS35M1GA
DS35Q1GA
ORGANIZATION
X1/X2/X4
X1/X2/X4
VCC RANGE
1.7 – 1.95 Volt
2.7 – 3.6 Volt
PACKAGE
16SOP, 8WSON
16SOP, 8WSON
Vcc
SI/SIO0
CS#
SCLK
SO/SIO1
WP#/SIO2
HOLD#/SIO3
Vss
1.1 Diagram
Figure 1.1 Logic
Name
CS#
SCLK
SI/SIO0
SO/SIO1
WP#/SIO2
HOLD#/SIO3
Vcc
Vss
NC
Function
Chip Select
Clock Input
Serial Data Input (for 1 x I/O) or
Serial Data Input & Output (for 2xI/O or 4xI/O mode)
Serial Data Output (for 1 x I/O) or
Serial Data Input & Output (for 2xI/O or 4xI/O mode)
WP# or
Serial Data Input & Output (for 4xI/O mode)
Hold# or
Serial Data Input & Output (for 4xI/O mode)
Power supply
Ground
No Connection
Table 1.1 Signal Name
Rev.03 (Feb 20, 2020) 9
PN: DS35X1GAXXX
1.2 Pin description
Pin Name
CS#
SCLK
SI/SIO0
SO/SIO1
WP#/SIO2
HOLD#/SIO3
VCC
VSS
NC / DNU
Description
Chip select
Places the device in active power mode when driven LOW. Deselects the device and places
SO at High-Z when HIGH
Serial clock
Provides serial interface timing. Latches commands, addresses, and data on SI on the rising
edge of SCLK. Triggers output on SO after the falling edge of SCLK.
Serial data input
Transfers data serially into the device. Device latches commands, addresses, and program
data on SI on the rising edge of SCLK. SI must not be driven by the host during x2 or x4 read
operations.
Serial data output
Transfers data serially out of the device on the falling edge of SCLK.
Write protect
When LOW, prevents overwriting block-lock bits if the block register write disable (BRWD) bit
is set.
WP# must not be driven by the host during x4 read operations.
Hold
Pauses any serial communication with the device without deselecting it. When driven LOW,
SO is at High-Z, and all inputs at SI and SCLK are ignored. Requires that CS# also be driven
LOW.
HOLD# must not be driven by the host during x4 read operations.
Supply Voltage
The VCC supplies the power for all the operations (Read, Write, Erase).
Ground
No Connection / Don’t Use
Table 1.2 Pin Description
Rev.03 (Feb 20, 2020) 10
PN: DS35X1GAXXX
1.3 Functional block diagram
SCLK
CS#
SI/
SO/
WP#/
HOLD#/
SIO0
SIO1
SIO2
SIO3
Serial NAND Controller
Cache
Vcc
Memory
Vss
NAND
Memory
Core
ECC and Status
Registers
Figure 1.2 Block Description
1.4 Address Map
Figure 1.3 Address Map
Rev.03 (Feb 20, 2020) 11
PN: DS35X1GAXXX
1.5 Command Set
Command
Code
Address
Bytes
Dummy
Bytes
Data
Bytes
GET FEATURE
SET FEATURE
WRITE ENABLE
WRITE DISABLE
PAGE READ
READ FROM CACHE
READ FROM CACHE x2
0Fh
1Fh
06h
04h
13h
03h, 0Bh
3Bh
1
1
0
0
3
2
2
0
0
0
0
0
1
1
1
1
0
0
0
1 to 2112
1 to 2112
READ FROM CACHE x4
6Bh
2
1
1 to 2112
PROGRAM LOAD
02h
2
0
1 to 2112
PROGRAM LOAD x4
32h
2
0
1 to 2112
PROGRAM LOAD RANDOM DATA
84h
2
0
1 to 2112
PROGRAM LOAD RANDOM DATA x4
34h
2
0
1 to 2112
PROGRAM EXECUTE
10h
3
0
0
BLOCK ERASE
READ ID
RESET
D8h
9Fh
FFh
3
0
0
0
1
0
0
2
0
FUNCTION
Comments
Get features
Set features
Array read
Output cache data on SO
Output cache data on SI and SO
Output cache data on SI, SO,
WP#,HOLD#
Load program data with cache
reset
Load program data on SI, SO,
WP#,HOLD# with cache reset
Load program data without
cache reset
Load program data on SI, SO,
WP#,HOLD# without cache
reset
Enter block/page address, no
data, execute
Block erase
Read device ID
Reset the device
Table 1.3 Command Set
Rev.03 (Feb 20, 2020) 12
PN: DS35X1GAXXX
2 BUS OPERATION
2.1 SPI Mode
Two SPI modes are supported.
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCLK, and output data is available from the falling edge of SCLK for
both modes.
When the bus master is in standby mode:
• SCLK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
• SCLK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)
Refer to Figure 2.1
Figure 2.1 SPI Modes Timing
2.2 CS#
Chip select (CS#) activates or deactivates the device. When CS goes LOW, the device is placed in active mode.
When CS is HIGH, the device is placed in inactive mode and SO is High-Z.
2.3 SI/SIO0
Writes use serial data in (SI). Data, commands, and addresses are transferred on SI in x1 mode at the rising edge
of SCLK. SI must not be driven by the host during x2 or x4 read operations.
SIO0 operation is enabled by issuing a READ FROM CACHE x2 or x4 command with data being clocked out of the
device at the falling edge of SCLK. During this time the host must wait until the READ FROM CACHE x2 or x4
command is complete before driving SI.
2.4 SO/SIO1
Reads use serial data out (SO). Device reads are performed in x1, or x2, or x4 modes. SO acts as the only output in
x1 READ operations, and as SIO1 in x2 and x4 read operations.
Data is clocked out of the device on SO at the falling edge of SCLK control signals.
2.5 WP#/SIO2
Write protect (WP#) prevents the block lock bits (BP0, BP1, and BP2) from being overwritten.
Rev.03 (Feb 20, 2020) 13
PN: DS35X1GAXXX
If the BRWD bit is set to 1 and WP# is LOW, the block protect bits cannot be altered. WP# must not be driven by
the host during READ FROM CACHE x4 operations.
SIO2 operation is enabled by issuing a READ FROM CACHE x4 command with data being clocked out of the device
at the falling edge of SCLK. During this time the host must wait until the READ FROM CACHE x4 command is
complete before driving WP#.
2.6 HOLD#/SIO3
HOLD# input provides a method to pause serial communication with the device but does not terminate any ERASE,
READ, or WRITE operation currently in progress.
Hold mode starts at the falling edge of HOLD# provided SCLK is also LOW. If SCLK is HIGH when HOLD# goes LOW,
hold mode begins after the next falling edge of SCLK. Similarly, hold mode is exited at the rising edge of HOLD#
provided SCLK is also LOW. If SCLK is HIGH, hold mode ends after the next falling edge of SCLK.
During hold mode, SO is High-Z, and SI and SCLK inputs are ignored.
SIO3 operation is enabled by issuing a READ FROM CACHE x4 command with data being clocked out of the device
at the falling edge of SCLK. During this time the host must wait until the READ FROM CACHE x4 command is
complete before driving HOLD#.
Rev.03 (Feb 20, 2020) 14
PN: DS35X1GAXXX
3 DEVICE OPERATION
3.1 Write Operations
The WRITE ENABLE (06h) command sets the WEL bit in the status register to 1. WRITE ENABLE is required in the
following operations that change the contents of the memory array:
• Page program
• OTP program
• BLOCK ERASE
Refer to Figure 3.1
Figure 3.1 Write Enable
The WRITE DISABLE (04h) command clears the WEL bit in the status register to 0. This disables the following
operations:
• Page program
• OTP program
• BLOCK ERASE
Refer to Figure 3.2
Figure 3.2 Write Disable
3.2 Feature Operations
The GET FEATURES (0Fh) and SET FEATURES (1Fh) commands are used to alter the device behavior from the
default power-on behavior. These commands use a 1-byte feature address to determine which feature is to be
Rev.03 (Feb 20, 2020) 15
PN: DS35X1GAXXX
read or modified. Features such as OTP and block locking can be enabled or disabled by setting specific bits in
feature address A0h and B0h (shown in the following table). The status register is mostly read, except WEL, which
is a writable bit with the WRITE ENABLE (06h) command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless
specified in the following table, once the device is set, it remains set, even if a RESET (FFh) command is issued.
Refer to Figure 3.3, 3.4.
Figure 3.3 Get Features(0Fh)
Figure 3.4 Set Features(1Fh)
Register
Address
Block lock
Data Bits
7
6
5
4
3
2
1
0
A0h
BRWD
Reserved
BP2
BP1
BP0
INV
CMP
Reserved
OTP
B0h
OTP_PRT
OTP_EN
Reserved
Reserved
Reserved
Reserved
QE
Status
Driver
Strength
C0h
Reserved
Reserved
ECC_S1
P_Fail
E_Fail
WEL
OIP
Reserved
Reserved
D0h
Reserved
DS_IO1
DS_IO0
ECC
Enable
ECC_S0
Reserved
Reserved
Reserved
Table 3.1 Status Register Coding
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3.3 Read Operations
The device supports "Power-on Read" function, after power up, the device will automatically load the data of the
1st page of 1st block from array to cache. The host micro-controller may directly read the 1st page of 1st block
data from the cache buffer. The data is also under the internal ECC protection.
The PAGE READ (13h) command transfers the data from the NAND Flash array to the cache register. The
command sequence is follows:
• 13h (PAGE READ to cache)
• 0Fh (GET FEATURES command to read the status)
• 0Bh / 03h / 3Bh / 6Bh (Random data read)
The PAGE READ command requires a 24-bit address consisting of 8 dummy bits followed by a 16-bit block/page
address. After the block/page addresses are registered, the device starts the transfer from the main array to the
cache register, and is busy for tR time. During this time, the GET FEATURE (0Fh) command can be issued to
monitor the status of the operation. Following a status of successful completion, the RANDOM DATA READ (03h
or 0Bh) command must be issued in order to read the data out of the cache. The RANDOM DATA READ command
requires 3 dummy bits, followed by a 12-bit column address for the starting byte address. The starting byte
address can be 0 to 2111. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache
x4 command
Refer to Figure 3.5, 3.6, 3.7, 3.8.
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Figure 3.5 Page Read (13h)
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Figure 3.6 Random Data Read (03h or 0Bh)
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Figure 3.7 Read From Cache x2
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Figure 3.8 Read From Cache x4
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command
3.4 Read ID
The READ ID command is used to read the 2 bytes of identifier code programmed into the NAND Flash device. The
READ ID command reads a 2-byte table (as below) that includes the Manufacturer ID and the device configuration.
Refer to Figure 3.9.
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Figure 3.9 Read ID (9Fh)
DENSITY
VCC
1Gbit
3.3V
1.8V
st
1
Manufactory ID
E5h
E5h
nd
2
Device ID
71h
21h
Table 3.2 Read ID for Supported Configurations
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3.5 Parameter Page
The following command flow must be issued by the memory controller to access the parameter page
1. Issue a SET FEATURES (1Fh) command with a feature address of B0h and data value of 40h (OTP enable, ECC
disable).
2. Issue a PAGE READ (13h) command with a block/page address of 0x01h, and then check the status of the read
completion using the GET FEATURES (0Fh) command with a feature address of C0h.
3. Issue a READ FROM CACHE (03h) command with an address of 0x00h to read the data out of the NAND device
(refer to the following Parameter Page Data Structure table for a description of the contents of the parameter
page).
4. To exit reading the parameter page, issue a SET FEATURES (1Fh) command with a feature address of B0h and
data value of 10h (main array READ, ECC enable).
Byte
0-3
4-5
6-7
8-9
10-31
32-43
Description
Parameter page signature
Revision number
Features supported
Optional commands supported
Reserved (0)
Device manufacturer (12 ASCII characters)
44-63
Device model (20 ASCII characters)
64
65-66
67-79
80-83
84-85
86-89
90-91
92-95
96-99
100
101
102
103-104
105-106
107
108-109
110
111
112
113
114
115-127
128
129-130
JEDEC manufacturer ID
Date code
Reserved (0)
Number of data bytes per page
Number of spare bytes per page
Number of data bytes per partial page
Number of spare bytes per partial page
Number of pages per block
Number of blocks per logical unit (LUN)
Number of logical units (LUNs)
Number of address cycles (N/A)
Number of bits per cell
Bad blocks maximum per LUN
Block endurance
Guaranteed valid blocks at beginning of target
Block endurance for guaranteed valid blocks
Number of programs per page
Partial programming attributes
Number of bits ECC correctability
Number of interleaved address bits
Interleaved operation attributes
Reserved (0)
I/O pin capacitance
Timing mode support
Value
4Fh, 4Eh, 46h, 49h
00h, 00h
00h, 00h
06h, 00h
All 00h
44h, 4Fh, 53h, 49h, 4Ch, 49h, 43h, 4Fh,
4Eh, 20h, 20h, 20h
3.3V: 44h, 53h, 33h, 35h, 51h, 31h, 47h,
41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
1.8V: 44h, 53h, 33h, 35h, 4Dh, 31h, 47h,
41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
E5h
00h, 00h
All 00h
00h, 08h, 00h, 00h
40h, 00h
00h, 02h, 00h, 00h
10h, 00h
40h, 00h, 00h, 00h
00h, 04h, 00h, 00h
01h
00h
01h
14h, 00h
01h, 05h
01h
01h, 03h
04h
00h
00h
00h
00h
All 00h
0Ah
00h, 00h
Rev.03 (Feb 20, 2020) 23
PN: DS35X1GAXXX
Byte
131-132
133-134
135-136
137-138
139-163
164-165
166-253
254-255
Description
Program cache timing mode support
tPROG Maximum page program time (µs)
tBERS Maximum block erase time (µs)
tR Maximum page read time (µs)
Reserved (0)
Vendor specific Revision number
Vendor specific
Integrity CRC
256-511
512-767
768+
Value of bytes 0-255
Value of bytes 0-255
Additional redundant parameter pages
Value
00h, 00h
BCh, 02h
10h, 27h
3.3V: 46h, 00h
All 00h
00h, 00h
All 00h
3.3V: 8Eh, 56h
1.8V: E4h, 84h
FFh
Table 3.3 Parameter Page Data
3.6 Unique ID Page
The following command flow must be issued by the memory controller to access the uniqueID
1. Issue a SET FEATURES (1Fh) command with a feature address of B0h and data value of 40h (OTP enable, ECC
disable).
2. Issue a PAGE READ (13h) command with a block/page address of 0x00h, and then check the status of the read
completion using the GET FEATURES (0Fh) command with a feature address of C0h.
3. Issue a READ FROM CACHE (03h) command with an address of 0x00h to read the data out of the NAND device.
(The contents of the uniqueID page are described in the following note.)
Note: The device stores 16 copies of the unique ID data. Each copy is 32 bytes; the first 16 bytes are unique data,
and the second 16 bytes are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the
second 16 bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. If a non-FFh result
is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data.
4. To exit reading the uniqueID page, issue a SET FEATURES (1Fh) command with a feature address of B0h and
data value of 10h (main array READ, ECC enable).
3.7 Program Operations
The PAGE PROGRAM operation sequence programs 1 byte to 2112 bytes of data within a page. The page program
sequence is as follows:
• 06h (WRITE ENABLE)
• 02h (PROGRAM LOAD) or 32h (PROGRAM LOAD x4)
• 10h (PROGRAM EXECUTE)
• 0Fh (GET FEATURE command to read the status)
Prior to performing the PROGRAM LOAD operation, a WRITE ENABLE (06h) command must be issued. As with any
command that changes the memory contents, the WRITE ENABLE must be executed in order to set the WEL bit. If
this command is not issued, then the rest of the program sequence is ignored. WRITE ENABLE must be followed
by a PROGRAM LOAD (02h or 32h) command. PROGRAM LOAD consists of an 8-bit Op code, followed by 3~4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The data bytes are loaded into
a cache register that is 2112 bytes long. Only four partial-page programs are allowed on a single page. If more
than 2112 bytes are loaded, then those additional bytes are ignored by the cache register. The command
sequence ends when CS goes from LOW to HIGH. Figure 3.10, 3.11 shows the PROGRAM LOAD operation.
After the data is loaded, a PROGRAM EXECUTE (10h) command must be issued to initiate the transfer of data
from the cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit
Rev.03 (Feb 20, 2020) 24
PN: DS35X1GAXXX
address (8 dummy bits and a 16-bit page/block address). After the page/block address is registered, the memory
device starts the transfer from the cache register to the main array, and is busy for tPROG time.
This operation is shown in Figure 3.12. During this busy time, the status register can be polled to monitor the
status of the operation (refer to the Status Register section). When the operation completes successfully, the next
series of data can be loaded with the PROGRAM LOAD command.
Refer to Figure 3.10, 3.11, 3.12
Figure 3.10 Program Load (02h)
Rev.03 (Feb 20, 2020) 25
PN: DS35X1GAXXX
Figure 3.11 Program Load x4 (32h)
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the program load x4 command.
Rev.03 (Feb 20, 2020) 26
PN: DS35X1GAXXX
Figure 3.12 Program Excute (10h)
Rev.03 (Feb 20, 2020) 27
PN: DS35X1GAXXX
The RANDOM DATA PROGRAM sequence programs or replaces data in a page with existing data. The random
data program sequence is as follows:
• 06h (WRITE ENABLE)
• 84h (PROGRAM LOAD RANDOM DATA) or 34h (PROGRAM LOAD RANDOM DATA x4)
• 10h (PROGRAM EXECUTE)
• 0Fh (GET FEATURE command to read the status)
Prior to performing a PROGRAM LOAD RANDOM DATA operation, a WRITE ENABLE (06h) command must be
issued to change the contents of the memory array. Following a WRITE ENABLE (06) command, a PROGRAM LOAD
RANDOM DATA (84h) command must be issued. This command consists of an 8-bit Op code, followed by 3~4
dummy bits and a 12-bit column address. New data is loaded in the column address provided with the 12 bits. If
the random data is not sequential, then another PROGRAM LOAD RANDOM DATA (84h) command must be issued
with a new column address. After the data is loaded, a PROGRAM EXECUTE (10h) command can be issued to start
the programming operation.
Refer to Figure 3.13, 3.14, 3.12
Figure 3.13 Program Load Random Data (84h)
Rev.03 (Feb 20, 2020) 28
PN: DS35X1GAXXX
Figure 3.14 Program Load Random Data x4 (34h)
The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The
INTERNAL DATA MOVE command sequence is as follows:
• 13h (PAGE READ to cache)
• 06h (WRITE ENABLE)
• 84h (PROGRAM LOAD RANDOM DATA) or 34h (PROGRAM LOAD RANDOM DATA x4)
• 10h (PROGRAM EXECUTE)
• 0Fh (GET FEATURE command to read the status)
Prior to performing an internal data move operation, the target page content must be read into the cache register.
This is done by issuing a PAGE READ (13h) command. The PAGE READ command must be followed with a WRITE
ENABLE (06h) command in order to change the contents of memory array. After the WRITE ENABLE command is
issued, the PROGRAM LOAD RANDOM DATA (84h) command can be issued.
This command consists of an 8-bit Op code, followed by 3 dummy bits, a 12-bit column address. New data is
loaded in the 12-bit column address. If the random data is not sequential, another PROGRAM LOAD RANDOM
DATA (84h) command must be issued with the new column address. After the data is loaded, a PROGRAM
EXECUTE (10h) command can be issued to start the programming operation.
Refer to Figure 3.13, 3.14, 3.12.
Rev.03 (Feb 20, 2020) 29
PN: DS35X1GAXXX
3.8 BLOCK ERASE
The BLOCK ERASE (D8h) command is used to erase at the block level. The blocks are organized as 64 pages per
block, 2112 bytes per page (2048 + 64 bytes). Each block is 132 Kbytes. The BLOCK ERASE command (D8h)
operates on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:
• 06h (WRITE ENBALE command)
• D8h (BLOCK ERASE command)
• 0Fh (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06h) command must be issued. As with any
command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the
WEL bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE
ENABLE command must be followed by a BLOCK ERASE (D8h) command. This command requires a 24-bit address
consisting of 8 dummy bits followed by an 16-bit row address.
After the row address is registered, the control logic automatically controls timing and erase-verify operations.
The device is busy for tBERS time during the BLOCK ERASE operation.
The GET FEATURES (0Fh) command can be used to monitor the status of the operation.
Refer to Figure 19.
Figure 3.15 Block Erase
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PN: DS35X1GAXXX
3.9 Block Lock Feature
The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM
and ERASE operations. After power-up, the device is in the “locked” state, i.e., bits 1, 2, 3, 4, and 5 of the block
lock register are set to 1. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be
issued with the A0h feature address, including the data bits shown in Table 3.4. When BRWD is set and WP is
LOW, none of the writable bits (1, 2, 3, 4, 5, and 7) in the block lock register can be set.
When an ERASE command is issued to a locked block, the erase failure, 04h, is returned. When a PROGRAM
command is issued to a locked block, program failure, 08h, is returned.
BP2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
BP1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
BP0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Invert
x
0
0
0
0
0
0
x
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Complementary
x
0
0
0
0
0
0
x
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Protection
all unlocked
upper 1/64 locked
upper 1/32 locked
upper 1/16 locked
upper 1/8 locked
upper 1/4 locked
upper 1/2 locked
all locked (default)
lower 1/64 locked
lower 1/32 locked
lower 1/16 locked
lower 1/8 locked
lower 1/4 locked
lower 1/2 locked
lower 63/64 locked
lower 31/32 locked
lower 15/16 locked
lower 7/8 locked
lower 3/4 locked
Block0
upper 63/64 locked
upper 31/32 locked
upper 15/16 locked
upper 7/8 locked
upper 3/4 locked
Block0
Table 3.4 Definition of Protectiong Bits
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PN: DS35X1GAXXX
3.10 OTP Feature
The serial device offers a protected, one-time programmable NAND Flash memory area. 30 full pages (2112 bytes
per page) are available on the device, and the entire range is guaranteed to be good. Customers can use the OTP
area any way they want; typical uses include programming serial numbers, or other data, for permanent storage.
To access the OTP feature, the user must issue the SET FEATURES command, followed by feature address B0h.
When the OTP is ready for access, pages 02h–1Fh can be programmed in sequential order. The PROGRAM LOAD
(02h) and PROGRAM EXECUTE (10h) commands can be used to program the pages. Also, the PAGE READ (13h)
command can be used to read the OTP area. The data bits used in feature address B0h to enable OTP access are
shown in the table below.
To access OTP, perform the following command sequence:
• Issue the SET FEATURES register write (1Fh)
• Issue the OTP feature address (B0h)
• Issue the PAGE PROGRAM or PAGE READ command
It is important to note that after bits 6 and 7 of the OTP register are set by the user, the OTP area becomes readonly and no further programming is supported. For OTP states, refer to the following table.
OTP Protection Bit
0
0
1
1
OTP Enabled Bit
0
1
0
1
State
Normal operation
Access the Secure OTP
Not applicable
OTP Protection by using the Program Execution command (10h)
Table 3.5 OTP States
Rev.03 (Feb 20, 2020) 32
PN: DS35X1GAXXX
3.11 Status Register
The NAND Flash device has an 8-bit status register that software can read during the device operation. The status
register will output the status of the operation. The description of data bits from status register are shown in the
following table.
SR Bit
SR[0]
(OIP)
Bit Name
Operation in
progress
SR[1]
(WEL)
Write enable
latch
SR[2]
(ERS_Fail)
Erase fail
SR[3]
(PGM_Fail)
Program fail
SR[5:4]
(ECC_S1,
ECC_S0)
ECC Status
SR[6:7]
Reserved
Description
The bit value indicates whether the device is busy in operations of
read/program execute/ erase/ reset command.
1: Busy, 0: Ready
The bit value indicates whether the device is set to internal write
enable latch.
When WEL bit sets to 1, which means the internal write enable latch is
set, and then the device can accept program/ erase command.
1: write enable, 0: not write enable
The bit value will be cleared (as "0") by issuing Write Disable
command(04h).
The bit value shows the status of erase failure or if host erase any
invalid address or protected area (including protected blocks or
protected Secure OTP area).
0: Passed, 1: Failed
The bit value will be cleared (as "0") by RESET command or at the
beginning of the block erase command operation.
The bit value shows the status of program failure or if host program
any invalid address or protected area (including protected blocks or
protected Secure OTP area).
0: Passed, 1: Failed
The bit value will be cleared (as "0") by RESET command or during the
program execute command operation.
The bit shows the status of ECC as below:
00b = 0 bit error
01b = 1 ~ 4 bits error and been corrected.
10b = More than 4-bit error and not corrected.
11b = Reserved
The value of ECC_Sx (S1:S0) bits will be clear as "00b" by Reset
command or at the start of the Read operation. After a valid Read
operation completion, the bit will be updated to reflect the ECC status
of the current valid Read operation.
The ECC_Sx (S1:S0) value reflects the ECC status of the content of the
page 0 of block 0 after a power-on reset.
If the internal ECC is disabled by the Set feature command, the ECC_
Sx(S1:S0) are invalid.
Table 3.6 Status Register Bit Descriptions
Rev.03 (Feb 20, 2020) 33
PN: DS35X1GAXXX
3.12 ECC Protection
The serial device offers data corruption protection by offering 4-bit internal ECC.
READs and PROGRAMs with internal ECC can be enabled or disabled by setting the ECC bit in the OTP register.
ECC is enabled after device power up, so the default READ and PROGRAM commands operate with internal ECC in
the “active” state.
To enable/disable ECC, perform the following command sequence:
• Issue the SET FEATURES register write (1Fh).
• Issue the OTP feature address (B0h).
• Then:
– To enable ECC Set Bit 4, ECC Enable, to 1.
– To disable ECC Clear Bit 4, ECC Enable, to 0.
During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the
page is written to the NAND Flash array. The ECC code is stored in the spare area of the page.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is
calculated and compared with the ECC code value read from the array. If a 1- to 4-bit error is detected, the error
is corrected in the cache register. Only corrected data is output on the I/O bus. The ECC status bit indicates if the
error correction was successful. The ECC Protection table below shows the ECC protection
scheme used throughout a page.
With internal ECC, the user must accommodate the following:
• The ECC protection coverage: please refer to Table 3.7. The Distribution of ECC Segment and Spare Area. Only
the grey areas are under internal ECC protection when the internal ECC is enabled.
• The number of partial-page program is not 4 in an ECC segment, the user need to program the main area
(512B)+Metadata1(4B) at one program time, so the ECC parity code can be calculated properly and stored in
the additional hidden spare area.
Area
Addr.
(Start)
Addr.
(End)
Size
Area
Addr.
(Start)
Addr.
(End)
Size
Main
Area
(0)
000h
Main
Area
(1)
200h
Main
Area
(2)
400h
Main
Area
(3)
600h
Spare(0)
Spare(1)
800h
M2
802h
M1
804h
R1
808h
810h
1FFh
3FFh
5FFh
7FFh
801h
803h
807h
80Fh
512(B)
512(B)
512(B)
512(B)
2(B)
2(B)
4(B)
8(B)
Main
Area
(0)
Main
Area
(1)
Main
Area
(2)
Main
Area
(3)
000h
200h
400h
1FFh
3FFh
512(B)
512(B)
M2
812h
M1
814h
R1
818h
811h
813h
817h
81Fh
2(B)
2(B)
4(B)
8(B)
Spare(2)
Spare(3)
600h
M2
820h 822h
M1
824h
R1
828h
830h
5FFh
7FFh
821h
823h
827h
82Fh
512(B)
512(B)
2(B)
2(B)
4(B)
8(B)
M2
832h
M1
834h
R1
838h
831h
833h
837h
83Fh
2(B)
2(B)
4(B)
8(B)
Table 3.7 The Distribution of ECC Segment and Spare Area
R1: Reserved
M2: Metadata 2
M1: Metadata 1
Grey area: Under ECC protection
Rev.03 (Feb 20, 2020) 34
PN: DS35X1GAXXX
4 Device Parameters
Parameter
Valid Block Number
Symbol
Min
NVB
1004
Typ
Max
Unit
1024
Blocks
Table 4.1 Valid Blocks Number
The First block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime.
Symbol
TA
TBIAS
TSTG
VIO
VCC
Parameter
1.8V
Value
Unit
3.3V
Ambient Operating Temperature (Temperature Range Option 1)
0 to 70
0 to 70
°C
Ambient Operating Temperature (Temperature Range Option 6)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
–40 to 85
–50 to 125
–65 to 150
–0.6 to 2.7
–0.6 to 2.7
–40 to 85
–50 to 125
–65 to 150
–0.6 to 4.6
–0.6 to 4.6
°C
°C
°C
V
V
Table 4.2 Absolute Maximum Ratings
.
Min
1.8Volt
Typ
Max
Min
-
10
20
-
15
30
mA
-
10
10
20
20
-
15
15
30
30
mA
mA
-
-
1
1
mA
-
10
50
10
50
uA
ILI
CE#=VIH,
WP#=0V/VCC
CE#=VCC-0.2,
WP#=0/VCC
VIN=0 to Vc (max)
-
-
±10
-
±10
uA
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
-
-
±10
-
±10
uA
Input High Voltage
VIH
-
-
VCC
+0.3
0.8x
VCC
-
VCC
+0.3
V
Input Low Voltage
VIL
-
-0.3
-
-0.3
-
Output High Voltage
Level
VOH
IOH = -100uA
VCC0.1
0.2x
VCC
-
-
-
-
0.1
3
4
-
Parameter
Symbol
Test Conditions
Sequential
Read
ICC1
tRC = 50ns, CE#=VIL,
IOUT=0mA
Program
Erase
ICC2
ICC3
Stand-by Current (TTL)
ICC4
Operating
Current
Stand-By Current
(CMOS)
Input Leakage Current
Output Low Voltage
Level
Output Low Current
(RB#)
ICC5
VOL
IOL (RB#)
IOH = -400uA
IOL = 100uA
IOL = 2.1mA
VOL=0.1V
VOL=0.4V
0.8xV
CC
3.3Volt
Typ
Max
0.2xV
CC
Unit
V
V
2.4
-
-
-
-
0.4
8
10
-
V
V
V
mA
mA
Table 4.3 DC and Operating Characteristics
Rev.03 (Feb 20, 2020) 35
PN: DS35X1GAXXX
Parameter
1.8Volt
0V to VCC
5ns
VCC / 2
1 TTL GATE and
CL=30pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (1.7V – 1.95V & 2.5V - 3.6V)
Value
3.3Volt
0V to VCC
5ns
VCC / 2
1 TTL GATE and CL=30pF
Table 4.4 AC Test Conditions
Item
Input / Output Capacitance (1)
Input Capacitance (1)
Symbol
CI/O
CIN
Test Condition
VIL = 0V
VIN = 0V
Min
-
Max
10
10
Unit
pF
pF
Table 4.5 Ping Capacitance (TA=25C,f=1.0MHz)
Parameter
Symbol
Read Time
Read Time with internal ECC enabled
Program Time
Program Time with internal ECC enabled
Number of partial Program
Main +
Cycles in the same page
Spare Array
Block Erase Time
tR
tR_ECC
tPROG
tPROG_ECC
Min
1.8Volt 3.3Volt
60
60
-
Typ
1.8Volt 3.3Volt
300
300
320
320
Max
1.8Volt 3.3Volt
25
25
70
70
700
700
700
700
Unit
us
us
us
us
NOP
-
-
-
-
4
4
Cycle
tBERS
-
-
2.0
2.0
10
10
ms
Table 4.6 Read/Program/Erase Characteristics
Rev.03 (Feb 20, 2020) 36
PN: DS35X1GAXXX
Parameter
Symbol
Clock Frequency
Clock HIGH time
Clock LOW time
Command deselect time
Chip select# hold time
Chip select# setup time
Chip select# non-active setup time
Chip select# non-active hold time
Output disable time
Hold# non-active setup time relative
to SCLK
Hold# setup time relative to SCLK
Data input hold time
Output hold time
Hold to output High-Z
Hold to output low-Z
Data input setup time
Clock LOW to output Valid
WP# hold time
WP# setup time
HOLD# high hold time relative to
SCLK
HOLD# low hold time relative to SCLK
fC
tWH
tWL
tCS
tCHSH
tSLCH
tSHCH
tCHSL
tDIS
Device Resetting Time
(Read/Program/Erase)
1.8/3.3 Volt
Min
Max
104
4
4
100
5
5
5
5
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
tHC
5
ns
tHD
tHDDAT
tHO
tHZ
tLZ
tSUDAT
tV
tWPH
tWPS
5
3.5
1
100
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHHH
5
ns
tCHHL
5
ns
3.5
tRST
15
15
8
5/10/
500
(1)
us
Table 4.7 AC Timing Characteristics
NOTE:
(1) If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
Rev.03 (Feb 20, 2020) 37
PN: DS35X1GAXXX
Figure 4.1 Serial Input Timing
Figure 4.2 Serial Output Timing
Figure 4.3 Hold Timing
Rev.03 (Feb 20, 2020) 38
PN: DS35X1GAXXX
Figure 4.4 WP# Setup/Hold Timing When BPRWD=1
VTH
5ms
Figure 4.5 Power on Sequence
Note : VTH = 1.5 Volt for 1.8 Volt Supply devices; 2.5 Volt for 3.3 Volt Supply devices
5 Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all
the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit
line and common source line by a select transistor. The devices are supplied with all the locations inside valid
blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the
spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block
Information must be read before any erase is attempted as the Bad Block Information may be erased. For the
system to be able to recognize the Bad Blocks based on the original information it is recommended to create a
Bad Block table following the flowchart
Rev.03 (Feb 20, 2020) 39
PN: DS35X1GAXXX
Figure 5.1 Bad Block Management Flowchart
Rev.03 (Feb 20, 2020) 40
PN: DS35X1GAXXX
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by
copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase
them will give errors in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, the block can
be replaced by re-programming the current data and copying the rest of the replaced block to an available valid
block.
Write
Read
Failure Mode
Erase Failure
Program Failure
Read Failure
Sequence
Block Replacement
Block Replacement
ECC
Table 5.1 Block Failure
Block Replacement flow is as below
1.When an error happens in the nth page of the Block ’A’ during erase or program operation.
2.Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
3.Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
4.Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.
Figure 5.2 Bad Block Replacement
.
Rev.03 (Feb 20, 2020) 41
PN: DS35X1GAXXX
6 Supported Packages
6.1 PIN CONFIGURATION
Figure 6.1 Pin Configuration
Rev.03 (Feb 20, 2020) 42
PN: DS35X1GAXXX
6.2 PACKAGE DIMENSIONS
WSON(8*6mm)
Figure 6.2 WSON (8*6mm)
Rev.03 (Feb 20, 2020) 43
PN: DS35X1GAXXX
SOP16
Figure 6.3 SOP16
Rev.03 (Feb 20, 2020) 44
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