A3T4GF40BBF-HP

A3T4GF30BBF/A3T4GF40BBF 4Gb DDR3 Specification Specifications Features • • • • • • • • • • • • • • • • • • Density: 4G bits Organization o 8 banks x 64M words x 8 bits o 8 banks x 32M words x 16 bits Package o 78-ball FBGA o 96-ball FBGA Power supply: o VDD, VDDQ =1.5V (1.425 to 1.575V) Data Rate: 1600Mbps/1866Mbps/2133Mbps (max.) 1KB page size (x8) o Row address: AX0 to AX15 o Column address: AY0 to AY9 2KB page size (x16) o Row address: AX0 to AX14 o Column address: AY0 to AY9 Eight internal banks for concurrent operation Burst lengths(BL): 8 and 4 with Burst Chop(BC) Burst type(BT) o Sequential (8, 4 with BC) o Interleave (8, 4 with BC) CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 12, 13 CAS Write Latency (CWL): 5, 6, 7, 8, 9 Precharge: auto precharge option for each burst access Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω) Refresh: auto-refresh, self-refresh Average refresh period o 7.8us at TC ≤ +85℃ o 3.9us at TC > +85℃ Operating temperature range o TC = 0°C to +95°C (Commercial grade)* o TC = -40°C to +95°C (Industrial grade)* o TC = -40°C to +105°C (Automotive grade)* • • • • • • • • • • • • • • • • • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture Double data-rate architecture: two data transfers per clock cycle Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver DQS is edge-aligned with data for READs; center aligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Data mask (DM) for write data Posted CAS by programmable additive latency for better command and data bus efficiency On-Die Termination (ODT) for better signal quality o Synchronous ODT o Dynamic ODT o Asynchronous ODT Multi Purpose Register (MPR) for pre-defined pattern read out ZQ calibration for DQ drive and ODT Programmable Partial Array Self-Refresh (PASR) RESET pin for Power-up sequence and reset function SRT(Self Refresh Temperature) range: o Normal/Extended/ASR Programmable output driver impedance control JEDEC compliant DDR3 RH-Free(Row Hammer Free) is available Note: Refer to operating temperature condition on page 7 for details Key Timing Parameters Speed Grade Data Rate(Mbps) CL tRCD tRP -JR 2133 14 14 14 -HP 1866 13 13 13 -GM 1600 11 11 11 -DK 1333 9 9 9 A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 1 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF Differences from JEDEC: A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 2 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF Table of Contents 4Gb DDR3 Specification (Preliminary) ....................................................................................................................1 1. Ordering Information ...................................................................................................................................4 2. Package Ball Assignment .............................................................................................................................5 3. Package outline drawing ..............................................................................................................................6 4. Electrical Specifications ...............................................................................................................................8 5. Block Diagram ............................................................................................................................................24 6. Pin Function ...............................................................................................................................................25 7. Command Operation .................................................................................................................................27 8. Functional Description ...............................................................................................................................31 A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 3 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 1. Ordering Information Part Number Organization (words x bits) Internal Banks 512M × 8 8 A3T4GF30BBF-JR/-JRI/-JRA A3T4GF30BBF-HP/-HPI/-HPA A3T4GF30BBF-GM/-GMI/-GMA Speed bin (CL-tRCD-tRP) DDR3-2133 (14-14-14) DDR3-1866 (13-13-13) DDR3-1600 (11-11-11) A3T4GF30BBF-DK/-DKI/-DKA DDR3-1333 (9-9-9) A3T4GF40BBF-JR/-JRI/-JRA DDR3-2133 (14-14-14) A3T4GF40BBF-HP/-HPI/-HPA 256M × 16 A3T4GF40BBF-GM/-GMI/-GMA DDR3-1866 (13-13-13) 8 DDR3-1600 (11-11-11) A3T4GF40BBF-DK/-DKI/-DKA A 3 T AP Memory 78-ball FBGA 96-ball FBGA DDR3-1333 (9-9-9) 4G 2G Interface T: SSTL_15 3: DRAM Package F 4 3 0B BF Die version 0C: Ver. 0C 0B: Ver. Package 4: 0B type x16 BF: FBGA 3: x8 Density: 2G: 2Gb F: DDR3 4G: 4Gb A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 HP I Option Blank : Commercial grade : Industrial grade I : Automotive grade A Speed JR – DDR3-2133 HP– DDR3-1866 GM–DDR3-1600 DK– DDR3-1333 4 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 2. Package Ball Assignment 78-ball, FBGA (x8 organizations) • 96 ball, FBGA (x16 organizations) 1 2 3 7 8 9 VSS VDD NC NU(/TDQS) VSS VDD VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ D • • • • • • • VSSQ DQ6 /DQS VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS /RAS CK VSS NC ODT VDD /CAS /CK VDD CKE NC /CS /WE A10(AP) ZQ NC DQ12 VDDQ VSS VSSQ VDD VSS /DQSU DQ14 VSSQ VDDQ DQ11 DQ9 DQSU DQ10 VDDQ VSSQ VDDQ DMU DQ8 VSSQ VDD VSS VSSQ DQ0 DML VSSQ VDDQ VDDQ DQ2 DQSL DQ1 DQ3 VSSQ VSSQ DQ6 /DQSL VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS /RAS CK VSS NC ODT VDD /CAS /CK VDD CKE NC /CS /WE A10(AP) ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12(/BC) BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS /RESET A13 A14 A8 VSS J VSS BA0 BA2 A15 VREFCA VSS K K VDD • DQ15 H J N DQ13 G H • VDDQ F G M 9 E F • 8 D E L 7 C C • 3 B B • 2 A A • 1 A3 A0 A12(/BC) BA1 VDD L VSS A5 A2 A1 A4 VSS M VDD A7 A9 A11 A6 VDD N VSS /RESET A13 A14 A8 VSS • P • R /xxx indicates active low signal T Pin name A0 to A15 (x8) *3 A0 to A14 (x16) *3 BA0 to BA2 *3 DQ0 to DQ7 (x8) DQ0 to DQ15 (x16) DQS, /DQS (x8) DQSU, /DQSU, DQSL, /DQSL (x16) DM (x8) DMU, DML (x16) TDQS, /TDQS (x8) /RESET *3 ZQ Function Address inputs A10(AP):Auto precharge A12(/BC):Burst chop Bank select Data input/output Differential data strobe Write data mask Termination data strobe Active low asynchronous reset Reference pin for ZQ calibration Pin name CK, /CK /CS *3 /RAS, /CAS, /WE *3 CKE *3 ODT *3 VDD VSS VDDQ VSSQ VREFDQ VREFCA NC *1 NU *2 Function Differential clock input Chip select Command input Clock enable ODT control Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Reference voltage for DQ Reference voltage for CA No connection Not Usable Notes: 1. 2. 3. Not internally connected with die Don’t connect. Internally connected Input only pins (address, command, CKE, ODT and /RESET) do not supply termination A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 5 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 3. Package outline drawing 78-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) Top View Bottom View Side View Note: The pin 1 index and 3 corner marks at bottom side are No Connection. A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 6 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 96-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) Top View Bottom View Side View Note: The pin 1 index and 3 corner marks at bottom side are No Connection. A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 7 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 4. Electrical Specifications All voltages are referenced to each VSS (GND) Execute power-up and Initialization sequence before proper device operation can be achieved. 4.1 Absolute Maximum Ratings Parameter Power supply voltage Power supply voltage for output Input voltage Output voltage Reference voltage Reference voltage for DQ Storage temperature Power dissipation Short circuit output current Symbol VDD VDDQ VIN VOUT VREFCA VREFDQ Tstg PD IOUT Rating -0.4 to +1.975 -0.4 to +1.975 -0.4 to +1.975 -0.4 to +1.975 -0.4 to 0.6 x VDD -0.4 to 0.6 x VDDQ -55 to +150 1.0 50 Unit V V V V V V °C W mA Notes 1, 3 1, 3 1 1 3 3 1, 2 1 1 Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 4.2 Operating Temperature Condition Product grades Commercial Industrial Automotive Parameter Operating case temperature Symbol TC TC TC Rating 0 to +95 -40 to +95 -40 to +105 Unit °C °C °C Note 1, 2, 3 1, 2, 3 1, 2, 3 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C (and +105°C for automotive grade only) case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: 4. Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9µs 5. If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]). A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 8 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 4.3 Recommended DC Operating Conditions Parameter Symbol min. typ. max. Unit Supply voltage VDD 1.425 1.5 1.575 V Supply voltage for DQ VDDQ 1.425 1.5 1.575 V Notes: 1. Under all conditions VDDQ must be less than or equal to VDD 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together 4.4 Note 1, 2 1, 2 AC and DC Input Measurement Levels [Refer to section 8 in JEDEC Standard No. JESD79-3F] 4.5 AC and DC Output Measurement Levels [Refer to section 9 in JEDEC Standard No. JESD79-3F] 4.6 Address / Command Setup, Hold and Derating [Refer to section 13.5 in JEDEC Standard No. JESD79-3F] 4.7 Overshoot and Undershoot Specifications [Refer to section 9.6 in JEDEC Standard No. JESD79-3F] 4.8 Output Driver DC Electrical Characteristics [Refer to section 9.7 in JEDEC Standard No. JESD79-3F] 4.9 On-Die Termination (ODT) Levels and I-V Characteristics [Refer to section 9.8 in JEDEC Standard No. JESD79-3F] A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 9 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 4.10 DC Characteristics Parameter Symbol Operating current (ACT-PRE) IDD0 Operating current (ACT-READ-PRE) IDD1 IDD2P1 Precharge power-down Standby current IDD2P0 Precharge standby current IDD2N Precharge standby current ODT current IDD2NT Precharge quiet standby Current IDD2Q Active power-down current (Always fast exit) IDD3P Active standby current IDD3N Operating current (Burst read operating) IDD4R Operating current (Burst write operating) IDD4W Burst refresh current IDD5B All bank interleave read current IDD7 RESET low current IDD8 A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 Data rate (Mbps) 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 2133 1866 1600 1333 - x8 x16 max. max. 51 61 49 59 47 57 45 55 67 87 64 84 61 81 59 79 18 18 16 16 14 14 12 12 8 8 8 8 8 8 8 8 28 28 26 26 24 24 22 22 32 35 30 33 28 31 26 29 28 28 26 26 24 24 22 22 30 30 28 28 26 26 24 24 34 42 32 40 30 38 28 36 165 175 155 165 145 155 135 145 165 175 155 165 145 155 135 145 180 180 175 175 170 170 165 165 200 210 190 200 180 190 170 180 Idd2P+2mA Idd2P+2mA 10 of 43 Unit Notes mA mA mA Fast PD Exit mA Slow PD Exit mA mA mA mA mA mA mA mA mA mA AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 4.11 Self-Refresh Current Parameter Symbol Data rate (Mbps) x8 max. x16 max. Unit Notes Self-refresh current IDD6 12 12 mA Normal temperature range Self-refresh current IDD6E 15 15 mA Extended temperature range Notes: 1. Enabling ASR could increase IDDx by up to an additional 2mA. 2. The IDD values must be derated (increased) on Industrial devices when operated outside of the range 0°C ≤ TC ≤ +85°C: • When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%. • When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by 2%; IDD2Px must be derated by 30%. [Refer to section 10 in JEDEC Standard No. JESD79-3F for detailed test condition] A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 11 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 4.12 Pin Capacitance(TC = 25°C, VDD, VDDQ = 1.5V  0.075V) Parameter Symbol DDR3-1066 Min Max 1.4 2.7 Input/output capacitance CIO Input capacitance, CK and CCK 0.8 /CK Input capacitance delta, CK CDCK 0 and /CK Input/output capacitance CDDQS 0 delta, DQS and /DQS Input capacitance, (control, address, command, inputCI 0.75 only pins) Input capacitance delta, (all CDI_CTRL -0.5 control input-only pins) Input capacitance delta, (all address/command inputCDI_ADD_CMD -0.5 only pins) Input/output capacitance delta, DQ, DM, DQS, /DQS, CDIO -0.5 TDQS, /TDQS Input/output capacitance of CZQ ZQ pin DDR3-1333 Min Max 1.4 2.5 DDR3-1600 Min Max 1.4 2.3 DDR3-1866 Min Max 1.4 2.2 DDR3-2133 Min Max 1.4 2.1 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 0.15 0 0.15 0 0.15 0 0.15 0.2 0 0.15 0 0.15 0 1.35 0.75 1.3 0.75 1.3 0.3 -0.4 0.2 -0.4 0.5 -0.4 0.4 0.3 -0.5 3 - Unit Notes pF 1, 2 1.3 pF 2 0 0.15 pF 2, 3 0.15 0 0.15 pF 2, 4 0.75 1.2 0.75 1.2 pF 2, 5 0.2 -0.4 0.2 -0.4 0.2 pF 2, 6, 7 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2, 8, 9 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2, 10 3 - 3 - 3 - 3 pF 2, 11 Notes: 1. Although the DM, TDQS and /TDQS pins have different functions, the loading matches DQ and DQS 2. VDD, VDDQ, VSS, VSSQ applied and all other pins floating (excepting the pin under test, CKE, /RESET and ODT as necessary). VDD = VDDQ =1.5V, VBIAS=VDD/2 and on die termination off. 3. Absolute value of CCK(CK) - CCK(/CK) 4. Absolute value of CIO(DQS) - CIO(/DQS) 5. CI applies to ODT, /CS, CKE, A0-A15, BA0-BA2, /RAS, /CAS and /WE 6. CDI_CTRL applies to ODT, /CS and CKE. 7. CDI_CTRL = CI(CTRL) - 0.5 x (CI(CK)+CI(/CK)) 8. CDI_ADD_CMD applies to A0-A15, BA0-BA2, /RAS, /CAS and /WE 9. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 x (CI(CK) + CI(/CK)) 10. CDIO = CIO(DQ, DM) - 0.5 x (CIO(DQS) + CIO(/DQS)) 11. Maximum external load capacitance on ZQ pin: 5pF A3T4GF340BBF DDR3.pdf - Rev. 1.1 Apr. 18, 2019 12 of 43 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved A3T4GF30BBF/A3T4GF40BBF 4.13 Standard Speed Bins Speed Bin CL-tRCD-tRP Parameter Internal read command to first data Symobl ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC tAA DDR3-1333 9-9-9 min. max. 13.5 20.0 (13.125) 13.5 (13.125) 13.5 (13.125) 49.5 (49.125) DDR3-1600 11-11-11 min. max. 13.75 20.0 (13.125) 13.75 (13.125) 13.75 (13.125) 48.75 (48.125) DDR3-1866 13-13-13 min. max. 13.91 20.0 (13.125) 13.91 (13.125) 13.91 (13.125) 47.91 (47.125) Unit ns ns ns ns ACT to PRE command tRAS period CL=5 CWL = 5 tCK (avg) CWL = 6, 7, 8, 9 tCK (avg) CL=6 CWL = 5 tCK (avg) CWL = 6 tCK (avg) CWL = 7, 8, 9 tCK (avg) CL=7 CWL = 5 tCK (avg) CWL = 6 tCK (avg) CWL = 7, 8, 9 tCK (avg) CL=8 CWL = 5 tCK (avg) CWL = 6 tCK (avg) CWL = 7, 8, 9 tCK (avg) CL=9 CWL = 5, 6 tCK (avg) CWL = 7 tCK (avg) CWL = 8, 9 tCK (avg) CL=10 CWL = 5, 6 tCK (avg) CWL = 7 tCK (avg) CWL = 8, 9 tCK (avg) CL=11 CWL = 5, 6, 7 tCK (avg) CWL= 8 tCK (avg) CWL= 9 tCK (avg) CL=12 CWL = 5, 6, 7, 8, 9 tCK (avg) CL=13 CWL = 5, 6, 7, 8 tCK (avg) CWL= 9 tCK (avg) Supported CL settings 3.0 3.3 Reserved 2.5 3.3 Reserved Reserved Reserved 1.875 < 2.5 Reserved Reserved 1.875 < 2.5 Reserved Reserved 1.5