F501D

F501D 600V Depletion-Mode Power MOSFET General Features        Proprietary Advanced Planar Technology Depletion Mode (Normally On) ESD improved Capability Rugged Polysilicon Gate Cell Structure Fast Switching Speed RoHS Compliant Halogen-free available BVDSX RDS(ON),typ. IDSS 600V 350Ω 12mA Applications      Synchronous Rectification Normally-on Switches Linear Amplifier, Converters Constant Current Source Telecom Ordering Information Part Number F501D Marking F501D Package SOT-23 Brand Absolute Maximum Ratings Symbol TC=25℃ unless otherwise specified Parameter F501D VDSX Drain-to-Source Voltage[1] 600 VGS Gate-to-Source Voltage ±20 Unit V Continuous Drain Current 0.030 Continuous Drain Current @ Tc=70℃ 0.025 Pulsed Drain Current [2] 0.120 ID IDM A Gate source ESD (HBM-C= 100pF, R=1.5k Ω) 300 V PD Power Dissipation 0.5 W TL Soldering Temperature Distance of 1.6mm from case for 10 seconds 300 TJ& TSTG Operating and Storage Temperature Range -55 to 150 VESD(G-S) ℃ Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. Thermal Characteristics Symbol RθJA Parameter Thermal Resistance, Junction-to-Ambient F501D Unit 250 K/W ©2016 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Page 1 / 6 Rev. A.2016 F501D Electrical Characteristics OFF Characteristics Symbol TJ =25℃ unless otherwise specified Parameter Min. Typ. Max. Unit BVDSX Drain-to-Source Breakdown Voltage 600 -- -- V -- -- 0.1 ID(OFF) Drain-to-Source Leakage Current IGSS VGS=-15V, ID=250uA VDS=600V, VGS=-5V uA -- -- 10 -- -- +100 VDS=480V, VGS=-5V, TJ =125℃ Gate-to-Source Leakage Current VGS=+10V, VDS=0V nA -- -- -100 ON Characteristics Symbol Test Conditions VGS=-10V, VDS=0V TJ =25℃ unless otherwise specified Parameter Min. Typ. Max. Unit Test Conditions 12 -- -- mA VDS=25V, VGS=0V -- 350 700 Ω VGS=0V, ID=3.0mA[3] IDSS Saturated Drain-to-Source Current RDS(ON) Static Drain-to-Source On-Resistance VGS(OFF) Gate-to-Source Cut-off Voltage -2.7 -1.8 -1.0 V VDS=3V, ID=8.0uA gfs Forward Transconductance 0.008 0.017 -- S VDS=50V, ID =0.01A Dynamic Characteristics Symbol Parameter Essentially independent of operating temperature Min. Typ. Max. Ciss Input Capacitance -- 50 -- Crss Reverse Transfer Capacitance -- 1.1 -- Coss Output Capacitance -- 4.5 -- Qg Total Gate Charge -- 1.1 -- Qgs Gate-to-Source Charge -- 0.5 -- Qgd Gate-to-Drain (Miller) Charge -- 0.35 -- Resistive Switching Characteristics Symbol Parameter Unit Test Conditions pF VGS=-5V, VDS=25V, f=1.0MHZ nC VGS=-5V~+5V, ID=10mA, VDS=400V Essentially independent of operating temperature Min. Typ. Max. td(ON) Turn-on Delay Time -- 9.9 -- trise Rise Time -- 50 -- td(OFF) Turn-Off Delay Time -- 55 -- tfall Fall Time -- 130 -- Unit Test Conditions nS ©2016 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. VDD=300V, ID=10mA, VGS= -5V~+5V RG=6.1Ω Page 2 / 6 Rev. A.2016 F501D Source-Drain Body Diode Characteristics Symbol IS ISM VSD trr Qrr Parameter Continuous Source Current (Body Diode) Maximum Pulsed Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge TJ=25℃ unless otherwise specified Min Typ. Max. ------ ---240 625 0.025 0.100 1.2 --- Unit Test Conditions A Ta=25°C V ns nC IS=15mA, VGS=-5V IF=10mA,Tj = 25°C, dIF/dt=100A/us, VR=300V Note: VGSO@IGS= ±1mA(Open Drain) >20 The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. ©2016 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Page 3 / 6 Rev. A.2016 F501D Typical Characteristics ©2016 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Page 4 / 6 Rev. A.2016 F501D ©2016 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Page 5 / 6 Rev. A.2016 F501D Disclaimers: Perfect Intelligent Power Semiconductor Co., Ltd (PIP) reserves the right to make changes without notice in order to improve reliability, function or design and to discontinue any product or service without notice. Customers should obtain the latest relevant information before orders and should verify that such information is current and complete. All products are sold subject to PIP’s terms and conditions supplied at the time of order acknowledgement. Perfect Intelligent Power Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale, Testing, reliability and quality control are used to the extent PIP deems necessary to support this warrantee. Except where agreed upon by contractual agreement, testing of all parameters of each product is not necessarily performed. Perfect Intelligent Power Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs described herein. Customers are responsible for their products and applications using PIP’s components. To minimize risk, customers must provide adequate design and operating safeguards. Perfect Intelligent Power Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent rights, nor the rights of others. Reproduction of information in PIP’s data sheets or data books is permissible only if reproduction is without modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business practice. Perfect Intelligent Power Semiconductor Co., Ltd is not responsible or liable for such altered documentation. Resale of PIP’s products with statements different from or beyond the parameters stated by Perfect Intelligent Power Semiconductor Co., Ltd for that product or service voids all express or implied warrantees for the associated PIP’s product or service and is unfair and deceptive business practice. Perfect Intelligent Power Semiconductor Co., Ltd is not responsible or liable for any such statements. Life Support Policy: Perfect Intelligent Power Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or systems without the expressed written approval of Perfect Intelligent Power Semiconductor Co., Ltd. As used herein: 1. Life support devices or systems are devices or systems which: a. are intended for surgical implant into the human body, b. support or sustain life, c. whose failure to perform when properly used in accordance with instructions for used provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©2016 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Page 6 / 6 Rev. A.2016