RTL8218D-CG
INTEGRATED OCTAL 10/100/1000M
ETHERNET TRANSCEIVER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
17 January 2018
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8218D
Datasheet
COPYRIGHT
©2018 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8218D IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
ELECTROSTATIC DISCHARGE (ESD) WARNING
This product can be damaged by Electrostatic Discharge (ESD). When handling, care must be taken.
Damage due to inappropriate handling is not covered by warranty.
Do not open the protective conductive packaging until you have read the following, and are at an
approved anti-static workstation.
Use an approved anti-static mat to cover your work surface.
Use a conductive wrist strap attached to a good earth ground
Always discharge yourself by touching a grounded bare metal surface or approved anti-static mat
before picking up an ESD-sensitive electronic component
If working on a prototyping board, use a soldering iron or station that is marked as ESD-safe
Always disconnect the microcontroller from the prototyping board when it is being worked on
REVISION HISTORY
Revision
1.0
Release Date
2018/01/17
Summary
First release.
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
Table of Contents
1.
GENERAL DESCRIPTION .............................................................................................................................................. 1
2.
FEATURES ......................................................................................................................................................................... 2
3.
SYSTEM APPLICATIONS ............................................................................................................................................... 3
3.1.
3.2.
3.3.
3.4.
24-PORT GIGABIT ETHERNET SWITCH ......................................................................................................................... 3
24-PORT GIGABIT ETHERNET SWITCH ......................................................................................................................... 4
20+4 COMBO PORT GIGABIT ETHERNET SWITCH......................................................................................................... 5
24+4 COMBO PORT GIGABIT ETHERNET SWITCH......................................................................................................... 6
4.
BLOCK DIAGRAM ........................................................................................................................................................... 7
5.
PIN ASSIGNMENTS ......................................................................................................................................................... 8
5.1.
5.2.
5.3.
6.
PIN DESCRIPTIONS ...................................................................................................................................................... 11
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
7.
PIN ASSIGNMENTS ....................................................................................................................................................... 8
PACKAGE IDENTIFICATION ........................................................................................................................................... 8
PIN ASSIGNMENT TABLES ............................................................................................................................................ 9
MEDIA DEPENDENT INTERFACE PINS ......................................................................................................................... 11
XSGMII PINS ............................................................................................................................................................ 13
QSGMII PINS ............................................................................................................................................................ 13
SERIAL LED PINS ...................................................................................................................................................... 13
CONFIGURATION PINS ................................................................................................................................................ 14
MISCELLANEOUS PINS ............................................................................................................................................... 15
POWER AND GND PINS .............................................................................................................................................. 16
TEST PINS .................................................................................................................................................................. 16
FUNCTION DESCRIPTION .......................................................................................................................................... 17
7.1.
MDI INTERFACE ........................................................................................................................................................ 17
7.2.
1000BASE-T TRANSMIT FUNCTION ........................................................................................................................... 17
7.3.
1000BASE-T RECEIVE FUNCTION .............................................................................................................................. 17
7.4.
100BASE-TX TRANSMIT FUNCTION........................................................................................................................... 17
7.5.
100BASE-TX RECEIVE FUNCTION ............................................................................................................................. 18
7.6.
10BASE-T TRANSMIT FUNCTION ............................................................................................................................... 18
7.7.
10BASE-T RECEIVE FUNCTION .................................................................................................................................. 18
7.8.
AUTO-NEGOTIATION FOR UTP .................................................................................................................................. 18
7.9.
CROSSOVER DETECTION AND AUTO CORRECTION ..................................................................................................... 19
7.10.
POLARITY CORRECTION ............................................................................................................................................. 19
7.11.
MDC/MDIO INTERFACE ........................................................................................................................................... 20
7.12.
TEN-GIGABIT MEDIA INDEPENDENT INTERFACE (XSGMII) ...................................................................................... 21
7.13.
QUAD SERIAL GIGABIT MEDIA INDEPENDENT INTERFACE (QSGMII) ....................................................................... 22
7.13.1.
XSGMII Interface............................................................................................................................................. 23
7.13.2.
QSGMII Interface ............................................................................................................................................ 23
7.14.
SERIAL LED............................................................................................................................................................... 24
7.14.1.
Port Status Indicator........................................................................................................................................ 24
7.14.2.
LED Configuration .......................................................................................................................................... 24
7.14.3.
Serial LED Configuration Register ................................................................................................................. 27
7.14.4.
Serial LED Timing Definitions ........................................................................................................................ 28
7.15.
REALTEK CABLE TEST (RTCT) ................................................................................................................................. 28
7.16.
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) ................................................................................................ 29
7.17.
INTERRUPT PIN FOR EXTERNAL CPU ......................................................................................................................... 29
7.18.
REG.0.11 POWER DOWN MODE ................................................................................................................................. 29
7.19.
REG.0.14 PHY DIGITAL LOOPBACK RETURN TO INTERNAL ...................................................................................... 30
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8.
REGISTER DESCRIPTIONS ......................................................................................................................................... 31
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
9.
REGISTER 0: CONTROL ............................................................................................................................................... 32
REGISTER 1: STATUS .................................................................................................................................................. 33
REGISTER 2: PHY IDENTIFIER 1 ................................................................................................................................. 34
REGISTER 3: PHY IDENTIFIER 2 ................................................................................................................................. 34
REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ................................................................................................. 34
REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY....................................................................................... 35
REGISTER 6: AUTO-NEGOTIATION EXPANSION .......................................................................................................... 36
REGISTER 7: AUTO-NEGOTIATION NEXT PAGE TRANSMIT ........................................................................................ 36
REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE ABILITY ................................................................... 37
REGISTER 9: 1000BASE-T CONTROL.......................................................................................................................... 37
REGISTER 10: 1000BASE-T STATUS ........................................................................................................................... 38
REGISTER 13: MMD ACCESS CONTROL REGISTER .................................................................................................... 38
REGISTER 14: MMD ACCESS ADDRESS DATA REGISTER .......................................................................................... 39
REGISTER 15: EXTENDED STATUS.............................................................................................................................. 39
ELECTRICAL CHARACTERISTICS .......................................................................................................................... 40
9.1.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 40
9.2.
OPERATING RANGE .................................................................................................................................................... 40
9.3.
POWER CONSUMPTION ............................................................................................................................................... 41
9.4.
IEEE 10/100/1000BASE-T SPECIFICATIONS .............................................................................................................. 43
9.5.
XSGMII CHARACTERISTICS ...................................................................................................................................... 44
9.5.1. XSGMII Differential Transmitter Characteristics ................................................................................................ 44
9.5.2. XSGMII Differential Receiver Characteristics ..................................................................................................... 44
9.5.3. QSGMII Differential Transmitter Characteristics ............................................................................................... 44
9.5.4. QSGMII Differential Receiver Characteristics .................................................................................................... 44
9.6.
XTALI CLOCK CHARACTERISTICS ............................................................................................................................ 45
9.7.
POWER AND RESET CHARACTERISTICS ...................................................................................................................... 45
9.8.
MDC/MDIO INTERFACE CHARACTERISTICS ............................................................................................................. 46
9.9.
LED CHARACTERISTICS ............................................................................................................................................. 47
9.9.1. Serial LED Timing ................................................................................................................................................ 47
10.
THERMAL CHARACTERISTICS ................................................................................................................................ 48
10.1.
ASSEMBLY DESCRIPTION ........................................................................................................................................... 48
10.2.
MATERIAL PROPERTIES.............................................................................................................................................. 48
10.3.
SIMULATION CONDITIONS .......................................................................................................................................... 48
10.4.
THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER STILL AIR CONVENTION ........................................ 49
10.5.
THERMAL PERFORMANCE OF E-PAD LQFP-128 WITH EXTERNAL HEAT-SINK ON PCB UNDER NATURAL
CONVENTION............................................................................................................................................................................ 49
11.
MECHANICAL DIMENSIONS...................................................................................................................................... 50
11.1.
11.2.
12.
LQFP-128 E-PAD PACKAGE ..................................................................................................................................... 50
MECHANICAL DIMENSIONS NOTES ............................................................................................................................ 50
ORDERING INFORMATION ........................................................................................................................................ 51
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List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE .............................................................................................................................................. 9
TABLE 2. MEDIA DEPENDENT INTERFACE PINS ........................................................................................................................... 11
TABLE 3. XSGMII PINS............................................................................................................................................................... 13
TABLE 4. QSGMII PINS............................................................................................................................................................... 13
TABLE 5. SERIAL LED PINS......................................................................................................................................................... 13
TABLE 6. CONFIGURATION PINS .................................................................................................................................................. 14
TABLE 7. MISCELLANEOUS PINS ................................................................................................................................................. 15
TABLE 8. POWER AND GND PINS ................................................................................................................................................ 16
TABLE 9. TEST PINS..................................................................................................................................................................... 16
TABLE 10. MEDIA DEPENDENT INTERFACE PIN MAPPING............................................................................................................. 19
TABLE 11. SERIAL LED PER-LED CONTROL ................................................................................................................................ 24
TABLE 12. SERIAL LED MODE CONFIGURATION (PER-PORT 3 LEDS) ......................................................................................... 26
TABLE 13. SERIAL LED CONFIGURATION REGISTER .................................................................................................................... 27
TABLE 14. REGISTER DESCRIPTIONS ............................................................................................................................................. 31
TABLE 15. REGISTER 0: CONTROL ................................................................................................................................................ 32
TABLE 16. REGISTER 1: STATUS.................................................................................................................................................... 33
TABLE 17. REGISTER 2: PHY IDENTIFIER 1 ................................................................................................................................... 34
TABLE 18. REGISTER 3: PHY IDENTIFIER 2 ................................................................................................................................... 34
TABLE 19. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ................................................................................................... 34
TABLE 20. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................ 35
TABLE 21. REGISTER 6: AUTO-NEGOTIATION EXPANSION ............................................................................................................ 36
TABLE 22. REGISTER 7: AUTO-NEGOTIATION NEXT PAGE TRANSMIT .......................................................................................... 36
TABLE 23. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE ABILITY ..................................................................... 37
TABLE 24. REGISTER 9: 1000BASE-T CONTROL ........................................................................................................................... 37
TABLE 25. REGISTER 10: 1000BASE-T STATUS ............................................................................................................................ 38
TABLE 26. REGISTER 13: MMD ACCESS CONTROL REGISTER ...................................................................................................... 38
TABLE 27. REGISTER 14: MMD ACCESS ADDRESS DATA REGISTER ............................................................................................ 39
TABLE 28. REGISTER 15: EXTENDED STATUS ............................................................................................................................... 39
TABLE 29. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 40
TABLE 30. OPERATING RANGE...................................................................................................................................................... 40
TABLE 31. XSGMII MODE POWER CONSUMPTION ....................................................................................................................... 41
TABLE 32.QSGMII MODE POWER CONSUMPTION ........................................................................................................................ 42
TABLE 33. IEEE 10/100/1000BASE-T SPECIFICATIONS ................................................................................................................ 43
TABLE 34. XSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS ......................................................................................... 44
TABLE 35. QSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ............................................................................................... 44
TABLE 36 QSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS .......................................................................................... 44
TABLE 37 QSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ................................................................................................ 44
TABLE 38. XTALI CLOCK CHARACTERISTICS .............................................................................................................................. 45
TABLE 39. POWER AND RESET CHARACTERISTICS ........................................................................................................................ 45
TABLE 40. MDIO TIMING CHARACTERISTICS AND REQUIREMENT ............................................................................................... 46
TABLE 41. SERIAL LED TIMING.................................................................................................................................................... 47
TABLE 42. ASSEMBLY DESCRIPTION ............................................................................................................................................. 48
TABLE 43. MATERIAL PROPERTIES ............................................................................................................................................... 48
TABLE 44. SIMULATION CONDITIONS ........................................................................................................................................... 48
TABLE 45. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER STILL AIR CONVENTION .......................................... 49
TABLE 46. THERMAL PERFORMANCE OF E-PAD LQFP-128 WITH EXTERNAL HEAT-SINK ON PCB UNDER NATURAL
CONVENTION ............................................................................................................................................................... 49
TABLE 47. ORDERING INFORMATION ............................................................................................................................................ 51
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
List of Figures
FIGURE 1. 24-PORT GIGABIT ETHERNET SWITCH (QSGMII & XSGMII INTERFACE) ................................................................... 3
FIGURE 2. 24-PORT GIGABIT ETHERNET SWITCH (QSGMII / XSGMII INTERFACE) ..................................................................... 4
FIGURE 3. 24+4-PORT COMBO GIGABIT ETHERNET SWITCH (QSGMII / XSGMII INTERFACE) .................................................... 5
FIGURE 4. 20 + 4-PORT COMBO GIGABIT ETHERNET SWITCH (QSGMII OR XGMII-PLUS INTERFACE) ........................................ 6
FIGURE 5. BLOCK DIAGRAM .......................................................................................................................................................... 7
FIGURE 6. PIN ASSIGNMENTS ........................................................................................................................................................ 8
FIGURE 7. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION .................................................................................................. 19
FIGURE 8. MDIO READ FRAME FORMAT .................................................................................................................................... 20
FIGURE 9. MDIO WRITE FRAME FORMAT ................................................................................................................................... 20
FIGURE 10. XSGMII INTERCONNECTION DIAGRAM ..................................................................................................................... 21
FIGURE 11. QSGMII INTERCONNECTION DIAGRAM ..................................................................................................................... 22
FIGURE 12. [MDI X 8] + [XSGMII X 1] ........................................................................................................................................ 23
FIGURE 13. [MDI X 8] + [QSGMII X 2] ........................................................................................................................................ 23
FIGURE 14. SERIAL LED TIMING DEFINITIONS ............................................................................................................................. 28
FIGURE 15. REG.0.14 PHY DIGITAL LOOPBACK ........................................................................................................................... 30
FIGURE 16. POWER AND RESET CHARACTERISTICS ....................................................................................................................... 45
FIGURE 17. MDIO SOURCED BY MASTER (MAC) ........................................................................................................................ 46
FIGURE 18. MDIO SOURCED BY RTL8218D (SLAVE) .................................................................................................................. 46
FIGURE 19. SERIAL LED TIMING .................................................................................................................................................. 47
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
1.
General Description
The RTL8218D-CG integrates octal independent 10/100/1000M Ethernet transceivers into a single IC,
and performs all the physical layer (PHY) functions for 1000Base-T, 100Base-TX, and 10Base-T
Ethernet on category 5 UTP cable except 1000Base-T half-duplex. 10Base-T functionality can also be
achieved on standard category 3 or 4 cable.
This device includes PCS, PMA, and PMD sub-layers. They perform encoding/decoding, clock/data
recovery, digital adaptive equalization, echo cancellers, crosstalk elimination, and line driver, as well as
other required supporting circuit functions. The RTL8218D also integrates an internal hybrid that allows
the use of inexpensive 1:1 transformer modules.
Each of the four independent transceivers features an innovative XSGMII / QSGMII for reduced PCB
traces. All transceivers can communicate with the MAC simultaneously through the same XSGMII.
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
2.
Features
Octal-port integrated 10/100/1000M
Ethernet transceiver
Each port supports full duplex in
10/100/1000M mode (half duplex is only
supported in 10/100M mode)
Supports XSGMII (Ten-Gigabit Serial
Media Independent Interface) and QSGMII
(Quad Serial Gigabit Media Independent
Interface) in 10/100/1000M mode
Supports IEEE 802.3az Energy Efficient
Ethernet (EEE)
Supports crossover detection and auto
correction in 10Base-T/100Base-T
Auto-detection and auto-correction of
wiring pair swaps, pair skew, and pair
polarity
Integrated Octal 10/100/1000M Ethernet Transceiver
Auto-detection and auto-correction of
wiring pair swaps, pair skew, and pair
polarity
Supports Realtek’s Cable Test (RTCT)
Supports one interrupt output to external
CPU for notification
Low power consumption
Easy layout, good EMI, and good thermal
performance
25MHz crystal or 3.3V OSC input
3.3V and 1.1V power supply
LQFP-128 E-PAD package
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Datasheet
3.
System Applications
3.1. 24-Port Gigabit Ethernet Switch
High-Ports Density
Gigabit MAC
QSGMII x 2
XSGMII x 1
XSGMII x 1
SD #0,1
SD #0
SD #0
RTL8218D
Gigabit PHY
RTL8218D
Gigabit PHY
RTL8218D
Gigabit PHY
PHY 0~7
LQFP-128
8G
Transformer
PHY 8~15
LQFP-128
8G
Transformer
PHY 16~23
LQFP-128
8G
Transformer
Figure 1. 24-Port Gigabit Ethernet Switch (QSGMII & XSGMII Interface)
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
3.2. 24-Port Gigabit Ethernet Switch
High-Ports Density
Gigabit MAC
QSGMII x 2
XSGMII x 1
XSGMII x 1
QSGMII x 1
SD #0,1
SD #0
SD #0
RTL8218D
Gigabit PHY
RTL8218D
Gigabit PHY
RTL8218D
Gigabit PHY
PHY 0~7
LQFP-128
8G
Transformer
PHY 8~15
LQFP-128
8G
Transformer
PHY 16~23
LQFP-128
8G
Transformer
SD #0
RTL8214FC
Gigabit PHY
PHY 24~27
TQFP-176
4G
Transformer
Figure 2. 24-Port Gigabit Ethernet Switch (QSGMII / XSGMII Interface)
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
3.3. 20+4 Combo Port Gigabit Ethernet Switch
High-Ports Density
Gigabit MAC
XSGMII x 1
QSGMII x 2 or
RSGMII-plus x 2
XSGMII x 1
SD #0
SD #0
SD #0,1
RTL8218D
Gigabit PHY
RTL8218D
Gigabit PHY
RTL8218FB
Gigabit PHY
PHY 0~7
LQFP-128
8G
Transformer
PHY 8~15
LQFP-128
8G
Transformer
TQFP-176
4G Combo
PHY 16~23
Transformer
Transformer
Figure 3. 24+4-Port Combo Gigabit Ethernet Switch (QSGMII / XSGMII Interface)
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
3.4. 24+4 Combo Port Gigabit Ethernet Switch
High-Ports Density
Gigabit MAC
XSGMII
QSGMII x2
QSGMII x 1 or
RSGMII-plus x 1
XSGMII
SD #0
SD #0
SD #0
RTL8218B-D
Gigabit PHY
RTL8218D
Gigabit PHY
RTL8218D
Gigabit PHY
PHY 0~7
LQFP-128
8G
Transformer
PHY 8~15
LQFP-128
8G
Transformer
PHY 16~23
LQFP-128
8G
Transformer
SD #0
RTL8214FC
Gigabit PHY
PHY 24~27
TQFP-176
4G
Transformer
Figure 4. 20 + 4-Port Combo Gigabit Ethernet Switch (QSGMII or XGMII-plus Interface)
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
Block Diagram
4.
S1RXN
S!RXP
S1TXN
1000Base-Tx
4DPAM5
EnDec,
Scrambler,
Viterbi,
& DFE
SerDes (#1)
(QSGMII)
S1TXP
S0RXN
S0RXP
S0TXN
S0TXP
MAC Interface
SerDes (#0)
(XSGMII
or QSGMII)
Equalizer
&
Echo, NEXT,
FEXT,
Cancellers
A/D
Pulse Shaper
F
I
F
O
100Base-Tx
4B/5B
EnDec
AGC,
Timing
Recovery,
Wander
Canceller
D/A
Filter
Scrambler/De
scrambler
Hybrid
Line-Driver
PAIR A
.
.
.
TwistPair
interface
PAIR B
PAIR C
Filter
PAIR D
MDI (Analog Front End)
10Base-T
Manchester
EnDec
MDC
MDIO
nRESET
Serial
Management
Interface
MII Register
PHYADD[4:0]
.
.
.
Auto Negotiation
.
.
.
.
.
.
PORT 0
PORT 1
PORT 7
PLL
Serial LED
SXTALI
SXTALO
LEDCK
LEDDA
Biasing
MDIREF
Figure 5. Block Diagram
Integrated Octal 10/100/1000M Ethernet Transceiver
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Datasheet
5.
Pin Assignments
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
AVDDH
PHYADDR2
PHYADDR3/LEDDA
PHYADDR4/LEDCK
nRESET
DVDDIO
XTALI
XTALO
SGND
S0TXP
S0TXN
SVDDL
S0RXP
S0RXN
SVDDL
SGND
Reserved
Reserved
SGND
Reserved
Reserved
SVDDL
NC
SVDDH
INTERRUPT
DVDDL
MDC
MDIO
DVDDIO
Reserved
PHYADDR0
PHYADDR1
EN_PHY
DVDDL
CHIP_MODE2
CHIP_MODE1
Reserved
AVDDH
5.1. Pin Assignments
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RTL8218D
LLLLLLL
GXXXV TAIWAN
LQFP-128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
P7MDIDN
P7MDIDP
P7MDICN
P7MDICP
AVDDL
P7MDIBN
P7MDIBP
P7MDIAN
P7MDIAP
AVDDH
P6MDIDN
P6MDIDP
P6MDICN
P6MDICP
AVDDL
P6MDIBN
P6MDIBP
P6MDIAN
P6MDIAP
AVDDH
NC
P5MDIDN
P5MDIDP
P5MDICN
P5MDICP
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
RTT1
RTT2
AVDDH
DVDDL
DVDDL
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL0
AVDDH
P2MDIAP
P2MDIAN
P2MDIBP
P2MDIBN
AVDDL
Figure 6. Pin Assignments
5.2. Package Identification
Green package is indicated by the ‘G’ in GXXXV (Figure 6). The version number is shown in the
location marked ‘V’.
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Datasheet
5.3. Pin Assignment Tables
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPD: Input Pin With Pull-Down Resistor
A: Analog Pin
IPU: Input Pin With Pull-Up Resistor;
OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75K Ohm)
(Typical Value = 75K Ohm)
SP: SerDes Power Pin
SG: SerDes Ground Pin
IS: Schmitt Trigger Input Pin
Pin Name
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
RTT1
RTT2
AVDDH
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Table 1. Pin Assignments Table
Type
Pin Name
AI/O
DVDDL
AI/O
DVDDL
AI/O
AVDDH
AI/O
P4MDIAP
AP
P4MDIAN
AI/O
P4MDIBP
AI/O
P4MDIBN
AI/O
AVDDL
AI/O
P4MDICP
AP
P4MDICN
AI/O
P4MDIDP
AI/O
P4MDIDN
AI/O
AVDDH
AI/O
P5MDIAP
AP
P5MDIAN
AG
P5MDIBP
AO
P5MDIBN
AP
AVDDL
AO
P5MDICP
AO
P5MDICN
AP
P5MDIDP
Integrated Octal 10/100/1000M Ethernet Transceiver
9
Pin No.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Type
P
P
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
Pin Name
P5MDIDN
NC
AVDDH
P6MDIAP
P6MDIAN
P6MDIBP
P6MDIBN
AVDDL
P6MDICP
P6MDICN
P6MDIDP
P6MDIDN
AVDDH
P7MDIAP
P7MDIAN
P7MDIBP
P7MDIBN
AVDDL
P7MDICP
P7MDICN
P7MDIDP
P7MDIDN
AVDDH
Reserved
CHIP_MODE1
CHIP_MODE2
DVDDL
EN_PHY
PHYADDR1
PHYADDR0
Reserved
DVDDIO
MDIO
MDC
DVDDL
INTERRUPT
SVDDH
NC
SVDDL
S1RXP
S1RXN
SGND
S1TXP
S1TXN
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Type
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
I/OPU
IPU
IPU
P
I/OPU
I/OPD
I/OPD
I/OPD
P
I/OPU
I
P
I/OPU
SP
SP
AO
AO
SG
AI
AI
Integrated Octal 10/100/1000M Ethernet Transceiver
Pin Name
SGND
SVDDL
S0RXN
S0RXP
SVDDL
S0TXN
S0TXP
SGND
XTALO
XTALI
DVDDIO
nRESET
PHYADDR4/LEDCK
PHYADDR3/LEDDA
PHYADDR2
AVDDH
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL0
AVDDH
P2MDIAP
P2MDIAN
P2MDIBP
P2MDIBN
AVDDL
GND
10
Pin No.
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
EPAD
Type
SG
SP
AO
AO
SP
AI
AI
SG
AO
AI
P
IPU
I/OPD
I/OPD
IPD
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AP
AI/O
AI/O
AI/O
AI/O
AP
G
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
6.
Pin Descriptions
6.1. Media Dependent Interface Pins
Pin Name
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
P2MDIAP
P2MDIAN
P2MDIBP
P2MDIBN
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
Pin No.
103
104
105
106
108
109
110
111
113
114
115
116
118
119
120
121
124
125
126
127
1
2
3
4
6
7
8
9
11
12
13
14
25
26
27
28
30
31
32
33
Table 2. Media Dependent Interface Pins
Type
Description
AI/O
Port 0 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
AI/O
Port 1 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
AI/O
Port 2 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
AI/O
Port 3 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
AI/O
Port 4 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
Integrated Octal 10/100/1000M Ethernet Transceiver
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Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
Pin Name
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
P5MDICP
P5MDICN
P5MDIDP
P5MDIDN
P6MDIAP
P6MDIAN
P6MDIBP
P6MDIBN
P6MDICP
P6MDICN
P6MDIDP
P6MDIDN
P7MDIAP
P7MDIAN
P7MDIBP
P7MDIBN
P7MDICP
P7MDICN
P7MDIDP
P7MDIDN
Pin No.
35
36
37
38
40
41
42
43
46
47
48
49
51
52
53
54
56
57
58
59
61
62
63
64
Type
AI/O
Description
Port 5 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
AI/O
Port 6 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
AI/O
Port 7 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-TX and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N
and MDIBP/N.
Each of the differential pairs has an internal 100ohm termination resistor.
Integrated Octal 10/100/1000M Ethernet Transceiver
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Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
6.2. XSGMII Pins
Pin Name
S0RXP
S0RXN
Pin No.
90
89
Type
AO
S0TXP
S0TXN
93
92
AI
Reserved
82
83
85
86
AO
Reserved
AI
Table 3. XSGMII Pins
Description
If CHIP_MODE[2:1] = 2’b01
XSGMII Differential Output.
10.3125GHz serial interfaces to transfer data from an External device that
supports the XSGMII interface.
Differential pairs have an internal 100ohm termination resistor.
If CHIP_MODE[2:1] = 2’b01
XSGMII Differential Input.
10.3125GHz serial interfaces to receive data from an External device that
supports the XSGMII interface.
Differential pairs have an internal 100ohm termination resistor.
Reserved. Requires either a 50 ohm resistor and 0.1µF cap in series to SVDDL,
or can be left floating
Reserved. Can be left floating
6.3. QSGMII Pins
Pin Name
S0RXP
S0RXN
S1RXP
S1RXN
S0TXP
S0TXN
S1TXP
S1TXN
Pin No.
90
89
82
83
93
92
85
86
Type
AO
AI
Table 4. QSGMII Pins
Description
If CHIP_MODE[2:1] = 2’b10
QSGMII Differential Output.
5GHz serial interfaces to transfer data from an External device that supports the
QSGMII interface.
Differential pairs have an internal 100ohm termination resistor.
If CHIP_MODE[2:1] = 2’b10
QSGMII Differential Input.
5GHz serial interfaces to receive data from an External device that supports the
QSGMII interface.
Differential pairs have an internal 100ohm termination resistor.
6.4. Serial LED Pins
Pin Name
LEDCK
LEDDA
Pin No.
99
100
Type
I/OPD
I/OPD
Table 5. Serial LED Pins
Description
Serial LED Clock Output
Serial LED Data Output
Integrated Octal 10/100/1000M Ethernet Transceiver
13
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
6.5. Configuration Pins
Pin Name
PHYADDR0
Pin No.
72
Type
I/OPD
PHYADDR1
71
I/OPD
PHYADDR2
101
IPD
PHYADDR3 /
LEDDA
100
I/OPD
PHYADDR4 /
LEDCK
99
I/OPD
EN_PHY
70
I/OPU
CHIP_MODE2
68
IPU
CHIP_MODE1
67
IPU
Table 6. Configuration Pins
Description
PHYADDR0, PHY Address Select. These pins are the 5-bit IEEE-specified
PHY address. The states of these five pins are latched during power-up or
reset.
Note: This pin must be kept floating, or pulled high or low via an external
4.7k ohm resistor upon power on or reset.
PHYADDR1, PHY Address Select. These pins are the 5-bit IEEE-specified
PHY address. The states of these five pins are latched during power-up or
reset.
Note: This pin must be kept floating, or pulled high or low via an external
4.7k ohm resistor upon power on or reset.
PHYADDR2, PHY Address Select. These pins are the 5-bit IEEE-specified
PHY address. The states of these five pins are latched during power-up or
reset.
Note: This pin must be kept floating, or pulled high or low via an external
4.7k ohm resistor upon power on or reset.
PHYADDR3, PHY Address Select. These pins are the 5-bit IEEE-specified
PHY address. The states of these five pins are latched during power-up or
reset.
Note: This pin must be kept floating, or pulled high or low via an external
4.7k ohm resistor upon power on or reset.
PHYADDR4, PHY Address Select. These pins are the 5-bit IEEE-specified
PHY address. The states of these five pins are latched during power-up or
reset.
Note: This pin must be kept floating, or pulled high or low via an external
4.7k ohm resistor upon power on or reset.
Enable PHY Power
1: Power up all ports.
0: Power down all ports and set the MII register 0.11 power down as 1.
Note: This pin must be kept floating, or pulled high or low via an external
4.7k ohm resistor upon power on or reset.
MAC Interface Configuration:
CHIP_MODE[2:1] =
01: XSGMII
10: Reserved for Internal use
11:Reserved for Internal use
00:Reserved for Internal use
Reference CHIP_MODE2
Integrated Octal 10/100/1000M Ethernet Transceiver
14
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
6.6. Miscellaneous Pins
Pin Name
MDC
Pin No.
76
Type
I
MDIO
75
I/OPU
INTERRUPT
78
I/OPU
nRESET
98
IPU
MDIREF
17
AO
NC
NC
XTALI
44
80
96
AI
XTALO
95
AO
Table 7. Miscellaneous Pins
Description
MII Management Interface Clock Input.
The clock reference for the MII management interface.
The maximum frequency support is 8MHz.
MII Management Interface Data Input/Output.
MDIO transfer management data in and out of the device synchronous to the
rising edge of MDC.
Interrupt output when Interrupt even occurs.
Active High by pull-down to GND via a 1K resistor.
Active Low by pull-up to DVDDIO via a 4.7K resistor.
Hardware Reset (Active Low Reset Signal).
To complete the reset function, this pin must be asserted for at least 10ms. It
must be pulled high for normal operation.
MDI Bias Resistor.
Adjusts the reference current for all PHYs.
This pin must connect to AGND via a 2.49k ohm resistor.
We suggest NC pins are left floating.
We suggest NC pins are left floating.
25MHz Crystal Clock Input.
25MHz±50ppm tolerance crystal reference or oscillator input.
When using a crystal, connect a loading capacitor from each pad to ground.
When either using an oscillator or driving an external 25MHz clock from
another device, XTALO should be kept floating.
The maximum XTALI input voltage is 3.3V.
25MHz Crystal Clock Output.
25MHz±50ppm tolerance crystal output. Refer to XTALI.
Integrated Octal 10/100/1000M Ethernet Transceiver
15
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
6.7. Power and GND Pins
Pin Name
AVDDH
AVDDL
PLLVDD0
SVDDH
SVDDL
DVDDIO
DVDDL
AGND
SGND
GND
6.8.
Table 8. Power and GND Pins
Pin No.
Type
Description
5, 15, 21, 24, 34, 45, 55,
AP
Analog High Voltage Power
65, 102, 112,123
10, 18, 29, 39, 50, 60,
AP
Analog Low Voltage Power
107, 117, 128
122
AP
PLL Power
This pin should be filtered with a low resistance series ferrite
bead and 1000pF + 2.2µF shunt capacitors to ground
79
SP
QSGMII / RSGMII-Plus SerDes High Voltage Power
81, 88, 91
SP
QSGMII / RSGMII-Plus SerDes Low Voltage Power
74, 97
P
Digital I/O Power
22, 23, 69, 77
P
Digital Low Voltage Power
16
AG
Analog Ground
84, 87, 94
SG
QSGMII/RSGMII-Plus SerDes Ground
EPAD
G
Digital/Analog Ground
Test Pins
Pin Name
RTT1
Pin No.
19
Type
AO
RTT2
20
AO
Reserved
66
I/OPU
Reserved
73
I/OPD
Table 9. Test Pins
Description
Reserved for Internal Use. Must be Left Floating or pulled-up to to
DVDDIO via 4.7K resistor.
Reserved for Internal Use. Must be Left Floating or pulled-up to to
DVDDIO via 4.7K resistor.
Reserved for Internal Use. Must be Left Floating or pulled-up to to
DVDDIO via 4.7K resistor.
Reserved. Must be tied to GND via a 1K resistor for normal operation
Integrated Octal 10/100/1000M Ethernet Transceiver
16
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.
Function Description
7.1. MDI Interface
The RTL8218D embeds octal 10/100/1000M Ethernet PHYs in one chip. Each port uses a single common
MDI interface to support 1000Base-T, 100Base-TX, and 10Base-T. This interface consists of four signal
pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and receive at
the same time. The MDI interface has internal termination resistors, and therefore reduces BOM cost and
PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same time. For
10/100M links and during auto-negotiation, only pairs A and B are used.
7.2. 1000Base-T Transmit Function
The 1000Base-T transmit function performs 8B/10B coding, scrambling, 4D-PAM5 encoding. These
code groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted
onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter.
7.3. 1000Base-T Receive Function
Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. The received signal is
processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.
The Rx MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the
packet buffer manager.
7.4. 100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven into the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also reduces EMI emissions.
Integrated Octal 10/100/1000M Ethernet Transceiver
17
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.5. 100Base-TX Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.
7.6. 10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.
7.7. 10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.
7.8. Auto-Negotiation for UTP
The RTL8218D obtains the states of duplex, speed, and flow control ability for each port in UTP mode
through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During autonegotiation, each port advertises its ability to its link partner and compares its ability with advertisements
received from its link partner. By default, the RTL8218D advertises full capabilities (1000full, 100full,
100half, 10full, 10half) together with flow control ability.
Integrated Octal 10/100/1000M Ethernet Transceiver
18
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.9. Crossover Detection and Auto Correction
The RTL8218D automatically determines whether or not it needs to crossover between pairs, so that an
external crossover cable is not required. When connecting to a device that does not perform MDI
crossover, the RTL8218D automatically switches its pin pairs to communicate with the remote device.
When connecting to a device that does have MDI crossover capability, an algorithm determines which
end performs the crossover function.
The crossover detection and auto correction function can be disabled via register configuration. The
RTL8218D is set to MDI Crossover by default. The pin mapping in MDI and MDI Crossover mode is
given below.
Pairs
A
B
C
D
Table 10. Media Dependent Interface Pin Mapping
MDI
MDI Crossover
1000Base-T
100Base-TX
10Base-T
1000Base-T
100Base-TX
A
TX
TX
B
RX
B
RX
RX
A
TX
C
Unused
Unused
D
Unused
D
Unused
Unused
C
Unused
10Base-T
RX
TX
Unused
Unused
7.10. Polarity Correction
The RTL8218D automatically corrects polarity errors on the receiver pairs in 1000Base-T and 10Base-T
modes. In 100Base-TX mode, the polarity is irrelevant.
In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle
symbols. Once the descrambler is locked, the polarity is also locked on all pairs. The polarity becomes
unlocked only when the receiver loses lock.
In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The
detection begins during the MDI crossover detection phase and locks when 10Base-T links up. The
polarity becomes unlocked when the link is down.
Link Partner
RTL8218D
+
RX _
+
_ TX
+
TX _
_
+
+
_ RX
Figure 7. Conceptual Example of Polarity Correction
Integrated Octal 10/100/1000M Ethernet Transceiver
19
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.11. MDC/MDIO Interface
The RTL8218D supports the IEEE compliant Management Data Input/Output (MDIO) Interface. This is
the only method for the MAC to acquire the status of the PHY. The Media Independent Interface
Management (MIIM) registers are written and read serially, using the MDC/MDIO pins. Data transferred
to and from the MDIO pins is synchronized with the MDC clock. All transfers are initiated by the MAC.
A clock of up to 8MHz must drive the MDC pin of the RTL8218D.
The MII register is a block of 32 registers, each 16 bits wide. Certain registers are defined by IEEE 802.3
and are required for compliance (0~10, 15).
The MDIO frame structure starts with a 32-bit preamble, which is required by the RTL8218D. The
following data includes a start-of-frame marker, an op-code, a 10-bit address field, and a 16-bit data field.
The address field is divided into two 5-bit segments. The first segment identifies the PHY address and the
second identifies the register being accessed.
The 5-bits of the PHY address are determined by the hardware strapping values during power up. The
MDIO protocol provides both read and write operations. During a write operation, the MAC drives the
MDIO line for the entire frame. For a read operation, a turn-around time is inserted in the frame to allow
the PHY to drive back to the MAC. The MDIO pin of the MAC must be put in high-impedance during
these bit times. Figure 8 and Figure 9 depict the MDIO read and write frame format respectively.
The RTL8218D is permanently programmed for preamble suppression. A preamble of 32 ‘1’ bits is
required only for the first read or write. The management preamble may be as short as 1 bit.
MDC
MDIO
(Read)
32“1”s
0
Preamble
1
1
0
A4
OP
Code
SFD
A0
R0
R4
PHY
Address
0
Z
Turn
Register
Address
D15
D1
D0
Idle
Data
Around
Figure 8. MDIO Read Frame Format
MDC
MDIO
(Write)
32“1”s
Preamble
0
1
SFD
0
1
OP
Code
A4
A0
PHY
Address
R4
R0
Register
Address
0
D15
Turn
Around
D1
Data
D0
Idle
Figure 9. MDIO Write Frame Format
Integrated Octal 10/100/1000M Ethernet Transceiver
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Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.12. Ten-Gigabit Media Independent Interface (XSGMII)
The XSGMII (Ten-Gigabit Media Independent Interface) reduces PCB complexity and IC pin count. This
innovative 10.3125 Gbps serial interface provides MAC to PHY communication path. XSGMII can carry
the full duplex gigabit Ethernet data streams of 8 ports simultaneously, using only 4 pins.
Port0
MAC
PHY
Port0
Port1
Port1
Port2
Port2
S0TXP/N
Port3
TX
TX
XSGMII
Port4
Port3
XSGMII
RX
RX
Port4
S0RXP/N
Port5
Port5
Port6
Port6
Port7
Port7
Figure 10. XSGMII Interconnection Diagram
Integrated Octal 10/100/1000M Ethernet Transceiver
21
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.13. Quad Serial Gigabit Media Independent Interface (QSGMII)
The QSGMII (Quad Serial Gigabit Media Independent Interface) reduces PCB complexity and IC pin
count. This innovative 5Gbps serial interface provides a MAC to PHY communication path. QSGMII can
carry the full duplex gigabit Ethernet data streams of four ports simultaneously, using only 4 pins.
Port0
MAC
PHY
Port0
S0TXP/N
Port1
TX
TX
QSGMII
Port2
Port1
QSGMII
RX
RX
Port2
S0RXP/N
Port3
Port3
Port4
Port4
S1TXP/N
Port5
TX
TX
QSGMII
Port6
Port5
QSGMII
RX
RX
Port6
S1RXP/N
Port7
Port7
Figure 11. QSGMII Interconnection Diagram
Integrated Octal 10/100/1000M Ethernet Transceiver
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Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.13.1.
XSGMII Interface
TX
RX
XSGMII
#0
(SerDes # 0)
MDI
#0
MDI
#1
MDI
#2
MDI
#3
MDI
#4
MDI
#5
MDI
#6
MDI
#7
MDI
#6
MDI
#7
Figure 12. [MDI x 8] + [XSGMII x 1]
7.13.2.
QSGMII Interface
TX
RX
TX
RX
QSGMII
#0
QSGMII
#1
(SerDes # 0)
(SerDes # 1)
MDI
#0
MDI
#1
MDI
#2
MDI
#3
MDI
#4
MDI
#5
Figure 13. [MDI x 8] + [QSGMII x 2]
Integrated Octal 10/100/1000M Ethernet Transceiver
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RTL8218D
Datasheet
7.14. Serial LED
7.14.1.
Port Status Indicator
The RTL8218D supports serial LED mode. In the serial LED mode, the data is clocked through a shift
register and the shifted symbols are output to the 36 LED pins. Each MDI port has three indicator
symbols and each fiber port has three indicator symbols. Each symbol may have different indicator
information
7.14.2.
LED Configuration
Table 11. Serial LED Per-LED Control
PHY0, Reg.30 = 8, Reg.=31=0x281
Reg.bit Name
18.[15:12] LED_00_Mode
Mode
RW
18.11
18.10
18.9
18.8
18.7
RW
RW
RW
RW
RW
18.6
RW
18.5
RW
18.4
18.3
18.2
18.1
RW
RW
RW
RW
18.0
RW
19[15:0]
LED_01_Mode
RW
Integrated Octal 10/100/1000M Ethernet Transceiver
Description
Assign LEDn to Port.
0000: MDI0
0001: MDI1
0010: MDI2
0011: MDI3
0100: MDI4
0101: MDI5
0110: MDI6
0111: MDI7
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100~1110: Reserved
1111: Disable
1000M Speed Indicator.
100M Speed Indicator.
10M Speed Indicator.
Reserved
1000M Activity Indicator. Act blinking when the
corresponding port is transmitting or receiving.
100M Activity Indicator. Act blinking when the
corresponding port is transmitting or receiving.
10M Activity Indicator. Act blinking when the
corresponding port is transmitting or receiving.
Reserved
Duplex Indicator.
Collision Indicator. Blinking when a collision occurs.
Tx Activity Indicator. Blinking when the corresponding
port is transmitting.
Rx Activity Indicator. Blinking when the corresponding
port is receiving.
Same as LED_00_Mode
24
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
Reg.bit
20[15:0]
21[15:0]
22[15:0]
23[15:0]
Name
LED_02_Mode
LED_03_Mode
LED_04_Mode
LED_05_Mode
Mode
RW
RW
RW
RW
Description
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Default
-
Mode
RW
RW
RW
RW
RW
RW
RW
RW
Description
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Default
-
Mode
RW
RW
RW
RW
RW
RW
RW
RW
Description
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Default
-
Mode
RW
RW
RW
RW
RW
RW
RW
RW
Description
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Default
-
PHY0, Reg.29 = 8, Reg.=31=0x282
Reg.bit
16[15:0]
17[15:0]
18[15:0]
19[15:0]
20[15:0]
21[15:0]
22[15:0]
23[15:0]
Name
LED_06_Mode
LED_07_Mode
LED_08_Mode
LED_09_Mode
LED_10_Mode
LED_11_Mode
LED_12_Mode
LED_13_Mode
PHY0, Reg.29 = 8, Reg.=31=0x283
Reg.bit
16[15:0]
17[15:0]
18[15:0]
19[15:0]
20[15:0]
21[15:0]
22[15:0]
23[15:0]
Name
LED_14_Mode
LED_15_Mode
LED_16_Mode
LED_17_Mode
LED_18_Mode
LED_19_Mode
LED_20_Mode
LED_21_Mode
PHY0, Reg.29 = 8, Reg.=31=0x284
Reg.bit
16[15:0]
17[15:0]
18[15:0]
19[15:0]
20[15:0]
21[15:0]
22[15:0]
23[15:0]
Name
LED_22_Mode
LED_23_Mode
LED_24_Mode
LED_25_Mode
LED_26_Mode
LED_27_Mode
LED_28_Mode
LED_29_Mode
Integrated Octal 10/100/1000M Ethernet Transceiver
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RTL8218D
Datasheet
PHY0, Reg.29 = 8, Reg.=31=0x285
Reg.bit
16[15:0]
17[15:0]
18[15:0]
19[15:0]
20[15:0]
21[15:0]
Name
LED_30_Mode
LED_31_Mode
LED_32_Mode
LED_33_Mode
LED_34_Mode
LED_35_Mode
Mode
RW
RW
RW
RW
RW
RW
Description
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Same as LED_00_Mode
Default
-
Table 12. Serial LED Mode Configuration (Per-Port 3 LEDs)
of Per-LED
LED_MODE LED_MODE LED_MODE LED_MODE
Register
[1:0]=11
[1:0]=10
[1:0]=01
[1:0]=00
LED35
0x0FF0
0x0880
0x0880
0x0FF0
LED34
0x1FF0
0x1880
0x1880
0x1FF0
LED33
0x2FF0
0x2880
0x2880
0x2FF0
LED32
0x3FF0
0x3880
0x3880
0x3FF0
LED31
0x4FF0
0x4880
0x4880
0x4FF0
LED30
0x5FF0
0x5880
0x5880
0x5FF0
LED29
0x6FF0
0x6880
0x6880
0x6FF0
LED28
0x7FF0
0x7880
0x7880
0x7FF0
LED27
0x0800
0x0440
0x0660
0x8CC0
LED26
0x1800
0x1440
0x1660
0x9CC0
LED25
0x2800
0x2440
0x2660
0xACC0
LED24
0x3800
0x3440
0x3660
0xBCC0
LED23
0x4800
0x4440
0x4660
0xF000
LED22
0x5800
0x5440
0x5660
0xF000
LED21
0x6800
0x6440
0x6660
0xF000
LED20
0x7800
0x7440
0x7660
0xF000
LED19
0x0400
0x0220
0x8880
0xF000
LED18
0x1400
0x1220
0x9880
0xF000
LED17
0x2400
0x2220
0xA880
0xF000
LED16
0x3400
0x3220
0xB880
0xF000
LED15
0x4400
0x4220
0x8440
0xF000
LED14
0x5400
0x5220
0x9440
0xF000
LED13
0x6400
0x6220
0xA440
0xF000
LED12
0x7400
0x7220
0xB440
0xF000
LED11
0x8CC0
0x8880
0xF000
0xF000
LED10
0x9CC0
0x9880
0xF000
0xF000
LED09
0xACC0
0xA880
0xF000
0xF000
LED08
0xBCC0
0xB880
0xF000
0xF000
LED07
0x8800
0x8440
0xF000
0xF000
LED06
0x9800
0x9440
0xF000
0xF000
LED05
0xA800
0xA440
0xF000
0xF000
LED04
0xB800
0xB440
0xF000
0xF000
LED03
0x8400
0xF000
0xF000
0xF000
Integrated Octal 10/100/1000M Ethernet Transceiver
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Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
of Per-LED
LED_MODE LED_MODE
Register
[1:0]=11
[1:0]=10
LED02
0x9400
0xF000
LED01
0xA400
0xF000
LED00
0xB400
0xF000
Notes:
LED_MODE [1:0]=11
MDI: [Link/Act] [SPD1000] [SPD100]
FX: [Link/Act] [SPD1000] [SPD100]
LED_MODE
[1:0]=01
0xF000
0xF000
0xF000
LED_MODE
[1:0]=00
0xF000
0xF000
0xF000
LED_MODE [1:0]=10
MDI: [SPD1000/Act] [SPD100/Act] [SPD10/Act]
FX: [SPD1000/Act] [SPD100/Act] [Disable]
LED_MODE [1:0]=01
MDI: [SPD1000/Act] [SPD100(10)/Act]
FX: [SPD1000/Act] [SPD100/Act]
LED_MODE [1:0]=00
MDI: [Link/Act]
FX: [Link/Act]
7.14.3.
Serial LED Configuration Register
Table 13. Serial LED Configuration Register
PHY0, Reg.29 = 8, Reg.=31=0x280
Reg.bit
16[15:14]
16[13:12]
Name
Reserved
cfg_led_mode
Mode
RW
RW
16[11]
16[10:8]
Reserved
Serial Blink Rate
RW
RW
16[7:6]
serial led burst cycle
RW
Integrated Octal 10/100/1000M Ethernet Transceiver
Description
Reserved
00: LED_Mode0. Per-Port 2 LEDs
01: LED_Mode1. Per-Port 2 LEDs
10: LED_Mode2. Per-Port 3 LEDs
11: LED_Mode3. Per-Port 3 LEDs
Reserved
LED Blink Rate Configuration.
000: 32ms
001: 64ms
010: 128ms
011: 256ms
100: 512ms
101: 1024ms
110: 48ms
111: 96ms
2'b00: 8 (ms)
2'b01: 16
2'b10: 32
2'b11: 64
27
Default
00
11
0
000
10
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
Reg.bit
16[5:4]
Description
Default
2'b00: 32 (ns)
11
2'b01: 64
2'b10: 96
2'b11: 192
16[3]
led_seri_active_low
RW
Serial LED active LOW
1
0: LED status active high
1: LED status active low
16[2]
led_seri_disable
RW
Disable Serial LED.
1: Disable
0: Enable
Default by strapping option (pin-30)
16[1]
led_data_e_b
RW
Serial LED DATA_EN
16[0]
led_clk_e_b
RW
Serial LED CLK_EN
Note: Upon reset, the RTL8218D supports chip diagnostics and LED functions by blinking all LEDs once via the
LED_PowerOn_Light strapping pin configuration.
7.14.4.
Name
serial led clock cycle
Mode
RW
Serial LED Timing Definitions
T2
T1
…
LEDCK
…
T3
LEDDA
LED
35
LED
34
LED
33
…
LED
02
LED
01
LED
35
LED
00
LED
34
LED
33
…
LED
02
LED
01
LED
00
Figure 14. Serial LED Timing Definitions
7.15. Realtek Cable Test (RTCT)
The RTL8218D physical layer transceivers use DSP technology to implement the Realtek Cable Test
(RTCT) feature. The RTCT function could be used to detect short, open, crossed, or impedance mismatch
in each differential pair.
Integrated Octal 10/100/1000M Ethernet Transceiver
28
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.16. IEEE 802.3az Energy Efficient Ethernet (EEE)
The RTL8218D supports IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T and 100BaseTX in full duplex operation.
The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access
Control (MAC) sub-layer with 100Base-T and 1000Base-T Physical Layers defined to support operation
in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the link can
disable portions of the functionality and save power during periods of low link utilization.
For 1000Base-T: Supports Energy Efficient Ethernet with the optional function of Low Power Idle
For 100Base-TX: Supports Energy Efficient Ethernet with the optional function of Low Power Idle
7.17. Interrupt Pin for External CPU
The RTL8218D provides one Interrupt output pin to interrupt an external CPU for 10/100/1000Base-T
ports. The polarity of the Interrupt output pin can be configured via register access. In configuration
registers, each port has link-up and link-down interrupt flags with mask.
When port link-up or link-down interrupt mask is enabled, the RTL8218D will raise the interrupt signal
to alarm the external CPU. The CPU can read the interrupt flag to determine which port has changed to
which status.
7.18. Reg.0.11 Power Down Mode
The RTL8218D implements power down mode on a per-port basis. Setting MII Reg.0.11 forces the
corresponding port of the RTL8218D to enter power down mode.
Integrated Octal 10/100/1000M Ethernet Transceiver
29
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
7.19. Reg.0.14 PHY Digital Loopback Return to Internal
The digital loopback mode of the PHY (return to MAC) may be enabled on a per-port basis by setting
MII Reg.0.14 to 1. In digital loopback mode, the TXD of the PHY is transferred directly to the RXD of
the PHY, with TXEN changed to CRS_DV, and returns to the MAC via an internal MII. The data stream
coming from the MAC will not egress to the physical medium, and an incoming data stream from the
network medium will be blocked in this mode. The packets will be looped back in 10Mbps, 100Mbps,
and 1000Mbps in full duplex mode. This function is useful for diagnostic purposes.
Loopback Return to MAC
PHY
RTL8218D
MAC
XSGMII
Figure 15. Reg.0.14 PHY Digital Loopback
As the RTL8218D only supports digital loopback in full duplex mode, PHY Reg.0.8 for each port will be
always kept to 1 when digital loopback is enabled. In loopback mode, the link LED of the loopback port
should be always turned on, and the speed combined with the duplex LED will reflect the link status
(1000full/100full/10full) correctly regardless of what the previous status of this loopback port was.
Integrated Octal 10/100/1000M Ethernet Transceiver
30
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.
Register Descriptions
Registers 0~15 of the MII are defined by the MII specification. Other registers are defined by Realtek
Semiconductor Corp. for internal use and are reserved.
The following abbreviations are used in this section:
RW: Read/Write
RO: Read Only
LL: Latch Low until clear
LH: Latch High until clear
Page
0
Register
0
1
2
3
4
5
6
7
8
9
10
11~14
13
14
15
16~30
SC: Self Clearing
Table 14. Register Descriptions
Description
Control
Status
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next Page Transmit
Auto-Negotiation Link Partner Next Page Ability
1000Base-T Control
1000Base-T Status
Reserved
1000Base-T MMD Access Control
1000Base-T MMD Access Address Data
Extended Status
ASIC Control
Integrated Octal 10/100/1000M Ethernet Transceiver
31
Default
0x1140
0x7989
0x001C
0xC983
0x05E1
0x0000
0x0064
0x2001
0x0000
0x0E00
0x0000
0x0000
0x0000
0x0000
0x2000
-
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.1. Register 0: Control
Reg.bit
0.15
Name
Reset
0.14
Loopback
(Digital loopback)
0.13
Speed Selection[0]
0.12
Auto Negotiation Enable
0.11
Power Down
0.10
Isolate
0.9
Restart Auto Negotiation
0.8
Duplex Mode
0.7
Collision Test
0.6
0.[5:0]
Speed Selection[1]
Reserved
Table 15. Register 0: Control
Mode Description
RW/SC 1: PHY reset
0: Normal operation
This bit is self-clearing.
RW
1: Enable loopback (this will loopback TXD to RXD and
ignore all activity on the cable media)
0: Normal operation
This function is usable only when this PHY is operated in
10Base-T full duplex, 100Base-TX full duplex, or
1000Base-T full duplex.
RW
[0.6, 0.13] Speed Selection [1:0].
11: Reserved
10: 1000Mbps
01: 100Mbps
00: 10Mbps
This bit can be set through SMI (Read/Write).
RW
1: Enable auto-negotiation process
0: Disable auto-negotiation process
This bit can be set through SMI (Read/Write).
RW
1: Power down (all functions will be disabled except SMI
function)
0: Normal operation
RW
1: Electrically isolates the PHY from QGMII (PHY still
responds to MDC/MDIO)
0: Normal operation
RW/SC 1: Restart Auto-Negotiation process
0: Normal operation
RW
1: Full duplex operation
0: Half duplex operation
This bit can be set through SMI (Read/Write).
RO
1: Collision test enabled
0: Normal operation
When set, this bit will cause the COL signal to be asserted
in response to the assertion of TXEN within 512-bit times.
The COL signal will be de-asserted within 4-bit times in
response to the de-assertion of TXEN.
RW
See Bit 13.
RO
Reserved.
Integrated Octal 10/100/1000M Ethernet Transceiver
32
Default
0
0
0
1
0
0
0
1
0
1
000000
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.2. Register 1: Status
Reg.bit
1.15
Name
100Base-T4
1.14
100Base-TX-FD
1.13
100Base-TX-HD
1.12
10Base-T-FD
1.11
10Base-T-HD
1.10
100Base-T2-FD
1.9
100Base-T2-HD
1.8
Extended Status
1.7
1.6
Reserved
MF Preamble Suppression
1.5
Auto-negotiate Complete
1.4
Remote Fault
1.3
Auto-Negotiation Ability
1.2
Link Status
1.1
Jabber Detect
1.0
Extended Capability
Table 16. Register 1: Status
Mode Description
RO
0: No 100Base-T4 capability
The RTL8218D does not support 100Base-T4 mode, and this
bit should always be 0.
RO
1: 100Base-TX full duplex capable
0: Not 100Base-TX full duplex capable
RO
1: 100Base-TX half duplex capable
0: Not 100Base-TX half duplex capable
RO
1: 10Base-T full duplex capable
0: Not 10Base-TX full duplex capable
RO
1: 10Base-T half duplex capable
0: Not 10Base-TX half duplex capable
RO
0: No 100Base-T2 full duplex capability
The RTL8218D does not support 100Base-T2 mode, and this
bit should always be 0.
RO
0: No 100Base-T2 half duplex capability
The RTL8218D does not support 100Base-T2 mode, and this
bit should always be 0.
RO
1: Extended status information in Register 15
The RTL8218D always supports Extended Status Register.
RO
Reserved.
RO
The RTL8218D will accept management frames with
preamble suppressed.
RO
1: Auto-negotiation process completed
0: Auto-negotiation process not completed
RO/ 1: Remote fault indication from link partner has been detected
LH
0: No remote fault indication detected
This bit will remain set until it is cleared by reading register 1
via the management interface.
RO
1: Auto-negotiation capable (permanently=1)
0: No Auto-negotiation capability
RO/ 1: Link has not failed since previous read
LL
0: Link has failed since previous read
If the link fails, this bit will be set to 0 until this bit is read.
RO/ 1: Jabber detected
LH
0: No Jabber detected
Jabber is supported only in 10Base-T mode.
RO
1: Extended register capable (permanently=1)
0: Not extended register capable
Integrated Octal 10/100/1000M Ethernet Transceiver
33
Default
0
1
1
1
1
0
0
1
1
0
0
0
1
0
0
1
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.3. Register 2: PHY Identifier 1
The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY part of this device.
The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's
model number, and the model revision number. A PHY may return a value of zero in each of the 32 bits
of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
Reg.bit
2.[15:0]
Name
OUI
Table 17. Register 2: PHY Identifier 1
Mode Description
RO
Composed of the 3rd to 18th Bits of the Organizationally Unique
Identifier (OUI), Respectively.
Default
0x001C
8.4. Register 3: PHY Identifier 2
Reg.bit
3.[15:10]
3.[9:4]
3.[3:0]
Name
OUI
Model Number
Revision Number
Table 18. Register 3: PHY Identifier 2
Mode Description
RO
Assigned to the 19th through 24th Bits of the OUI.
RO
Manufacturer’s Model Number.
RO
Manufacturer’s Revision Number.
Default
110010
011000
0011
8.5. Register 4: Auto-Negotiation Advertisement
This register contains the advertisement abilities of this device as they will be transmitted to its Link
Partner during Auto-negotiation.
Note: Each time the link ability of the RTL8218D is reconfigured, the auto-negotiation process should be
executed to allow the configuration to take effect.
Reg.bit
4.15
4.14
4.13
4.12
4.11
4.10
4.9
4.8
Table 19. Register 4: Auto-Negotiation Advertisement
Name
Mode Description
Next Page
RO
1: Additional next pages exchange desired
0: No additional next pages exchange desired
Acknowledge
RO
Permanently=0.
Remote Fault
RW 1: Advertises that the RTL8218D has detected a remote fault
0: No remote fault detected
Reserved
RO
Reserved.
Asymmetric Pause
RW 1: Advertises that the RTL8218D has asymmetric flow control
capability
0: No asymmetric flow control capability
Pause
RW 1: Advertises that the RTL8218D has flow control capability
0: No flow control capability
100Base-T4
RO
1: 100Base-T4 capable
0: Not 100Base-T4 capable (permanently=0)
100Base-TX-FD
RW 1: 100Base-TX full duplex capable
0: Not 100Base-TX full duplex capable
Integrated Octal 10/100/1000M Ethernet Transceiver
34
Default
0
0
0
0
0
1
0
1
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
Reg.bit
4.7
Name
100Base-TX
Mode Description
RW 1: 100Base-TX half duplex capable
0: Not 100Base-TX half duplex capable
4.6
10Base-T-FD
RW 1: 10Base-TX full duplex capable
0: Not 10Base-TX full duplex capable
4.5
10Base-T
RW 1: 10Base-TX half duplex capable
0: Not 10Base-TX half duplex capable
4.[4:0] Selector Field
RO
00001: IEEE 802.3
Note 1: This Register 4 setting has no effect unless auto-negotiation is restarted or link down.
Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted.
Default
1
1
1
00001
8.6. Register 5: Auto-Negotiation Link Partner Ability
This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The
content changes after a successful Auto-negotiation.
Reg.bit
5.15
5.14
5.13
5.12
5.11
5.10
5.9
5.8
5.7
5.6
5.5
5.[4:0]
Table 20. Register 5: Auto-Negotiation Link Partner Ability
Name
Mode Description
Next Page
RO
1: Link partner desires Next Page transfer
0: Link partner does not desire Next Page transfer
Acknowledge
RO
1: Link Partner acknowledges reception of Fast Link Pulse (FLP)
0: Not acknowledged by Link Partner
Remote Fault
RO
1: Remote Fault indicated by Link Partner
0: No remote fault indicated by Link Partner
Reserved
RO
Technology Ability Field.
Received code word bit 12.
Asymmetric Pause
RO
1: Asymmetric Flow control supported by Link Partner
0: No Asymmetric flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link Partner
ability (Read only).
Pause
RO
1: Flow control supported by Link Partner
0: No flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link Partner
ability (Read only).
100Base-T4
RO
1: 100Base-T4 supported by Link Partner
0: 100Base-T4 not supported by Link Partner
100Base-TX-FD
RO
1: 100Base-TX full duplex supported by Link Partner
0: 100Base-TX full duplex not supported by Link Partner
100Base-TX
RO
1: 100Base-TX half duplex supported by Link Partner
0: 100Base-TX half duplex not supported by Link Partner
10Base-T-FD
RO
1: 10Base-TX full duplex supported by Link Partner
0: 10Base-TX full duplex not supported by Link Partner
10Base-T
RO
1: 10Base-TX half duplex supported by Link Partner
0: 10Base-TX half duplex not supported by Link Partner
Selector Field
RO
00001: IEEE 802.3
Integrated Octal 10/100/1000M Ethernet Transceiver
35
Default
0
0
0
0
0
0
0
0
0
0
0
00000
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.7. Register 6: Auto-Negotiation Expansion
Reg.bit
6.[15:7]
6.6
6.5
6.4
6.3
6.2
6.1
6.0
Table 21. Register 6: Auto-Negotiation Expansion
Name
Mode Description
Reserved
RO
Ignore On Read.
Receive Next Page
RO
1: Received next page storage location is
Location
specified by bit (6.5)
Able
0: Received next page storage location is
not specified by bit (6.5)
Received Next Page
RO
1: Link Partner next pages are stored in
Storage
Register 8
Location
0: Link Partner next pages are stored in
Register 5
Parallel Detection Fault
RO/LH 1: A fault has been detected via the Parallel Detection
function
0: No fault has been detected via the Parallel Detection
function
Link Partner Next Page
RO
1: Link Partner is Next Page able
Ability
0: Link Partner is not Next Page able
Local Next Page Ability
RO
1: RTL8218D is Next Page able
Page Received
RO/LH 1: A New Page has been received
0: A New Page has not been received
Link Partner AutoRO
If Auto-Negotiation is Enabled, this bit means:
Negotiation Ability
1: Link Partner is Auto-Negotiation able
0: Link Partner is not Auto-Negotiation able
Default
0
1
1
0
0
1
0
0
8.8. Register 7: Auto-Negotiation Next Page Transmit
Reg.bit
7.15
7.14
7.13
7.12
7.11
7.[10:0]
Table 22. Register 7: Auto-Negotiation Next Page Transmit
Mode Description
RW
1: Another next page desired
0: No other next page to send
Reserved
RO
1: A fault has been detected via the Parallel Detection
function
0: No fault has been detected via the Parallel Detection
function
Message Page
RW
1: Message page
Acknowledge 2
RW
1: Local device has the ability to comply with the message
received
0: Local device has no ability to comply with the message
received
Toggle
RO
Toggle Bit.
Message/Unformatted Field
RW
Content of Message/Unformatted Page.
Name
Next Page
Integrated Octal 10/100/1000M Ethernet Transceiver
36
Default
0
0
1
0
0
000000
00001
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.9. Register 8: Auto-Negotiation Link Partner Next Page Ability
Reg.bit
8.15
8.14
8.13
8.12
8.11
8.[10:0]
Table 23. Register 8: Auto-Negotiation Link Partner Next Page Ability
Name
Mode Description
Next Page
RO
Received Link Code Word Bit 15.
Acknowledge
RO
Received Link Code Word Bit 14.
Message Page
RO
Received Link Code Word Bit 13.
Acknowledge 2
RO
Received Link Code Word Bit 12.
Toggle
RO
Received Link Code Word Bit 11.
Message/Unformatted Field
RO
Received Link Code Word Bit 10:0.
Default
0
0
0
0
0
0
8.10. Register 9: 1000Base-T Control
Table 24. Register 9: 1000Base-T Control
Mode Description
RW
Test Mode Select.
000: Normal mode
001: Test mode 1–Transmit waveform test
010: Test mode 2–Transmit jitter test in MASTER mode
011: Test mode 3–Transmit jitter test in SLAVE mode
100: Test mode 4–Transmitter distortion test
101, 110, 111: Reserved
MASTER/SLAVE Manual
RW
1: Enable MASTER/SLAVE manual configuration
Configuration Enable
0: Disable MASTER/SLAVE manual configuration
MASTER/SLAVE
RW
1: Configure PHY as MASTER during MASTER/SLAVE
Configuration Value
negotiation, only when 9.12 is set to logical one
0: Configure PHY as SLAVE during MASTER/SLAVE
negotiation, only when 9.12 is set to logical one
Port Type
RW
1: Multi-port device
0: Single-port device
1000Base-T Full-Duplex
RW
1: Advertise PHY is 1000Base-T Full-Duplex capable
0: Advertise PHY is not 1000Base-T Full-Duplex capable
1000Base-T Half-Duplex
RW
1: Advertise PHY is 1000Base-T Half-Duplex capable
0: Advertise PHY is not 1000Base-T Half-Duplex capable
Reserved
RW
Reserved.
Reg.bit Name
9.[15:13] Test Mode
9.12
9.11
9.10
9.9
9.8
9.[7:0]
Integrated Octal 10/100/1000M Ethernet Transceiver
37
Default
000
0
1
1
1
0
0
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.11. Register 10: 1000Base-T Status
Reg.bit
10.15
10.14
10.13
10.12
10.11
10.10
10.[9:8]
10.[7:0]
Table 25. Register 10: 1000Base-T Status
Name
Mode Description
MASTER/SLAVE
RO/LH/ 1: MASTER/SLAVE configuration fault detected
Configuration Fault
SC
0: No MASTER/SLAVE configuration fault detected
MASTER/SLAVE
RO
1: Local PHY configuration resolved to MASTER
Configuration Resolution
0: Local PHY configuration resolved to SLAVE
Local Receiver Status
RO
1: Local receiver OK
0: Local receiver not OK
Remote Receiver Status
RO
1: Remote receiver OK
0: Remote receiver not OK
Link Partner 1000Base-T
RO
1: Link partner is capable of 1000Base-T Full-Duplex
Full-Duplex
0: Link partner is not capable of 1000Base-T Full-Duplex
1000Base-T Half-Duplex
RO
1: Link partner is capable of 1000Base-T Half-Duplex
0: Link partner is not capable of 1000Base-T Half-Duplex
Reserved
RO
Reserved.
Idle Error Count
RO/SC Idle Error Counter.
The counter stops automatically when it reaches 0xFF.
Default
0
0
0
0
0
0
0
0
8.12. Register 13: MMD Access Control Register
Reg.bit Name
13.[15:14] Function
13.[13:5] Reserved
13.[4:0] MMD DEVAD
Table 26. Register 13: MMD Access Control Register
Mode Description
RW
13.[15:14]
00: Address
01: Data, no post increment
10: Data, post increment on read and writes
11: Data, post increment on writes only
RW
Write as 0, ignore on read
RW
Device address
Integrated Octal 10/100/1000M Ethernet Transceiver
38
Default
0
0
0
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
8.13. Register 14: MMD Access Address Data Register
Table 27. Register 14: MMD Access Address Data Register
Reg.bit Name
Mode Description
13.[15:10] MMD Address Data
RW
If 13.[15:14] = 00, MMD DEVAD’s address register.
Otherwise, MMD DEVAD’s data register as indicated by
the content of its address register
Default
0
8.14. Register 15: Extended Status
Table 28. Register 15: Extended Status
Reg.bit Name
Mode Description
15.15
1000Base-X Full-Duplex
RO
1: 1000Base-X Full-Duplex capable
0: Not 1000Base-X Full-Duplex capable
15.14
1000Base-X Half-Duplex
RO
1: 1000Base-X Half-Duplex capable
0: Not 1000Base-X Half-Duplex capable
15.13
1000Base-T Full-Duplex
RO
1: 1000Base-T Full-Duplex capable
0: Not 1000Base-T Full-Duplex capable
15.12
1000Base-T Half-Duplex
RO
1: 1000Base-T Half-Duplex capable
0: Not 1000Base-T Half-Duplex capable
15.[11:0] Reserved
RO
Reserved.
Integrated Octal 10/100/1000M Ethernet Transceiver
39
Default
0
0
1
0
0
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
9.
Electrical Characteristics
9.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability may be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 29. Absolute Maximum Ratings
Parameter
Min
Junction Temperature (Tj)
Storage Temperature
-45
DVDDIO, AVDDH Supply Voltage Referenced to GND
GND-0.3
DVDDL, AVDDL, SVDDL, PLLVDDL Supply Voltage
GND-0.3
Referenced to GND
Digital Input Voltage
GND-0.3
Max
+125
+125
+3.63
Units
C
C
V
+1.21
V
VDDIO+0.3
V
9.2. Operating Range
Table 30. Operating Range
Parameter
Min
Ambient Operating Temperature (Ta)
0
DVDDIO, AVDDH Supply Voltage Range
3.135
DVDDL, AVDDL, SVDDL, PLLVDDL Supply Voltage Range
1.05
Integrated Octal 10/100/1000M Ethernet Transceiver
40
Typ
3.3
1.1
Max
70
3.465
1.2
Units
C
V
V
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
9.3. Power Consumption
Table 31. XSGMII Mode Power Consumption
Parameter
Symbol
Min
Typ
System Idle (All ports are in link-down state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
35
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
411
1000Base-T Active (8 1000base-T Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
452
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
1583
EEE 1000Base-T Linkup (8 1000base-T Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
36
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
532
100Base-TX Active (8 100base-TX Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
150
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
646
EEE 100Base-TX Linkup (8 100base-TX Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
34
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
490
10Base-T Active (8 10base-T Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
319
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
450
DVDDIO=3.3V
TTL Input High Voltage
VIH
2.0
TTL Input Low Voltage
VIL
Output High Voltage
VOH
2.7
Output Low Voltage
VOL
Note: DVDDIO=3.3V, AVDDH=3.3V, DVDDL=1.10V, AVDDL=1.10V, SVDDL=1.10V.
Integrated Octal 10/100/1000M Ethernet Transceiver
41
Max
Units
-
mA
mA
-
mA
mA
-
mA
mA
-
mA
mA
-
mA
mA
-
mA
mA
0.7
0.6
V
V
V
V
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
Table 32.QSGMII Mode Power Consumption
Symbol
Min
Typ
System Idle (All ports are in link-down state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
40
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
548
1000Base-T Active (8 1000base-T Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
468
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
1665
EEE 1000Base-T Linkup (8 1000base-T Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
40
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
664
100Base-TX Active (8 100base-TX Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
155
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
781
EEE 100Base-TX Linkup (8 100base-TX Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
40
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
621
10Base-T Active (8 10base-T Ports are in link-up state)
Power Supply Current for VDDH
IDVDDIO, IAVDDH, ISVDDH
315
Power Supply Current for VDDL
IDVDDL, IAVDDL, ISVDDL, IPLLVDDL
607
DVDDIO=3.3V
TTL Input High Voltage
VIH
2.0
TTL Input Low Voltage
VIL
Output High Voltage
VOH
2.7
Output Low Voltage
VOL
Note: DVDDIO=3.3V, AVDDH=3.3V, DVDDL=1.10V, AVDDL=1.10V, SVDDL=1.10V.
Parameter
Integrated Octal 10/100/1000M Ethernet Transceiver
42
Max
Units
-
mA
mA
-
mA
mA
-
mA
mA
-
mA
mA
-
mA
mA
-
mA
mA
0.7
0.6
V
V
V
V
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
9.4. IEEE 10/100/1000Base-T Specifications
Table 33. IEEE 10/100/1000Base-T Specifications
Parameter
Min
Typ
Max
Units
670
670
-
724.5
726.0
0.467
0.47
820
820
1
2
mV
mV
%
%
-
0.66
2
%
73.1
73.1
-
85.4
826
8.5
46.4
10
50
%
%
mV
mV
950
-950
0.98
3
3
3
3
-
1017
-1017
1.001
3.56
3.51
3.54
3.48
70.2
70.1
0.8
1.1
0.62
0.61
80
1050
-1050
1.02
5
5
5
5
500
500
5
5
1.4
1.4
500
mV
mV
ns
ns
ns
ns
ps
ps
%
%
ns
ns
ps
8
2.2
-
16
2.57
1.7
8.2
11.73
0.9
1.2
1.3
23.55
24
2.8
11
22
22
16
40
40
50
ms
V
ns
ns
ns
ns
ns
ns
mV
1000Base-T
Peak Voltage of Point A
Peak Voltage of Point B
Difference between the Peak Voltage of Point A and Point B
Difference between the Peak Voltage of Point C and 0.5 Times the Average of the Peak
Voltage of Points A and B
Difference between the Peak Voltage of Point D and 0.5 Times the Average of the Peak
Voltage of Points A and B
Droop of Point G
Droop of Point J
Transmitter Distortion
Common Mode Output Voltage
100Base-TX
Peak Voltage (+Vout)
Peak Voltage (-Vout)
Amplitude Symmetry
Rise Time (+Vout)
Rise Time (-Vout)
Fall Time (+Vout)
Fall Time (-Vout)
Rise/Fall Symmetry (+Vout)
Rise/Fall Symmetry (-Vout)
Overshoot (+Vout)
Overshoot (-Vout)
Transmit Jitter (+Vout)
Transmit Jitter (-Vout)
Distortion (Duty Cycle)
10Base-T
Link Pulse Timing
Differential Voltage
Peak-to-Peak Normal Jitter with Cable
Peak-to-Peak 8.0 BT Jitter with Cable
Peak-to-Peak 8.5 BT Jitter with Cable
Peak-to-Peak Normal Jitter without Cable
Peak-to-Peak 8.0 BT Jitter without Cable
Peak-to-Peak 8.5 BT Jitter without Cable
Common Mode Output Voltage
Integrated Octal 10/100/1000M Ethernet Transceiver
43
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
9.5.
XSGMII Characteristics
9.5.1.
Symbol
UI
VTX-DIFFp-p
TJ
RTX
9.5.2.
Symbol
UI
VRX-DIFFp-p
RRX
9.5.3.
XSGMII Differential Transmitter Characteristics
Table 34. XSGMII Differential Transmitter Characteristics
Parameter
Min
Typ
Max
Units
Unit Interval
97
ps
Output Differential Voltage
400
900
mV
Output Jitter
0.28
UI
Differential Resistance
100
ohm
XSGMII Differential Receiver Characteristics
Table 35. QSGMII Differential Receiver Characteristics
Parameter
Min
Typ
Max
Units
Unit Interval
97
ps
Input Differential Voltage
200
950
mV
Differential Resistance
100
ohm
Notes
-
QSGMII Differential Transmitter Characteristics
Table 36 QSGMII Differential Transmitter Characteristics
Parameter
Symbol
Min
Typ
Unit Interval
UI
199.94
200
Output Offset Voltage
VTX-OFFSET
600
800
Output Differential Voltage
VTX-DIFFp-p
400
700
Output Total Jitter
T_TJ
-
9.5.4.
Notes
-
Max
200.06
1000
900
0.35
Units
ps
mV
mV
UI
Max
200.06
950
-
Units
ps
mV
ohm
QSGMII Differential Receiver Characteristics
Parameter
Unit Interval
Input Differential Voltage
Differential Resistance
Table 37 QSGMII Differential Receiver Characteristics
Symbol
Min
Typ
UI
199.94
200
VRX-DIFFp-p
200
RRX
100
Integrated Octal 10/100/1000M Ethernet Transceiver
44
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
9.6.
XTALI Clock Characteristics
Table 38. XTALI Clock Characteristics
Parameter
Min
Typ
Max
Units
Frequency of XTALI
25
MHz
Frequency Tolerance of XTALI
-50
+50
ppm
Duty Cycle of XTALI
40
60
%
Rise Time of XTALI
12.5
ns
Fall Time of XTALI
12.5
ns
Note: PLL generated clocks are not recommended as input to XTALI since they can have excessive jitter. Zero delay
buffers are also not recommended for the same reason.
9.7. Power and Reset Characteristics
T3
DVDDL
AVDDL
SVDDL
T1
T4
DVDDIO
AVDDH
T2
nRESET
Figure 16. Power and Reset Characteristics
Parameter
Reset Delay Time
Reset Low Time
VDDL Power Rise Settling
Time
VDDH Power Rise Settling
Time
Table 39. Power and Reset Characteristics
SYM Description/Condition
Type
t1
The duration from ‘all power steady’ to
I
the reset signal released to high
t2
The duration of reset signal remaining
I
low time before issuing a reset to the
RTL8218D
t3
DVDDL, AVDDL, and SVDDL power
I
rise settling time
t4
DVDDIO, and AVDDH power rise
I
settling time
Integrated Octal 10/100/1000M Ethernet Transceiver
45
Min
10
Typical
-
Max
-
Units
ms
10
-
-
ms
1
-
-
ms
1
-
-
ms
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
9.8. MDC/MDIO Interface Characteristics
The RTL8218D supports the IEEE compliant Management Data Input/Output (MDIO) Interface. This is
the only method for the MAC to acquire the status of the PHY. The MDIO is a bi-directional signal that
can be sourced by the Master or the Slave. In a write command, the master sources the MDIO signal. In
a read command, the slave sources the MDIO signal.
The timing characteristics t1, t2, and t3 (Figure 17) of the Master (MAC) are provided by the Master
when the Master sources the MDIO signal (Write command)
The timing characteristics t4 (Figure 18) of the Slave (RTL8218D) are provided by the RTL8218D
when the RTL8218D sources the MDIO signal (Read command)
t1
VIH
MDC
VIL
VIH
MDIO
VIL
t2
t3
Figure 17. MDIO Sourced by Master (MAC)
VIH
MDC
VIL
VIH
MDIO
VIL
t4
Figure 18. MDIO Sourced by RTL8218D (Slave)
Table 40. MDIO Timing Characteristics and Requirement
Parameter
SYM
Description/Condition
Type Min
MDC Clock Period
t1
Clock Period
I
125
MDIO to MDC Rising Setup
t2
Input Setup Time
I
10
Time (Write Data)
MDIO to MDC Rising Hold
t3
Input Hold Time
I
10
Time (Write Data)
MDC to MDIO Delay Time
t4
Clock (Rising Edge) to Data
O
20
(Read Data)
Delay Time
Integrated Octal 10/100/1000M Ethernet Transceiver
46
Typical
-
Max
-
Units
ns
-
-
ns
-
-
ns
-
100
ns
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
9.9.
LED Characteristics
9.9.1.
Serial LED Timing
T2
T1
LEDCK
T3
Figure 19. Serial LED Timing
Symbol
T1
T2
T3
Table 41. Serial LED Timing
Description
Min
Serial LED Clock Cycle Time
Serial LED Clock On/Off Duration
Serial LED Burst Cycle Time
-
Integrated Octal 10/100/1000M Ethernet Transceiver
47
Typ
192
6.82
32
Max
-
Units
ns
us
ms
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
Thermal Characteristics
10.
10.1. Assembly Description
Package
PCB
Heat Sink
Table 42. Assembly Description
Type
E-Pad LQFP-128
Dimension (L×W)
14×20mm
Thickness
1.4mm
PCB Dimension (L×W)
273×156.6mm
PCB Thickness
1.6mm
Number of Cu Layer-PCB
4-Layer (2S2P)
35.8 x 35 x 28 mm3
10.2. Material Properties
Item
Package
Die
Silver Paste
Lead Frame
Mold Compound
PCB
Table 43. Material Properties
Material
Thermal Conductivity K (W/m-k)
Si
147
1.0
1033BF
CDA7025
168
G631
0.9
Cu
400
FR4
0.2
10.3. Simulation Conditions
Table 44. Simulation Conditions
3.1W
4L (2S2P)
Air Flow = 0m/s
Input Power
Test Board (PCB)
Control Condition
Integrated Octal 10/100/1000M Ethernet Transceiver
48
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
10.4. Thermal Performance of E-Pad LQFP-128 on PCB under
Still Air Convention
Table 45. Thermal Performance of E-Pad LQFP-128 on PCB under Still Air Convention
PCB Layer
θJA
θJC
ΨJT
4L PCB
14.3
7.3
3.3
.
10.5. Thermal Performance of E-Pad LQFP-128 with External
Heat-Sink on PCB under Natural Convention
External Heat-Sink size: 100 x 24.5 x 20.3 mm3
Table 46. Thermal Performance of E-Pad LQFP-128 with External Heat-Sink on
PCB under Natural Convention
PCB Layer
θJA
θJC
ΨJT
ΨJB
4L PCB
10.7
6.2
8.5
Note:
θJA: Junction to ambient thermal resistance.
ΨJT: Junction to top center of package thermal characterization.
ΨJB: Junction to bottom surface center of PCB thermal characterization.
.
Integrated Octal 10/100/1000M Ethernet Transceiver
49
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
11.
Mechanical Dimensions
11.1. LQFP-128 E-PAD Package
11.2. Mechanical Dimensions Notes
Symbol
Dimension in mm
Min
Nom
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
b
0.17
0.2
0.27
D
22.00 BSC
D1
20.00 BSC
D2/E2
5.6
6.55
7.50
E
16.00BSC
E1
14.00BSC
e
0.50BSC
L
0.45
0.60
0.75
L1
1.00 REF
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MS-26.
Integrated Octal 10/100/1000M Ethernet Transceiver
Min
—
0.002
0.053
0.007
0.220
0.018
50
Dimension in inch
Nom
—
—
0.055
0.009
0.866 BSC
0.787 BSC
0.258
0.630BSC
0.551BSC
0.020BSC
0.024
0.039 REF
Max
0.063
0.006
0.057
0.011
0.295
0.030
Track ID: JATR-8275-15 Rev. 1.0
RTL8218D
Datasheet
12.
Ordering Information
Table 47. Ordering Information
Part Number
Package
RTL8218D-CG
LQFP-128 EPAD Green Package
Note: See page 8 for package identification information.
Status
Mass Production
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II,
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
Integrated Octal 10/100/1000M Ethernet Transceiver
51
Track ID: JATR-8275-15 Rev. 1.0
工商网监
湘ICP备2023018690号
