CAN5119

tia l en fid C on ek Rev 1.1 April 1, 2014 C an aa nT CAN5119 Product Description This datasheet is intended for customer’s evaluation and application of the CAN5119 device. Under no circumstances it should be circulated outside the customer’s company. This datasheet is preliminary and CanaanTek reserves the right to modify and to improve the data. 2 en tia l APPLICATIONS  Smartphone with GPS capability  PNDs (Personal Navigation Devices)  PMPs (Personal Media Players)  Automobile Navigation Systems  GNSS tracking systems  GNSS industrial applications  Software GPS  iPad like Mobile PCs fid TECHNOLOGY  Device in a small 1.45mmx1mm 6-pin uDFN RoHS-compliant package  Integrated LDO  Silicon CMOS 0.18um process with 1.8/3.3V operation C on PRODUCT DESCRIPTION CAN5119 is a high-gain, low-noise amplifier (LNA) designed for GPS, Galileo, Glonass and Beidou GNSS applications. Designed in a standard low-cost RF CMOS process, the LNA achieves 16.0dB gain and 0.75dB noise figure. Together with the CanaanTek GNSS receiver CAN5115, CAN5119 forms the optimal RF front-end for the reception of GNSS satellites. Packaged in a 6-pin µDFN package, the CAN5119 sits on a small form factor PCB space. It can operate from a 1.6V to 3.6V single supply and draws only 5.5mA DC current. The shutdown leakage current is only 1uA. C an aa PIN ASSIGNMENT PIN 1 Mark GND 1 GND 2 LNA_IN 3 CAN5119 nT ek FEATURES  Ultra-low-noise figure of 0.75dB  High-power gain of 16.0dB  Low-power of 5.5mA operated from a single 1.6V to 3.6V voltage  Small footprint of 1.45mmx1mm  Thin profile of 0.55mm  Lead-free and RoHS-compliant package  High integration with few off-chip BOM and low cost  Temperature from –40o to 85o range 6 LNA_OUT 5 PD_EN 4 VDD 3 PIN CONNECTIONS AND INTERNAL BLOCK DIAGRAM LNA_OUT GND PD_EN Block Diagram for LNA fid Figure 1 VDD en Bias LNA_IN tia l GND C on Pin Out Description Pin No. Name Description Connection 1 GND Ground connection Connect to PCB ground plane. 2 GND Ground connection Connect to PCB ground plane. 3 LNA_IN RF Input Requires a DC-blocking capacitor and external matching components. VDD power supply for LNA 5 PD_EN 6 LNA_OUT ek 4 Shut down Input A logic-low disables the device. RF Output RF output. Connect either direct to saw filter input, or to match component using an inductor. nT aa an C Supply Voltage. 4 ABSOLUTE MAXIMUM RATINGS Symbol Test Conditions VDD VPD_EN Supply Voltage Power Down Voltage LNA Max RF Input Power Min Max Unit TA=+25℃ 4.0 V TA=+25℃ 4.0 V 0 dBm Pin ESD: HBM, 150pF/1.5KOhm - 2.5 Storage Temperature TSTG -40 Solder Reflow Temperature TSLDR tia l Parameter kV +150 °C +260 C en This device should be handled with care within the above stress ratings. This IC has ESD RECOMMENDED OPERATING CONDITIONS Symbol Ambient Operating Temperature Supply Voltage Power Down Turn-on Voltage Power Down Turn-off Voltage Min. Typ. Max. TA -40 +25 +85 VDD 1.6 2.7 3.6 VPDon 1.6 - VDD VPDoff 0 - 0.4 V C on Parameter fid protection circuits within but must be handled and assembled according to the industry practice and at the ESD protected work platforms. Unit 0 C V ek ELECTRICAL CHARACTERISTICS (TA = +25℃, VDD = VPD_EN = 2.7V, fin = 1575.42MHz, unless otherwise specified) Symbol Test Conditions Min. Typ. Max. Unit nT Parameter circuit current Icc No Signal 4.5 5.5 6.5 mA Power Gain Gp Pin=-35dBm 14.5 16.0 17 dB NF - 0.75 1.1 dB Input Return Loss RLin - 12 - dB Output Return Loss RLout - 5.5 - dB aa Noise Figure an STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25℃, VDD = VPD_EN = 2.7V, fin = 1 575.42MHz, unless otherwise specified) Symbol Isolation ISL Input 3rd Order Distortion Intercept Point IIP3 Gain 1 dB Compression Input Power Pin(1dB) C Parameter Test Conditions （Note1） Reference Unit 29 dB 2 dBm -12.5 dBm Note1: Measured with the two tones located at 5MHz and 10MHz offset from the center of the GPS band with -40dBm/tone. 5 3 Input VPD_EN 4 VDD L1 en C2 fid C1 5 tia l 2 Output 6 + 1 CAN5119 Typical Application Diagram C on BOM LIST BOM Descriptions Chip Capacitor Chip inductor Chip Capacitor Symbol Size Value Unit C1 0402 100 pF L1 0402 8.2 nH C2 0402 10 nF nT ek Notes: One inductor of 5.6nH is recommended to be in series with the output for better output return loss and higher gain. C an aa These component values are for reference only and are subject to change with customer specific PCB layout design. 6 PACKAGE DIMENSIONS SIDE VIEW Symbol BOTTOM VIEW C on VIEW ek TOP fid en tia l 6-PIN PLASTIC TSON (UNIT: mm) Dimensions In Millimeters nT Min. Dimensions In Inches Max. Min. Max. A 0.450 0.550 0.018 0.022 A1 0.000 0.050 0.000 0.002 aa A3 D 0.110REF. 1.374 1.526 0.054 1 0.060 0.0394 —— —— —— —— —— —— —— —— C D1 an E 0.004REF. E1 k b 0.200MIN. 0.150 e 0.250 0.008MIN. 0.006 0.500TYP. 0.010 0.020TYP. L 0.250 0.350 0.010 0.014 L1 0.300 0.400 0.012 0.016 L2 0.000 0.100 0.000 0.004 7 RECOMMANDED REFLOW PROFILE Table2 Reflow Test Condition Profile Feature Pb-Free Assembly Preheat & Soak 150℃ Temperature max (Tsmax) 200℃ Time (Tsmin to Tsmax)(ts) 60-120 seconds tia l Temperature min (Tsmin) 3℃/second max. Liquidous temperature (TL) 217℃ Time at liquidous (tL) 60-150 seconds Peak package body temperature (Tp) * See classification temp in Table 3 Time 30**seconds within 5℃ of the specified clsssification temperature (Tc) fid (tp)** en Average ramp-up rate (Tsmax to Tp) Average ramp-down rate (Tp to Tsmax) 6℃/second max. Time 25℃ to peak temperature 8 minutes max. C on * Tolerance for peak profile temperature (TP) is defined as a supplier minimum and a user maximum. **Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Remark: All temperatures refer to the package body surface temperature. The highest temperature of reflow profile can not exceed 265℃. ek Note 1: All temperatures refer to the center of the package，measured on the package body surface that is facing up during assembly reflow (e.g.，live-bug). If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e.，dead-bug)，Tp shall be within ±2℃ of the nT live-bug Tp and still meet the Tc requirements，otherwise，the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body temperatures refer to JEP140 for recommended thermocouple use. aa Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly profiles should be developed based on specific process needs and board designs and should not exceed the parameters in C an Table2. For example，if Tc is 260℃ and time tp is 30 seconds，this means the following for the supplier and the user. For a supplier: The peak temperature must be at least 260℃ .The time above 255℃ must be at least 30 seconds. For a user: The peak temperature must not exceed 260℃. The time above 255℃ must not exceed 30 seconds. Note 3: All components in the test load shall meet the classification profile requirements. Note4: SMD packages classified to a given moisture sensitivity level by using Procedures or Criteria defined within any previous version of J-STD-020，JESD22-A112 (rescinded)，IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in classification level or a higher peak classification temperature is desired. 8 Table 3 Pb-Free Process – Classification Temperatures (Tc) Volume mm3 < 350 Volume mm3 350 - 2000 Volume mm3 > 2000 < 1.6 mm 260℃ 260℃ 260℃ 1.6 mm - 2.5 mm 260℃ 250℃ > 2.5 mm 250℃ 245℃ Critical Zone TL to Tp C on Ramp-up tL Tsmax Tsmin ek ts Preheat aa nT Temperature 245℃ en tp Tp 25 245℃ fid Reflow Profile TL tia l Package Thickness Ramp-down t 25℃ to Peak Time C an The reflow profile shown above should not be exceeded, since excessive temperatures or transport times during reflow can damage the chip. 9 PACKING SPEC TAPE REEL BOX PCS/REEL REEL/BOX PCS/BOX BOX/CARTON PCS/CARTON MIS1.45X1 IC-ZD-26 7’’(IC-JP-05) SOT23 3000 10 30000 4 120000 tia l PKG C on 5 aa nT ek 0 .0 o 0. 55± an C 8.00±0.30 05 0. fid 4.00±0.10 1.75±0.10 5± 2.00±0.05 3.50±0.05 .5 o1 4.00±0.10 en Tape & Real Dimension