VIS2007

VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Description Features The VIS2007 is a high efficiency, current mode, fully integrated boost converter, which can start up from an input voltage as low as 1.8V and convert up to 5.5V output voltage. During shutdown, it can disconnect the output from the input.  1.8V Minimum Input Voltage  Output Voltage Range: 2.5V to 5.5V  8A Peak Switching Current Limit  10mΩ(LS) / 30mΩ(HS) Power MOSFETs  High Efficiency (96.2% at VIN = 3.7V, VOUT = The converter integrates 10mΩ/30mΩ power MOSFETs and can deliver up to 3A output current at 5V output with 2.5V input supply. When the output is shorted, the VIS2007 enters hiccup protection mode and recovers automatically when the output short is removed. 5V, IOUT = 3A)  True Load Disconnection from Input  1% Accurate Reference Voltage  Internal Compensation and Soft Start  Low Shutdown Current < 1µA The VIS2007 also includes input under voltage lockout, output over voltage protection, cycle-bycycle over current protection, short circuit protection and thermal shutdown to prevent damage in the event of output overload. The VIS2007 is available in a low profile 10-pin 2mmx2mm FCQFN package.  Over-Current and Short-Circuit Protection Applications Ordering Information  Output Overvoltage Protection  Thermal Shutdown  2x2mm FCQFN 10-Pin Package  This is a Pb−Free Device  Tablets Device  USB Power Supply Package FCQFN-10 2007 3000 (2x2mm) YWLL Tape & Reel * Top Marking Code: Y is Year, W is Week, LL is Lot. † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications.  Power Banks, Battery Backup Units Typical Application Circuit 5V VIS2007 51.1k LBI 100k LBO 470k AOUT LBO LBI EN 10 9 8 7 22uF/ 10V *5 POUT 1 6 AOUT SW 2 5 VIN PGND 3 4 AGND FB PGND AGND 88.7k EN FB POUT VIN 110k 22uF/ 10V *2 Pinout (Top View) 1.5uH SW Shipping† VIS2007  Battery Powered Products 1.8 ~ 4.2V Top Marking* FCQFN-10 (2x2mm) October, 2020 – Rev. 0.9 Voltaic Semiconductor Confidential and Proprietary Information 1 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Pin Functions Pin Name Description 1 POUT Power Output. POUT must be locally bypassed. 2 3 4 5 SW PGND AGND VIN Switch Node. SW is connected to the internal high-side MOSFET and low-side MOSFET. Power Ground. Analog Ground. Input Supply. VIN must be locally bypassed. 6 AOUT Analog Output. AOUT must be locally bypassed. 7 EN 8 9 10 LBI LBO FB Enable pin of the chip. This pin is internally integrated with a 1M pull-down resistor. Low Battery Comparator Input (comparator enabled with EN). Low Battery Comparator Output (open drain). Feedback Input. Connecting a resistor divider from V OUT to this pin to adjust VOUT voltage. VIN EN Enable AOUT Start Up SW OVP /SCP Body Control OSC /RAMP Control Logic Gate Driver POUT PWM COMP PGND Compensation LBI FB LBI COMP EA 0.5V 0.8V LBO AGND Figure 1. Functional Block Diagram October, 2020 – Rev. 0.9 Voltaic Semiconductor Confidential and Proprietary Information 2 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Absolute Maximum Ratings (1) All Pins Junction Temperature Lead Temperature Storage Temperature Continuous Power Dissipation (TA= 25oC) (2) Recommended Operating Conditions -0.3V to +6V 150°C 260°C -65°C to 150°C 2.5W (3) Supply Voltage VIN Output Voltage VOUT Operating Junction Temperature 1.8V to 5.25V 2.5V to 5.5V -40°C to +125°C Thermal Resistance (4) Junction to Case ΘJC Junction to Ambient ΘJA 10°C/W 50°C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. These data are based on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and 2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device. October, 2020 – Rev. 0.9 Voltaic Semiconductor Confidential and Proprietary Information 3 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Electrical Characteristics VIN = VEN = 3.3V, VOUT = 5V, typical values are tested at TA = 25C, unless otherwise noted. Parameter Symbol Condition Operating Input Voltage VIN VINUVLO_R VIN rising Undervoltage Falling VINUVLO_F VIN falling IINS IINQ Supply Current (Quiescent) IOUTQ Typ 1.8 Undervoltage Rising Supply Current (Shutdown) Min Max Units 5.25 V 1.75 V 650 VEN = 0V, measured at VIN IC enabled, no load, no switching, measured at VIN IC enabled, no load, no switching, measured at VOUT 0.1 mV 1 μA 1.8 μA 190 μA 600 kHz 95 % Switching Frequency FS Maximum Duty Cycle DMAX EN High Threshold VENH VEN rising EN Low Threshold VENL VEN falling EN Pull-down Resistor REN VEN = 3.3V Feedback Voltage High-side MOSFET On-resistance Low-side MOSFET On-resistance VFB RONH 30 mΩ RONL 10 mΩ Linear Charge Current Limit (5) ILIM_LN SW Current Limit (5) Output Overvoltage Protection Threshold LBI Threshold ILIM_SW LBI Hysteresis VLBIhys 90 1.2 0.4 1000 792 LBI Leakage Current ILBI 800 VOUT = 0V 0.6 VOUT = 1V 1.6 808 490 mV A A 5.7 VLBI falling V kΩ 8 VOVP VLBI V 500 V 510 8 mV mV VEN= VIN 20 nA LBO Low Voltage VLBO VOUT = 3.3V, ILBO = 100 μA 0.4 V LBO Leakage Current ILBO VLBO = 5.5V 0.1 μA Thermal Shutdown (5) Thermal Shutdown Hysteresis (5) TSD 150 C TSDhys 25 C Notes: 5) Guaranteed by characterization, not production tested. October, 2020 – Rev. 0.9 Voltaic Semiconductor Confidential and Proprietary Information 4 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Typical Performance Characteristics VIN = VEN = 3.3V, VOUT = 5V, IOUT = 0A, TA = 25°C, L = 1.5uH, C = 22uF * 5, unless otherwise noted. Efficiency Output Voltage Regulation Steady State (Iout = 0A) Steady State (Iout = 0.05A) Time (40us/div) Time (2us/div) Steady State (Iout = 1A) Steady State (Iout = 5A) Time (2us/div) Time (800ns/div) October, 2020 – Rev. 0.9 Voltaic Semiconductor Confidential and Proprietary Information 5 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Typical Performance Characteristics (Continued) VIN = VEN = 3.3V, VOUT = 5V, IOUT = 0A, TA = 25°C, L = 1.5uH, C = 22uF * 5, unless otherwise noted. Power Up (Vin = 3.3V, Vout = 5V, Iout = 0A) Power Down (Vin = 3.3V, Vout = 5V, Iout = 3A) Time (400us/div) Time (4us/div) Load Transient (Vin = 3.7V, Vout = 5V, Iout = 1A ~ 2A) Over Voltage Protection (Vin = 3.6V, Iout = 3A, external 6.3V applied to Vout) Time (40us/div) Time (4us/div) Over Current Protection (Vin = 3.7V, Vout = 5V, Iout = 3A ~ 8A) Short Circuit Protection (Vin = 3.7V, Vout shorted to GND before SS) Time (10us/div) Time (4ms/div) October, 2020 – Rev. 0.9 Voltaic Semiconductor Confidential and Proprietary Information 6 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Operation Information The VIS2007 is a high efficiency synchronous boost converter. The device features fixedfrequency (600kHz) current-mode PWM control for excellent load and line regulation. Integrated low on-resistance power MOSFETs, combining with frequency stretching and power save mode (PSM) at light load, improve the efficiency over a wide load range. Internal soft-start and loop compensation simplifies the design process and minimizes the number of external components. Enable and Disable The device is enabled by setting EN pin high (>1.2V). When EN pin is pulled to ground, the device is disabled, switching is stopped and entire internal circuitry is turned off. The output is isolated from the input. Linear Charge Mode After the device is enabled, the internal reference and bias circuits are activated when the rising VIN trips the under-voltage lockout threshold (VINUVLO_R). At first, the PMOS rectifier turns on to charge the output capacitor linearly in linear charge mode. The device exits linear charge mode when the output is charged to 1.7V. In linear charge mode, the PMOS charging current is being regulated to avoid inrush current and limit the output current during short-circuit protection (SCP). This charging current is proportional to the output voltage, which is 0.6A when the output is 0V and ramps up as the output voltage increases. Once the output reaches 1.7V, the device starts switching and the output slowly ramps up to the targeted value in soft start. Soft Start In linear charge mode, the soft-start voltage follows the voltage on FB pin. As the device starts switching, the soft-start voltage is rising slowly by charging an internal capacitor with a current source. The reference voltage rises at the same rate of soft-start voltage. The soft-start ends when the soft-start voltage reaches 0.8V. The typical soft-start time is 2ms. Soft-start October, 2020 – Rev. 0.9 mechanism prevents high inrush current from the input power supply to the output capacitors. PWM and PSM The VIS2007 automatically enters power save mode (PSM) when the load decreases and resumes pulse width modulation (PWM) mode when the load increases. In the PWM mode, at the beginning of each cycle, the internal Nchannel MOSFET switch is turned on, forcing the inductor current to rise. The current of this switch is measured and converted to a voltage by a current sense amplifier. That voltage is compared to the output voltage of the error amplifier. When the two voltages are equal, the PWM comparator turns off the N-channel MOSFET and forces the inductor current to flow into the output capacitor through the internal Pchannel MOSFET, and the inductor current decreases. The peak inductor current is controlled by VCOMP, which in turn is controlled by the output voltage, thus the output voltage is regulated through the inductor current to satisfy the load. In the PSM, the device lowers the switching frequency and then switches to pulse skip mode if the load drops further. Step-down Mode In case that VOUT is lower than VIN+0.3V which usually happens during soft start and large load or line transients, the VIS2007 operates in a step-down mode with a lower peak current limit than that in step-up (boost) mode. In this stepdown mode, the PWM operation is similar to that in the boost mode except that the gate of internal P-channel MOSFET is tied to VIN. One thing needs to pay more attention is that SW node voltage stress in step-down mode is about 1V higher than boost mode and more power dissipation from the device. Current Limit To avoid an accidental large peak current, an internal cycle-by-cycle current limit operation is adopted. The internally sensed inductor current is converted to a voltage and compared to the peak current limit. The internal N-channel Voltaic Semiconductor Confidential and Proprietary Information 7 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter MOSFET switch is turned off immediately as soon as the inductor current exceeds the limit. If the load current is further increased and the output is pulled below the input voltage, the VIS2007 enters short circuit protection (SCP) mode. Low Battery Detector When the device is shut down, the VIS2007 disconnects VOUT from VIN by eliminating body diode conduction of the internal P-channel MOSFET switch. This prevents either VOUT or VIN being discharged by each other when the VIS2007 is disabled. The VIS2007 integrates a low-battery detector to monitor the input battery voltage and generate an error flag when that voltage drops below a user-set threshold voltage. The function is active only when the device is enabled. When the device is disabled, the LBO pin is high impedance. The switching threshold is 500 mV at LBI. During normal operation, LBO stays at high impedance because the voltage at LBI is above the threshold. It becomes actively low when the voltage at LBI goes below 500 mV. The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV, which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the application section for more details about the programming of the LBI threshold. Output Over-Voltage Protection Thermal Shutdown Short Circuit Protection Once short circuit protection (SCP) is triggered, the VIS2007 stops switching immediately and restarts after about 1ms as a new power-on cycle. The device continues this hiccup steady state until the overload condition is removed. Output Disconnection The VIS2007 provides output over-voltage protection. If the output voltage exceeds the over voltage protection (OVP) threshold of 5.7V, the device stops switching and both of the N-channel and P-channel MOSFET switches turn off. When the output voltage drops below the OVP voltage, the device resumes switching automatically. This function secures the circuits connected to the output from excessive overvoltage. October, 2020 – Rev. 0.9 The VIS2007 has a built-in temperature monitor. If the chip temperature exceeds thermal shutdown threshold, the device goes into the thermal shutdown and switching is stopped. If the temperature drops below the thermal shutdown falling threshold, the converter resumes the normal operation. Voltaic Semiconductor Confidential and Proprietary Information 8 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Application Information Following information provides a general component design reference in a typical application of the VIS2007. Output Voltage Setting Output voltage VOUT is programmed by a resistor divider connected between VOUT sense point and analog ground AGND, as depicted in Figure 2, having a value of 𝑉 =𝑉 ∙ 1+ 𝑅1 𝑅2 (1) where VFB is feedback voltage, which equals to an internal reference voltage 0.8V when the VOUT is in regulation. VOUT Compensation rule of thumb is to allow the peak-to-peak ripple current to be approximately 30-50% of the maximum input current, and the maximum peak inductor current in normal operation should not be over 75% of the current limit to maintain good output regulation. In most applications, a 1.5uH inductor could be a good choice though users may select an alternative inductor in a range from 1uH to 4.7uH. For a given inductor L, the peak-to-peak ripple current in Continuous Conduction Mode (CCM) is 𝐼 = 𝑉 ∙ (𝑉 −𝑉 ) 𝑉 ∙𝐹 ∙𝐿 where FS is switching frequency in CCM. To avoid overheating the inductor, the maximum DC current IIN_MAX under the worst condition needs to be calculated by R1 FB 𝐼 _ = 𝑉 EA R2 0.8V AGND Figure 2. Output Voltage Setting Usually the resistor R1 is predetermined in applications, having a typical value of 470k. When there is a need, users may fine tune closeloop response by adjusting R1 value in a range from 100 k to 1M . The smaller R1 resistance, the higher close-loop bandwidth while probably lower stability margin. After R1 is selected, R2 value is given by 𝑅2 = 𝑅1 𝑉 𝑉 −1 (2) 𝑉 ∙𝐼 _ _ ∙ A low-DCR SMD inductor is recommended for a high-efficiency and compact design. A general (4) where VIN_MIN is the minimum input voltage, IOUT_MAX is the maximum load current, and  is the conversion efficiency. To make sure the inductor does not saturate in a large load step transient, an additional rated saturation current margin should be added on top of the peak current in normal operation, that is 𝐼 =𝐾 ∙ 𝐼 _ + _ 𝐼 2 (5) In equation (5), the coefficient Km could be about 1.5. Due to the cycle-by-cycle peak current protection of the VIS2007, with a built-in switching peak current limit of ILIM_SW, the input DC current limit IIN_LIM is also a function of the inductor peak-topeak ripple current Ipp, we have Inductor Selection October, 2020 – Rev. 0.9 (3) 𝐼 _ =𝐼 _ − 𝐼 2 Voltaic Semiconductor Confidential and Proprietary Information (6) 9 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter And hence, an approximated corresponding output DC current limit IOUT_LIM can be obtained as 𝐼 = _ 𝑉 ∙𝐼 𝑉 ∙ _ (7) Input Capacitor Selection A 22uF or more ceramic capacitors are recommended to stabilize the input voltage, absorb hot plug voltage spike, and bypass the inductor ripple current with a low power loss. Output Capacitor Selection Low-ESR capacitors, such as X5R or better ceramic capacitors, are preferred to keep the output voltage ripple to a minimum and reduce voltage transient spikes. The output voltage ripple can be estimated as 𝑉 ≈ 𝑉 𝑉 𝐹 ∙𝐶 1− 𝐼  Low Battery Detection Low battery detection and indication can be done by applying a resistor divider from the input voltage VIN to LBI pin and pull LBO pin up to VOUT via a 100k resistor, as shown in Figure 3. The programmed low battery voltage threshold is 𝑉 = 0.5𝑉 ∙ 1 + 𝑅3 𝑅4 (9) Note that LBI should not be left float. If the function is unnecessary in an application, users can simply connect LBI pin to VIN or ground and leave LBO pin float. VIN AOUT 100K R3 LBI LBI COMP LBO R4 𝐸𝑆𝑅 ∙ 𝑉 + 𝑉 0.5V (8) where COUT is a total output capacitance value and ESR is an equivalent series resistance value, taking account of all the output capacitors in parallel. October, 2020 – Rev. 0.9 Figure 3. Low Battery Detection Voltaic Semiconductor Confidential and Proprietary Information 10 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter PCB Layout Guideline Following information provides a general board layout guideline in a typical application, taking the VIS2007 demo board as a reference. Electrical Layout Considerations Good electrical layout is a key to ensure proper operation, high efficiency, and noise reduction.  Power Paths: Use wide and short traces or copper pours for power paths (such as VIN, VOUT, SW, and PGND) to reduce parasitic inductance and high-frequency loop area. It is appreciated for efficiency improvement as well.  Power Supply Decoupling: The converter should be well decoupled by input capacitors. A 22uF or more MLCC capacitors are directly placed at VIN pin.  POUT Decoupling: At least one or more lowESL MLCC output capacitors must be placed very close to POUT pin, and the decoupling loop area should be as small as possible to reduce parasitic inductance, switching voltage spike, and noise emission.  AOUT Decoupling: Place a 4.7uF or larger decoupling capacitor as close as possible to AOUT pin.  Switching Node: SW node should be a copper pour, but compact because it is also a noise source. October, 2020 – Rev. 0.9  Ground: It would be good to have multiple layers of ground planes on PCB. Directly connect PGND pin and AGND pin to GND planes through vias close to the pins.  Voltage Sense: Use a short trace and arrange a “quiet” path for the output voltage sense. Keep FB trace short to minimize its capacitance to ground. All feedback components must be kept close to FB pin to prevent noise injection on FB traces. Thermal Layout Considerations Good thermal layout helps high power dissipation from a small package with reduced temperature rise.  All the pins of the device must be well soldered on the board.  A four or more layers PCB board with solid ground planes is preferred for efficient heat dissipation.  More vias are welcome to be around the device to connect more layers to reduce thermal impedance.  Use large-area copper pours to help thermal conduction and radiation.  Distribute heat sources to be not too close together. Voltaic Semiconductor Confidential and Proprietary Information 11 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Package Dimensions 0.50 2.00 0.50 0.50 0.30 1.50 0.55 2.30 LAND PATTERN RECOMMENDATION Notes:       Dimensioning and tolerancing confirm to ASME Y14.5M-1994. All dimensions are in millimeters, angles are in degrees. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. Dimension b applies to metallized terminal and is measured between 0.15mm to 0.30mm from the terminal tip. Dimension b should not be measured in radius area. All specs take JEDEC MO-220 for reference. October, 2020 – Rev. 0.9 Voltaic Semiconductor Confidential and Proprietary Information 12 VIS2007 5V/8A High-Efficiency Synchronous Boost Converter Tape and Reel Information Notes:         10 sprocket hole pitch cumulative tolerance ±0.2. Camber not to exceed 1mm in 250mm. Material: Polycarbonate. Ao and Bo measured on a plane 0.3mm above the bottom of the pocket. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. Pocket center and pocket hole center must be same position. Surface resistivity:10E+5~10E+9 OHMS/SQ. Tape Width 8mm October, 2020 – Rev. 0.9 A (1.0) 178.0mm N (2.0) 54.0mm W1 (+1.5/-0) 8.4mm W2 (MAX) 14.4mm Voltaic Semiconductor Confidential and Proprietary Information 13