MXD86C2

MXD86C2 DP12T Switch with MIPI for LTE TRX Application VED APPRO This document contains information that is confidential and proprietary to Maxscend Microelectronics Company Limited (Maxscend) and may not be reproduced in any form without express written consent of Maxscend. No transfer or licensing of technology is implied by this document. Page 1 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application General Description Features The MXD86C2 is a low loss, high isolation DP12T  Excellent insertion loss - 0.50 dB Insertion Loss at 2.7GHz switch for antenna TRX application. The MXD86C2 is compatible with MIPI control,  P0.1dB @ 35dBm which is a key requirement for many cellular  Multi-Band operation 400MHz to 3800MHz  RFFE serial control interface  Compact 2.0mm x 2.4mm in LGA-18 package  No DC blocking capacitors required (unless transceivers. This part is packaged in a compact 2.0mm x 2.4mm, 18-pin, LGA package which allows for a small solution size with no need for external DC blocking capacitors (when no external external DC is applied to the RF ports) DC is applied to the device ports). Applications  3G/4G multimode cellular handsets (UMTS and CDMA2000)  Carrier aggregation diversity Functional Block Diagram and Pin Function RFA1 RFA2 ANT_A RFA3 RFA4 RFA5 RFA6 Ground Paddle RFB1 RFB2 ANT_B RFB3 RFB4 RFB5 RFB6 VIO VDD SCLK SDATA Figure 1 Functional Block Diagram and Pinout (Top View) Page 2 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application RFB2 RFB3 RFB4 RFB5 RFB6 Application Circuit RFB1 ANT_B Ground Paddle ANT_A RFA1 ANT_B ANT_A RFA1 RFA2 RFA3 C4 DN1 RFA4 C3 DN1 RFA5 C2 33nF RFA6 C1 100pF RFB1 Figure 2 Evaluation Board Schematic Table 1. Pin Description Pin No. 1 2 3 4 5 6 7 8 9 Ground Paddle Name RFB2 RFB3 RFB4 RFB5 RFB6 VDD VIO SDATA SCLK Description RF port B2 RF port B3 RF port B4 RF port B5 RF port B6 Power supply Supply voltage for MIPI MIPI data input/output MIPI clock GND Ground Pin No. 10 11 12 13 14 15 16 17 18 Name RFA6 RFA5 RFA4 RFA3 RFA2 RFA1 ANT_A ANT_B RFB1 Description RF port A6 RF port A5 RF port A4 RF port A3 RF port A2 RF port A1 Antenna port A Antenna port B RF port B1 Note: Bottom ground paddles must be connected to ground. Page 3 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application Truth Table Table 2. Register_0 Truth Table (ANT_B) Register_0 State Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ISO RFB1 RFB2 RFB3 RFB4 RFB5 RFB6 RFB6+RFB5 RFB6+RFB4 RFB6+RFB3 RFB6+RFB2 RFB6+RFB1 RFB5+RFB4 RFB5+RFB3 RFB5+RFB2 RFB5+RFB1 RFB4+RFB3 RFB4+RFB2 RFB4+RFB1 RFB3+RFB2 RFB3+RFB1 RFB2+RFB1 ISO ISO ISO ISO ISO ISO ISO ISO ISO ISO D7 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x D6 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x D5 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 x x x x x x x x x x x x x x x x x x x x x x x x x x x x D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 3. Register_1 Truth Table (ANT_A) Register_1 State Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ISO RFA1 RFA2 RFA3 RFA4 RFA5 RFA6 RFA6+RFA5 RFA6+RFA4 RFA6+RFA3 RFA6+RFA2 RFA6+RFA1 RFA5+RFA4 RFA5+RFA3 RFA5+RFA2 RFA5+RFA1 RFA4+RFA3 RFA4+RFA2 RFA4+RFA1 RFA3+RFA2 RFA3+RFA1 RFA2+RFA1 ISO ISO ISO ISO ISO ISO D7 x x x x x x x x x x x x x x x x x x x x x x x x x x x x D6 x x x x x x x x x x x x x x x x x x x x x x x x x x x x D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Page 4 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application ISO ISO ISO ISO 29 30 31 32 x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Recommended Operation Range Table 4. Recommended Operation Condition Parameters Operation Frequency Power supply Power supply for MIPI MIPI Control Voltage High MIPI Control Voltage Low Symbol Min Typ Max Units f1 VDD VIO VH VL 0.4 2.5 1.65 0.8*VIO 0 2.8 1.8 1.8 0 3.8 3.0 1.95 1.95 0.3 GHz V V V V Min Typical Max Units 2.5 2.8 3.0 V 55 90 uA Specifications Table 5. Electrical Specifications Parameter Symbol Test Condition DC Specifications Supply voltage VDD Supply current IDD VIO supply voltage VIO 1.65 1.8 1.95 V IIO VCTL_H VCTL_L 0.8* VIO 0 10% to 90% RF 4 VIO 0 1 10 1.95 0.3 2 uA V V uS 0.1 to 1.0 GHz 1.0 to 2.0 GHz 2.0 to 2.7 GHz 3.4 to 3.8 GHz 0.1 to 1.0 GHz 1.0 to 2.0 GHz 2.0 to 2.7 GHz 3.4 to 3.8 GHz 0.1 to 1.0 GHz 1.0 to 2.0 GHz 2.0 to 2.7 GHz 3.4 to 3.8 GHz 0.50 0.60 0.65 0.90 30 28 22 18 20 15 12 10 0.40 0.45 0.50 0.70 45 35 28 22 25 20 15 13 dB dB dB dB dB dB dB dB dB dB dB dB +34 +35 VIO Supply current SDATA, SCLK control voltage: High Low Switching Speed, one RF to another RF Specifications Insertion loss (ANT_A pin to RFA1/2/3/4/5/6 pins; ANT_B pin to RFB1/2/3/4/5/6 pins) IL Isolation (ANT_A pin to RFA1/2/3/4/5/6 pins; ANT_B pin to RFB1/2/3/4/5/6 pins) Iso Input return loss (ANT_A pin to RFA1/2/3/4/5/6 pins; ANT_B pin to RFB1/2/3/4/5/6 pins) RL 0.1 dB Compression Point (ANT_A pin to RFA1/2/3/4/5/6 pins; ANT_B pin to RFB1/2/3/4/5/6 pins) P0.1dB 0.4 GHz to 3.8 GHz dBm Page 5 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application MIPI Read and Write Timing MIPI supports the following Command Sequences: • Register Write • Register_0 Write • Register Read Figures 3 and 4 provide the timing diagrams for register write commands and read commands, respectively. Figure 5 shows the Register 0 Write Command Sequence. Refer to the MIPI Alliance Specification for RF Front-End Control Interface (RFFE), v1.10 (26 July 2011) for additional information on MIPI USID programming sequences and MIPI bus specifications. CLK SA3 Data SA2 SA1 SA0 0 SSC 1 0 A4 A3 A2 A1 A0 P A0 P Register Write Command Frame CLK Data P D7 D6 D5 D4 D3 D2 D1 D0 P 0 Bus Park Data Frame Signal driven by Master Signal not driven, pull down only For reference only Figure 3 Register Write Command Sequence CLK SA3 Data SA2 SA1 SA0 0 SSC 1 1 A4 A3 A2 A1 Register Read Command Frame CLK Data P 0 Bus Park D7 D6 D5 D4 D3 D2 D1 Data Frame (from Slave) D0 P 0 Bus Park Signal driven by Master Signal driven by Slave Signal not driven, pull down only by Master For reference only Figure 4 Register Read Command Sequence Page 6 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application In the timing figures, SA[3:0] is slave address. A[4:0] is register address. D[7:0] is data. “P” is odd parity bit. Register 0 Write Command Sequence Figure shows the Register 0 Write Command Sequence. The Command Sequence starts with an SSC, followed by the Register 0 Write Command Frame containing the Slave address, a logic one, and a seven bit word to be written to Register 0. The Command Sequence ends with a Bus Park Cycle. CLK SA3 Data SSC SA2 SA1 SA0 1 D6 D5 Slave Address D4 D3 D2 Data D1 D0 P 0 Parity Bus Park Signal driven by Master Signal not driven, pull down only For reference only Figure 5 Register 0 Write Command Sequence Page 7 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application Register definition Table 6. Register definition table Register Address Register Name Data Bits R/W Function Description Default BROADC AST_ID support Trigger support 0x00 REGISTER_0 7:0 R/W RF Control Register_0 truth Table: Table 2 0x00 No Yes 0x01 REGISTER_1 7:0 R/W RF Control Register_1 truth Table: Table 3 0x00 No Yes 0x001B GROUP_SID 7:4 R RESERVED 0x0 No No 3:0 R/W GSID Group Slave ID 0x0 No No 0b00 Yes No 0x001C PM_TRIG 0x001D PRODUCT_ID 0x001E MANUFACTU RER_ID 0x001F MAN_USID 7:6 R/W PWR_MODE 00: Normal Operation (ACTIVE) 01: Reset all registers to default settings (STARTUP) 10: Low power (LOW POWER) 11: Reserved Note: Write PWR_MODE=2’h1 will reset all register, and puts the device into STARTUP state. 5 R/W Trigger_Mask_2 If this bit is set, trigger 2 is disabled 1 No No 4 R/W Trigger_Mask_1 If this bit is set, trigger 1 is disabled 1 No No 1 No No 3 R/W Trigger_Mask_0 If this bit is set, trigger 0 is disabled Note: When all triggers are disabled, writing to a register that is associated with trigger 0, 1, or 2, causes the data to go directly to the destination register. 2 W Trigger_2 A write of a one to this bit loads trigger 2's registers 0 Yes No 1 W Trigger_1 A write of a one to this bit loads trigger 1's registers 0 Yes No 0 Yes No 0 W Trigger_0 A write of a one to this bit loads trigger 0's registers Note: Trigger processed immediately then cleared. Trigger 0, 1, and 2 will always read as 0. 7:0 R PRODUCT_ID Product Number 0x05 No No 7:0 R MANUFACTUR ER_ID[7:0] Lower eight bits of MIPI registered Manufacturer ID 0x81 No No 7:6 R RESERVED 0b00 No No 5:4 R MANUFACTUR ER_ID[9:8] Upper two bits of MIPI registered Manufacturer ID 0b11 No No 3:0 R/W USID USID of the device. 0xa No No Page 8 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application Absolute Maximum Ratings Table 7. Maximum ratings Parameters Symbol Minimum Maximum Units Supply voltage Supply voltage for MIPI MIPI Control voltage (SDATA, SCLK) RF input power Operating temperature Storage temperature Electrostatic Discharge Human body model (HBM), Class 1C Machine Model (MM), Class A Charged device model (CDM), Class III VDD VIO +2.0 +1.0 +3.3 +2.0 V V VCTL 0 +2.0 V PIN TOP TSTG –20 –40 +36 +85 +125 dBm ℃ ℃ ESD_HBM 1500 ESD_MM 150 ESD_CDM 500 V Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device Power ON and OFF sequence Here is the recommendation about power-on/off sequence in order to avoid damaging the device. Power ON 1) Apply voltage supply - VDD 2) Apply logic supply - VIO 3) Wait 10μs or greater and then apply MIPI bus signals – SCLK and SDATA 4) Wait 5μs or greater after MIPI bus goes idle and then apply the RF Signal Power OFF 1) Remove the RF Signal 2) Remove MIPI bus – SCLK and SDATA 3) Remove logic supply - VIO 4) Remove voltage supply - VDD VDD ON VDD VIO ON MIPI RF Trigger ON RF OFF VIO OFF ≥100us VDD OFF ≥100us VIO Slave State SDATA,SCLK SHUTDOWN STARTUP ≥10us ACTIVE SHUTDOWN ≥5us RF Signal Note: VIO can be applied to the device before VDD or removed after VDD. It is important to wait 10μs after VIO & VDD are applied before sending SDATA to ensure correction data transmission. The minimum time between a power up and power down sequence (and vice versa) is ≥ 100us. Page 9 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application Package Outline Dimension Figure 6 package outline dimension Page 10 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential MXD86C2 – DP12T Switch with MIPI for LTE TRX Application Reflow Chart tP TP Critical Zone TL to TP Ramp-up Temperature TL TSmax tL TSmin Ramp-down tS Preheat t 25 ℃ to Peak Time Figure 7 Recommended Lead-Free Reflow Profile Table 7. Reflow condition Profile Parameter Ramp-up rate（TSmax to Tp） Preheat temperature（TSmin to TSmax） Preheat time（ts） Time above TL , 217℃（tL） Peak temperature（Tp） Time within 5℃ of peak temperature(tp) Ramp-down rate Time 25℃ to peak temperature Lead-Free Assembly, Convection, IR/Convection 3℃/second max. 150℃ to 200℃ 60 - 180 seconds 60 - 150 seconds 260℃ 20 - 40 seconds 6℃/second max. 8 minutes max. ESD Sensitivity Integrated circuits are ESD sensitive and can be damaged by static electric charge. Proper ESD protection techniques should be used when handling these devices. RoHS Compliant This product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE), and are considered RoHS compliant. 1.3.1 Page 11 of 11 Maxscend Microelectronics Company Limited. All rights reserved. Maxscend Confidential