MXD85A0F
SP10T TRX Switch with MIPI
VED
APPRO
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Company Limited (Maxscend) and may not be reproduced in any form without express written consent of
Maxscend. No transfer or licensing of technology is implied by this document.
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MXD85A0F – SP10T TRX Switch with MIPI
General Description
Features
The MXD85A0F is a low loss, high isolation
Excellent insertion loss
- 0.75 dB Insertion Loss at 2.7GHz
SP10T switch for antenna TRX application.
The MXD85A0F is compatible with MIPI control,
P0.1dB @ 35dBm
which is a key requirement for many cellular
Multi-Band operation 400MHz to 3000MHz
RFFE serial control interface
Compact 2.4mm x 2.4mm in QFN-20
transceivers. This part is packaged in a compact
2.4mm x 2.4mm, 20-pin, QFN package which
package
allows for a small solution size with no need for
external DC blocking capacitors (when no external
No DC blocking capacitors required (unless
external DC is applied to the RF ports)
DC is applied to the device ports).
Applications
2G/3G/4G antenna diversity
Cellular modems and USB Devices
Functional Block Diagram and Pin Function
RF1
RF2
RF3
RF4
RF5
ANT
RF6
RF7
Ground
Paddle
RF8
RF9
RF10
VIO
VDD
SCLK
SDATA
Figure 1 Functional Block Diagram and Pinout (Top View)
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MXD85A0F – SP10T TRX Switch with MIPI
16
RF5
RF5
RF4
RF4
RF3
RF3
RF2
RF2
19
8
GND
20
7
GND
1
2
RF10
3
4
5
6
RF6
C4
DN1
ANT
ANT
RF6
C3
DN1
GND
9
Ground
Paddle
RF7
C2
33nF
11
10
18
NC
C1
100pF
17
RF7
SCLK
12
RF8
SDATA
13
RF8
VIO
14
RF9
VDD
15
RF9
SDATA SCLK
RF1
VIO
RF10
VDD
GND
RF1
Application Circuit
Figure 2 Evaluation Board Schematic
Table 1. Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
Ground
Paddle
Name
NC
RF10
RF9
RF8
RF7
RF6
GND
GND
ANT
GND
Description
Not Connect
RF port10
RF port9
RF port8
RF port7
RF port6
Ground
Ground
Antenna port
Ground
GND
Ground
Pin No.
11
12
13
14
15
16
17
18
19
20
Name
RF5
RF4
RF3
RF2
RF1
GND
VDD
VIO
SDATA
SCLK
Description
RF port5
RF port4
RF port3
RF port2
RF port1
Ground
Power supply
Supply voltage for MIPI
MIPI data input/output
MIPI clock
Note: Bottom ground paddles must be connected to ground.
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MXD85A0F – SP10T TRX Switch with MIPI
Truth Table
Table 2.
State
Mode
1
2
3
4
5
6
7
8
9
10
11
ISO
RF1 on
RF2 on
RF3 on
RF4 on
RF5 on
RF6 on
RF7 on
RF8 on
RF9 on
RF10 on
Register_0
D7
x
x
x
x
x
x
x
x
x
x
x
D6
0
0
0
0
0
0
0
0
0
0
0
D5
0
0
0
0
0
0
0
0
0
0
0
D4
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
1
1
1
0
1
0
0
1
1
D2
0
0
0
1
0
0
0
1
1
1
0
D1
0
1
1
1
1
0
0
1
0
0
0
D0
0
0
0
0
1
1
1
0
0
0
0
Symbol
Min
Typ
Max
Units
f1
VDD
VIO
VH
VL
0.7
2.5
1.65
0.8*VIO
0
2.8
1.8
1.8
0
3.0
3.0
1.95
1.95
0.3
GHz
V
V
V
V
Min
Typical
Max
Units
2.5
2.8
3.0
V
55
80
uA
1.65
1.8
1.95
V
0.8* VIO
0
10% to 90% RF
4
VIO
0
1
10
1.95
0.3
2
uA
V
V
uS
0.1 to 1.0 GHz
1.0 to 2.0 GHz
2.0 to 2.7 GHz
0.1 to 1.0 GHz
1.0 to 2.0 GHz
2.0 to 2.7 GHz
0.1 to 1.0 GHz
1.0 to 2.0 GHz
2.0 to 2.7 GHz
0.50
0.65
0.75
40
30
20
25
20
15
dB
dB
dB
dB
dB
dB
dB
dB
dB
+35
dBm
Recommended Operation Range
Table 3. Recommended Operation Condition
Parameters
Operation Frequency
Power supply
Power supply for MIPI
MIPI Control Voltage High
MIPI Control Voltage Low
Specifications
Table 4. Electrical Specifications
Parameter
Symbol
Test Condition
DC Specifications
Supply voltage
VDD
Supply current
IDD
VIO supply voltage
VIO
VIO Supply current
SDATA, SCLK control voltage: High
Low
Switching Speed, one RF to another
IIO
VCTL_H
VCTL_L
RF Specifications
Insertion loss (ANT pin to
RF1/2/3/4/5/6/7/8/9/10 pins)
IL
Isolation (ANT pin to
RF1/2/3/4/5/6/7/8/9/10 pins)
Iso
Input return loss (ANT pin to
RF1/2/3/4/5/6/7/8/9/10 pins)
RL
0.1 dB Compression Point (ANT pin
to RF1/2/3/4/5/6/7/8/9/10 pins)
P0.1dB
35
25
18
20
15
12
0.7 GHz to 3.0 GHz
Page 4 of 10
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MXD85A0F – SP10T TRX Switch with MIPI
MIPI Read and Write Timing
MIPI supports the following Command Sequences:
• Register Write
• Register_0 Write
• Register Read
Figures 3 and 4 provide the timing diagrams for register write commands and read commands,
respectively. Figure 5 shows the Register 0 Write Command Sequence. Refer to the MIPI Alliance
Specification for RF Front-End Control Interface (RFFE), v1.10 (26 July 2011) for additional information on
MIPI USID programming sequences and MIPI bus specifications.
CLK
SA3
Data
SA2
SA1
SA0
0
SSC
1
0
A4
A3
A2
A1
A0
P
A0
P
Register Write Command Frame
CLK
Data
P
D7
D6
D5
D4
D3
D2
D1
D0
P
0
Bus
Park
Data Frame
Signal driven by Master
Signal not driven, pull down only
For reference only
Figure 3 Register Write Command Sequence
CLK
SA3
Data
SA2
SA1
SA0
0
SSC
1
1
A4
A3
A2
A1
Register Read Command Frame
CLK
Data
P
0
Bus
Park
D7
D6
D5
D4
D3
D2
Data Frame (from Slave)
D1
D0
P
0
Bus
Park
Signal driven by Master
Signal driven by Slave
Signal not driven, pull down only by Master
For reference only
Figure 4 Register Read Command Sequence
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MXD85A0F – SP10T TRX Switch with MIPI
In the timing figures, SA[3:0] is slave address. A[4:0] is register address. D[7:0] is data. “P” is odd parity
bit.
Register 0 Write Command Sequence
Figure shows the Register 0 Write Command Sequence. The Command Sequence starts with an SSC,
followed by the Register 0 Write Command Frame containing the Slave address, a logic one, and a seven
bit word to be written to Register 0. The Command Sequence ends with a Bus Park Cycle.
CLK
SA3
Data
SSC
SA2
SA1
SA0
1
D6
D5
Slave Address
D4
D3
Data
D2
D1
D0
P
0
Parity
Bus
Park
Signal driven by Master
Signal not driven, pull down only
For reference only
Figure 5 Register 0 Write Command Sequence
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MXD85A0F – SP10T TRX Switch with MIPI
Register definition
Table 5. Register definition table
Register
Address
Register
Name
Data
Bits
R/W
Function
Description
Default
BROADC
AST_ID
support
Trigger
support
0x00
REGISTER_0
7:0
R/W
RF Control
Register_0 truth Table: Table 2
0x00
No
Yes
0x001B
GROUP_SID
7:4
R
RESERVED
0x0
No
No
3:0
R/W
GSID
Group Slave ID
0x0
No
No
0b10
Yes
No
0x001C
PM_TRIG
0x001D
PRODUCT_ID
0x001E
MANUFACTU
RER_ID
0x001F
MAN_USID
7:6
R/W
PWR_MODE
00: Normal Operation (ACTIVE)
01: Reset all registers to default settings
(STARTUP)
10: Low power (LOW POWER)
11: Reserved
Note: Write PWR_MODE=2’h1 will reset all
register, and puts the device into STARTUP
state.
5
R/W
Trigger_Mask_2
If this bit is set, trigger 2 is disabled
0
No
No
4
R/W
Trigger_Mask_1
If this bit is set, trigger 1 is disabled
0
No
No
0
No
No
3
R/W
Trigger_Mask_0
If this bit is set, trigger 0 is disabled
Note: When all triggers are disabled, writing
to a register that is associated with trigger 0,
1, or 2, causes the data to go directly to the
destination register.
2
W
Trigger_2
A write of a one to this bit loads trigger 2's
registers
0
Yes
No
1
W
Trigger_1
A write of a one to this bit loads trigger 1's
registers
0
Yes
No
0
Yes
No
0
W
Trigger_0
A write of a one to this bit loads trigger 0's
registers
Note: Trigger processed immediately then
cleared. Trigger 0, 1, and 2 will always read
as 0.
7:0
R
PRODUCT_ID
Product Number
0x01
No
No
7:0
R
MANUFACTUR
ER_ID[7:0]
Lower eight bits of MIPI registered
Manufacturer ID
0x81
No
No
7:6
R
RESERVED
0b00
No
No
5:4
R
MANUFACTUR
ER_ID[9:8]
Upper two bits of MIPI registered
Manufacturer ID
0b11
No
No
3:0
R/W
USID
USID of the device.
0xa
No
No
Page 7 of 10
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MXD85A0F – SP10T TRX Switch with MIPI
Absolute Maximum Ratings
Table 6. Maximum ratings
Parameters
Symbol
Minimum
Maximum
Units
Supply voltage
Supply voltage for MIPI
MIPI Control voltage
(SDATA, SCLK)
RF input power
(RF1/2/3/4/5/6/7/8/9/10)
Operating temperature
Storage temperature
Electrostatic Discharge
Human
body
model
(HBM), Class 1C
Machine Model (MM),
Class A
Charged device model
(CDM), Class III
VDD
VIO
+2.0
+1.0
+3.3
+2.0
V
V
VCTL
0
+2.0
V
+36
dBm
+85
+125
℃
℃
PIN
–20
–40
TOP
TSTG
ESD_HBM
1000
ESD_MM
100
ESD_CDM
500
V
Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with
only one parameter set at the limit and all other parameters set at or below their nominal value. Exceeding any of the limits listed
here may result in permanent damage to the device
Power ON and OFF sequence
Here is the recommendation about power-on/off sequence in order to avoid damaging the device.
Power ON
1) Apply voltage supply - VDD
2) Apply logic supply - VIO
3) Wait 10μs or greater and then apply MIPI bus signals – SCLK and SDATA
4) Wait 5μs or greater after MIPI bus goes idle and then apply the RF Signal
Power OFF
1) Remove the RF Signal
2) Remove MIPI bus – SCLK and SDATA
3) Remove logic supply - VIO
4) Remove voltage supply - VDD
VDD
ON
VDD
VIO
ON
MIPI RF
Trigger ON
RF
OFF
≥100us
VIO
OFF
VDD
OFF
≥100us
VIO
Slave State
SDATA,SCLK
SHUTDOWN
STARTUP
≥10us
ACTIVE
SHUTDOWN
≥5us
RF Signal
Note: VIO can be applied to the device before VDD or removed after VDD.
It is important to wait 10μs after VIO & VDD are applied before sending SDATA to ensure correction data transmission.
The minimum time between a power up and power down sequence (and vice versa) is ≥ 100us.
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MXD85A0F – SP10T TRX Switch with MIPI
Package Outline Dimension
Figure 6 package outline dimension
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MXD85A0F – SP10T TRX Switch with MIPI
Reflow Chart
tP
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
TSmax
tL
TSmin
Ramp-down
tS
Preheat
t 25 ℃ to Peak
Time
Figure 7 Recommended Lead-Free Reflow Profile
Table 7. Reflow condition
Profile Parameter
Ramp-up rate(TSmax to Tp)
Preheat temperature(TSmin to TSmax)
Preheat time(ts)
Time above TL , 217℃(tL)
Peak temperature(Tp)
Time within 5℃ of peak temperature(tp)
Ramp-down rate
Time 25℃ to peak temperature
Lead-Free Assembly, Convection, IR/Convection
3℃/second max.
150℃ to 200℃
60 - 180 seconds
60 - 150 seconds
260℃
20 - 40 seconds
6℃/second max.
8 minutes max.
ESD Sensitivity
Integrated circuits are ESD sensitive and can be damaged by static electric charge. Proper ESD
protection techniques should be used when handling these devices.
RoHS Compliant
This product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls
(PBB) and polybrominated diphenyl ethers (PBDE), and are considered RoHS compliant.
1.0.1
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