KTM5030
USB Type-C / DisplayPort 1.4 MST Hub (DSC)
Features
• USB Type-C DisplayPort Alt-mode de-mux
Simultaneous USB3.2 Gen2 and 2 lanes DP1.4a
input OR 4 lanes DP1.4a input
Flip option for connector plug orientation
DP lane swap and polarity swap
• DisplayPort® (DP) ver.1.4a compliant receiver
Link rate 1.62 / 2.74 / 5.4 / 8.1Gbps
1, 2, or 4 lanes configuration
MST up to 6 streams (compressed /uncompressed)
FEC Decode
DSC Transport & Decode
AUX CH 1 Mbps
HPD_OUT
Adaptive receiver equalization
TPS4 EQ Phase LT support
Scrambling of main link data
De-spreading of link frequency
Video Stream Handling
■ RGB/ YCC 444/422/420 pixel format up to 16
bpc
■ Up to 1080 Mpix/sec dual pixel path
DPCD
■ DPCD data structure revision 1.4
■ DSC support capability & control
■ FEC capability & control
■ SST Split SDP capability
■ VSC_EXT_SDP for VESA & CTA
■ Protocol converter capability & control
■ Virtual DP Peer Device capability & control
■ CEC tunneling over AUX
Chainable SDP packets (2KB or more metadata
per stream)
Adaptive Sync SDP
PPS SDPAudio stream handling
■ Non-HBR Compressed Formats
• 2/8 ch layouts
• Up to 192kHz sample rates
• Dolby Digital, Digital+, Atmos
HBR Audio Formats
■ 8 ch layout
■ Up to 1536kHz sample rates
■ Dolby TrueHD, Atmos, DTS Master
■ LPCM Formats
■ 2/8/16/32 Ch
■ Up to 192kHz sample rates
■ 3D LPCM, speaker allocation & mapping
March 2023 - Revision 04d
OneBit DSD Formats
■ 2/8 ch
■ Single & Double Rate
■ 12288 kHz sample rates
DST DSD Formats
■ Single/Double rate
■ Up to 22579.2kHz
Audio InfoFrame/ ACP/ ISRC/ Audio Metadata DI
packets
• Triple DP1.4a / HDMI2.0b (DP++) transmitters
DP mode
■ Lane count, Link rate conversion
■ Link rate 1.62 / 2.74 / 5.4 / 8.1Gbps
■ 1, 2, or 4 lanes configuration
■ DSC stream transport with FEC Encode
■ MST up to 6 streams (compressed /
uncompressed)
■ AUX CH 1 Mbps
■ 3.3V HPD_IN
HDMI mode
■ TX1 & TX3: VML AC coupled HDMI
■ TX2: CML DC-coupled HDMI
■ No External Level shifters needed
■ 600 MHz maximum TMDS character clock
■ TMDS character-clock divide_by_4 mode
■ HPD_IN (5V Tolerant)
■ DDC CH (5V Tolerant)
• HDMI 2.1 Features
Through 6GHz TMDS Mode
Supports 4k120Hz,4:2:0, 8bpc with Adaptive Sync
to VRR conversion
Dynamic HDR Metadata through Extended
Metadata Packet
Supports VRR, FVA, QMS, QFT, ALLM
Scrambler for DP/HDMI output
Programmable signal amplitude and edge rate
control
Programmable pre-emphasis control
Pixel format RGB / YCC 444/422/420
Deep color up to 16 bits per color
3D video timings
CEC support – snooping, tunneling
SCDC read request handling
Metadata handling
Conversion to DVI output
Link power management
Page 1 of 35
Kinetic Technologies Confidential
KTM5030
Features (continued)
• USB3.2 compliant re-timer
5Gbps and 10Gbps support
Spread spectrum clocking
LFPS polling and processing
Lane polarity inversion
Bit level re-timer for SS mode
SRIS (Separate Reference Clock Independent
SSC) for SSP mode
Adaptive Receiver Equalization
Multi-tap FIR EQ Transmitter Emphasis
• Video processing
MST to SST conversions or pass-through
SST lef-right separation
Color space conversion from RGB to YCC
Colorimetry support: BT2020, BT709, BT601, and
Adobe RGB
Color bit depth expansion (10 to 12 bits) 16 bits per
color pass through
DP to HDMI Stereoscopic 3D Transport
Frame sequential to stacked top-bottom conversion
Pass through of other 3D formats
Programmable coefficient 3x3 matrix
■ Programmable input offset
■ Programmable output offset
■ Programmable output clipping levels
Chroma down sampling
■ 5-tap H & V FIR filters with programmable
coefficients
■ 12 bits per color input width
■ 12 bits per color output width
■ YCbCr444 to YCbCr420 conversion
■ YCbCr444 to YCbCr422 conversion
Pass through for YCbCr444/422/420
Dual DSC1.2A stream decoding
1/2/4 Slice DSC1.2Aa RGB/YCC444/422/420 10-b
format support
FEC decoding / encoding
Video Horizontal blanking expansion
Pixel stream de-skewing
Adaptive Sync Video
• Max video resolution and color depth on DP output
uncompressed
■ 5K3K60Hz, RGB/YCbCr444, 8 bpc
■ 8K4K60Hz, YCbCr420 up to 8 bpc
■ 4K2K120Hz, RGB/YCbCr444, 8 bpc
• Max video resolution and color depth on DP output
compressed (DSC)
■ 8K4K60Hz, RGB/YCC444 up to 8 bpc
■ 5K3K60Hz, RGB/YCbCr444, 12 bpc
■ 4x 4K2K60Hz, RGB/YCbCr444, 8 bpc
March 2023 - Revision 04d
• Max video resolution and color depth on HDMI TX
■ 4Kp60Hz, RGB/YCbCr444, 8 bpc
■ 4Kp60Hz, YCbCr420, up to 16 bpc
■ 4Kp30Hz, RGB/YCbCr444, up to 16 bpc
• Audio processing
Audio stream forwarding from DP RX to HDMI TX
Conversion to I2S or TDM audio output (8 CH)
Conversion to SPDIF audio output (2CH)
• HDCP support
HDCP1.3 to HDCP1.4 Repeater function
HDCP2.3 to HDCP1.4 Repeater function
HDCP2.3 to HDCP2.3 Repeater function
Read- protected embedded HDCP keys
• Enhanced security
Encrypted on-chip key storage
RSA-2048bit signed application firmware
Secure Boot & In-system Programming
Test, debug ports deactivation
• Metadata handling
HDMI TX DVI/HDMI mode setting (DPCD register)
YCbCr444-420 conversion (DPCD register)
IEC60958 BYTE3 channel status overwrite
CTA861G INFO FRAME generation
CTA861.3 HDR and Mastering InfoFrame
Chainable VSC_EXT SDP packing format
• ARM processor and peripheral controllers
ARM Cortex M3 core
SPI controller
I2C master, slave controller
On-Chip, RAM, ROM, OTP
• Device configuration options
Application FW stored in SPI flash
AUX CH, I2C host interface
• Internal video pattern generator
Configurable through vendor specific DPCD
registers
• EMI reduction support
Spread spectrum for DP input, output
Scrambler for DP and HDMI outputs
• Low power operation
860mW nominal operation with retimer
700mW nominal operation without retimer
Under 10mW Standby operation
• ESD specification
ESD: ±2kV HBM, 500 V CDM
• Package
289 LFBGA (12 x 12mm)
Halogen free Halogen free RoHS and Green
Compliant
• Power supply voltages
1.8V Analog and I/O, 0.95V Analog and core
Page 2 of 35
Kinetic Technologies Confidential
KTM5030
Description
The KTM5030 is an advanced DisplayPort1.4a MST
hub with an integrated USB type-C de-multiplexer,
targeted primarily for Mobile Notebook accessory and
display applications. This device functions as a multistream audio-video splitter and protocol converter with
an HDCP1.x/ HDCP2.3 repeater supporting both
compressed (DSC) and uncompressed AV streams.
KTM5030 has a DP alt-mode capable USB Type-C
Upstream Facing Port (UFP). The four high speed
lanes of UFP can receive DP1.4a MST audio-video
and USB3.2 Gen2 data streams simultaneously. The
input lane mapping is flexible and meets standard DP
or the USB Type-C connector with flip orientation
requirements. The incoming DP and USB signals are
de-multiplexed, retimed, and transmitted on the
Downstream Facing Ports (DFP). The KTM5030
consists of three AC coupled DP/DP++ or DC coupled
HDMI/DVI DFPs, each with four high-speed lanes and
one USB port with USB3.2 TX and RX pair. The
Stream Routing Logic in KTM5030 allows flexible
routing of incoming DP MST stream converted into any
combination of MST or SST streams on any of the DFP
video ports with link rate and lane count change
option. Also, the SST stream can be replicated on two
or more DFP ports. In addition, the DP SST stream
can be converted into a HDMI or DVI output (TMDS
signal format).
The combo receiver in KTM5030 supports all DP
standard data rates up to HBR3 (8.1 Gbps/lane) and
USB3.2 Gen1 (5.0 Gbps) and Gen2 (10.0 Gbps). The
dual mode (DP++) transmitters support DP standard
data rates up to 8.1 Gbps/lane and TMDS data rates
up to 6.0 Gbps/lane. The side-band channel uses 1.0
Mbps Manchester-coded AUX signaling for DP and
DDC signaling up to 100kbps for the HDMI interface.
KTM5030 is capable of processing up to six DP audiovideo streams compressed or uncompressed. FEC
decoding and encoding is employed for the reliable
reception and transmission of DSC1.2a compressed
streams. These streams can be part of one single
large video timing or six independent video timings
from a single source with corresponding independent
multi-channel audio. The highest video timing per
stream and the number of streams transported is
limited by the DP1.4a and HDMI2.0 link bandwidth.
When the received DP MST stream is in DSC1.2a
compressed format, KTM5030 can decode the
March 2023 - Revision 04d
streams (max two streams) or pass through to the
downstream sink or to another cascaded KTM5030
device. If a DP source sends an 8k4k60Hz
RGB/YCC444 DSC1.2a encoded video as four
4k2k60Hz MST, then two KTM5030 devices are
needed to decode all four streams. KTM5030 supports
both RGB 444 and YCC444/422/420 video pixel
encoding formats with a color depth up to 16 bpc (bits
per component or 48 bits per pixel). It has a pixel
processing unit capable of video pixel encoding format
conversion from RGB444 to YCC444 with bit depth
expansion and down scaling from YCC444 to
YCC422/420. Pixel format conversion along with
horizontal
blanking
expansion
improves
interoperability and smooth rendering of CVT video
timings from a mobile PC on a consumer displays such
as TVs and projectors which supports only CEA
timings.
KTM5030 processes High Dynamic Range (HDR)
video content specified in BT601, BT709, BT2020,
BT2100 , Adobe RGB colorimetry format with the
proper metadata conversion from DP to HDMI. It also
offers secure reception and transmission of high
bandwidth digital audio and video content with
HDCP1.x or HDCP2.3 content protection. As a branch
device KTM5030 functions as a HDCP1.x and
HDCP2.3 repeater between the DP source and DP or
HDMI sink.
KTM5030 uses an external 25 MHz reference clock for
its operation. The reference clock can be generated
from a 25MHz crystal or from an external source. It has
a 300MHz ARM Cortex M3 CPU with on-chip
memories for code and data storage. The peripheral
subsystem includes SPI, UART (debug only), and I2C
master, slave interfaces. An internal Power-On Reset
(POR) circuit senses the voltage on the reset input and
provides the chip reset during system power-up. The
KTM5030 uses an external 16 Mbit SPI flash memory
for storing the RSA-2048 signed application firmware
with fail-safe recovery. At boot up, the CPU goes
through a secure boot process authenticating the
application code image stored in the SPI flash. It
supports both standard mode and quad mode SPI
operation. Firmware update for the SPI flash is done
securely through the DP AUX_CH or I2C host
interface (Secure In-System-Programming).
Page 3 of 35
Kinetic Technologies Confidential
KTM5030
Table 1. Part Numbers
Features
KTM5030
USB-C
(DP alt-mode)
(DP 4 lanes OR
2 lanes DP and
2 lanes USB3.2)
3x DP++
(DP or HDMI)
1x USB3.2
Yes
Input
Outputs
USB De-mux & Re-timer
HDCP2.2
Yes
HDR, Pixel Processor
Yes
DSC & FEC
Yes
Package
LFBGA 12x12mm / 0.65mm pitch
Applications
The target applications of the KTM5030 are:
• Mobile PC docking stations
• Dongles
• MST video hubs
• AR / VR devices
• High end displays such as digital signage
• Daisy-chain monitors
DisplayPort and USB Type-C are the prominent interfaces in these applications and the KTM5030 offers the highest
performance at the optimum bill of material cost.
Docking Station Application
In a mobile docking station topology, the KTM5030 is part of a larger system which has a system controller such as
TCPC, USB hub, etc. The docking station can be a traditional dock with a custom connector or a travel dock with a
USB Type-C tethered cable. The audio-video interface between the notebook and the docking station is either DP
or DP Alt-Mode over USB Type-C. The KTM5030 is an ideal device for a Type-C docking station where it can function
as a Type-C Port Manager (TCPM) along with an external TCPC device (e.g. Kinetic MCDP9000 TCPC). It is
designed with integrated features such as a USB-C de-mux, a video hub, a protocol converter, and an HDCP repeater
in a single chip. The downstream video ports can be configured as DP1.4a or HDMI2.0 depending on the
requirements.
Docking Station
DP or HDMI cable
Monitor
TCPC
DP or HDMI cable
Notebook
KTM5030
Monitor
DP or USB Type-C
Connector /cable
USB
Hub
DP or HDMI cable
Monitor
USB Type-A or Type-C Ports
Figure 1. KTM5030 Docking Station Use Case
March 2023 - Revision 04d
Page 4 of 35
Kinetic Technologies Confidential
KTM5030
Daisy-Chain Monitor / Signage Application
A daisy-chain monitor or signage featuring the USB Type-C connector supporting the DP Alt-mode requires a USB
Type-C de-mux and a DP MST hub device with two or more video outputs. KTM5030 is an ideal fit for such
applications where it can receive the USB and multiple video streams simultaneously. It then routes one of the video
stream to the internal SoC and the remaining streams to the downstream units. In this use case, the KTM5030 can
support two 4K60Hz displays without DSC or up to four 4K60Hz displays with DSC.
For a Large Format Display Application, such as a 5x5 video wall configuration, KTM5030 can support 25 or more
daisy chained displays.
Signage System
SoC
KTM5030
Signage System
Signage System
SoC
SoC
KTM5030
KTM5030
Signage System
SoC
KTM5030
Figure 2. KTM5030 Digital Signage Use Case
AR/VR Application
The current AR/VR head mount displays use a video splitter device for routing the video from the graphics source to
the dual OLED panels. Future designs are targeting higher video resolutions, refresh rates, and low latency. The
KTM5030 is suitable for such designs; it can deliver up to 2x 2560x2160 @120 Hz without DSC or up to 2x
3860x2160@ 90 Hz with DSC. Additionally, the KTM5030 can generate a global frame synchronization signal for
synchronizing the video with the sensor inputs. Also it can deliver up to 8CH compressed or LPCM audio through the
I2S or TDM format to audio codec for the best quality audio experience.
HMD System
TCPC
eDP
USB-C
KTM5030
Panel
eDP
I2S/
TDM
Sensor
Hub
Panel
Audio
Codec
Figure 3. KTM5030 AR/VR Head Mount Display Use Case
March 2023 - Revision 04d
Page 5 of 35
Kinetic Technologies Confidential
KTM5030
Functional Block Diagram
USB Receiver
/ Transmitter
USB3.1 TX
USB3.1 RX
ML0_RX_P/_N
USB Retimer
ML1_RXTX_P/_N
ML3_RX_P/_N
DP/HDMI
Combo
Transmitter
Demux
USB-DP
Combo
Receiver /
Transmitter
ML2_RXTX_P/_N
RX_AUX_P/_N
Audio, Video
processing
(DSC, Color
Conversion )
Routing
Logic,
Lane, Link
Conversion
RX_HPD_OUT
XTAL
Clock
Generation
TCLK
GPIO
SPI
UART
I2C Slave
DP / HDMITX2_P /_N
DP / HDMITX2_P /_N
DP / HDMITX2_P /_N
DP / HDMITX2_P /_N
AUX / DDC CH
HPD_IN
DP / HDMITX3_P /_N
DP / HDMITX3_P /_N
DP / HDMITX3_P /_N
DP / HDMITX3_P /_N
AUX / DDC CH
HPD_IN
I2S /SPDIF
I2S /SPDIF Out
CEC
HDMITX_CEC
ALERTN
I2CM_SDA
Page 6 of 35
AUX / DDC CH
HPD_IN
I2C Master
I2CM_SCL
I2C_SDA
I2C_SCL
UART_RX
UART_TX
SPI_DI
SPI_DO
SPI_CLK
SPI_CS
SPI_WPN
GPIO0
*
*
GPIO37
March 2023 - Revision 04d
DP/HDMI
Combo
Transmitter
OCM
ARM- M3
Reset
Generation
RESETN
DP/HDMI
Combo
Transmitter
DP / HDMITX1_P /_N
DP / HDMITX1_P /_N
DP / HDMITX1_P /_N
DP / HDMITX1_P /_N
Kinetic Technologies Confidential
KTM5030
BGA Footprints and Pin Mapping
The ball grid array (BGA) diagrams give the allocation of pins to the package shown, from the top looking down, using
the PCB footprint.
Some signal names in BGA diagrams have been abbreviated. Refer to the pin list for full signal names sorted by pin
number.
2
3
4
5
A
HPD_OUT_
GPIO2
1
GND
SSRX2P
_RX3N
GND
SSTX2P
_RX2N
B
I2CM_SCL_
PCONF1
GND
SSRX2N
_RX3P
GND
C
ALERTN_PP
OL
GND
GND
GND
6
7
8
9
10
11
12
13
14
15
16
17
GND
RX_REXT
REFCLK_OU
T
GND
SSTX1P
_RX1P
GND
SSRX1P
_RX0P
GND
TX0_ SSRXP
GND
TX0_ SSTXP
GND
A
SSTX2N
_RX2P
GND
EXT_RESETN
GND
GND
SSTX1N
_RX1N
GND
SSRX1N
_RX0N
GND
TX0_ SSRXN
GND
TX0_ SSTXN
GND
B
GND
GND
XTAL_IN
XTAL_OUT
GND
GND
GND
GND
GND
C
GND
NC
TX1_
CONFIG1_G
PIO11
SPI_DO
D
AVDD18_UFP AVDD18_UFP AVDD18_UFP AVDD18_UFP
D
I2CM_SDA_
PCONF0
GND
RX_AUXN_SB RX_AUXP_S
AVDDP9_UF AVDDP9_UF
AVDDP9_UFP AVDDP9_UFP AVDDP9_UFP
AVDDP9_UFP AVDDP9_UFP AVDDP9_UFP AVDDP9_UFP
U1
BU2
P
P
E
TX3_
DDC_SCL
GPIO0_
I2C_SDA
GND
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
DVDD18
SPI_CLK
SPI_HOLD
E
F
TX3_
HPD_IN
GPIO1_
I2C_SCL
GND
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
DVDD18
SPI_CSN
SPI_DI
F
G
TX2_
DDC_SCL
TX3_
DDC_SDA
DVDD18
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
TEST
SPI_WPN
URX_GPIO8
G
H
TX1_
DDC_SDA
TX2_
DDC_SDA
DVDD18
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
DVDD18
TX2_
UTX_GPIO9 CONFIG1_G
PIO12
H
J
TX1_
DDC_SCL
TX2_
HPD_IN
GND
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
DVDD18
TX3_
DBUG0_GPI
CONFIG1_G
O6
PIO13
J
K
TX1_CEC_G
PIO10
TX1_
HPD_IN
GND
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
DVDD18
I2S_WCK_G DBUG1_GPI
PIO14
O7
K
L
TX3_CEC_G GPIO37_TX2
PIO36
_CEC
GND
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
DVDD18
I2S_D0_GPI I2S_FCK_G
O16
PIO15
L
I2S_D2_GPIO I2S_D3_GPI I2S_D1_GPI
18
O19
O17
M
M
GND
GND
TX2_AUX_N
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
N
TX1_L3_HD
MICLK_N
GND
TX2_AUX_P
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N
P
TX1_L3_HD
MICLK_P
GND
TX1_AUX_N
AVDDP9_TX AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
GND
TX3_AUX_N
GND
TX3_L0_HD
MICH2_P
P
R
TX1_L2_HD
MICH0_N
GND
TX1_AUX_P
AVDD18_TX
TX1_CM
AVDD18_TX
AVDD18_TX
TX2_CM
AVDD18_TX
AVDD18_TX
AVDD18_TX
TX3_CM
AVDD18_TX
GND
TX3_AUX_P
GND
TX3_L0_HD
MICH2_N
R
T
TX1_L2_HD
MICH0_P
GND
GND
GND
GND
TX2_L3_HDMI
CLK_N
GND
GND
GND
GND
TX2_L0_HDMI
CH2_P
GND
GND
GND
GND
GND
TX3_L1_HD
MICH1_P
T
U
TX1_L1_HD TX1_L1_HD TX1_L0_HDMI TX1_L0_HD
MICH1_N
MICH1_P
CH2_N
MICH2_P
GND
TX2_L3_HDMI TX2_L2_HDMI TX2_L2_HDM TX2_L1_HDM TX2_L1_HDM TX2_L0_HDMI
CLK_P
CH0_N
ICH0_P
ICH1_N
ICH1_P
CH2_N
GND
TX3_L3_HDMI TX3_L3_HDMI TX3_L2_HDMI TX3_L2_HD TX3_L1_HD
CLK_N
CLK_P
CH0_N
MICH0_P
MICH1_N
U
1
2
3
4
5
6
7
AVDDP9_TX AVDDP9_TX AVDDP9_TX
8
9
10
11
12
13
14
15
16
17
TOP VIEW
10GHz
SERDES
GND
ANALOG
DIGITAL 1.8V
I/O
DIGITAL 5V
1.8V ANALOG
TOL OPEN- 0.9V DIGITAL 0.9V ANALOG 1.8V DIGITAL
VDD
DRAIN I/O
289-Pin 12.0mm x 12.0mm x 1.3mm
LFBGA Package, 0.65mm pitch
Figure 4. KTM5030 BGA Diagram
March 2023 - Revision 04d
Page 7 of 35
Kinetic Technologies Confidential
KTM5030
KTM5030B0
TNNNNN ES
YYWWVXXX
289-Pin 12.0mm x 12.0mm x 1.3mm
LFBGA Package, 0.65mm pitch
Table 2. Field Marking Description
Field
Description
Marking
DOT
Pin1 indicator
DOT
Line 1
Company logo
Kinetic Logo
Line 2
Part Number + IC revision
Traceability codes
TNNNNN: Fab Lot Number
ES: for Engineering Samples
YYWW: Assembly Date Code (Work Year & Work Week)
V: Assembly Vendor Code
XXX: Serial Number
KTM5030B0
Line 3
Line 4
March 2023 - Revision 04d
Page 8 of 35
“Variant”
“Variant”
Kinetic Technologies Confidential
KTM5030
Table 3. Pin List
Pin #
Name
Pin #
Name
Pin #
Name
A1
A2
A3
A4
A5
HPD_OUT_GPIO2
GND
SSRX2P _RX3N
GND
SSTX2P _RX2N
C9
C10
C11
C12
C13
GND
AVDD18_UFP
AVDD18_UFP
AVDD18_UFP
AVDD18_UFP
E17
F1
F2
F3
F4
SPI_HOLD
TX3_HPD_IN
GPIO1_I2C_SCL
GND
DVDDP9
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
GND
RX_REXT
REFCLK_OUT
GND
SSTX1P _RX1P
GND
SSRX1P _RX0P
GND
TX0_ SSRXP
GND
TX0_ SSTXP
GND
C14
C15
C16
C17
D1
D2
D3
D4
D5
D6
D7
D8
GND
GND
GND
GND
I2CM_SDA_PCONF0
GND
RX_AUXN_SBU1
RX_AUXP_SBU2
AVDDP9_UFP
AVDDP9_UFP
AVDDP9_UFP
AVDDP9_UFP
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDDP9
DVDD18
SPI_CSN
B1
B2
B3
B4
B5
B6
B7
I2CM_SCL_PCONF1
GND
SSRX2N _RX3P
GND
SSTX2N _RX2P
GND
EXT_RESETN
D9
D10
D11
D12
D13
D14
D15
F17
G1
G2
G3
G4
G5
G6
SPI_DI
TX2_DDC_SCL
TX3_DDC_SDA
DVDD18
DVDDP9
GND
GND
B8
GND
D16
G7
GND
B9
B10
B11
B12
B13
B14
B15
B16
B17
GND
SSTX1N _RX1N
GND
SSRX1N _RX0N
GND
TX0_ SSRXN
GND
TX0_ SSTXN
GND
D17
E1
E2
E3
E4
E5
E6
E7
E8
AVDDP9_UFP
AVDDP9_UFP
AVDDP9_UFP
AVDDP9_UFP
AVDDP9_UFP
GND
NC
TX1_
CONFIG1_GPIO11
SPI_DO
TX3_DDC_SCL
GPIO0_I2C_SDA
GND
DVDDP9
GND
GND
GND
GND
G8
G9
G10
G11
G12
G13
G14
G15
G16
GND
GND
GND
GND
GND
GND
DVDDP9
TEST
SPI_WPN
C1
C2
C3
C4
C5
C6
C7
C8
ALERTN_PPOL
GND
GND
GND
GND
GND
XTAL_IN
XTAL_OUT
E9
E10
E11
E12
E13
E14
E15
E16
GND
GND
GND
GND
GND
DVDDP9
DVDD18
SPI_CLK
G17
H1
H2
H3
H4
H5
H6
H7
URX_GPIO8
TX1_DDC_SDA
TX2_DDC_SDA
DVDD18
DVDDP9
GND
GND
GND
Continues on page 12
March 2023 - Revision 04d
Page 9 of 35
Kinetic Technologies Confidential
KTM5030
Pint List (Continued)
Pin #
Name
Pin #
Name
Pin #
Name
H8
H9
H10
H11
H12
GND
GND
GND
GND
GND
K16
K17
L1
L2
L3
I2S_WCK_GPIO14
DBUG1_GPIO7
TX3_CEC_GPIO36
GPIO37_TX2_CEC
GND
N7
N8
N9
N10
N11
GND
GND
GND
GND
GND
H13
H14
H15
H16
GND
DVDDP9
DVDD18
UTX_GPIO9
TX2_
CONFIG1_GPIO12
TX1_DDC_SCL
TX2_HPD_IN
GND
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
L4
L5
L6
L7
DVDDP9
GND
GND
GND
N12
N13
N14
N15
GND
GND
GND
GND
L8
GND
N16
GND
L9
L10
L11
L12
L13
L14
L15
L16
L17
M1
M2
M3
GND
GND
GND
GND
GND
DVDDP9
DVDD18
I2S_D0_GPIO16
I2S_FCK_GPIO15
GND
GND
TX2_AUX_N
N17
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
GND
TX1_L3_HDMICLK_P
GND
TX1_AUX_N
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
AVDDP9_TX
M4
M5
M6
M7
DVDDP9
GND
GND
GND
P12
P13
P14
P15
AVDDP9_TX
AVDDP9_TX
GND
TX3_AUX_N
H17
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
M8
GND
P16
GND
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
GND
DVDDP9
DVDD18
DBUG0_GPIO6
TX3_
CONFIG1_GPIO13
TX1_CEC_GPIO10
TX1_HPD_IN
GND
DVDDP9
GND
GND
GND
GND
GND
GND
GND
GND
M9
M10
M11
M12
M13
M14
M15
M16
M17
N1
N2
N3
GND
GND
GND
GND
GND
DVDDP9
I2S_D2_GPIO18
I2S_D3_GPIO19
I2S_D1_GPIO17
TX1_L3_HDMICLK_N
GND
TX2_AUX_P
P17
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
TX3_L0_HDMICH2_P
TX1_L2_HDMICH0_N
GND
TX1_AUX_P
AVDD18_TX
TX1_CM
AVDD18_TX
AVDD18_TX
TX2_CM
AVDD18_TX
AVDD18_TX
AVDD18_TX
K13
K14
K15
GND
DVDDP9
DVDD18
N4
N5
N6
GND
GND
GND
R12
R13
R14
TX3_CM
AVDD18_TX
GND
J17
Continues on page 13
March 2023 - Revision 04d
Page 10 of 35
Kinetic Technologies Confidential
KTM5030
Pint List (Continued)
Pin #
Name
R15
R16
R17
T1
T2
TX3_AUX_P
GND
TX3_L0_HDMICH2_N
TX1_L2_HDMICH0_P
GND
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
GND
GND
GND
TX2_L3_HDMICLK_N
GND
GND
GND
GND
TX2_L0_HDMICH2_P
GND
GND
GND
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
U9
GND
GND
TX3_L1_HDMICH1_P
TX1_L1_HDMICH1_N
TX1_L1_HDMICH1_P
TX1_L0_HDMICH2_N
TX1_L0_HDMICH2_P
GND
TX2_L3_HDMICLK_P
TX2_L2_HDMICH0_N
TX2_L2_HDMICH0_P
TX2_L1_HDMICH1_N
U10
U11
U12
U13
U14
U15
U16
U17
TX2_L1_HDMICH1_P
TX2_L0_HDMICH2_N
GND
TX3_L3_HDMICLK_N
TX3_L3_HDMICLK_P
TX3_L2_HDMICH0_N
TX3_L2_HDMICH0_P
TX3_L1_HDMICH1_N
March 2023 - Revision 04d
Page 11 of 35
Kinetic Technologies Confidential
KTM5030
Ordering Information
Part Number
Functional Description
KTM5030B0
USB-C/ DP alt-mode
DP 4 lanes OR 2 lanes DP and 2 lanes
USB3.2
DSC
KTM5030B0T
Marking1
Operating
Temperature
Package
External
Package
TRAYS
KTM5030B0
0°C to +70°C
289- LFBGA
Tape and Reel
Absolute Maximum Ratings2
(TA = 25C unless otherwise noted)
Symbol
Description
Value
Units
VVDD_1.8
VDD1.8V to GND
-0.3 to 2.16
V
VVDD_0.95
VIO0.95V to GND
-0.3 to 1.14
V
VIN5tol
Input voltage tolerance for 3.3V, 5V tolerant I/O pins
-0.3 to 5.5
V
TSTG
Storage temperature
-40 to 150
C
TSOL
Peak IR reflow soldering temperature
260
C
ESD and Latch-up Ratings3
Symbol
Description
Value
Units
VESD_HBM
JEDEC JESD22-A114 ESD HBM (all pins)
±2.0
kV
VESD_CDM
JEDEC JESD22-C101 ESD CDM (all pins)
±500
V
JEDEC JESD78
±100
mA
Value
Units
27
C/W
ILU
Thermal Capabilities4
Symbol Description
ΘJA
Thermal Resistance – Junction to Ambient
ΘJC
Thermal Resistance – Junction to Case
8.473
C/W
TA
Ambient Operating Temperature Range
0 to 70
C
TJ
Junction Operating Temperature Range
0 to 125
C
1. See Table 1 for trace codes marking details;. ES – Engineering Sample.
2. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions
other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
3. ESD and Latch-up Ratings conform to JEDEC industry standards. Some pins may actually have higher performance. Ratings apply with chip
enabled, disabled, or unpowered, unless otherwise noted.
4. Junction to Ambient thermal resistance is highly dependent on PCB layout. Values are based on thermal properties of the device when soldered
to a four-layer JEDEC PCB board, no heat spreader, and no air flow.
March 2023 - Revision 04d
Page 12 of 35
Kinetic Technologies Confidential
KTM5030
Electrical Characteristics5
Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of
0°C to +70°C and VDD_1.8V = 1.8V, VDD_0.95V = 0.95V. Typical values are specified at TA = +25°C.
DC Characteristics
Supply Specifications
Symbol Description
Min
Typ
Max
Units
VVDD_1.8
1.8V supply voltages (analog and digital)
Conditions
1.71
1.8
1.89
V
VVDD_0.9
0.95V supply voltages (analog and digital)
0.90
0.95
1.00
V
550
600
mW
626
711
mW
712
795
mW
Power
Protocol converter Mode
Measurement condition:
Nominal corner, 25°C, Nominal power supply
Operating condition 1
Input: DP MST HBR3 (4L)
Output1: DP SST HBR3 (4L) 4k2k30Hz
Output2: DP SST HBR3 (4L) 4k2k30Hz
Output3: HDMI 4k2k30Hz
Operating condition 2
Input: DP MST HBR3 (4L)
Output1: DP SST HBR3 (4L) 1080p60Hz
Output2: DP SST HBR3 (4L) 4k2k30Hz
Output3: HDMI 4k2k60Hz
Operating condition 3
Input: DP SST HBR3 (4L) 4k2k60Hz
Output1: DP SST HBR3 (4L) 4k2k60Hz
Output2: DP SST HBR3 (4L) 4k2k60Hz
Output3: HDMI 4k2k60Hz
Standby
IDD_0.95V
0.95V Supply Current
IDD_1.8V
1.8V Supply Current7
9.2
Nominal corner, 25°C,
Nominal power supply
Operating condition 3 (See above)
VDD (analog and digital) 0.95V
VDD (analog and digital) 1.8V
TRAMP_MIN Minimum Power Rail Ramp up Time
100
mW
7336
892
mA
146
155
mA
µS
5. Device is guaranteed to meet performance specifications over the 0°C to +70°C operating temperature range by design, characterization and
correlation with statistical process controls.
6. Values are for Power Supply design only and not indicative for Max Power Consumption.
7. Ripple amplitude for power supplies should be 20mV or lower with max ripple frequency up to 30MHz.
March 2023 - Revision 04d
Page 13 of 35
Kinetic Technologies Confidential
KTM5030
Electrical Characteristics5 (continued)
Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of
0°C to +70°C and VDD_1.8V = 1.8V, VDD_0.95V = 0.95V. Typical values are specified at TA = +25°C.
3.3V IO Signals, 5V Tolerant Open Drain Type
Symbol
VPAD
Description
Conditions
Min
Input Voltage at PAD
VIH
Input High voltage
Typ
Max
Units
5
6
V
2.0
V
VIL
Input Low voltage
0.8
V
VOL
Output Low voltage
0.4
V
IOL
Output Low current (measured at VOL = 0.4V)
8.7
10.7
mA
IIL
2.4
3.8
A
2
3.2
A
Ivref
Input Leakage current
Input Leakage in Fail Safe (unpowered
VDD/VREF)
VREF DC current
0.1
0.8
nA
Ivdd
VDD DC current
0.8
3.9
A
Typ
Max
Units
IIL_off
5.3
1.8V IO Signals, 1.8V Tolerant, TRISTATE
Symbol
Description
Conditions
Min
VIH
Input High voltage
VIL
Input Low voltage
0.55
V
VOL
Output Low voltage
0.45
V
VOH
Output High voltage
-10
10
A
-10
10
A
IIH
IIL
1.25
V
1.35
Input Leakage current
V
Tri-state output Leakage current
Pull-up Resistor
80
kΩ
RPD
Pull-down Resistor
95
kΩ
March 2023 - Revision 04d
-10
Page 14 of 35
10
A
IOZ
RPU
Kinetic Technologies Confidential
KTM5030
Electrical Characteristics5 (continued)
Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of
0°C to +70°C and VDD_1.8V = 1.8V, VDD_0.95V = 0.95V. Typical values are specified at TA = +25°C.
AC Characteristics8
Maximum Speed of Operation
Symbol
Description
Conditions
Min
Typ
Max
Units
TCLK
Reference Input Clock
25
MHz
OCLK
On-Chip Microcontroller Clock
300
MHz
SLAVE_SCL
I2C host interface clock
400
kHz
MSTRx_SCL
DDC Master
400
kHz
SPI Clock
75
MHz
Max
Units
800
mV
SPI
DisplayPort Receiver Characteristics
Receiver Operating Range
Symbol
Description
Conditions
Min
Typ
VRX_DIF_PP_RANGE
Differential Input Voltage Range
40
RRX_TERM_RANGE
RX Termination Control Range
80
100
120
Ω
Min
Typ
Max
Units
System Parameters
Symbol
Description
Conditions
UIHBR3
HBR3 unit interval (8.1Gbps)
123
Ps
UIHBR2
HBR2 unit interval (5.4Gbps)
185
Ps
UIHBR
HBR unit interval (2.7Gbps)
370
Ps
UIRBR
RBR unit interval (1.62Gbps)
617
ps
Link clock down spreading
Modulation frequency range of
30kHz to 33kHz
0
0.5
%
8. AC characteristics parameters are guaranteed by the silicon characterization across operating condition unless otherwise specified. Not all
parameters are tested in the production test.
March 2023 - Revision 04d
Page 15 of 35
Kinetic Technologies Confidential
KTM5030
Electrical Characteristics5 (continued)
Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of
0°C to +70°C and VDD_1.8V = 1.8V, VDD_0.95V = 0.95V. Typical values are specified at TA = +25°C.
Main Link and AUX CH Parameters
Symbol
Description
Main Link Jitter Tolerance, Target Bit Error Rate
TRX_TJ_RBR
TRX_Non-ISI_RBR
TRX_TJ_HBR
TRX_Non-ISI_HBR
TRX_TJ_HBR2
TRX_Non-ISI_HBR2
TRX_TJ_HBR3
TRX_NON_ISI_HBR3
Conditions
Min
Typ
Max
Units
0.747
UI
0.177
UI
0.491
UI
0.330
UI
0.62
UI
0.40
UI
0.62
UI
0.38
UI
0.27
1.36
V
0.29
1.38
V
10-9
RBR Total jitter at TP3
EH = 56 mVdiff_pp
RBR non-ISI jitter
HBR Total jitter at TP3_EQ
EH = 160 mVdiff_pp
HBR non-ISI jitter
HBR2 Total jitter at TP3_EQ
EH = 100 mVdiff_pp
HBR2 non-ISI jitter
HBR3 Total jitter at TP3_CTLE
EH = 50 mVdiff_pp
HBR3 non-ISI jitter
AUX Parameters
VAUX_RX_DIF_RANGE
VAUX_TX_DIF_RANGE
RAUX_TERM_RANGE
Differential Input Voltage Range
Differential Output Voltage
Range
RX DIFF Termination Control
Range
March 2023 - Revision 04d
TP3
100
Page 16 of 35
Ω
Kinetic Technologies Confidential
KTM5030
Electrical Characteristics5 (continued)
Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of
0°C to +70°C and VDD_1.8V = 1.8V, VDD_0.95V = 0.95V. Typical values are specified at TA = +25°C.
DisplayPort Transmitter Characteristics
Transmitter Operating Range
Symbol
Description
Conditions
VTX_DIF_PP_RANGE
Differential Output Voltage Range
RTX_TERM_RANGE
TX Termination Control Range
Min
80
Typ
100
Max
Units
1.38
V
120
Ω
DisplayPort Transmitter System Parameters
UIHBR3
HBR3 unit interval (8.1Gbps)
123
ps
UIHBR2
HBR2 unit interval (5.4Gbps)
185
ps
UIRBR
HBR unit interval (2.7Gbps)
370
ps
UIRBR
RBR unit interval (1.62Gbps)
617
ps
Modulation frequency range of
30kHz to 33kHz
All Main lanes and AUX CH need
AC coupling on the transmitter
side
Link clock down spreading
CTX
Coupling capacitor
0
0.5
100
%
nF
DisplayPort Transmitter TP2 Parameters
TTX_SKEW_INTER_PAIR
Lane-to-Lane output Skew
TTX_SKEW_INRA_PAIR
Lane Intra pair Skew
Target bit error rate
TTX_TJ_TPS4_HBR3
Applies to all pairwise
combinations of supported lanes
Applies to all supported lanes
1250
ps
30
ps
0.47
UI
0.23
UI
0.58
UI
0.36
UI
10-9
HBR3 Total Jitter at TP3_CTLE
TTX_NonISI_TPS4_HBR3
HBR3 Non-ISI Jitter
TTX_TJ_CP2520_HBR2
HBR2 Total Jitter at TP3_EQ
VSL/PEL = 1/1, Adc = -3 dB
VSL/PEL = 1/1
TTX_NonISI_CP2520_HBR2 HBR2 Non-ISI Jitter
TTX_TJ_D10.2_HBR2
HBR2 Total Jitter with D10.2
Measured at TP3_EQ
0.40
UI
TTX_DJ_D10.2_HBR2
HBR2 Dual-Dirac Jitter with D10.2
Measured at TP3_EQ
0.27
UI
TTX_RJ_D10.2_HBR2
HBR2 Random Jitter with D10.2
Measured at TP3_EQ
19.2
mUIrms
0.27
1.38
V
0.29
1.38
V
AUX Parameters
VAUX_RX_DIFF_PP
Differential Input Voltage Range
VAUX_TX_DIFF_PP
Differential Output Voltage Range
RX DIFF Termination Control
Range
RAUX_TERM_RANGE
March 2023 - Revision 04d
50mV/step in 4 steps
Page 17 of 35
100
Ω
Kinetic Technologies Confidential
KTM5030
Electrical Characteristics5 (continued)
Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of
0°C to +70°C and VDD_1.8V = 1.8V, VDD_0.95V = 0.95V. Typical values are specified at TA = +25°C.
HDMI Transmitter I/O Characteristics
HDMI Transmitter DC Specifications
Symbol
VTX_PP
VTX_DIF_
HIGH
Description
Conditions
Differential output: single ended
swing amplitude
Differential output: Single ended
high-level output
Min
Typ
Max
Units
0.4
0.5
0.6
V
Sink supply dependent
(typical VDD = 3.3V)
3.3
V
HDMI Transmitter AC Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
fTX_CHR_CLK
TMDS Character Clock
Programmable
25
600
MHz
VTX_DIF_PP
Differential Output Voltage
In 64 steps (usable range 0.8 – 1.2 V)
VTX_DIF_PP + APREMPH should be less
than 1.2 V
0
1.2
V
0
6
dB
APREMPH
RTX_TERM_
RANGE
TTX_CLK_
JITTER
TX Pre-Emphasis Level
TX Differential Termination Control
Range
Programmable Termination
(range 85-600)
TX Clock jitter
Tighter than HDMI specification
TX Data Jitter
Refer to the tables below.
March 2023 - Revision 04d
Page 18 of 35
Ω
100
0.25
TBIT
Kinetic Technologies Confidential
KTM5030
B
C
A
D
E
F
Figure 5. HDMI1.4b EYE Diagram at TP1 at TMDS Character Clock Rate ≤ 340MHz
Table 4. TMDS TX EYE Opening Specification for TMDS Character Clock Rate ≤ 340MHz
Point
H(UI)
V (mV_diff_pp)
A
0.13
0
B
0.20
200
C
0.80
200
D
0.87
0
E
0.80
-200
F
0.20
-200
Figure 6. HDMI2.0 EYE Diagram at TP2_EQ at TMDS Character Clock Rate > 340MHz
Table 5. TMDS TX PHY Jitter Specification at TMDS Character Clock Rate > 340 MHz
TMDS Bit Rate (Gbps)
H (Tbit)
V (mV_diff_pp)
3.4 < Rbit < 3.712
0.72
-0.0332 Rbit2 + 0.2312
Rbit + 0.1998
0.48
335
-19.66 Rbit2 + 106.74
Rbit + 209.58
150
3.712 < Rbit ≤ 5.94
5.94 < Rbit ≤ 6.0
March 2023 - Revision 04d
Page 19 of 35
Kinetic Technologies Confidential
KTM5030
USB 3.2x1 Transmitter and Receiver Characteristics
USB 3.2 x1 transmitter (SSRX pin and Type-C interface in USB mode)
Symbol
Description
UIUSB_GEN1
Unit interval in Gen1
UIUSB_GEN2
Unit interval in Gen2
Conditions
Min
Typ
Max
Units
199.94
200.46
ps
99.97
100.03
ps
AC coupling capacitor
75
265
nF
SSC deviation
0
-5000
ppm
Modulation rate
30
33
kHz
Differential peak-to-peak voltage
swing
0.8
1.2
V
De-emphasis in Gen1
3.0
4.0
dB
VTX_PS_RATIO Pre-shoot in Gen2
VTX_DE_RATIO
De-emphasis in Gen2
1.2
3.2
dB
2.1
4.1
dB
RTX_DIFF_DC
VTX_RCV_
72
120
Ω
0.6
V
CTX_USB
tSSC_FREQ_
DEVIATION
tSSC_MOD_
RATE
VUSB_TX_
DIFF_PP
VTX_DE_RATIO
_GEN1
_GEN2
DETECT
tCDR_SLEW_
RATE
SSCdfdt
VEYE_HEIGHT_
GEN1
VEYE_HEIGHT_
GEN2
DC differential impedance
The amount of voltage change
during Rx detection
Maximum slew rate
In Gen1
10
ms/s
SSC df/dt
In Gen2
1250
ppm/
µs
Eye height at TP4 in Gen1
100
1000
mV
Eye height at TP4 in Gen2
70
1000
mV
DjUSB_GEN1
Deterministic jitter at TP4 in Gen1
430
mUI
DjUSB_GEN2
Deterministic jitter at TP4 in Gen2
530
mUI
RjUSB_GEN1
3.22
ps
1
ps
TjUSB_GEN1
RMS Random jitter at TP4 in Gen1
RMS Deterministic jitter at TP4 in
Gen2
Total jitter at TP4 in Gen1
660
mUI
TjUSB_GEN1
Total jitter at TP4 in Gen2
DjUSB_GEN2
tPERIOD
VTX_DIFF_PP_
LFPS
TDUTY_LFPS
LFPS tPERIOD
LFPS peak-to-peak differential
amplitude
LFPS duty cycle
March 2023 - Revision 04d
Page 20 of 35
671
mUI
20
80
ns
800
1000
mV
40
60
%
Kinetic Technologies Confidential
KTM5030
USB 3.2 x1 Receiver (SSRX pin and Type-C interface in USB mode)
Symbol
Description
UIUSB_GEN1
Unit interval in Gen1
UIUSB_GEN2
tSSC_FREQ_
Unit interval in Gen2
DEVIATION
tSSC_MOD_
RATE
RRX_DC
RRX_DIFF_DC
ZRX_HIGH_IMP
_DC_POS
VRX_LFPS_
DET_DIFFp-p
Conditions
Max
Units
199.94
200.46
ps
99.97
100.23
ps
SSC deviation
0
-5000
ppm
Modulation rate
30
33
kHz
18
30
Ω
72
120
Ω
Receiver DC common mode
impedance
DC differential impedance
Min
Receiver high impedance
10k
LFPS detect threshold
100
Typ
Ω
300
mV
DDC (I2C) Interface Timing Characteristics
DDC (I2C) Interface Timing
Symbol
Description
Conditions
fSCL
SCL clock rate
Fast mode
Hold time START
After this period, the 1st clock starts
tLOW
Low period of clock
SCL
tHIGH
High period of clock
SCL
tHD-STA
Min
Typ
Max
Units
0
-
400
kHz
1.2
-
-
s
1.3
-
-
s
1.2
-
-
s
1.2
-
-
s
0.7
-
0.99
s
tsu;STA
Set up time for a repeated START
tHD;DAT
Data hold time
tSU;DAT
Data setup time
Bus free time between STOP and
START
Capacitance load for each bus line
380
-
-
ns
1.3
-
-
s
-
100
400
pF
tr
Rise time
220
-
300
ns
tf
Fall time
60
0.25
VDD
0.2
VDD
-
300
ns
-
-
V
-
-
V
TBUF
CB
Vnh
Noise margin at high level
Vnl
Noise margin at low level
For master
9. The maximum tHD;DAT only has to be met if the device does not stretch the low period t LOW of the SCL signal. In the diagram below,
S = start, P = stop, Sr = Repeated start, and SP = Repeated stop conditions.
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Kinetic Technologies Confidential
KTM5030
I2C Host Interface Timing (Figure 7. I2C Timing)
Symbol
FSCL
Description
Min
Typ
SCL Clock Frequency
Max
Units
400
kHz
thd: DAT
Data hold time
0
-
µs
tSU :DAT
Data set-up time
50
-
ns
20x
(VDD/5.5)
0.5
120
ns
120
ns
tR
Rise time of both SDA and SCL signals
tF
Fall time of both SDA and SCL signals
tBUF
Bus free time between a STOP and START condition
-
µs
CB
Capacitance load for each bus line
-
550
pF
Data valid time
-
0.45
µs
Data valid acknowledge time
-
0.45
µs
Time for I2C SINGLE BYTE READ
-
110
µs
Time for I2C SINGLE BYTE WRITE
-
85
µs
Time for I2C Multi BYTE READ
-
100+35/byte
µs
85+30/byte
µs
tVD: DAT
tVD: ACK
tI2C_SBR
(400 kHz)
tI2C_SBW
(400 kHz)
tI2C_MBR
(400 kHz)
tI2C_MBW
(400 kHz)
Time for I2C Multi BYTE WRITE
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
tHD ; STA
tHD;DAT
tHIGH
tSU ;STA
Sr
tSU; STO
P
S
Figure 7. I2C Timing
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Kinetic Technologies Confidential
KTM5030
SPI Interface Timing Characteristics
SPI Interface Timing for Normal Operating Mode10
Symbol
Description
Min
Typ
Max
Units
50
75
MHz
FCLK
SPI_CLK output clock frequency for normal SPI mode
TSCKH
Serial clock high time
9.2
ns
TSCKL
Serial clock low time
9.2
ns
TR_SPI_CLK
SPI_CLK rise time @10mA drive 10pF load
TF_SPI_CLK
SPI_CLK fall time @10mA drive 10pF load
2.8
ns
3.2
ns
TCSN_SU
CSN output setup time requirement
7
ns
TCSN_HLD
CSN output hold time requirement
7
ns
T_DO_PD
Data Output propagation delay
6
ns
TDI_SU
Data Input setup time
3
ns
TDI_HLD
Data Input hold time
5
ns
10. These specifications specify the typical SPI_CLK output frequency and the minimum requirements of the interface between the SPI NOR Flash
device and KTM5030.
March 2023 - Revision 04d
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Kinetic Technologies Confidential
KTM5030
Interface Description
UFP AV Interface
The UFP AV interface consists of 4 highspeed lanes, Auxiliary channel (Side band channel) and HPD out. The highspeed lanes can receive DP audio-video streams or USB data from a source device through DP or USB Type-C link.
The high-speed lane mapping is configurable to match the standard DP connector or the USB Type-C connector.
The following table shows the KTM5030 high-speed main lanes and side band channel signal mapping for the USB
Type-C and DP connector.
STRAIGHT MAP
FLIPPED MAP
USB TYPE-C
STD DP
Assignment
Assignment
Assignment
Assignment CONNECTOR
CONNECTOR
C
D
C
D
PIN NAME
DP
DP + USB
DP_BR
DP_BR+USB PIN
NAME
KTM5030
PIN
SIGNAL NAME
B8
SBU2
AUX_CH_P
AUX_CH_P
AUX_CH_N
AUX_CH_N
15 AUX_CH_P D4 RX_AUXP_SBU2
A8
SBU1
AUX_CH_N
AUX_CH_N
AUX_CH_P
AUX_CH_P
17 AUX_CH_N D3 RX_AUXN_SBU1
B11
RX1+
ML2+
SSRX+
ML1+
ML1+
12
ML0_P
A12 RX_L0P_SSRX1P
B10
RX1-
ML2-
SSRX-
ML1-
ML1-
10
ML0_N
B12 RX_L0N_SSRX1N
A2
TX1+
ML3+
SSTX+
ML0+
ML0+
9
ML1_P
A10 RX_L1P_SSTX1P
A3
TX1-
ML3-
SSTX-
ML0-
ML0-
7
ML1_N
B10 RX_L1N_SSTX1N
B3
TX2-
ML0-
ML0-
ML3-
SSTX-
6
ML2_P
B5 RX_L2P_SSTX2N
B2
TX2+
ML0+
ML0+
ML3+
SSTX+
4
ML2_N
A5 RX_L2N_SSTX2P
A10
RX2-
ML1-
ML1-
ML2-
SSRX-
3
ML3_P
B3 RX_L3P_SSRX2N
A11
RX2+
ML1+
ML1+
ML2+
SSRX+
1
ML3_N
A3 RX_L3N_SSRX2P
RX PHY
AUX CH
LANE 0
LANE1
LANE 2
LANE 3
If the UFP connector in the system is DP, then all the UFP interface signals are routed to the connector, if the UFP
connector is USB Type-C then only the high-speed lanes are routed connector, HPD may connect to the PD controller
or remain unused. The AUX signal shall use the AC-coupling capacitors and 1M termination (Pull-up on AUX_CH_P
and Pull-down on AUX_CH_N). The HPD out is a 1.8V TTL signal, it shall use 100K pull-down to GND. The KTM5030
can be powered from the connected DP or USB Type-C source or from an external power supply depending on the
application.
The AUX CH supports both native AUX transaction syntax and I2C-over-AUX transaction syntax. DP source access
the EDID from the downstream sink using I2C-over-AUX transactions. EDID larger than 256 bytes can be accessed
using segmented addressing mechanism specified in the E-DDC standard.
The KTM5030 supports link training with AUX transactions as specified in DP1.4A. The usage of TPS4 (Training
Pattern Sequence 4) is recommended to optimize both DPTX PHY drive setting of DP source and its own DPRX EQ
setting. If a DP source does not support TPS4, POST_LT_ADJ_REQ procedure is recommended as defined in
DP1.4A. Once the DP source has performed link training, but later stops the main link signal transmission (for
example, transitioning to the power saving state with DPCD 00600h set to 02h), another full link training is required
to re-establish the link. KTM5030 also supports the link training policy defined for DP alternative mode sources. In
this policy, the lane count is reduced to match the number of lanes physically connected based on the DPCD clock
recovery status register [LANEx-CR_DONE].
By default, the firmware keeps DP_HPD asserted unless it is in power OFF state, regardless of whether DFP HPD
input is asserted or not. The DFP HPD input status is reflected on SINK_COUNT value at DPCD 00200h. The value
is 1 when the DFP_HPD input is asserted, and 0 when de-asserted. Whenever KTM5030 detects DFP_HPD input
status change, it generates IRQ_HPD on the UFP_HPD line.
Other signaling requirements for UFP interface such as cable sense or power sense are supported through GPIOs.
March 2023 - Revision 04d
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Kinetic Technologies Confidential
KTM5030
DFP Interfaces
The KTM5030 DFP interface consists of three AV ports, one USB3.2 port and a digital audio output port.
AV Interface
The three DFP interfaces can be configured as below:
DFP
Drive
Architecture
AC Coupled
DP++
DC Coupled
HDMI
AC Coupled
HDMI
TX1
VML
Y
N
Y
TX2
CML
Y
Y
Y
TX3
VML
Y
N
Y
Each interface has 4 high speed main lanes, side band channels (AUX CH or DDC CH) and HPD inputs. The max
signaling rate is 8.1Gbps per lane in AC coupling mode and 6.0Gbps in DC coupling mode. TX2 transmitter has a
port determination power pin TX_CM which decides the AC or DC coupled mode of operation. For AC coupled DP++
mode TX_CM pin shall connect to 1.8 V, for DC coupled HDMI mode it is left open. The high-speed main lanes shall
use 0.1µF capacitor in DP++ mode or terminated to 3.3 V by the downstream sink in HDMI mode. KTM5030
autonomously controls both TMDS character clock divide by 4 and scrambling as defined by HDMI2.0b. Differential
voltage swing, pre-emphasis, edge rate, and source termination can be controlled through programming..
When a Port is used in HDMI AC-Couple mode, external level translators are not required. On- board passive circuitry
on High-speed and VCM Pins allow direct connection to HDMI connectors.
Each DFP AV interface has an AUX CH and DDC CH pins. In DP++ mode these signals are routed to the DP
connector using an external analog switch. The switching selection is based on the CONFIG1 signal status. In HDMI
mode the DDC pins are directly connected to the HDMI connector with a pull-up to VDD33.
The HPD input on each AV interface is directly connected to the HPD from the downstream sink through DP or HDMI
connector. A 47K pull-down is recommended for the HPD input.
USB3.2 Interface
The DFP USB3.2 interface has a TX and a RX differential pair supporting USB 3.2 Gen1 and Gen2 bit rate streams.
This is an extension of the UFP USB interface with signal integrity enhancement. KTM5030 supports BLR (Bit-LevelRetimer for the SS mode and SRIS (Separate Reference clock Independent SSC) for SSP mode. The TX and RX
pair may connect to an in-system USB hub or to a downstream facing USB connector.
Audio Interface
The audio output interface in KTM5030 can be configured to transmit audio in I2S, TDM or SPDIF format exclusively.
This digital audio interface comprises of 6 multi-purpose input/output pins. Functional description of these pins is
covered in the connection section. KTM5030 is capable of extracting audio from the incoming AV streams and
transmit on the digital audio interface for external audio CODEC. The audio stream selection and the output format
selection are configurable through firmware. In SPDIF configuration, there are 4 audio pins, each can be configured
to drive 2-Channel PCM or compressed audio data from a single stream source. Maximum toggle rate in this format
is limited to 50MHz. In I2S configuration 6 audio pins (4 data, bit clock, word clock) are used to drive 8-Channel audio
data. In TDM format 3 audio pins (1 data, bit clock, word clock) are used to driver 8-Channel audio in time division
multiplexing. The security policy engine in KTM5030 prevents transmission of protected audio through digital audio
interface port.
SPI Interface
KTM5030 uses an external SPI flash memory to store the firmware. This is a standard SPI interface comprises of
following signals: SPI_CSN, SPI_WPN, SPI_HOLD, SPI_DO, SPI_DI, SPI_CLK. KTM5030 supports single, dual,
quad and QPI read mode operation. SPI clock speed is programmable, and the maximum supported clock speed is
75MHz. Commercial SPI flash of 16Mbit size, operating at 1.8V supply is recommended. Contact Kinetic for the list
of qualified SPI flash devices.
March 2023 - Revision 04d
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Kinetic Technologies Confidential
KTM5030
I2C Interface
KTM5030 has an I2C master and a slave interface port for in-system connectivity with peripheral devices. It supports
standard I2C protocol with maximum data rate up to 400Kbps. The I2C data and clock pins are 3.3V/5V tolerant and
should connect to a 3.3 or 5V supply through an external 2.2K pull-up. The I2C master interface signals are multifunction pins; these pins can also function as operating mode configuration signals for external PD / TCPC controller.
The I2C slave interface uses an ALERT signal to interrupt the external master.
The I2C slave, host interface, is initialized to accept I2C transactions directed to device identifier 0xE0-0xE7.
Bootstrap 6 and 7 shall be used to select the I2C slave device identifier according to the table below:
Table 6. Bootstrap Selectable I2C Slave Device Identifiers
Bootstrap 7
Low
Low
High (1.8V)
Bootstrap 6
Low
High(1.8V)
Low
I2C Device
Identifier
E0/E1
E2/E3
E4/E5
High(1.8V)
High(1.8V)
E6/E7
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Kinetic Technologies Confidential
KTM5030
Chip Power-up Sequence and Reset
KTM5030 requires 0.95V, 1.8V - power supply for its operation. These power supply rails can be generated from
external voltage regulators. Refer to the electrical specification section for the supply ratings and maximum power
consumption of the device.Power Sequencing is not required by the SOC between the 1.8V & 0.95V Rails though
there may be requirements based on specific usage (Type-C Interface). However care must be taken to ensure that
ramp-up of Power Rails is greater than 100uS.
Power-On Reset
The Power-On Reset unit generates an internal chip reset under two conditions:
One, when the both 1.8V and 0.95V supply voltages cross the threshold level.
Two, when the RESETN signal to the chip is held low for certain duration and released.
The figure below shows internal reset signal generation in relation to the power supply threshold, ramp-up sequence
and RESETN signal timing. During rail power up, the voltage (pull-up resistor to 1.8V supply) on RESETN pin is
sensed by the internal Power-On Reset (POR) circuit to generate an internal reset pulse. The internal reset pulse is
low until both the 1.8V and 0.95V rails are stable and continues to stay low for at least 1.5ms after the 0.95V power
rail reaches 0.675Vand the 1.8V power rail reaches 1.35V (nominal threshold levels). During the device power up,
the 1.8V supply should lead the 0.95V supply (VDD18 >= VDDP9 for t > 0).
VDD18
EXT_ RESETn pulled low by
for 0.2ms
VDD1V8 Rail
VT18
Voltage
1.35V
At any time: VDD18> = VDD0P9
VDD0P9 Rail
VT09
t
0.675V
tR
1.5 ms (typ)
EXT_ RESETn kept low by
INTERNAL_RESETn after a
narrow glitch( ~ 25ns)
INTERNAL_RESETn
(dotted line)
Time
tP
> 0.2ms 1.5 ms (typ)
Figure 8. Power-up and Reset Timing Sequence
Any time a power supply glitch causes the power rails to fall below the nominal threshold voltage levels, the internal
reset signal drops and stays low for at least 1.5ms after both power rail exceed their nominal threshold voltage levels
again.
The external reset signal pin RESETN should be connected to 1.8V power supply through a 2.2K resistor. The
RESETN pin may be driven by an external open-collector drive or push-button switch to assert a chip reset. A 10pF
external capacitor is recommended at the RESET pin to keep the external reset signal low at least 0.2ms to generate
proper chip reset.
RESETn pin is input/output open-drain analog pad, therefore it require external pull-up resistor to 1.8V/3.3V.
RESETn is an “Active-LOW” signal.
IO Pad behavior as open-drain Output pad:
• Chip can drive RESETn pin either “LOW” or “Hi-Z”
• During power ramp-up, RESETn pad is used as status pin.
• It is weakly pulled High (follows the power rail) by external resistor, once power rails reached set thresholds
internal driver pulls it Low and chip enters in Reset mode.
• After ~1.5mS reset is de-asserted switching-off the internal driver and RESETn pin is pulled High by external
resistor, chip comes out of reset mode and ready for normal operation.
• Leakage current when driver is off ~20nA – 100nA depending on process corner and junction temp
March 2023 - Revision 04d
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Kinetic Technologies Confidential
KTM5030
IO Pad behavior as Input pad:
• Internal driver is off, RESETn is High (pulled up by external resistor) and chip is in normal mode of operation
• When External Reset is required, LOW pulse should be applied to RESETn externally
• RESETn input pulse is processed through input buffer and generates a reset signal to core.
• For input buffer to detect signal as Low, voltage at RESETn pin
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