65HVD1787EIM/TR

65HVD1785/1786/1787 65HVD1791/1792/1793 65HVD17xx Fault-Protected RS-485 Transceivers With Extended Common-Mode Range Features Description • These devices are designed to survive overvoltage faults such as direct shorts to power supplies, miswiring faults, connector failures, cable crushes, and tool mis-applications. They are also robust to ESD events, with high levels of protection to human-body model specifications. 1 • • • • • • Bus-Pin Fault Protection to: – > ±70 V ('HVD1785, 86, 91, 92) – > ±30 V ('HVD1787, 93) Common-Mode Voltage Range (–20 V to 25 V) More Than Doubles TIA/EIA 485 Requirement Bus I/O Protection – ±16 kV JEDEC HBM Protection Reduced Unit Load for Up to 256 Nodes Failsafe Receiver for Open-Circuit, Short-Circuit and Idle-Bus Conditions Low Power Consumption – Low Standby Supply Current, 1 μA Typical – ICC 5 mA Quiescent During Operation Power-Up, Power-Down Glitch-Free Operation These devices combine a differential driver and a differential receiver, which operate from a single power supply. In the 'HVD1785, 'HVD1786, and 'HVD1787, the driver differential outputs and the receiver differential inputs are connected internally to form a bus port suitable for half-duplex (two-wire bus) communication. In the 'HVD1793, the driver differential outputs and the receiver differential inputs are separate pins, to form a bus port suitable for fullduplex (four-wire bus) communication. These ports feature a wide common-mode voltage range, making the devices suitable for multipoint applications over long cable runs. These devices are characterized from –40°C to 105°C. Applications • Designed for RS-485 and RS-422 Networks For similar features with 3.3-V supply operation, see the 65HVD1781 (SLLS877). Example of Bus Short to Power Supply VFAULT up to 70 V http://www.hgsemi.com.cn 1 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Pin Configuration and Functions D or P Package 8-Pin SOIC or PDIP 65HVD1785, 1786, 1787 Top View R 1 8 VCC RE 2 7 B DE 3 6 A D 4 5 GND Pin Functions (65HVD1785, 65HVD1786, 65HVD1787) PIN NAME TYPE NO. DESCRIPTION A 6 Bus input/output Driver output or receiver input (complementary to B) B 7 Bus input/output Driver output or receiver input (complementary to A) D 4 Digital input Driver data input DE 3 Digital input Driver enable, active high GND 5 Reference potential R 1 RE 2 Digital input VCC 8 Supply Local device ground Digital output Receive data output http://www.hgsemi.com.cn Receiver enable, active low 4.5-V-to-5.5-V supply 2 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Pin Configuration and Functions D Package 14-Pin SOIC 65VD1791, 1792, 1793 Top View NC 1 14 VCC R 2 13 VCC RE 3 12 A DE 4 11 B D 5 10 Z GND 6 9 Y GND 7 8 NC NC - No internal connection Pins 6 and 7 are connected together internally. Pins 13 and 14 are connected together internally. Pin Functions (65HVD1791, 65HVD1792, 65HVD1793) PIN NAME TYPE NO. DESCRIPTION A 12 Bus input Receiver input (complementary to B) B 11 Bus input Receiver input (complementary to A) Y 9 Bus output Driver output (complementary to Z) Z 10 Bus output Driver output (complementary to Y) D 5 Digital input Driver data input DE 4 Digital input Driver enable, active high 6, 7 Reference potential GND R 2 Local device ground Digital output Receive data output RE 3 Digital input VCC 13, 14 Supply NC 1, 8 No connect Receiver enable, active low 4.5-V to 5.5-V supply No connect; should be left floating Absolute Maximum Ratings (1) MIN VCC Supply voltage Voltage at bus pins MAX UNIT V –0.5 7 'HVD1785, 86, 91, 92, 93 A, B pins –70 70 V 'HVD1787 A, B pins –70 30 V 'HVD1793 Y, Z pins –70 30 V V Input voltage at any logic pin –0.3 VCC + 0.3 Transient overvoltage pulse through 100 Ω per TIA-485 –100 100 V Receiver output current –24 24 mA TJ Junction temperature 170 °C Tstg Storage temperature 160 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. http://www.hgsemi.com.cn 3 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1), JEDEC Standard 22, Test Method A114 V(ESD) Electrostatic discharge Bus terminals and GND ±16000 All pins ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2), JEDEC Standard 22, Test Method C101 ±2000 Machine Model, JEDEC Standard 22, Test Method A115 IEC 60749-26 ESD (human-body model) (1) (2) UNIT V ±400 Bus terminals and GND ±16000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX VCC Supply voltage 4.5 5 5.5 UNIT V VI Input voltage at any bus terminal (separately or common mode) (1) –20 25 V V VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V VID Differential input voltage –25 25 V Output current, driver –60 60 mA Output current, receiver –8 8 mA RL Differential load resistance 54 CL Differential load capacitance 1/tUI Signaling rate IO 60 Ω 50 pF HVD1785, HVD1791 115 HVD1786, HVD1792 1 HVD1787, HVD1793 10 kbps Mbps TA Operating free-air temperature (see application section for thermal information) –40 105 °C TJ Junction temperature –40 150 °C (1) By convention, the least positive (most negative) limit is designated as minimum in this data sheet. Thermal Information 65HVD1785, 65HVD1786, 65HVD1787 THERMAL METRIC (1) 65HVD1791, 65HVD1792, 65HVD1793 D (SOIC) P (PDIP) D (SOIC) 8 PINS 8 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 138 59 95 °C/W RθJA (low-K) Junction-to-case (top) thermal resistance 242 128 168 °C/W RθJC(top) Junction-to-board thermal resistance 61 61 44 °C/W RθJB Junction-to-top characterization parameter 62 39 40 °C/W ψJT Junction-to-board characterization parameter 3.4 17.6 8.2 °C/W ψJB Junction-to-case (bottom) thermal resistance 33.4 28.3 25 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. http://www.hgsemi.com.cn 4 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER |VOD| Driver differential output voltage magnitude TEST CONDITIONS RS-485 with common-mode load, VCC > 4.75 V, see Figure 5 MIN TA ≤ 85°C 1.5 TA ≤ 105°C 1.4 RL = 54 Ω, 4.75 V ≤ VCC ≤ 5.25 V RL = 100 Ω, 4.75 V ≤ VCC ≤ 5.25 V Δ|VOD| Change in magnitude of driver differential output RL = 54 Ω voltage VOC(SS) Steady-state common-mode output voltage ΔVOC Change in differential driver output commonmode voltage VOC(PP) Peak-to-peak driver common-mode output voltage COD Differential output capacitance VIT+ Positive-going receiver differential input voltage threshold VIT– Negative-going receiver differential input voltage threshold VHYS Receiver differential input voltage threshold hysteresis (VIT+ – VIT–) VOH Receiver high-level output voltage IOH = –8 mA Receiver low-level output voltage II Driver input, driver enable, and receiver enable input current IOZ Receiver output high-impedance current IOS Driver short-circuit output current II ICC Bus input current (disabled driver) Supply current (quiescent) Supply current (dynamic) http://www.hgsemi.com.cn IOL = 8 mA 2 2 2.5 –0.2 0 0.2 V 1 VCC/2 3 V –100 0 100 mV 500 mV 23 pF –10 mV –200 –150 mV 30 50 mV 2.4 VCC – 0.3 V 4 TA ≤ 85°C 0.2 0.4 TA ≤ 105°C 0.2 0.5 –100 VO = 0 V or VCC, RE at VCC VCC = 4.5 to 5.5 V or VCC = 0 V, DE at 0 V UNIT V –100 VCM = –20 V to 25 V MAX 1.5 Center of two 27-Ω load resistors, see Figure 6 IOH = –400 μA VOL TYP 85, 86, 91, 92 87, 93 –1 1 μA 250 mA 75 –100 125 –40 VI = 12 V VI = –7 V μA –250 VI = 12 V VI = –7 V 100 V 500 μA –400 Driver and receiver enabled DE = VCC, RE = GND, no load 4 6 Driver enabled, receiver disabled DE = VCC, RE = VCC, no load 3 5 Driver disabled, receiver enabled DE = GND, RE = GND, no load 2 4 Driver and receiver disabled DE = GND, D = open RE = VCC, no load 0.5 5 mA μA See Typical Characteristics 5 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Thermal Considerations PARAMETER 85, 91 TEST CONDITIONS VALUE VCC = 5.5 V, TJ = 150°C, RL = 300 Ω, CL = 50 pF (driver), CL = 15 pF (receiver) 5-V supply, unterminated (1) 290 VCC = 5.5 V, TJ = 150°C, RL = 100 Ω, CL = 50 pF (driver), CL = 15 pF (receiver) 5-V supply, RS-422 load (1) 320 VCC = 5.5 V, TJ = 150°C, RL = 54 Ω, CL = 50 pF (driver), CL = 15 pF (receiver) 5-V supply, RS-485 load (1) 400 UNIT 85, 91 86 PD Power dissipation mW 87 85, 91 86 87 Thermal-shutdown junction temperature TSD (1) 170 °C Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: HVD1785, 1791 at 115 kbps, HVD1786 at 1 Mbps, HVD1787 at 10 Mbps) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER (HVD1785 AND HVD1791) tr, tf Driver differential output rise/fall time tPHL, tPLH Driver propagation delay tSK(P) Driver differential output pulse skew, |tPHL – tPLH| tPHZ, tPLZ Driver disable time tPZH, tPZL Driver enable time 0.4 RL = 54 Ω, CL = 50 pF, see Figure 7 Receiver enabled See Figure 8 and Figure 9 Receiver disabled 1.7 2.6 μs 0.8 2 μs 20 250 ns 0.1 5 μs 0.2 3 3 12 μs DRIVER (HVD1786 AND HVD1792) tr, tf Driver differential output rise/fall time tPHL, tPLH Driver propagation delay tSK(P) Driver differential output pulse skew, |tPHL – tPLH| tPHZ, tPLZ Driver disable time 50 RL = 54 Ω, CL = 50 pF, see Figure 7 Receiver enabled tPZH, tPZL Driver enable time See Figure 8 and Figure 9 Receiver disabled Receiver enabled VCM > VCC 300 ns 200 ns 25 ns 3 μs 300 ns 10 μs 500 ns DRIVER (HVD1787 AND HVD1793) tr, tf Driver differential output rise/fall time tPHL, tPLH Driver propagation delay tSK(P) Driver differential output pulse skew, |tPHL – tPLH| tPHZ, tPLZ Driver disable time 3 RL = 54 Ω, CL = 50 pF, see Figure 7 Receiver enabled tPZH, tPZL Driver enable time Receiver disabled Receiver enabled http://www.hgsemi.com.cn See Figure 8 and Figure 9 6 VCM > VCC 500 30 ns 50 ns 10 ns 3 μs 300 ns 9 μs ns 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Switching Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED) tr, tf Receiver output rise/fall time tPHL, tPLH Receiver propagation delay time tSK(P) Receiver output pulse skew, |tPHL – tPLH| tPLZ, tPHZ Receiver disable time tPZL(1), tPZH(1) tPZL(2), tPZH(2) Receiver enable time http://www.hgsemi.com.cn 85, 86, 91, 92 CL = 15 pF, see Figure 10 4 15 100 200 87, 93 85, 86, 91, 92 70 6 87, 93 20 5 ns ns ns Driver enabled, see Figure 11 15 100 Driver enabled, see Figure 11 80 300 ns Driver disabled, see Figure 12 3 9 μs 7 ns 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Typical Characteristics 70 120 IO − Driver Output Current − mA 60 50 ICC − RMS Supply Current − mA TA = 25°C DE at VCC D at VCC RL = 54 W 40 30 20 10 TA = 25°C RE at VCC DE at VCC RL = 54 W CL = 50 pF VCC = 5 V 100 80 60 0 −10 0.0 40 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 VCC − Supply Voltage − V 0 1.0 0.5 0.0 −0.5 −1.5 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 60 VIN − Bus Pin Voltage − V VCC = 5.5 V VCC = 5 V Load = 60 W VCC = 4.5 V 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Idiff - Differential Load Current - mA 90 G004 Figure 3. Bus Pin Current vs Bus Pin Voltage http://www.hgsemi.com.cn Load = 100 W Load = 300 W 0 2 4 30 10 Figure 2. HVD1787 RMS Supply Current vs Signaling Rate −1.0 0 8 G002 VOD - Differential Output Voltage - V IIN − Bus Pin Current − mA 1.5 −30 6 G001 Figure 1. Driver Output Current vs Supply Voltage −60 4 Signaling Rate − Mbps 2.0 −2.0 −90 2 Figure 4. Differential Output Voltage vs. Differential Load Current 8 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Parameter Measurement Information Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω. 375 W ±1% VCC DE 0 V or 3 V D A VOD 60 W ±1% + _ B –20 V < V(test) < 25 V 375 W ±1% S0301-01 Figure 5. Measurement of Driver Differential Output Voltage With Common-Mode Load VCC 27 W ±1% DE Input A D A VA B VB VOC(PP) VOC B DVOC(SS) CL = 50 pF ±20% 27 W ±1% VOC CL Includes Fixture and Instrumentation Capacitance S0302-01 Figure 6. Measurement of Driver Differential and Common-Mode Output With RS-485 Load 3V VCC DE D Input Generator VI CL = 50 pF ±20% A VOD 50 W B RL = 54 W ±1% CL Includes Fixture and Instrumentation Capacitance VI 50% 50% tPLH VOD tPHL »2V 90% 90% 0V 10% 0V 10% tr » –2 V tf S0303-01 Figure 7. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays 3V D DE Input Generator VI 50 W A 3V S1 B CL = 50 pF ±20% CL Includes Fixture and Instrumentation Capacitance VO VI RL = 110 W ± 1% 50% 50% 0.5 V tPZH VO 0V VOH 90% 50% tPHZ »0V S0304-01 NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output. Figure 8. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load http://www.hgsemi.com.cn 9 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Parameter Measurement Information (continued) 3V A 3V D S1 »3V VI VO 50% 50% 0V B DE Input Generator RL = 110 W ±1% tPZL tPLZ CL = 50 pF ±20% VI 50 W »3V CL Includes Fixture and Instrumentation Capacitance VO 50% 10% VOL S0305-01 NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output. Figure 9. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load A Input Generator R VI 50 W 1.5 V 0V VO B CL = 15 pF ±20% RE CL Includes Fixture and Instrumentation Capacitance 3V VI 50% 50% 0V tPLH VO tPHL 90% 90% 50% 10% 50% 10% tr VOH VOL tf S0306-01 Figure 10. Measurement of Receiver Output Rise and Fall Times and Propagation Delays http://www.hgsemi.com.cn 10 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Parameter Measurement Information (continued) 3V VCC DE A 0 V or 3 V D B VI S1 CL = 15 pF ±20% RE Input Generator 1 kW ± 1% R VO CL Includes Fixture and Instrumentation Capacitance 50 W 3V VI 50% 50% 0V tPZH(1) tPHZ VOH 90% VO 50% D at 3 V S1 to GND »0V tPZL(1) tPLZ VCC VO 50% D at 0 V S1 to VCC 10% VOL S0307-01 Figure 11. Measurement of Receiver Enable/Disable Times With Driver Enabled http://www.hgsemi.com.cn 11 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Parameter Measurement Information (continued) VCC A 0 V or 1.5 V R VO S1 B 1.5 V or 0 V RE Input Generator VI 1 kW ± 1% CL = 15 pF ±20% CL Includes Fixture and Instrumentation Capacitance 50 W 3V VI 50% 0V tPZH(2) VOH VO A at 1.5 V B at 0 V S1 to GND 50% GND tPZL(2) VCC VO 50% VOL A at 0 V B at 1.5 V S1 to VCC S0308-01 Figure 12. Measurement of Receiver Enable Times With Driver Disabled http://www.hgsemi.com.cn 12 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Detailed Description Overview The 65HVD17xx family of RS-485 transceivers are designed to operate up to 115 kbps (HVD1785 and HVD1791), 1 Mbps (HVD1786 and HVD1792), or 10 Mbps (HVD1787 or HVD1793) and to withstand DC overvoltage faults on the bus interface pins. This helps to protect the devices against damages resulting from direct shorts to power supplies, cable mis-wirings, connector failures, or other common faults. The 65HVD178x devices are half-duplex, and thus have the transmitter and receiver bus interfaces connected together internally. The 65HVD179x family leaves these two interfaces separate, allowing for full-duplex communication. The low receiver loading allows for up to 256 nodes to share a common RS-485 bus. The devices feature a wide common-mode range as well as fail-safe receivers, which ensure a stable logic-level output during bus open, short, or idle conditions. Functional Block Diagram 3 DE 4 D 2 RE 6 A 1 R Bus 7 B Figure 13. Half-Duplex Transceiver Logic Diagram (Positive Logic) DE D RE R 4 9 5 10 Y Z 3 12 2 11 A B S0300-01 Figure 14. Full Duplex Transceiver Feature Description Hot-Plugging These devices are designed to operate in hot swap or hot pluggable applications. Key features for hot-pluggable applications are power-up, power-down glitch free operation, default disabled input/output pins, and receiver failsafe. As shown in Figure 1, an internal Power-On Reset circuit keeps the driver outputs in a high-impedance state until the supply voltage has reached a level at which the device will reliably operate. This ensures that no spurious transitions (glitches) will occur on the bus pin outputs as the power supply turns on or turns off. As shown in Device Functional Modes, the ENABLE inputs have the feature of default disable on both the driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R pin until the associated controller actively drives the enable pins. http://www.hgsemi.com.cn 13 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Feature Description (continued) Receiver Failsafe The differential receiver is failsafe to invalid bus states caused by: • open bus conditions such as a disconnected connector, • shorted bus conditions such as cable damage shorting the twisted-pair together, • or idle bus conditions that occur when no driver on the bus is actively driving. In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the receiver is not indeterminate. In the HVD17xx family of RS-485 devices, receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than 200 mV, and must output a Low when the VID is more negative than -200 mV. The HVD17xx receiver parameters which determine the failsafe performance are VIT+ and VIT– and VHYS. In the Electrical Characteristics table, VIT– has a typical value of –150 mV and a minimum (most negative) value of -200 mV, so differential signals more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than 200 mV will always cause a High receiver output, because the typical value of VIT+ is -100mV, and VIT+ is never more positive than -10 mV under any conditions of temperature, supply voltage, or common-mode offset. When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output will be High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+. For the HVD17xx devices, the typical noise immunity is typically about 150 mV, which is the negative noise level needed to exceed the VIT– threshold (VIT- TYP = –150 mV). In the worst case, the failsafe noise immunity is never less than 40 mV, which is set by the maximum positive threshold (VIT+ MAX = –10 mV) plus the minimum hysteresis voltage (VHYS MIN = 30 mV). 70-V Fault-Protection The 65HVD17xx family of RS-485 devices is designed to survive bus pin faults up to ±70V. The devices designed for fast signaling rate (10 Mbps) will not survive a bus pin fault with a direct short to voltages above 30V when: 1. the device is powered on AND 2a. the driver is enabled (DE=HIGH) AND D=HIGH AND the bus fault is applied to the A pin OR 2b. the driver is enabled (DE=HIGH) AND D=LOW AND the bus fault is applied to the B pin Under other conditions, the device will survive shorts to bus pin faults up to 70V. Table 1 summarizes the conditions under which the device may be damaged, and the conditions under which the device will not be damaged. http://www.hgsemi.com.cn 14 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Feature Description (continued) Table 1. Device Conditions POWER DE D A B OFF X X -70V < VA < 70V -70V < VB < 70V Device survives RESULTS ON LO X -70V < VA < 70V -70V < VB < 70V Device survives ON HI L -70V < VA < 70V -70V < VB < 30V ON HI L -70V < VA < 70V 30V < VB Device survives Damage may occur ON HI H -70V < VA < 30V -70V < VB < 30V Device survives ON HI H 30V < VA -70V < VB < 30V Damage may occur Additional Options The 65HVD17xx family also has options for J1708 applications, for always-enabled full-duplex versions (industry-standard 65LBC179 footprint) and for inverting-polarity versions, which allow users to correct a reversal of the bus wires without re-wiring. Table 2. 65HVD17xx Options for J1708 Applications PART NUMBER 65HVD17xx FOOTPRINT/FUNCTION SLOW MEDIUM FAST Half-duplex (176 pinout) 85 86 87 Full-duplex no enables (179 pinout) 88 89 90 Full-duplex with enables (180 pinout) 91 92 93 Half-duplex with cable invert 94 95 96 Full-duplex with cable invert and enables 97 98 99 J1708 08 09 10 1 R 2 RE 6 A 4 D 7 B 3 DE Figure 15. 65HVD1708E Transceiver for J1708 Applications 5 Y 3 D 6 Z 8 A 2 R 7 B Figure 16. 65HVD17xx Always-Enabled Driver Receiver http://www.hgsemi.com.cn 15 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 1 R 2 INV 6 A 4 7 D B 3 DE 1 RINV 12 2 A R 11 B 3 RE 8 9 5 10 Y DINV D Z 4 DE Figure 17. 65HVD17xx Options With Inverting Feature to Correct for Miswired Cables Device Functional Modes Table 3. Driver Function Table INPUT ENABLE D DE A OUTPUTS B H H H L Actively drive bus high L H L H Actively drive bus low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drive bus high by default Table 4. Receiver Function Table DIFFERENTIAL INPUT ENABLE OUTPUT VID = VA – VB RE R VIT+ < VID L H Receive valid bus high VIT– < VID < VIT+ L ? Indeterminate bus state VID < VIT– L L Receive valid bus low X H Z Receiver disabled X OPEN Z Receiver disabled by default Open-circuit bus L H Fail-safe high output Short-circuit bus L H Fail-safe high output Idle (terminated) bus L H Fail-safe high output http://www.hgsemi.com.cn 16 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Application Information The 65HVD17xx family consists of both half-duplex and full-duplex transceivers that can be used for asynchronous data communication. Half-duplex implementations require one signaling pair (two wires), while fullduplex implementations require two signaling pairs (four wires). The driver and receiver enable pins of the 65HVD17xx family allow for control over the direction of data flow. Since it is common for multiple transceivers to share a common communications bus, care should be taken at the system level to ensure that only one driver is enabled at a time. This avoids bus contention, a fault condition in which multiple drivers attempt to send data at the same time. Typical Application An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer cable length. R R R A RE D RT B DE R A RT D A R B A R D RE B DE D B D D R RE DE D R RE DE D Figure 18. Typical RS-485 Network With Half-duplex Transceivers A Y R D Z RT RT B R R RE DE Master RE Slave B D R A DE Z RT RT A B Z Y D D Y R Slave D R RE DE D Figure 19. Typical RS-485 Network With Full-duplex Transceivers http://www.hgsemi.com.cn 17 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Typical Application (continued) Design Requirements RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of applications with varying requirements, such as distance, data rate, and number of nodes. Data Rate and Bus Length There is an inverse relationship between data rate and cable length, which means the higher the data rate, the short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or 10%. 10000 Cable Length (ft) 5%, 10%, and 20% Jitter 1000 Conservative Characteristics 100 10 100 1k 10k 100k 1M 10M 100M Data Rate (bps) Figure 20. Cable Length vs Data Rate Characteristic Even higher data rates are achievable (for example, 10 Mbps for the 65HVD1787 and 65HVD1793) in cases where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the data. Stub Length When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as shown in Equation 1. L stub £ 0.1´ tr ´ v ´ c where • • • tr is the 10/90 rise time of the driver c is the speed of light (3 × 108 m/s) v is the signal velocity of the cable or trace as a factor of c (1) Receiver Failsafe The differential receiver of the 65HVD17xx family is failsafe to invalid bus states caused by: • Open bus conditions, such as a disconnected connector • Shorted bus conditions, such as cable damage shorting the twisted-pair together • Idle bus conditions that occur when no driver on the bus is actively driving n any of these cases, the differential receiver will output a failsafe logic high state so that the output of the receiver is not indeterminate. http://www.hgsemi.com.cn 18 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Typical Application (continued) Receiver failsafe is accomplished by offsetting the receiver thresholds such that the “input indeterminate” range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than +200 mV, and must output a low when VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT(+) and VIT(-). As shown in the Electrical Characteristics table, differential signals more negative than -200 mV will always cause a low receiver output, and differential signals more positive than +200 mV will always cause a high receiver output. When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of -10 mV, and the receiver output will be high. Detailed Design Procedure Although the 65HVD17xx family is internally protected against human-body-model ESD strikes up to 16 kV, additional protection against higher-energy transients can be provided at the application level by implementing external protection devices. Application Curve Figure 21. 65HVD1785 Differential Output at 115 kbps http://www.hgsemi.com.cn 19 2019 NOV 65HVD1785/1786/1787 65HVD1791/1792/1793 Important statement: Huaguan Semiconductor Co,Ltd. reserves the right to change the products and services provided without notice. Customers should obtain the latest relevant information before ordering, and verify the timeliness and accuracy of this information. Customers are responsible for complying with safety standards and taking safety measures when using our products for system design and machine manufacturing to avoid potential risks that may result in personal injury or property damage. Our products are not licensed for applications in life support, military, aerospace, etc., so we do not bear the consequences of the application of these products in these fields. Our documentation is only permitted to be copied without any tampering with the content, so we do not accept any responsibility or liability for the altered documents. http://www.hgsemi.com.cn 20 2019 NOV