LO613A-25M-50-C

LO6x3 Series EMI Reduction Oscillator Features ⚫ FCC Applications approved method of EMI attenuation ⚫ SATA, ⚫ Proprietary SaΦic™ technology, a non-PLL phase modulation implementation and algorithm Supply ⚫ Voltage 1.65V~1.95V ⚫ Frequency range 20~30Mhz ⚫ CMOS Output ⚫ Modulated clock output Enable/Disable Function ⚫ Low EMI buffer for enhanced EMI reduction ⚫ RoHS compliant & Pb free ⚫ Products available in AEC-Q100 compliant ⚫ Package 2.5x2.0mm, 3.2x2.5mm Ethernet, PCI express, Video, Wireless ⚫ Computing, Storage, Networking, Telecom, Industrial Control Table1. Electrical Characteristics Parameter Output Frequency Range Frequency Stability Symbol Min. Typ. Max. Unit. F 20 - 30 MHz VDD=1.8V PPM Inclusive of initial tolerance at 25 ºC，and variations over operating temperature, rated power supply voltage and load. -30 +30 -50 +50 F_stab -60 +60 Condition -100 +100 Operating Temperature Range TUSE -40 +125 ºC Supply Volage VDD 1.65 1.95 V Output Load CL 9 pF Current Consumption IDD 4.0 5.0 mA 9pF Load, f=27MHz, VDD =1.8V SSEN mode current ISS 3.0 3.5 mA When SSEN=GND, 9pF Load, f=27MHz, VDD =1.8V output is Pulled Down Duty Cycle DC 45 55 % Tr 5.5 6.0 7.0 nS Tf 6.0 6.5 7.5 nS Output Voltage High VOH 0.75* VDD - - V Output Voltage Low VOL - - 0.25* VDD V Input Voltage High VIH 0.66* VDD - - V Input Volage Low VIL - - 0.33* VDD V Startup Time T_start - 1 mS RMS Phase Jitter T_phj - F_aging -1.5 +1.5 PPM -3 +3 PPM - 1.8 Rise/Fall Time 9pF load, 10%~90% VDD, high drive (VDD=1.8V) IOH=-4mA, IOL=4mA First year Aging 0.63 pS Measure from the time VDD reaches its rated minimum value. F=27MHz, integration bandwidth=12KHz to 5MHz, SSEN=GND 25 ºC 10-year Aging Rev:1.4 Notice: The information in this document is subject to change without notice. 1/5 www.lfc-semi.com LO6x3 Series Table2. Pin Configuration Pin Symbol Functionality 1 SSEN Input Modulation Output Clock Mode Enable Pin H (Logic "1"): Enable L (Logic "0"): Disable Internal pull-high resistor 2 GND Power Electrical ground 3 OUT Output Phase modulated buffered output 4 VDD Power Power supply voltage Table3. Deviation select Table Deviation Select 1 2 Frequency 3 4 Deviation 24MHz ±0.61% ±0.39% ±0.28% ±0.22% 25MHz ±0.66% ±0.41% ±0.30% ±0.23% 27MHz ±0.72% ±0.46% ±0.34% ±0.27% Notes:1. Please refer to ordering information for deviation select Test Circuit and Waveform Figure 1. Test Circuit Figure 2. Waveform Notes:2. Duty Cycle is computed as Duty Cycle = TH/Period. Rev:1.4 Notice: The information in this document is subject to change without notice. 2/5 www.lfc-semi.com LO6x3 Series Timing Diagram Figure 3. Startup Timing Ordering Information Marking Temperature Grade Temperature Range Frequency Stability (PPM) I -40~85℃ ±30 E -40~105℃ ±50 / ±60 A -40~125℃ ±50 / ±100 Rev:1.4 Notice: The information in this document is subject to change without notice. 3/5 www.lfc-semi.com LO6x3 Series Dimensions 2520 3225 Rev:1.4 Notice: The information in this document is subject to change without notice. 4/5 www.lfc-semi.com LO6x3 Series Revision History Revision Number Date of Release 1.0 04/07/2021 1.1 06/01/2021 1.2 Changes 1) Preliminary datasheet 1) Modify Pin1 function，frequency range, Tr, Tf. 06/07/2021 1) Modify IDD, ISS 1.3 10/12/2021 1) Add Dimensions 1.4 11/30/2021 1) Delete 2016 package, add 3225 package Rev:1.4 Notice: The information in this document is subject to change without notice. 5/5 www.lfc-semi.com