GD32VW553HMQ7

GigaDevice Semiconductor Inc. GD32VW553xx RISC-V 32-bit MCU Datasheet Revision 1.1 (Nov. 2023) GD32VW553xx Datasheet Table of Contents Table of Contents ..................................................................................................... 1 List of Figures .......................................................................................................... 4 List of Tables ............................................................................................................ 5 1. General description ........................................................................................... 7 2. Device overview ................................................................................................. 8 2.1. Device information ................................................................................................ 8 2.2. Block diagram ........................................................................................................ 9 2.3. Pinouts and pin assignment ............................................................................... 10 2.4. Memory map ........................................................................................................ 12 2.5. Clock tree ............................................................................................................. 16 2.6. Pin definitions ...................................................................................................... 17 2.6.1. GD32VW553Hx QFN40 pin definitions .......................................................................... 17 2.6.2. GD32VW553Kx QFN32 pin definitions .......................................................................... 21 2.6.3. GD32VW553xx pin alternate functions .......................................................................... 24 3. Functional description..................................................................................... 26 3.1. RISC-V core.......................................................................................................... 26 3.2. On-chip memory .................................................................................................. 26 3.3. Clock, reset and supply management ................................................................ 27 3.4. Boot modes.......................................................................................................... 27 3.5. Power saving modes ........................................................................................... 29 3.6. Electronic fuse (EFUSE) ...................................................................................... 31 3.7. General-purpose inputs / outputs (GPIOs) ........................................................ 31 3.8. CRC calculation unit (CRC)................................................................................. 31 3.9. True Random number generator (TRNG) ........................................................... 32 3.10. Direct memory access controller (DMA)......................................................... 32 3.11. Analog to digital converter (ADC) ................................................................... 32 3.12. Real time clock (RTC) ...................................................................................... 33 3.13. Timers and PWM generation ........................................................................... 33 3.14. Universal synchronous asynchronous receiver transmitter (USART) ......... 35 3.15. Inter-integrated circuit (I2C) ............................................................................ 35 1 GD32VW553xx Datasheet 3.16. Serial peripheral interface (SPI) ...................................................................... 35 3.17. Quad-SPI interface (QSPI) ............................................................................... 36 3.18. Cryptographic acceleration Unit (CAU) .......................................................... 36 3.19. Hash acceleration unit (HAU) .......................................................................... 36 3.20. Public Key Cryptographic Acceleration Unit (PKCAU) .................................. 37 3.21. Infrared ray port (IFRP) .................................................................................... 37 3.22. Wireless ............................................................................................................ 38 3.22.1. Wi-Fi ............................................................................................................................... 38 3.22.2. BLE (Bluetooth Low Energy) .......................................................................................... 39 3.22.3. Radio .............................................................................................................................. 39 3.23. Debug mode ..................................................................................................... 40 3.24. Package and operation temperature............................................................... 40 4. Electrical characteristics ................................................................................. 41 4.1. Absolute maximum ratings ................................................................................. 41 4.2. Operating conditions characteristics ................................................................. 41 4.3. Power consumption ............................................................................................ 43 4.4. EMC characteristics ............................................................................................ 48 4.5. Power supply supervisor characteristics .......................................................... 49 4.6. Electrical sensitivity ............................................................................................ 50 4.7. External clock characteristics ............................................................................ 50 4.8. Internal clock characteristics ............................................................................. 52 4.9. PLL characteristics ............................................................................................. 53 4.10. Memory characteristics ................................................................................... 53 4.11. NRST pin characteristics ................................................................................. 53 4.12. GPIO characteristics ........................................................................................ 54 4.13. ADC characteristics ......................................................................................... 57 4.14. Temperature sensor characteristics ............................................................... 58 4.15. I2C characteristics ........................................................................................... 59 4.16. SPI characteristics ........................................................................................... 60 4.17. USART characteristics..................................................................................... 61 4.18. TIMER characteristics ...................................................................................... 61 4.19. WDGT characteristics ...................................................................................... 62 4.20. Wi-Fi Radio characteristics ............................................................................. 62 2 GD32VW553xx Datasheet 4.21. Bluetooth LE Radio characteristics ................................................................ 64 4.22. Parameter conditions....................................................................................... 68 5. Package information ........................................................................................ 69 5.1. QFN40 package outline dimensions .................................................................. 69 5.2. QFN32 package outline dimensions .................................................................. 71 5.3. Thermal characteristics ...................................................................................... 73 6. Ordering information ....................................................................................... 75 7. Revision history ............................................................................................... 76 3 GD32VW553xx Datasheet List of Figures Figure 2-1. GD32VW553xx block diagram .......................................................................................... 9 Figure 2-2. GD32VW553Hx QFN40 pinouts ...................................................................................... 10 Figure 2-3. GD32VW553Kx QFN32 pinouts ...................................................................................... 11 Figure 2-4. GD32VW553xx clock tree ................................................................................................ 16 Figure 4-1. Recommended power supply decoupling capacitors(1)(2)(3) ......................................... 42 Figure 4-2. Recommended external NRST pin circuit ..................................................................... 54 Figure 4-3. I/O port AC characteristics definition ............................................................................ 57 Figure 4-4. I2C bus timing diagram ................................................................................................... 59 Figure 4-5. SPI timing diagram - master mode ................................................................................ 60 Figure 4-6. SPI timing diagram - slave mode ................................................................................... 61 Figure 5-1. QFN40 package outline ................................................................................................... 69 Figure 5-2. QFN40 recommended footprint ...................................................................................... 70 Figure 5-3. QFN32 package outline ................................................................................................... 71 Figure 5-4. QFN32 recommended footprint ...................................................................................... 72 4 GD32VW553xx Datasheet List of Tables Table 2-1. GD32VW553xx devices features and peripheral list ........................................................ 8 Table 2-2. GD32VW553xx memory map ............................................................................................ 12 Table 2-3. GD32VW553Hx QFN40 pin definitions ............................................................................ 17 Table 2-4. GD32VW553Kx QFN32 pin definitions ............................................................................ 21 Table 2-5. Port A alternate functions summary ............................................................................... 24 Table 2-6. Port B alternate functions summary ............................................................................... 25 Table 2-7. Port C alternate functions summary ............................................................................... 25 Table 3-1. BOOT0 modes.................................................................................................................... 28 Table 3-2. BOOT1 modes.................................................................................................................... 28 Table 3-3. Boot address modes ......................................................................................................... 28 Table 4-1. Absolute maximum ratings (1)(4) ....................................................................................... 41 Table 4-2. DC operating conditions ................................................................................................... 41 Table 4-3. Clock frequency (1) ............................................................................................................. 42 Table 4-4. Operating conditions at Power up / Power down (1)....................................................... 42 Table 4-5. Start-up timings of Operating conditions (1)(2)(3) ............................................................. 42 Table 4-6. Power saving mode wakeup timings characteristics (1)(2) ............................................. 43 Table 4-7. Wi-Fi Power consumption characteristics ...................................................................... 43 Table 4-8. Wi-Fi Power consumption characteristics (1)(2)(3) ............................................................ 43 Table 4-9. Power consumption characteristics (2)(3)(4)(5)(6) ................................................................ 44 Table 4-10. EMS characteristics (1) .................................................................................................... 48 Table 4-11. Power supply supervisor characteristics ..................................................................... 49 Table 4-12. ESD characteristics (1) ..................................................................................................... 50 Table 4-13. Static latch-up characteristics (1) ................................................................................... 50 Table 4-14. High speed external clock (HXTAL) generated from a crystal / ceramic characteristics ..................................................................................................................................... 50 Table 4-15. High speed external user clock characteristics (HXTAL in bypass mode) ............... 51 Table 4-16. Low speed external clock (LXTAL) generated from a crystal / ceramic characteristics ..................................................................................................................................... 51 Table 4-17. Low speed external user clock characteristics (LXTAL in bypass mode) ................ 51 Table 4-18. High speed internal clock (IRC16M) characteristics.................................................... 52 Table 4-19. Low speed internal clock (IRC32K) characteristics ..................................................... 52 Table 4-20. PLLDIG characteristics ................................................................................................... 53 Table 4-21. Flash memory characteristics........................................................................................ 53 Table 4-22. NRST pin characteristics ................................................................................................ 53 Table 4-23. I/O port DC characteristics (1)(3) ...................................................................................... 54 Table 4-24. I/O port AC characteristics (1)(2) ...................................................................................... 56 Table 4-25. ADC characteristics ........................................................................................................ 57 Table 4-26. ADC RAIN max for fADC = 42 MHz (1) ................................................................................. 58 Table 4-27. ADC dynamic accuracy at fADC = 42 MHz (1) .................................................................. 58 Table 4-28. ADC static accuracy at fADC = 42 MHz............................................................................ 58 Table 4-29. Temperature sensor characteristics (1) ......................................................................... 58 5 GD32VW553xx Datasheet Table 4-30. I2C characteristics (1)(2)(3) ................................................................................................. 59 Table 4-31. Standard SPI characteristics Table 4-32. USART characteristics Table 4-33. TIMER characteristics (1) (1) (1) ...................................................................................... 60 ................................................................................................ 61 ................................................................................................. 61 Table 4-34. FWDGT min/max timeout period at 32 kHz (IRC32K) Table 4-35. WWDGT min-max timeout value at 40 MHz (fPCLK1) Table 4-36. Transmitter power characteristics Table 4-38. Rx Maximum Input Level ............................................... 62 (1) .............................................. 62 (1)(2) .......................................................................... 62 (1) .......................................................................... 63 Table 4-37. Receiver sensitivity characteristics (1) (1) ............................................................................................ 64 Table 4-39. Adjacent Channel Rejection (1)(4) .................................................................................... 64 Table 4-40. Transmitter Characteristics - Bluetooth LE 1 Mbps .................................................... 64 Table 4-41. Transmitter Characteristics - Bluetooth LE 2 Mbps .................................................... 65 Table 4-42. Transmitter Characteristics - Bluetooth LE 125 Kbps ................................................. 65 Table 4-43. Receiver Characteristics - Bluetooth LE 1 Mbps ......................................................... 65 Table 4-44. Receiver Characteristics - Bluetooth LE 2 Mbps ......................................................... 66 Table 4-45. Receiver Characteristics - Bluetooth LE 125 Kbps...................................................... 67 Table 4-46. Receiver Characteristics - Bluetooth LE 500 Kbps...................................................... 67 Table 5-1. QFN40 package dimensions ............................................................................................ 69 Table 5-2. QFN32 package dimensions ............................................................................................ 71 Table 5-3. Package thermal characteristics(1) .................................................................................. 73 Table 6-1. Part ordering code for GD32VW553xx devices .............................................................. 75 Table 7-1. Revision history................................................................................................................. 76 6 GD32VW553xx Datasheet 1. General description The GD32VW553xx is a highly integrated 2.4GHz Wi-Fi and BLE System-on-Chip (SoC) that includes an RISC-V processor, a single stream IEEE 802.11b/g/n/ax MAC/baseband/radio, a power amplifier (PA), and a receive low-noise amplifier (LNA). It is an optimized SoC designed for a broad array of smart devices for Internet of Things (IoT) applications. The GD32VW553xx device incorporates the RISC-V 32-bit processor core operating at 160 MHz frequency to obtain maximum efficiency. It provides up to 4096 KB on-chip Flash memory and 320KB (288 KB + 32KB Shared) SRAM memory. An extensive range of enhanced I/Os and peripherals connect to two APB buses. The devices offer a 12-bit ADCs, up to four general 16-bit timers, one basic timers, one PWM advanced timer, as well as standard and advanced communication interfaces: one SPI, two I2Cs, one USARTs, two UARTs, a Wireless (BLE / Wi-Fi). Additional peripherals as cryptographic acceleration unit (CAU), hash acceleration unit (HAU), public key cryptographic acceleration unit (PKCAU) and quad-SPI interface (QSPI) are included. The device operates from a 1.8 to 3.6 V power supply and available in –40 to +85 °C temperature range for grade 6 devices, -40 to +105 °C temperature range for grade 7 devices. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32VW553xx devices suitable for a wide range of applications, especially in areas such as industrial control, smart home control system, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike, IoT and so on. 7 GD32VW553xx Datasheet 2. Device overview 2.1. Device information Table 2-1. GD32VW553xx devices features and peripheral list Part Number GD32VW553xx KIQ7 KMQ6 KMQ7 HIQ6 HIQ7 HMQ6 HMQ7 FLASH (KB) 2048 2048 4096 4096 2048 2048 4096 4096 SRAM (KB) 320 320 320 320 320 320 320 320 Timers KIQ6 General 2 2 2 2 2 2 2 2 timer(16-bit) (15-16) (15-16) (15-16) (15-16) (15-16) (15-16) (15-16) (15-16) General 2 2 2 2 2 2 2 2 timer(32-bit) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) Advanced 1 1 1 1 1 1 1 1 timer(16-bit) (0) (0) (0) (0) (0) (0) (0) (0) Basic 1 1 1 1 1 1 1 1 timer(16-bit) (5) (5) (5) (5) (5) (5) (5) (5) 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (0) (0) (0) (0) (0) (0) (0) (0) SysTick(64bit) ADC Connectivity USART 2 2 2 2 2 2 2 2 (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) I2C 2 2 2 2 2 2 2 2 SPI 1 1 1 1 1 1 1 1 QSPI 1 1 1 1 1 1 1 1 Wi-Fi 1 1 1 1 1 1 1 1 BLE5.2 1 1 1 1 1 1 1 1 TRNG 1 1 1 1 1 1 1 1 CAU 1 1 1 1 1 1 1 1 HAU 1 1 1 1 1 1 1 1 PKCAU 1 1 1 1 1 1 1 1 GPIO 21 21 21 21 28 28 28 28 Units 1 1 1 1 1 1 1 1 Channels 9 9 9 9 9 9 9 9 UART Package QFN32 QFN40 8 GD32VW553xx Datasheet 2.2. Block diagram Figure 2-1. GD32VW553xx block diagram POR/ PDR JTAG I-Cache System RISC-V CPU Fmax:160MHz Flash Memory LVD AHB1: Fmax = 160MHz F-C BUS Slave Master GP DMA 8 chs M P Master AHB Matrix ECLIC Slave Flash Memory Controller AHB2: Fmax = 160MHz Slave SRAM SRAM Controller BLE Master IRC16M 16MHz TRNG CAU HAU PKCAU Master WIFI LDO 1.1V EFUSE QSPI CRC GPIO RCU QSPI: Fmax = 160MHz Slave Slave Slave AHB to APB Bridge2 Powered By V DD/VDDA QSPI_flash memory HXTAL 8-52MHz AHB to APB Bridge1 Slave PLL F max : 160MHz Interrput request Powered By V DD_RF WWDGT 12-bit SAR ADC Slave Slave ADC FWDGT Powered By V DDA UART2 PMU SPI SYSCFG TIMER15 TIMER16 TIMER0 APB1: Fmax = 80MHZ WIFI_RF APB2: Fmax = 160MHz EXTI USART0 UART1 I2C0 I2C1 RTC TIMER5 TIMER1 TIMER2 RFI 9 GD32VW553xx Datasheet 2.3. Pinouts and pin assignment Figure 2-2. GD32VW553Hx QFN40 pinouts PC15-OSC32OUT 5 NRST 6 PA8 3 PA9 PC13 PC14-OSC32IN PA10 2 PA11 PA12-WKUP3 PB3 PA15-WKUP1 PB4 VDD 1 PA13 PA14 PC8-BOOT0 40 39 38 37 36 35 34 33 32 31 GigaDevice GD32VW553Hx QFN40 4 30 PB15 29 PB13 28 PB12 27 PB11 26 PB2 25 PB1 24 23 PB0 PU 7 AVDD33_ANA 8 NC 9 22 PA6 RF 10 21 PA5 GND 11 12 13 14 15 16 17 18 19 20 PA7-WKUP2 PA4 PA3 PA2 PA1 PA0-WKUP0 XTAL2 VDDA XTAL1 AVDD33_CLK AVDD33_PA 10 GD32VW553xx Datasheet Figure 2-3. GD32VW553Kx QFN32 pinouts PA8 PB3 PA12-WKUP3 PB4 PA13 PA14 VDD PC8-BOOT0 32 31 30 29 28 27 26 25 PA15-WKUP1 PC13 1 2 PC14-OSC32IN 3 PC15-OSC32OUT 4 24 PB15 GigaDevice GD32VW553Kx QFN32 23 PB1 GND 22 PB0 21 PA7-WKUP2 NRST 5 20 PA6 PU 6 19 PA5 AVDD33_ANA 7 18 PA4 RF 8 17 PA3 9 10 11 12 13 14 15 16 PA2 PA1 PA0-WKUP0 VDDA XTAL2 XTAL1 AVDD33_CLK AVDD33_PA 11 GD32VW553xx Datasheet 2.4. Memory map Table 2-2. GD32VW553xx memory map Pre-defined Regions External device Bus QSPI AHB2 Peripheral AHB1 Address Peripherals 0xD100 0000 – 0xD200 10000 RISC-V internal peripherals 0x9800 0000 – 0xD0FF FFFF Reserved 0x9000 0000 - 0x97FF FFFF QSPI_FLASH (MEM) 0x7000 0000 - 0x8FFF FFFF Reserved 0x6000 0000 - 0x67FF FFFF Reserved 0x4C06 3000 - 0x4FFF FFFF Reserved 0x4C06 1000 - 0x4C06 2FFF PKCAU 0x4C06 0C00 - 0x4C06 0FFF Reserved 0x4C06 0800 - 0x4C06 0BFF TRNG 0x4C06 0400 - 0x4C06 07FF HAU 0x4C06 0000 - 0x4C06 03FF CAU 0x4C05 0400 - 0x4C05 FFFF Reserved 0x4C05 0000 - 0x4C05 03FF Reserved 0x4C04 0000 - 0x4C04 FFFF Reserved 0x4C00 0000 - 0x4C03 FFFF Reserved 0x4904 0000 - 0x4BFF FFFF Reserved 0x4900 0000 - 0x4903 FFFF Reserved 0x400B 1000 - 0x48FF FFFF Reserved 0x400B 0800 - 0x400B 0FFF Reserved 0x400B 0400 - 0x400B 07FF Reserved 0x400B 0000 - 0x400B 03FF Reserved 0x400A 1000 - 0x400A FFFF Reserved 0x400A 0C00 - 0x400A 0FFF Reserved 0x400A 0800 - 0x400A 0BFF Reserved 0x400A 0400 - 0x400A 07FF Reserved 0x400A 0000 - 0x400A 03FF Reserved 0x4008 0400 - 0x4009 FFFF Reserved 0x4008 0000 - 0x4008 03FF Reserved 0x4003 0000 - 0x4007 FFFF WIFI 0x4002 BC00 - 0x4002 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF Reserved 0x4002 6000 - 0x4002 63FF DMA 0x4002 5C00 - 0x4002 5FFF Reserved 12 GD32VW553xx Datasheet Pre-defined Regions Bus APB2 Address Peripherals 0x4002 5800 - 0x4002 5BFF QSPI_FLASH(REG) 0x4002 5400 - 0x4002 57FF Reserved 0x4002 5000 - 0x4002 53FF Reserved 0x4002 4000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Reserved 0x4002 3800 - 0x4002 3BFF RCU 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF EFUSE 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1C00 - 0x4002 1FFF Reserved 0x4002 1800 - 0x4002 1BFF Reserved 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF Reserved 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 0x4001 8800 - 0x4001 FFFF Reserved 0x4001 8400 - 0x4001 87FF TIMER16 0x4001 8000 - 0x4001 83FF TIMER15 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF WIFI_RF 0x4001 6800 - 0x4001 77FF Reserved 0x4001 6000 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5FFF Reserved 0x4001 5400 - 0x4001 57FF Reserved 0x4001 4C00 - 0x4001 53FF Reserved 0x4001 4800 - 0x4001 4BFF Reserved 0x4001 4400 - 0x4001 47FF Reserved 0x4001 4000 - 0x4001 43FF Reserved 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI 0x4001 2C00 - 0x4001 2FFF Reserved 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC 0x4001 1400 - 0x4001 1FFF Reserved 13 GD32VW553xx Datasheet Pre-defined Regions Bus APB1 SRAM Code AHB AHB Address Peripherals 0x4001 1000 - 0x4001 13FF UART2 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF Reserved 0x4001 0000 - 0x4001 03FF TIMER0 0x4000 D000 - 0x4000 FFFF Reserved 0x4000 CC00 - 0x4000 CFFF RFI 0x4000 7400 - 0x4000 CBFF Reserved 0x4000 7000 - 0x4000 73FF PMU 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 5C00 - 0x4000 6BFF Reserved 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 4C00 - 0x4000 53FF Reserved 0x4000 4800 - 0x4000 4BFF USART0 0x4000 4400 - 0x4000 47FF UART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF Reserved 0x4000 3800 - 0x4000 3BFF Reserved 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF Reserved 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF Reserved 0x4000 1400 - 0x4000 17FF Reserved 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF Reserved 0x4000 0800 - 0x4000 0BFF Reserved 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2101 0000 - 0x3FFF FFFF Reserved 0x2100 0000 - 0x2100 FFFF BLE 0x2005 0000 - 0x20FF FFFF Reserved 0x2003 0000 - 0x2004 FFFF SRAM3 (96KB + shared 32KB) 0x2002 0000 - 0x2002 FFFF SRAM2 (64KB) 0x2001 0000 - 0x2001 FFFF SRAM1 (64KB) 0x2000 0000 - 0x2000 FFFF SRAM0 (64KB) 0x1000 0000 - 0x1FFF FFFF External memories remap 0x0FFC 0100 - 0x0FFF FFFF Reserved 14 GD32VW553xx Datasheet Pre-defined Regions Bus Address Peripherals 0x0FFC 0000 - 0x0FFC 00FF EFUSE (256 bytes) 0x0BF8 0000 –0x0FFB FFFF Reserved 0x0BF4 0000 - 0x0BF7 FFFF ROM(256KB) 0x0A07 0000 - 0x0BF3 FFFF Reserved 0x0A04 0000 - 0x0A06 FFFF Reserved 0x0A02 0000 - 0x0A03 FFFF Reserved 0x0A01 0000 - 0x0A01 FFFF Reserved 0x0A00 0000 - 0x0A00 FFFF Reserved 0x0840 0000 - 0x09FF FFFF Reserved 0x0800 0000 - 0x083F FFFF Flash memory 0x0000 0000 - 0x07FF FFFF External memories remap 15 GD32VW553xx Datasheet 2.5. Clock tree Figure 2-4. GD32VW553xx clock tree BKP HCLK Prescaler Hclk÷4 CK_BKP HCLK (to AHB bus,RISCV,SRAM,DMA,peripherals) AHB enable CK_FWDGT To FWDGT RTCSRC FCLK 32k Hz IRC32K (free running clock) 10 APB1 Prescaler ÷1,2,4,8,16 CK_RTC 32.768k Hz LXTAL OSC 01 RTCDIV ÷1 ~ 32 To RTC FMC CK_APB1 PCLK1 80 MHz max IRC16 MDIV 16 MHz IRC16M CK_IRC16M CK_HXTAL TIMER1,2,5 CK_APB1 x1 x2 or x4 00 01 AHB Prescaler ÷1,2...512 CK_SYS 160 MHz max CK_PLLDIG to APB1 peripherals Peripheral enable SCS 11 160 MHz max CK_TIMERx TIMERx enable to TIMER1,2,5 CK_AHB APB2 Prescaler ÷1,2,4,8,16 160 MHz max 10 CK_APB2 PCLK2 160 MHz max to APB2 peripherals Peripheral enable 8-52 MHz HXTAL Clock Monitor TIMER0,15,16 CK_APB2 x1 x2 or x4 0 1 160 MHz max TIMERx enable ADC Prescaler ÷2,4,6,8 PLLDIGSEL CK_TIMERx to TIMER0,15,16 ADCCK[2] 0 CK_ADC to ADC 42 MHz max ADC Prescaler ÷5,6,10,20 PLLDIGDIV_S YS PLLDIG OSEL VCO 1 TRNGCK DIV to TRNG TRNG enable xN PLLDIG CK240_WIFI WIFI enable 240 MHz max 240 MHz max to WIFI BLEDIV ÷5 CK48_BLE 48 MHz max BLE enable to BLE CKOUT0DIV ÷1,2,3,4,5 000 001 010 CK_IRC16M CK_LXTAL CK_HXTAL 011 100 101 CK_PLLDIG IRC32K CK_SYS BLEDIV ÷3 CK80_RFI 80 MHz max RFI enable to RFI CKOUT0SEL[2:0] I2C0SEL[1:0] USART0SEL[1:0] CKOUT1DIV ÷1,2,3,4,5 00 CK_SYS 01 CK_IRC16M 10 CK_HXTAL 11 CK_PLLDIG CK_APB1 00 CK_APB1 00 CK_SYS 01 CK_USART0 CK_SYS 01 CK_LXTAL 10 to USART0 CK_IRC16M 10 CK_IRC16M 11 CK_IRC16M 11 I2C0CLK to I2C0 CKOUT1SEL[1:0] Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC16M: Internal 16M RC oscillator IRC32K: Internal 32K RC oscillator 16 GD32VW553xx Datasheet 2.6. Pin definitions 2.6.1. GD32VW553Hx QFN40 pin definitions Table 2-3. GD32VW553Hx QFN40 pin definitions GD32VW553Hx QFN40 Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PC8 PC8-BOOT0 1 I/O 5VT Alternate: TIMER2_CH2, I2C0_SDA, I2C1_SDA, USART0_TX, UART1_TX, EVENTOUT Additional: BOOT0 Default: JTDI, PA15 PA15WKUP1 Alternate: TIMER1_CH0, TIMER1_ETI, I2C0_SCL, 2 I/O 5VT I2C1_SCL, USART0_RX, UART1_RX, EVENTOUT Additional: WKUP1 Default: PC13 PC13 3 I/O 5VT Alternate: USART0_CK, EVENTOUT Additional: RTC_TAMP_0, RTC_OUT, RTC_TS PC14OSC32IN PC15OSC32OUT Default: PC14 4 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN Default: PC15 5 I/O 5VT Alternate: IFRP_OUT, EVENTOUT Additional: OSC32OUT NRST 6 I/O - Default: NRST PU 7 - - Default: PU 8 P - Default: AVDD33_ANA NC 9 - - - RF 10 AI/AO AVDD33_PA 11 P 12 P - Default: AVDD33_CLK XTAL1 13 AI - Default: XTAL1 XTAL2 14 AO - Default: XTAL2 VDDA 15 P - Default: VDDA AVDD33_AN A AVDD33_CL K Default: RF Default: AVDD33_PA Default: PA0 Alternate: USART0_TX, TIMER1_CH0, PA0-WKUP0 16 I/O 5VT TIMER1_ETI, SPI_MOSI, UART1_CTS, TIMER0_ETI, EVENTOUT Additional: ADC_IN0, WAKEUP0, RTC_TAMP1 Default: PA1 PA1 17 I/O 5VT Alternate: USART0_RX, TIMER1_CH1, SPI_MISO, UART1_RTS, EVENTOUT 17 GD32VW553xx Datasheet GD32VW553Hx QFN40 Pin Name Pins Pin I/O Type(1) Level(2) Functions description Additional: ADC_IN1 Default: PA2 Alternate: USART0_CTS, TIMER1_CH2, PA2 18 I/O 5VT I2C0_SCL, SPI_SCK, TIMER0_CH0, UART1_TX, EVENTOUT Additional: ADC_IN2 Default: PA3 Alternate: USART0_RTS, TIMER1_CH3, PA3 19 I/O 5VT I2C0_SDA, SPI_NSS, TIMER0_CH0_ON, UART1_RX, RTC_OUT, EVENTOUT Additional: ADC_IN3 Default: PA4 PA4 20 I/O 5VT Alternate: UART1_TX, SPI_MOSI, QSPI_SCK, SPI_NSS, TIMER0_CH1, EVENTOUT Additional: ADC_IN4 Default: PA5 Alternate: UART1_RX, TIMER2_ETI, QSPI_CSN, PA5 21 I/O 5VT SPI_MISO, SPI_SCK, TIMER0_CH1_ON , EVENTOUT Additional: ADC_IN5 Default: PA6 Alternate: TIMER2_CH0, QSPI_IO0, I2C1_SCL, PA6 22 I/O 5VT SPI_MISO, SPI_SCK, TIMER0_CH1 , TIMER1_CH1, UART2_TX, EVENTOUT Additional: ADC_IN6 Default: PA7 Alternate: I2C1_SDA , TIMER0_CH0_ON, PA7-WKUP2 23 I/O 5VT TIMER2_CH1, QSPI_IO1, SPI_NSS, SPI_MOSI, TIMER0_CH1_ON, UART2_RX, TIMER1_CH2, EVENTOUT Additional: ADC_IN7, WAKEUP2 Default: PB0 Alternate: TIMER0_CH1_ON, TIMER0_CH0, PB0 24 I/O 5VT TIMER0_CH2, UART1_TX, I2C0_SCL, TIMER2_ETI, TIMER16_CH0, UART2_CTS, TIMER0_BRKIN, EVENTOUT Additional: ADC_IN8 Default: PB1 Alternate: TIMER0_CH2_ON, TIMER0_CH0_ON, PB1 25 I/O 5VT TIMER2_CH2, UART1_RX, I2C0_SDA, TIMER16_CH0_ON, UART2_RTS, EVENTOUT Additional: BOOT1 Default: PB2 PB2 26 I/O 5VT Alternate: TIMER1_CH3, TIMER2_CH3, UART1_CTS, TIMER0_ETI, TIMER16_BRKIN, EVENTOUT 18 GD32VW553xx Datasheet GD32VW553Hx QFN40 Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PB11 PB11 27 I/O 5VT Alternate: CK_OUT1, TIMER1_CH2, TIMER0_CH1_ON, UART1_RTS, TIMER15_BRKIN, EVENTOUT Default: PB12 PB12 28 I/O 5VT Alternate: TIMER0_BRKIN, TIMER0_CH3, TIMER1_CH2, I2C1_SCL, EVENTOUT Default: PB13 PB13 29 I/O 5VT Alternate: TIMER0_CH0_ON, TIMER1_CH3, I2C1_SDA, TIMER15_CH0, EVENTOUT Default: PB15 PB15 30 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER2_CH0, I2C0_SCL, I2C1_SCL, UART1_TX, USART0_TX, IFRP_OUT , EVENTOUT Default: PA8 Alternate: CK_OUT0, TIMER0_CH0, USART0_RX, PA8 31 I/O 5VT UART1_RX, I2C0_SDA, I2C1_SDA, USART0_CK, TIMER15_CH0, RTC_OUT, TIMER0_CH2_ON , EVENTOUT Default: PA9 PA9 32 I/O 5VT Alternate: SPI_MOSI , TIMER0_CH1, QSPI_SCK, USART0_TX, TIMER15_CH0_ON, EVENTOUT Default: PA10 PA10 33 I/O 5VT Alternate: SPI_MISO, TIMER0_CH2, QSPI_CSN, TIMER16_CH0, USART0_RX, EVENTOUT Default: PA11 PA11 34 I/O 5VT Alternate: SPI_SCK, TIMER0_CH3, QSPI_IO0, TIMER16_BRKIN, TIMER1_CH3, EVENTOUT Default: PA12 PA12WKUP3 Alternate: TIMER0_ETI, TIMER0_CH3, QSPI_IO1, 35 I/O 5VT SPI_NSS, USART0_CK, TIMER1_CH2, TIMER16_CH0_ON, EVENTOUT Additional: WKUP3 Default: JTDO, PB3 PB3 36 I/O 5VT Alternate: TIMER1_CH1, QSPI_IO2, USART0_RX, UART1_RX, TIMER15_BRKIN, EVENTOUT Default: NJTRST, PB4 PB4 37 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, QSPI_IO3, USART0_TX, UART1_TX, EVENTOUT Default: JTMS, PA13 PA13 38 I/O 5VT Alternate: I2C0_SMBA, I2C1_SCL, USART0_CTS, UART1_CTS, EVENTOUT Default: JTCK, PA14 PA14 39 I/O 5VT Alternate: I2C1_SMBA, I2C1_SDA, USART0_RTS, UART1_RTS, EVENTOUT 19 GD32VW553xx Datasheet GD32VW553Hx QFN40 Pin Name Pins VDD 40 Pin I/O Type(1) Level(2) P - Functions description Default: VDD Note: (1) Type: I = input, O = output, A = analog, P = power. (2) I/O Level: 5VT = 5 V tolerant. 20 GD32VW553xx Datasheet 2.6.2. GD32VW553Kx QFN32 pin definitions Table 2-4. GD32VW553Kx QFN32 pin definitions GD32VW553Kx QFN32 Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: JTDI, PA15 PA15WKUP1 Alternate: TIMER1_CH0, TIMER1_ETI, I2C0_SCL, 1 I/O 5VT I2C1_SCL, USART0_RX, UART1_RX, EVENTOUT Additional: WKUP1 Default: PC13 PC13 2 I/O 5VT Alternate: USART0_CK, EVENTOUT Additional: RTC_TAMP_0, RTC_OUT, RTC_TS PC14OSC32IN PC15OSC32OUT Default: PC14 3 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN Default: PC15 4 I/O 5VT Alternate: IFRP_OUT, EVENTOUT Additional: OSC32OUT Default: NRST NRST 5 I/O PU 6 - Default: PU 7 P Default: AVDD33_ANA RF 8 AI/AO AVDD33_PA 9 P Default: AVDD33_PA 10 P Default: AVDD33_CLK XTAL1 11 AI Default: XTAL1 XTAL2 12 AO Default: XTAL2 VDDA 13 P Default: VDDA AVDD33_AN A AVDD33_CL K Default: RF Default: PA0 Alternate: USART0_TX, TIMER1_CH0, PA0-WKUP0 14 I/O 5VT TIMER1_ETI, SPI_MOSI, UART1_CTS, TIMER0_ETI, EVENTOUT Additional: ADC_IN0, WAKEUP0, RTC_TAMP1 Default: PA1 PA1 15 I/O 5VT Alternate: USART0_RX, TIMER1_CH1, SPI_MISO, UART1_RTS, EVENTOUT Additional: ADC_IN1 Default: PA2 Alternate: USART0_CTS, TIMER1_CH2, PA2 16 I/O 5VT I2C0_SCL, SPI_SCK, TIMER0_CH0, UART1_TX, EVENTOUT Additional: ADC_IN2 PA3 17 I/O 5VT Default: PA3 Alternate: USART0_RTS, TIMER1_CH3, 21 GD32VW553xx Datasheet GD32VW553Kx QFN32 Pin Name Pins Pin I/O Type(1) Level(2) Functions description I2C0_SDA, SPI_NSS, TIMER0_CH0_ON, UART1_RX, RTC_OUT, EVENTOUT Additional: ADC_IN3 Default: PA4 PA4 18 I/O 5VT Alternate: UART1_TX, SPI_MOSI, QSPI_SCK, SPI_NSS, TIMER0_CH1, EVENTOUT Additional: ADC_IN4 Default: PA5 Alternate: UART1_RX, TIMER2_ETI, QSPI_CSN, PA5 19 I/O 5VT SPI_MISO, SPI_SCK, TIMER0_CH1_ON , EVENTOUT Additional: ADC_IN5 Default: PA6 Alternate: TIMER2_CH0, QSPI_IO0, I2C1_SCL, PA6 20 I/O 5VT SPI_MISO, SPI_SCK, TIMER0_CH1 , TIMER1_CH1, UART2_TX, EVENTOUT Additional: ADC_IN6 Default: PA7 Alternate: I2C1_SDA , TIMER0_CH0_ON, PA7-WKUP2 21 I/O 5VT TIMER2_CH1, QSPI_IO1, SPI_NSS, SPI_MOSI, TIMER0_CH1_ON, UART2_RX, TIMER1_CH2, EVENTOUT Additional: ADC_IN7, WAKUP2 Default: PB0 Alternate: TIMER0_CH1_ON, TIMER0_CH0, PB0 22 I/O 5VT TIMER0_CH2, UART1_TX, I2C0_SCL, TIMER2_ETI, TIMER16_CH0, UART2_CTS, TIMER0_BRKIN, EVENTOUT Additional: ADC_IN8 Default: PB1 Alternate: TIMER0_CH2_ON, TIMER0_CH0_ON, PB1 23 I/O 5VT TIMER2_CH2, UART1_RX, I2C0_SDA, TIMER16_CH0_ON, UART2_RTS, EVENTOUT Additional: BOOT1 Default: PB15 PB15 24 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER2_CH0, I2C0_SCL, I2C1_SCL, UART1_TX, USART0_TX, IFRP_OUT , EVENTOUT Default: PA8 Alternate: CK_OUT0, TIMER0_CH0, USART0_RX, PA8 25 I/O 5VT UART1_RX, I2C0_SDA, I2C1_SDA, USART0_CK, TIMER15_CH0, RTC_OUT, TIMER0_CH2_ON , EVENTOUT PA12WKUP3 26 I/O 5VT Default: PA12 22 GD32VW553xx Datasheet GD32VW553Kx QFN32 Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: TIMER0_ETI, TIMER0_CH3, QSPI_IO1, SPI_NSS, USART0_CK, TIMER1_CH2, TIMER16_CH0_ON, EVENTOUT Additional: WKUP3 Default: JTDO, PB3 PB3 27 I/O 5VT Alternate: TIMER1_CH1, QSPI_IO2, USART0_RX, UART1_RX, TIMER15_BRKIN, EVENTOUT Default: NJTRST, PB4 PB4 28 I/O 5VT Alternate: TIMER1_CH0, TIMER1_ETI, QSPI_IO3, USART0_TX, UART1_TX, EVENTOUT Default: JTMS, PA13 PA13 29 I/O 5VT Alternate: I2C0_SMBA, I2C1_SCL, USART0_CTS, UART1_CTS, EVENTOUT Default: JTCK, PA14 PA14 30 I/O 5VT Alternate: I2C1_SMBA, I2C1_SDA, USART0_RTS, UART1_RTS, EVENTOUT VDD 31 Default: VDD P Default: PC8 PC8-BOOT0 32 I/O 5VT Alternate: TIMER2_CH2, I2C0_SDA, I2C1_SDA, USART0_TX, UART1_TX, EVENTOUT Additional: BOOT0 Note: (1) Type: I = input, O = output, A = analog, P = power. (2) I/O Level: 5VT = 5 V tolerant. 23 GD32VW553xx Datasheet 2.6.3. GD32VW553xx pin alternate functions Table 2-5. Port A alternate functions summary Pin Name PA0 PA1 PA2 PA3 AF0 USART0_T X USART0_ RX USART0_ CTS USART0_ RTS PA4 UART1_TX PA5 UART1_R X PA6 PA7 PA8 PA9 PA10 PA11 PA12 AF1 AF2 JTMS PA14 JTCK PA15 JTDI AF4 I2C0_SCL I2C0_SDA SPI_MOSI QSPI_SCK TIMER2_E TI TIMER2_C H0 TIMER0_C TIMER2_C I2C1_SDA H0_ON H1 TIMER0_C USART0_ CK_OUT0 H0 RX TIMER0_C SPI_MOSI H1 TIMER0_C SPI_MISO H2 TIMER0_C SPI_SCK H3 TIMER0_E TIMER0_C TI H3 PA13 AF3 TIMER1_C H0/TIMER 1_ETI TIMER1_C H1 TIMER1_C H2 TIMER1_C H3 TIMER1_C H0/TIMER 1_ETI AF5 AF6 SPI_MOSI UART1_C TS SPI_MISO UART1_R TS UART1_R X SPI_SCK SPI_MOSI SPI_SCK TIMER0_C H1_ON I2C0_SMB A I2C1_SMB A USART0_ CK USART0_T X TIMER16_ CH0 TIMER16_ BRKIN USART0_ SPI_NSS CK USART0_ I2C1_SCL CTS USART0_ I2C1_SDA RTS I2C0_SCL I2C1_SCL I2C0_SDA I2C1_SDA QSPI_SCK QSPI_CSN QSPI_IO0 QSPI_IO1 AF9 AF10 TIMER0_E TI TIMER0_C UART1_TX H0 TIMER0_C UART1_R SPI_NSS H0_ON X QSPI_IO0 I2C1_SCL SPI_MISO SPI_NSS AF8 SPI_SCK SPI_NSS QSPI_CSN SPI_MISO QSPI_IO1 AF7 RTC_OUT TIMER0_C H1 TIMER0_C H1_ON TIMER0_C TIMER1_C UART2_TX H1 H1 UART2_R TIMER1_C X H2 TIMER15_ TIMER0_C RTC_OUT CH0 H2_ON TIMER15_ CH0_ON USART0_ RX TIMER1_C H3 TIMER1_C TIMER16_ H2 CH0_ON UART1_C TS UART1_R TS USART0_ UART1_R RX X AF11 AF12 AF13 AF14 AF15 EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T EVENTOU T 24 GD32VW553xx Datasheet Table 2-6. Port B alternate functions summary Pin Name PB0 PB1 PB2 PB3 PB4 PB11 PB12 PB13 PB15 AF0 AF1 TIMER0_C H1_ON TIMER0_C H2_ON TIMER1_C H3 TIMER1_C JTDO H1 TIMER1_C NJTRST H0/TIMER 1_ETI TIMER1_C CK_OUT1 H2 TIMER0_B RKIN TIMER0_C H0_ON RTC_REFI TIMER0_C N H2_ON AF2 AF3 AF4 AF5 TIMER0_C TIMER0_C UART1_TX H0 H2 TIMER0_C TIMER2_C UART1_R H0_ON H2 X TIMER2_C UART1_C H3 TS AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 TIMER2_E TIMER16_ UART2_C TIMER0_B I2C0_SCL TI CH0 TS RKIN TIMER16_ UART2_R I2C0_SDA CH0_ON TS TIMER0_E TIMER16_ TI BRKIN USART0_ TIMER15_ UART1_TX RX BRKIN QSPI_IO2 USART0_T UART1_R X X QSPI_IO3 TIMER0_C H1_ON TIMER0_C TIMER1_C H3 H2 TIMER1_C H3 TIMER2_C I2C0_SCL H0 AF15 EVENTOU T(1) EVENTOU T(1) EVENTOU T(1) EVENTOU T EVENTOU T UART1_R TS TIMER15_ BRKIN EVENTOU T EVENTOU T EVENTOU T EVENTOU T I2C1_SCL TIMER15_ CH0 USART0_T I2C1_SCL UART1_TX IFRP_OUT X I2C1_SDA Table 2-7. Port C alternate functions summary Pin Name AF0 USART0_ CK PC14 PC15 AF2 TIMER2_C H2 PC8 PC13 AF1 IFRP_OUT AF3 AF4 I2C0_SDA AF5 AF6 AF7 AF8 USART0_T I2C1_SDA UART1_TX X AF9 AF10 AF11 AF12 AF13 AF14 AF15 EVENTOU T EVENTOU T EVENTOU T EVENTOU T 25 GD32VW553xx Datasheet 3. Functional description 3.1. RISC-V core The devices of GD32VW553xx series devices are 32-bit general-purpose microcontrollers based on the Nuclei N307 processor. The N307 processor is based on the RISC-V architecture instruction set. The RISC-V processor includes two AHB buses known as I-Cache bus and System bus. All memory accesses of the RISC-V processor are executed on the two buses according to the different purposes and the target memory spaces. The memory organization uses a Harvard architecture, pre-defined memory map and up to 4 GB of memory space, making the system flexible and extendable. It supports 64 general purpose registers (GPRs):  3-pipeline stages, using state-of-the-art processor micro-architecture to deliver the best-of-class performance efficiency and lowest cost.  Machine (M) and User (U) Privilege levels support.  Non-maskable interrupt (NMI) support.  Support dynamic branch predictor.  Configurable instruction prefetch logic, which can prefetch subsequent two instructions to hide the instruction memory access latency.  Support WFI (Wait for Interrupt) and WFE (Wait for Event) scheme to enter sleep mode.  Interrupt priority levels configurable and programmable.  Enhancement of vectored interrupt handling for real-time performance.  Support interrupt preemption with priority.  Support interrupt tail chaining.  Standard 4-wire JTAG debug port and 2-wire cJTAG debug port.  Support interactive debug functionalities.  Support 8 triggers for hardware breakpoint.  RV32I / M / A / F / D / C / P / B instruction extensions support.  Support two-level sleep modes: shallow sleep mode, and deep sleep mode.  Support 64-bits widereal-time counter (can be used as System Tick).  Support Physical Memory Protection (PMP) to protect the memory, 8 entries.  Support Instruction Cache (I-Cache), 2-way associative, cache line size 32 bytes, total 32KB. 3.2.  Support single / double precision FPU.  Support 2 cycle floating point MAC.  Support packed-SIMD DSP. On-chip memory  Up to 4096 Kbytes of Flash memory. 26 GD32VW553xx Datasheet  Up to 288 Kbytes + 32 Kbyte (shared SRAM) SRAM memory. 4096 Kbytes Flash memory, and 320 Kbytes (288 Kbytes + 32 Kbyte Shared) SRAM at most is available for storing programs and data. Table 2-2. GD32VW553xx memory map shows the memory map of the GD32VW553xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 3.3. Clock, reset and supply management  Internal 16 MHz factory-trimmed RC and external 8 to 52 MHz crystal oscillator.  Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator.  Integrated system clock PLL.  1.8 to 3.6 V application supply and I/Os.  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD). The Clock Control Unit (CCTL) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 160 MHz/160 MHz/80MHz. See Figure 2-4. GD32VW553xx clock tree for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 1.55 V and down to 1.51V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 1.8 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA is 0 V.  VDDA range: 1.8 to 3.6 V, external analog power supply for ADC, reset blocks, RCs and PLL. 3.4. Boot modes At startup, BOOT0 value and BOOT1 value are used to select the boot address. BOOT0 value and BOOT1 value are determined by configurations shown in Table 3-1. BOOT0 modes and Table 3-2. BOOT1 modes respectively.  The BOOT0 value may come from the BOOT0 pin or from the value of SWBOOT0 bit in the EFUSE_CTL0 register to free the GPIO pad if needed. 27 GD32VW553xx Datasheet  The BOOT1 value may come from the PB1 pin or from the value of SWBOOT1 bit in the EFUSE_CTL0 register to free the GPIO pad if needed. Table 3-1. BOOT0 modes SWBOOT0 EFBOOT0 BOOT0 PC8 pin BOOT0 0 - 0 0 0 - 1 1 1 0 - 0 1 1 - 1 Table 3-2. BOOT1 modes BOOT1 PB1 SWBOOT1 EFBOOT1 0 - 0 0 0 - 1 1 1 0 - 0 1 1 - 1 pin BOOT1 Refer to Table 3-3. Boot address modes for boot address. When BOOT0 value is 0:  The boot address is selected according to EFSB bit value in EFUSE_CTL0 register. When BOOT0 value is 1:  When the EFBOOTLK bit in the EFUSE_CTL0 register is 0, the boot address is selected according to BOOT0 value and BOOT1 value.  When the EFBOOTLK bit in the EFUSE_CTL0 register is 1, the boot address is selected according to BOOT0 value. Table 3-3. Boot address modes EFBOO BOOT0 BOOT1 EFSB Boot address Boot area - 0 - 0 0x08000000 SIP Flash - 0 - 1 0x0BF46000 secure boot 0 1 0 - 0x0BF40000 Bootloader / ROM 0 1 1 - 0x0A000000 SRAM0 1 1 - - 0x0BF40000 Bootloader / ROM TLK The BOOTx (x=0/1) value (either coming from the pin or the EFBOOTx bit) is latched upon reset release. It is up to the user to set BOOTx values to select the required boot mode. The BOOTx pin or EFBOOTx bit (depending on the EFBOOTLK and SWBOOTx bit value in the EFUSE_CTL0 register) is also re-sampled when exiting from Standby mode. Consequently, they must be kept in the required Boot mode configuration in Standby mode. After startup delay, the selection of the boot area is done before releasing the processor reset. The embedded bootloader is located in the System memory, which is used to reprogram 28 GD32VW553xx Datasheet the Flash memory. The bootloader can be activated through one of the following serial interfaces: USART0 (PB15 and PA8), UART1 (PA4 and PA5), UART2 (PA6 and PA7). 3.5. Power saving modes The MCU supports six kinds of power saving modes to achieve even lower power consumption. They are Sleep, Deep-sleep, Standby, SRAM_sleep, WIFI_sleep and BLE_sleep mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode The sleep mode is corresponding to the SLEEPING mode of the RISC-V. In sleep mode, only clock of RISC-V is off. To enter the sleep mode, it is only necessary to clear the CSR_SLEEPVALUE bit in the RISC-V System Control Register, and execute a WFI or WFE instruction. If the sleep mode is entered by executing a WFI instruction, any interrupt can wake up the system. If it is entered by executing a WFE instruction, any wakeup event can wake up the system. The mode offers the lowest wakeup time as no time is wasted in interrupt entry or exit.  Deep-sleep mode The deep-sleep mode is based on the SLEEPDEEP mode of the RISC-V. In deepsleep mode, all clocks in the 1.1V domain are off, and all of IRC16M, HXTAL and PLLs are disabled. The contents of SRAM0/1/2/3 and registers are preserved. The LDO can operate normally or in low power mode depending on the LDOLP bit in the PMU_CTL0 register. Before entering the Deep-sleep mode, it is necessary to set the CSR_SLEEPVALUE bit in the RISC-V System Control Register, and clear the STBMOD bit in the PMU_CTL0 register. Then, the device enters the deep-sleep mode after a WFI or WFE instruction is executed. If the Deep-sleep mode is entered by executing a WFI instruction, any interrupt from EXTI lines can wake up the system. If it is entered by executing a WFE instruction, any wakeup event from EXTI lines can wake up the system. When exiting the Deep-sleep mode, the IRC16M is selected as the system clock. Notice that an additional wakeup delay will be incurred if the LDO operates in low power mode. The low-driver mode in deep-sleep mode can be entered by configuring the LDEN[1:0], LDNP, LDLP, LDOLP bits in the PMU_CTL0 register. The low-driver mode provides lower drive capability, and the low-power mode take lower power. Normal-driver & Normal-power: The Deep-sleep mode is not in low-driver mode by configure LDEN[1:0] to 00 in the PMU_CTL0 register, and not in low-power mode depending on the LDOLP bit reset in the PMU_CTL0 register. Normal-driver & Low-power: The Deep-sleep mode is not in low-driver mode by configure LDEN[1:0] to 00 in the PMU_CTL0 register. The low-power mode enters depending on the LDOLP bit set in the PMU_CTL0 register. Low-driver & Normal-power: The low-driver mode in Deep-sleep mode when the LDO in normal-power mode depending on the LDOLP bit reset in the PMU_CTL0 register enters by configure LDEN[1:0] to 0b11 and LDNP to 1 in the PMU_CTL0 29 GD32VW553xx Datasheet register. Low-driver & Low-power: The low-driver mode in Deep-sleep mode when the LDO in low-power mode depending on the LDOLP bit set in the PMU_CTL0 register enters by configure LDEN[1:0] to 0b11 and LDLP to 1 in the PMU_CTL0 register. No Low-driver: The Deep-sleep mode is not in low-driver mode by configure LDEN[1:0] to 00 in the PMU_CTL0 register. Note: In order to enter deep-sleep mode smoothly, all EXTI line pending status (in the EXTI_PD register) and RTC alarm / timestamp / tamper / auto wakeup flag must be reset. If not, the program will skip the entry process of deep-sleep mode to continue to execute the following procedure.  Standby mode The standby mode is based on the SLEEPDEEP mode of the RISC-V, too. In standby mode, the whole 1.1V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLLs are disabled. Before entering the standby mode, it is necessary to set the CSR_SLEEPVALUE bit in the RISC-V System Control Register, and set the STBMOD bit in the PMU_CTL0 register, and clear WUF bit in the PMU_CS0 register. Then, the device enters the standby mode after a WFI or WFE instruction is executed, and the STBF status flag in the PMU_CS0 register indicates that the MCU has been in standby mode. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm / time stamp / tamper / auto wakeup events, the FWDGT reset, and the rising edge on WKUP pins. The standby mode achieves the lowest power consumption, but spends longest time to wake up. Besides, the contents of SRAM0 / SRAM1 / SRAM2 / SRAM3 and registers in 1.1V power domain are lost in standby mode. When exiting from the standby mode, a power-on reset occurs and the RISC-V will execute instruction code from the 0x00000000 address.  SRAM_sleep mode When at least one of SRAM0 / SRAM1 / SRAM2 / SRAM3 is powered off, set the SRAMxPSLEEP (x = 0/1/2/3) bit in PMU_CTL1 register, then corresponding SRAMx (x = 0/1/2/3) will enter power off state (wait for several PCLK clocks, SRAM can completely power off and enter the SRAM sleep mode). When the SRAMxPWAKE (x = 0/1/2/3) bit in PMU_CTL1 register is set, the SRAMx (x = 0/1/2/3) will be powered on. SRAM0 / SRAM1 / SRAM2 / SRAM3 can be configured power on or power off when in run / sleep / deep_sleep mode. SRAM0 / SRAM1 / SRAM2 / SRAM3 are power off when in standby mode.  WIFI_sleep mode The Wi-Fi_sleep mode can enter by software (set WPEN bit to 1 and set WPSLEEP bit to 1), or by hardware (driven by Wi-Fi hardware signal sleep_wl when WPEN is 1). This mode can exit by clearing WPEN bit to 0, or by setting WPEN bit to 1 then setting WPSLEEP bit to 1, or by hardware (driven by Wi-Fi hardware signal wake_wl when WPEN is 1). When Wi-Fi enter Wi-Fi_sleep mode, Wi-Fi_OFF domain power off.  BLE_sleep mode 30 GD32VW553xx Datasheet When BLE enter BLE_sleep mode, BLE_OFF domain power off. When exit from BLE_sleep mode, BLE is active mode, all BLE power domain power on. 3.6. Electronic fuse (EFUSE)  One-time programmable nonvolatile EFUSE storage cells organized as 128*8 bit.  All bits in the efuse cannot be rollback from 1 to 0.  Can only be accessed through corresponding registers. The Efuse controller has Efuse macro that store system paramters. As a non-volatile unit of storage, the bit of Efuse macro cannot be restored to 0 once it is programmed to 1. According to the software opration, the Efuse controller can program all bits in the system parameters. 3.7. General-purpose inputs / outputs (GPIOs)  Up to 29 fast GPIOs, all mappable on 16 external interrupt lines.  Analog input/output configurable.  Alternate function input/output configurable. There are up to 29 general purpose I/O pins (GPIO) in GD32VW553xx, named PA0 ~ PA15, PB0 ~ PB4, PB11 ~ PB13, PB15, PC8 and PC13 ~ PC15 to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/Event Controller Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), input, peripheral alternate function or analog mode. Most of the GPIO pins are shared with digital or analog alternate functions. 3.8. CRC calculation unit (CRC)  32-bit data input and 32-bit data output. Calculation period is 4 AHB clock cycles for 32-bit input data size from data entered to the calculation result available.  Free 8-bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices.  Fixed polynomial: 0x4C11DB7 X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC 31 GD32VW553xx Datasheet calculation unit can be used to calculate 32 bit CRC code with fixed polynomial. 3.9. True Random number generator (TRNG)  About 40 periods of TRNG_CLK are needed between two consecutive random numbers.  Disable TRNG module will significantly reduce the chip power consumption.  32-bit random value seed is generated from analog noise, so the random number is a true random number. The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. 3.10. Direct memory access controller (DMA)  8 channels for DMA controller, up to 8 peripherals per channel with fixed hardware peripheral requests.  Support independent single, 4, 8, 16-beat incrementing burst memory and peripheral transfer.  Peripherals supported: Timers, ADC, SPI, QSPI, I2Cs, USARTs, CAU and HAU. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data. Two AHB master interfaces and eight four-word depth 32-bit width FIFOs are presented in DMA controller, which achieves a high DMA transmission performance. There are 8 independent channels in the DMA controller. Each channel is assigned a specific or multiple target peripheral devices for memory access request management. Two arbiters respectively for memory and peripheral are implemented inside to handle the priority among DMA requests. Both the DMA controller and the RISC-V core implement data access through the system bus. An arbitration mechanism is implemented to solve the competition between these two masters. When the same peripheral is targeted, the MCU access will be suspended for some specific bus cycles. A round-robin scheduling algorithm is utilized in the bus matrix to guaranty at least half the bandwidth to the MCU. 3.11. Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 3 MSPS.  Hardware oversampling ratio adjustable from 2x to 256x improves resolution to 1632 GD32VW553xx Datasheet bit.  Input voltage range: 0 ≤ VIN ≤ VDDA.  Temperature sensor. A 12-bit 3 MSPS multi-channel ADC is integrated in the device. It has a total of 11 multiplexed channels: up to 9 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT). The input voltage range is between 0 and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. The analog watchdog allows the application to detect whether the input voltage goes outside the user-defined higher or lower thresholds. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the TIMERx (x= 0,1,2,5,15,16) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN9 input channel which is used to convert the sensor output voltage in a digital value. To ensure a high accuracy on ADC, the independent power supply VDDA is implemented to achieve better performance of analog circuits. VDDA can be externally connected to VDD through the external filtering circuit that avoids noise on V DDA, and VSSA should be connected to VSS through the specific circuit independently. 3.12. Real time clock (RTC)  Independent binary-coded decimal (BCD) format timer / counter with twenty 32-bit backup registers.  Calendar with sub-second, second, minute, hour, week day, day, month and year automatically correction.  Alarm function with wake up from deep-sleep and standby mode capability.  Atomic clock adjust (max adjust accuracy is 0.95PPM) for calendar calibration performed by digital calibration function. The RTC provides a time which includes hour / minute / second / sub-second and a calendar includes year / month / day / week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time. Working in power saving mode and smart wakeup is software configurable. Support improving the calendar accuracy using extern accurate low frequency clock. 3.13. Timers and PWM generation  One 16-bit advanced timer (TIMER0), two 32-bit general timer (TIMER1, TIMER2), two 16-bit general timers (TIMER15, TIMER16), and one 16-bit basic timer (TIMER5). 33 GD32VW553xx Datasheet  Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input.  16-bit, motor control PWM advanced timer with programmable dead-time generation for output match.  Encoder interface controller with two inputs using quadrature decoder.  64-bit SysTick timer up counter.  2 watchdog timers (free watchdog timer and window watchdog timer). The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features. The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 and TIMER2 are based on a 32-bit auto-reload up/down counter and a 16-bit prescaler. TIMER15 and TIMER16 are based on a 16-bit auto-reload up counter and a 16-bit prescaler. Only TIMER1 and TIMER2 supports an encoder interface with two inputs using quadrature decoder. The basic timer TIMER5, is mainly used as a simple 16-bit time base. The GD32VW553xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and an 8-stage prescaler. It is clocked from an independent 32 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a freerunning timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below:  A 64-bit up counter.  Maskable system interrupt generation when the counter and comparison values are equal.  Programmable clock source. 34 GD32VW553xx Datasheet 3.14. Universal synchronous asynchronous receiver transmitter (USART)  Maximum speed up to 20 MBits/s.  Supports both asynchronous and clock synchronous serial communication modes.  IrDA SIR encoder and decoder support.  LIN break generation and detection.  ISO 7816-3 compliant smart card interface.  Dual clock domain.  Wake up from Deep-sleep mode. The USART (USART0, UART1, UART2) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication. 3.15. Inter-integrated circuit (I2C)  Support both master and slave mode with a frequency up to 1 MHz (Fast mode plus).  Provide arbitration function, optional PEC (packet error checking) generation and checking.  Supports 7-bit and 10-bit addressing mode and general call addressing mode.  SMBus 3.0 and PMBus 1.3 compatible.  Wakeup from Deep-sleep mode on I2C0 address match. The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 3.16. Serial peripheral interface (SPI)  SPI interfaces with a frequency of up to 40 MHz.  Support both master and slave mode.  Hardware CRC calculation and transmit automatic CRC error checking.  SPI quad mode configuration available in master mode. 35 GD32VW553xx Datasheet The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). SPI can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.17. Quad-SPI interface (QSPI)  Support normal mode, read polling mode and memory map mode.  Fully programmable command format for both normal mode and memory map mode.  Integrated FIFO for transmission/reception.  8, 16, or 32-bit data accesses.  DMA channel for normal mode. The QSPI is a specialized interface that communicate with Flash memories. This interface support single, dual or quad SPI FLASH. 3.18. Cryptographic acceleration Unit (CAU)  Supports DES, TDES or AES (128, 192, or 256) algorithms.  DES/TDES supports Electronic codebook (ECB) or Cipher block chaining (CBC) mode.  AES supports 128bits-key, 192bits-key or 256 bits-key.  AES supports Electronic codebook (ECB), Cipher block chaining (CBC) mode, Counter mode (CTR) mode, Galois/counter mode (GCM), Galois message authentication code mode (GMAC), Counter with CBC-MAC (CCM), cipher message authentication code mode (CMAC), Cipher Feedback mode (CFB) and Output Feedback mode (OFB).  DMA transfer for incoming and outgoing data is supported. The Cryptographic Acceleration Unit supports acceleration of DES, TDES or AES (128, 192, or 256) algorithms. The DES/TDES supports Electronic codebook (ECB) or Cipher block chaining (CBC) mode. The AES supports Electronic codebook (ECB), Cipher block chaining (CBC) mode, Counter mode (CTR) mode, Galois/counter mode (GCM), Galois message authentication code mode (GMAC), Counter with CBC-MAC (CCM), Cipher Feedback mode (CFB) and Output Feedback mode (OFB). 3.19. Hash acceleration unit (HAU)  Supports SHA-1, SHA-224 and SHA-256 algorithms, compliant with FIPS PUB 1802 (Federal Information Processing Standards Publication 180-2).  Supports MD5 compliant with IETF RFC 1321 (Internet Engineering Task Force Request For Comments number 1321). 36 GD32VW553xx Datasheet  Supports HMAC (keyed-hash message authentication code) algorithm.  Automatic swapping to comply with the big-endian or little-endian for MD5, SHA-1, SHA-224 and SHA-256 algorithms.  Automatic padding to fit module 512.  Support DMA mode for input data flow. The HAU supports acceleration of SHA-1, SHA-224, SHA-256, MD5 algorithm and the HMAC (keyed-hash message authentication code) algorithm, which calling the SHA-1, SHA-224, SHA-256 or MD5 hash function to calculate key, message, digest three times. 3.20. Public Key Cryptographic Acceleration Unit (PKCAU)  Support RSA/DH algorithms with up to 3136 bits of operands.  Support ECC algorithm with up to 640 bits of operands.  Embedded RAM of 3584 bytes.  Conversion between the Montgomery domain and the natural domain.  only 32-bit access is supported. Public key encryption is also called asymmetric encryption, asymmetric encryption algorithms use different keys for encryption and decryption. The Public Key Cryptographic Acceleration Unit (PKCAU) can accelerate RSA (Rivest, Shamir and Adleman), Diffie-Hellmann (DH key exchange) and ECC (elliptic curve cryptography) in GF(p) (Galois domain). These operations are performed in the Montgomery domain to improve computational efficiency. 3.21. Infrared ray port (IFRP)  The IFRP output signal is decided by TIMER15_CH0 and TIMER16_CH0.  To get correct infrared ray signal, TIMER15 should generate low frequency modulation envelope signal, and TIMER16 should generate high frequency carrier signal. Infrared ray port (IFRP) is used to control infrared light LED, and send out infrared data to implement infrared ray remote control. There is no register in this module, which is controlled by TIMER15 and TIMER16. The IFRP_OUT pin can be configured by GPIO alternate function selected register. 37 GD32VW553xx Datasheet 3.22. Wireless 3.22.1. Wi-Fi Standards Supported  802.11b / g / n /ax compatible.  802.11e QoS Enhancement (WMM).  802.11i (WPA, WPA2, WPA3). Open, shared key, and pair-wise key authentication services.  WiFi WPS.  WiFi Direct.  Integrated TCP / IP protocol. Wi-Fi MAC  Target Wake up Time (TWT) operation.  Two NAV.  Multiple BSSID operation.  OFDMA-based random access.  Spatial reuse.  Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput.  Support for immediate ACK and Block-ACK policies.  Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP), and multiphase PSMP operation.  Interframe space timing support, including RIFS.  Support for RTS / CTS and CTS-to-self frame sequences for protecting frame exchanges.  Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.  Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware.  Hardware engine for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, and support for key management.  Programmable independent basic service set (IBSS) or infrastructure basic service set or Access Point functionality. Wi-Fi PHY  Single antenna 1x1 stream in 20MHz channels.  20M bandwidth.  MU-OFDMA in UL and DL as a non-AP STA.  DL MU-MIMO as a non-AP STA.  Beamforming as a beamformee. 38 GD32VW553xx Datasheet  Rx STBC scheme (1 spatial stream and 2 space-time streams).  Mid-amble.  DCM.  All guard interval (0.8 / 1.6 / 3.2us).  Support of 802.11ax MCS up to MCS9 with Max phy rate as 114.7Mbps.  Per packet TX power control.  Advanced channel estimation / equalization, automatic gain control, CCA, carrier/symbol recovery, and frame detection.  Digital calibration algorithms to handle CMOS RF chip process, voltage, and temperature (PVT) variations. 3.22.2.  Per-packet channel quality and signal-strength measurements.  Compliance with FCC and other worldwide regulatory requirements. BLE (Bluetooth Low Energy) Standards Supported  BLE5.2. BLE Linker Layer  Support multiple simulateneous hardware connection.  Advertising Extension.  High duty cycle non-connectable advertising.  Channel selection algorithm #2.  Support multiple simultaneous BLE connections. BLE Modem 3.22.3.  High speed 2M PHY.  Long range coded PHY.  Data rate: 250, 500, 1000 and 2000kbps. Radio Radio is shared between Wi-Fi and BLE.  Fractional-N for multiple reference clock support.  Integrated PA with power control.  Optimized Tx gain distribution for linearity and noise performance.  Direct conversion architecture.  On-chip gain selectable LNA with optimized noise figure.  High dynamic range AGC. 39 GD32VW553xx Datasheet 3.23. Debug mode  RISC-V External Debug Support Version 0.13. The GD32VW553xx series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the RISC-V module together with a daisy chained standard TAP controller. Debug functions are integrated into the RISC-V. The debug system supports standard JTAG debug. 3.24. Package and operation temperature  QFN40 (GD32VW553Hx) and QFN32 (GD32VW553Kx).  Operation temperature range: -40°C to +105°C (GD32VW553HxQ7), -40°C to +85°C (GD32VW553HxQ6). 40 GD32VW553xx Datasheet 4. Electrical characteristics 4.1. Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute maximum ratings (1)(4) Symbol Parameter Min Max Unit VDD External voltage range(2) - 0.3 3.6 V VDDA External analog supply voltage - 0.3 3.6 V AVDD33_ANA RF Analog voltage - 0.3 3.6 V AVDD33_PA RF PA voltage - 0.3 3.6 V AVDD33_CLK RF Clock voltage - 0.3 3.6 V - 0.3 VDD + 3.6 V Input voltage on other I/O - 0.3 3.6 V |ΔVDDx| Variations between different VDD power pins — 50 mV IIO Maximum current for GPIO pin — ±25 mA TA Operating temperature range -40 +105 °C Power dissipation at TA = 105°C of QFN40 — 418 Power dissipation at TA = 105°C of QFN32 — 389 TSTG Storage temperature range -65 +150 °C TJ Maximum junction temperature — 125 °C VIN PD(5) (1) (2) (3) (4) (5) 4.2. Input voltage on 5V tolerant pin(3) mW Guaranteed by design, not tested in production. All main power and ground pins should be connected to an external power source within the allowable range. VIN maximum value cannot exceed 5.5 V. It is recommended that VDD and VDDA are powered by the same source. The maximum difference between VDD and VDDA does not exceed 300 mV during power-up and operation. When RF power off. Operating conditions characteristics Table 4-2. DC operating conditions Min(1) Typ Max(1) Unit Symbol Parameter Conditions VDD Supply voltage — 1.8 3.3 3.6 V VDDA Analog supply voltage — 1.8 3.3 3.6 V AVDD33_ANA RF Analog voltage — 2.5(2) 3.3 3.6 V AVDD33_PA RF PA voltage — 2.5(2) 3.3 3.6 V AVDD33_CLK RF Clock voltage — 2.5(2) 3.3 3.6 V (1) (2) Based on characterization, not tested in production. RF performance may degrade below 3V. 41 GD32VW553xx Datasheet Figure 4-1. Recommended power supply decoupling capacitors(1)(2)(3) VDD GND 10uF+N*100 nF VDDA GND 1uF+10 nF AVDD33 10 μF+N*1 μF (1) (2) (3) GND When using precision internal reference voltage, and a bypass capacitor about 0.1 μF (or 1 μF connected in parallel, which is recommended) to ground is required. AVDD33 include AVDD33_PA, AVDD33_ANA, AVDD33_CLK. All decoupling capacitors need to be as close as possible to the pins on the PCB board. Table 4-3. Clock frequency (1) Symbol Parameter Conditions Min Max Unit fHCLK AHB clock frequency — — 160 MHz fAPB1 APB1 clock frequency — — 160 MHz fAPB2 APB2 clock frequency — — 80 MHz Min Max Unit — ∞ TBD — (1) Guaranteed by design, not tested in production. Table 4-4. Operating conditions at Power up / Power down (1) Symbol tVDD (1) Parameter Conditions VDD rise time rate — VDD fall time rate Guaranteed by design, not tested in production. Table 4-5. Start-up timings of Operating conditions Symbol Parameter tstart-up Start-up time (1) (2) μs /V (1)(2)(3) Conditions Typ Clock source from HXTAL 181 Clock source from IRC16M 1.03 Unit ms Based on characterization, not tested in production. After power-up, the start-up time is the time between the rising edge of NRST high and the first I/O 42 GD32VW553xx Datasheet (3) instruction. PLL is off. Table 4-6. Power saving mode wakeup timings characteristics (1)(2) Symbol Parameter Typ tSleep Wakeup from Sleep mode 15.2 Wakeup from Deep-sleep mode (LDO On) 67 Wakeup from Deep-sleep mode (LDO in low power mode) 66.8 Wakeup from Deep-sleep mode (LDO On and Low driver mode) 66.6 tDeep-sleep Wakeup from Deep-sleep mode (LDO in low power and Low driver mode) tStandby (1) (2) 4.3. Wakeup from Standby mode Unit μs 66.6 1030 Based on characterization, not tested in production. The wakeup time is measured from the wakeup event to the point at which the application code reads the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC16M = System clock = 16 MHz. Power consumption GD32VW553xx is designed with advanced power management technologies and suitable for Internet of Things applications. Table 4-7. Wi-Fi Power consumption characteristics Power Mode MCU State Wi-Fi State Active Active Active Wi-Fi Sleep Active Mild Sleep Power on, PLL off, Clock gated Hibernation Shutdown Power save mode: Wi-Fi wake up periodically to listen beacon frame to stay connected to the AP. Power save mode: Wi-Fi wake up periodically to listen beacon frame to stay connected to the AP. Mostly power off, only the wake up source is power on — Power off Power off Table 4-8. Wi-Fi Power consumption characteristics (1)(2)(3) Power Mode Description Consumption unit Wi-Fi Tx 802.11b, CCK 1Mbps, Pout = +18dBm(4) 331 mA Wi-Fi Tx 802.11b, CCK 11Mbps, Pout = +17dBm(4) 315 mA 317 mA 283 mA 316 mA 275 mA Wi-Fi Tx 802.11g, OFDM 6Mbps, Pout = +18dBm(4) Active Wi-Fi Tx 802.11g, OFDM 54Mbps, Pout = +15dBm(4) Wi-Fi Tx 802.11n, HT 20M MCS0, Pout = +18dBm(4) Wi-Fi Tx 802.11n, HT 20M MCS7, Pout = +14dBm(4) 43 GD32VW553xx Datasheet Power Mode Description Consumption unit 316 mA 265 mA Wi-Fi Rx 802.11b, CCK 1Mbps, -90dBm(5) 99 mA Wi-Fi Rx 802.11b, CCK 11Mbps, -80Bm(5) 100 mA Wi-Fi Rx 802.11g, OFDM 6Mbps, -80dBm(5) 101 mA Wi-Fi Rx 802.11g, OFDM 54Mbps, -70dBm(5) 102 mA Wi-Fi Rx 802.11n, HT 20M MCS0, -75dBm(5) 100 mA Wi-Fi Rx 802.11n, HT 20M MCS7, -65dBm(5) 103 mA Wi-Fi Rx 802.11ax, HE 20M MCS0, -75dBm(5) 101 mA Wi-Fi Rx 802.11ax, HE 20M MCS9, -60dBm(5) 107 mA MCU in Run mode(6) 37.6 mA DTIM=1 1.4 mA DTIM=3 0.55 mA 0.31 mA TBD μA — mA Wi-Fi Tx 802.11ax, HE 20M MCS0, Pout = +18dBm(4) Wi-Fi Tx 802.11ax, HE 20M MCS9, Pout = +12dBm(4) Wi-Fi Sleep Mild Sleep(7) DTIM=10 Hibernation MCU in Standby Shutdown (1) (2) (3) (4) (5) (6) (7) (8) mode(8) — Below data are measured at antenna port of GD Wi-Fi Demo board. Unless otherwise specified, all values given for TA condition and test result is mean value. DC Power = 3.3 V, HXTAL = 40 MHz, System clock = 160 MHz. Continuous Tx, Duty cycle = 100%. Rx Packet Length = 1024 Bytes. VDD = VDDA = 3.3 V, HXTAL = 40 MHz, System clock = 160 MHz, all peripherals enabled, except Wi-Fi. The DTIM power consumption is equal to the average power consumption of multiple beacon intervals. VDD = VDDA = 3.3 V, LXTAL off, IRC32K on, RTC on. Table 4-9. Power consumption characteristics (2)(3)(4)(5)(6) Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 160 MHz, All peripherals — 35.52 — mA — 18.72 — mA — 28.26 — mA — 15.49 — mA — 25.74 — mA enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 160 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, IDD+IDDA System clock = 120 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 120 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals enabled 44 GD32VW553xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 108 MHz, All peripherals — 14.24 — mA — 23.93 — mA — 13.55 — mA — 19.22 — mA — 12.74 — mA — 15.21 — mA — 10.61 — mA — 12.43 — mA — 7.55 — mA — 7.72 — mA — 5.03 — mA — 5.18 — mA — 3.37 — mA — 3.41 — mA — 2.51 — mA disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 96 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 96 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 72 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 72 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 48 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 48 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 36 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 36 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 25 MHz, PLL off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 25 MHz, PLL off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System clock = 16 MHz, PLL off, All peripherals enabled VDD = VDDA = 3.3 V, use IRC16M, System clock = 16 MHz, PLL off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System clock = 8 MHz, PLL off, All peripherals enabled VDD = VDDA = 3.3 V, use IRC16M, System 45 GD32VW553xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit clock = 8 MHz, PLL off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System clock = 4 MHz, PLL off, All peripherals — 2.53 — mA — 2.08 — mA — 2.09 — mA — 1.86 — mA — 30.88 — mA — 14.09 — mA — 24.8 — mA — 12.01 — mA — 22.62 — mA — 11.11 — mA — 21.14 — mA — 10.77 — mA — 17.14 — mA — 9.25 — mA enabled VDD = VDDA = 3.3 V, use IRC16M, System clock = 4 MHz, PLL off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System clock = 2 MHz, PLL off, All peripherals enabled VDD = VDDA = 3.3 V, use IRC16M, System clock = 2 MHz, PLL off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 160 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 160 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 120 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 120 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 108 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 108 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 96 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 96 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 72 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 72 MHz, CPU clock off, All 46 GD32VW553xx Datasheet Symbol Parameter Conditions Min Typ(1) Max Unit peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 48 MHz, CPU clock off, All — 13.82 — mA — 8.28 — mA — 11.40 — mA — 7.27 — mA — 7.02 — mA — 4.33 — mA — 4.39 — mA — 2.60 — mA — 3.02 — mA — 2.12 — mA — 2.32 — mA — 1.88 — mA — 1.98 — mA — 1.75 — mA peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 48 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 36 MHz, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 36 MHz, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 25 MHz, PLL off, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System Clock = 25 MHz, PLL off, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 16 MHz, PLL off, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 16 MHz, PLL off, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 8 MHz, PLL off, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 8 MHz, PLL off, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 4 MHz, PLL off, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 4 MHz, PLL off, CPU clock off, All peripherals disabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 2 MHz, PLL off, CPU clock off, All peripherals enabled VDD = VDDA = 3.3 V, use IRC16M, System Clock = 2 MHz, PLL off, CPU clock off, All peripherals disabled 47 GD32VW553xx Datasheet Symbol Parameter Min Typ(1) Conditions Max Unit VDD = VDDA = 3.3 V, LDO in normal power and normal driver mode, IRC32K off, RTC — 188.93 — μA — 170.50 — μA — 150.00 — μA — 130.77 — μA — 99.07 — μA — 3.30 — μA — 3.05 — μA — 2.73 — μA off, All GPIOs analog mode VDD = VDDA = 3.3 V, LDO in low power and normal driver mode, IRC32K off, RTC off, All GPIOs analog mode Supply current (Deep-Sleep VDD = VDDA = 3.3 V, LDO in normal power and low driver mode, IRC32K off, RTC off, All GPIOs analog mode mode) VDD = VDDA = 3.3 V, LDO in low power and low driver mode, IRC32K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LDO in low power and low driver mode, IRC32K off, RTC off, All GPIOs analog mode, Wi-Fi、SRAM1、 SRAM2、SRAM3 sleep VDD = VDDA = 3.3 V, LXTAL off, IRC32K on, RTC on Supply current VDD = VDDA = 3.3 V, LXTAL off, IRC32K on, (Standby mode) RTC off VDD = VDDA = 3.3 V, LXTAL off, IRC32K off, RTC off (1) (2) (3) (4) (5) (6) 4.4. Based on characterization, not tested in production. Unless otherwise specified, all values given for TA condition and test result is mean value. When System Clock is greater than 16 MHz, a crystal 25 MHz is used, and the HXTAL bypass function is closed, using PLL. When analog peripheral blocks such as ADCs, HXTAL, LXTAL, IRC16M, or IRC32K are ON, an additional power consumption should be considered. With large margin, it will be adjusted according to the mass production data. When Wi-Fi power off. EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in Table 4-10. EMS characteristics, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 4-10. EMS characteristics (1) Symbol VESD Parameter Voltage applied to all device pins to induce a functional disturbance Conditions Level/Class VDD = VDDA = AVDD33 = 3.3 V, TA = 25 °C, Wi-Fi on, QFN40, TBD fHCLK = 160 MHz 48 GD32VW553xx Datasheet Symbol Parameter Conditions Level/Class conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB induce a functional disturbance through 100 pF on VDD and GND (1) 4.5. VDD = VDDA = AVDD33 = 3.3 V, TA = 25 °C, Wi-Fi on, QFN40, TBD fHCLK = 160 MHz conforms to IEC 61000-4-4 Based on characterization, not tested in production. Power supply supervisor characteristics Table 4-11. Power supply supervisor characteristics Symbol VLVD(1) VLVDhyst(2) VPOR(1) VPDR(1) VPDRhyst(2) Parameter Conditions Min Typ Max Unit LVDT[2:0] = 000, rising edge — 2.19 — V LVDT[2:0] = 000, falling edge — 2.08 — V LVDT[2:0] = 001, rising edge — 2.33 — V LVDT[2:0] = 001, falling edge — 2.22 — V LVDT[2:0] = 010, rising edge — 2.47 — V LVDT[2:0] = 010, falling edge — 2.36 — V LVDT[2:0] = 011, rising edge — 2.61 — V Low Voltage Detector LVDT[2:0] = 011, falling edge — 2.50 — V Threshold LVDT[2:0] = 100, rising edge — 2.75 — V LVDT[2:0] = 100, falling edge — 2.64 — V LVDT[2:0] = 101, rising edge — 2.90 — V LVDT[2:0] = 101, falling edge — 2.79 — V LVDT[2:0] = 110, rising edge — 3.04 — V LVDT[2:0] = 110, falling edge — 2.92 — V LVDT[2:0] = 111, rising edge — 3.17 — V LVDT[2:0] = 111, falling edge — 3.06 — V — — 100 — mV — 1.55 — V — 1.51 — V — 40 — mV LVD hysteresis Power on reset threshold Power down reset threshold PDR hysteresis — 49 GD32VW553xx Datasheet Symbol Parameter tRSTTEMPO(2) Reset temporization (1) (2) 4.6. Conditions Min Typ Max Unit — 2.6 — ms Based on characterization, not tested in production. Guaranteed by design, not tested in production. Electrical sensitivity The device is strained in order to determine its performance in terms of electrical sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up (LU) test is based on the two measurement methods. Table 4-12. ESD characteristics (1) Symbol VESD(HBM) VESD(CDM) (1) (2) Parameter Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Conditions Min Typ Max Unit — — TBD V — — TBD V Min Typ Max Unit — — TBD mA — — TBD V TA = 25 °C; ESDA/JEDEC JS-0012017 TA = 25 °C; ESDA/JEDEC JS-0022018 Based on characterization, not tested in production. There is space for adjustment, it will be tested soon. Table 4-13. Static latch-up characteristics (1) Symbol Parameter Conditions I-test LU TA = 25 °C; JESD78E Vsupply over voltage 4.7. (1) Based on characterization, not tested in production. (2) There is space for adjustment, it will be tested soon. External clock characteristics Table 4-14. High speed external clock (HXTAL) generated from a crystal / ceramic characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fHXTAL Frequency Range — 19.2 40 52 MHz CHXTAL Crystal load Capacitance — 9 10 12 pF ESR Equivalent Series Resistance — — — 70 Ω f_tol Frequency tolerance -20 — 20 ppm tSUHXTAL(1) Crystal startup time — 0.75 — ms Initial and over temperature VDD = 3.3 V, TA = 25 °C, fHXTAL = 40 MHz Based on characterization, not tested in production. 50 GD32VW553xx Datasheet Table 4-15. High speed external user clock characteristics (HXTAL in bypass mode) Symbol Parameter Conditions Min fHXTAL_ext Frequency Range — — 40 — MHz VHXTAL OSCIN Input Voltage — 0.7 — 2.5 V Ducy(HXTAL) Duty cycle — 45 50 55 % @1kHz, fHXTAL = 40 MHz — — -125 dBc/Hz @10kHz fHXTAL = 40 MHz — — -138 dBc/Hz @100kHz fHXTAL = 40 MHz — — -143 dBc/Hz -20 — PN Phase Noise f_tol Frequency tolerance Initial and over temperature Typ Max 20 Unit ppm Table 4-16. Low speed external clock (LXTAL) generated from a crystal / ceramic characteristics fLXTAL (1) Parameter Conditions Min Typ Max Unit Crystal or ceramic frequency VDD = 3.3 V — 32.768 — kHz — — 15 — pF Lower driving capability — 4.5 — — 6.5 — Recommended matching CLXTAL (2)(3) capacitance on OSC32IN and OSC32OUT Medium low driving gm(2) Oscillator transconductance capability Medium high driving capability Higher driving capability VDD = VDDA = 3.3 V, Lower driving capability VDD = VDDA = 3.3 V, Medium IDDLXTAL(1) Crystal or ceramic operating low driving capability current VDD = VDDA = 3.3 V, Medium high driving capability VDD = VDDA = 3.3 V, Higher driving capability tSULXTAL(1)(4) (1) (2) (3) (4) Crystal or ceramic startup time VDD = 3.3 V μA/V — 13 — — 19 — — 0.8 — — 0.94 — μA — 1.34 — — 1.74 — — 2 — s Based on characterization, not tested in production. Guaranteed by design, not tested in production. CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer. Table 4-17. Low speed external user clock characteristics (LXTAL in bypass 51 GD32VW553xx Datasheet mode) Symbol Parameter External clock source or fLXTAL_ext(1) oscillator frequency 4.8. voltage Typ Max Unit VDD = 3.3 V — 32.768 1000 kHz 0.7*VDD — — VDD = 3.3 V OSC32IN input pin low level (2) voltage V — — 0.3*VDD tH/L(LXTAL)(2) OSC32IN high or low time — 450 — — tR/F(LXTAL)(2) OSC32IN rise or fall time — — — 50 CIN(2) OSC32IN input capacitance — — 5 — pF Duty cycle — 30 — 70 % Ducy(LXTAL) (1) (2) Min OSC32IN input pin high level VLXTALH(2) VLXTALL Conditions (2) ns Based on characterization, not tested in production. Guaranteed by design, not tested in production. Internal clock characteristics Table 4-18. High speed internal clock (IRC16M) characteristics Symbol fIRC16M Parameter High Speed Internal Oscillator (IRC16 M) frequency Conditions Min VDD = VDDA = 3.3 V — 16 — MHz -2.0 — +2.0 % -1.0 — +1.0 % — — 0.5 — % VDD = VDDA = 3.3 V 45 50 55 % VDD = VDDA = 3.3 V — 70 — μA VDD = VDDA = 3.3 V — 1.51 — μs 2.7 V ≤ VDD = VDDA ≤ 3.63 V, IRC16 M oscillator Frequency TA = -40 °C ~ +105 °C(1) accuracy, Factory-trimmed VDD = VDDA = 3.3 V, ACCIRC16M TA = 25°C IRC16 M oscillator Frequency accuracy, User trimming step(1) DucyIRC16M(2) IDDAIRC16M(1) tSUIRC16M(1) (1) (2) IRC16 M oscillator duty cycle IRC16 M oscillator operating current IRC16 M oscillator startup time Typ Max Unit Based on characterization, not tested in production. Guaranteed by design, not tested in production. Table 4-19. Low speed internal clock (IRC32K) characteristics Symbol Parameter Low Speed Internal fIRC32K(1) oscillator (IRC32K) frequency IDDAIRC32K(2) tSUIRC32K(2) (1) Conditions Min Typ Max Unit — 32 — kHz VDD = VDDA = 3.3 V — 0.31 — μA VDD = VDDA = 3.3 V — 26.9 — μs VDD = VDDA = 3.3 V, TA = -40 °C ~ +105 °C IRC32K oscillator operating current IRC32K oscillator startup time Guaranteed by design, not tested in production. 52 GD32VW553xx Datasheet (2) 4.9. Based on characterization, not tested in production. PLL characteristics Table 4-20. PLLDIG characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLIN(2) PLL input clock frequency — 19.2 40 52 MHz fPLLOUT(2) PLL output clock frequency — — — 480 MHz — — 960 — MHz fVCO(2) (1) (2) 4.10. PLL VCO output clock frequency tLOCK(1) PLL lock time — — — 50 μs IDDA(1) Current consumption — — 1.8 — mA JitterPLL(1) Absolute RMS Jitter XTAL freq = 40 MHz — 8 — ps Based on characterization, not tested in production. Guaranteed by design, not tested in production. Memory characteristics Table 4-21. Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit TA = -40 °C ~ +105 °C 100 — — kcycles Number of guaranteed PECYC(1) program /erase cycles before failure(Endurance) tRET(1) Data retention time — — 20 — years tPROG(2) word programming time TA = -40 °C ~ +105 °C — 1000 — μs tERASE(2) Page(3) erase time TA = -40 °C ~ +105 °C — 100 — ms tMERASE(2) Mass erase time TA = -40 °C ~ +105 °C — 12 — s (1) (2) (3) 4.11. Based on characterization, not tested in production. Guaranteed by design, not tested in production. 4KB. NRST pin characteristics Table 4-22. NRST pin characteristics Symbol VIL(NRST) (1) VIH(NRST) (1) Vhyst(1) VIL(NRST) (1) VIH(NRST) (1) Vhyst(1) VIL(NRST) Conditions Min Typ Max 0.3VDD — TBD TBD — 0.7VDD Schmidt trigger Voltage hysteresis — 370 — NRST Input low level voltage 0.3VDD — TBD TBD — 0.7VDD — 420 — 0.3VDD — TBD TBD — 0.7VDD NRST Input low level voltage NRST Input high level voltage NRST Input high level voltage VDD = VDDA = 1.8 V VDD = VDDA = 3.3 V Schmidt trigger Voltage hysteresis (1) VIH(NRST) Parameter (1) NRST Input low level voltage NRST Input high level voltage VDD = VDDA = 3.6 V Unit V mV V mV 53 V GD32VW553xx Datasheet Symbol Vhyst Rpu (1) (2) (1) Parameter Conditions Schmidt trigger Voltage hysteresis (2) — Pull-up equivalent resistor Min Typ Max Unit — 440 — mV — 40 — kΩ Based on characterization, not tested in production. Guaranteed by design, not tested in production. Figure 4-2. Recommended external NRST pin circuit VDD VDD Ext ernal reset circuit RPU 10 kΩ NRST K 100 nF GND 4.12. GPIO characteristics Table 4-23. I/O port DC characteristics (1)(3) Symbol Parameter Standard IO Low VIL level input voltage 5V-tolerant IO Low level input voltage Standard IO Low VIH level input voltage 5V-tolerant IO Low level input voltage VOL (IO_speed = MAX) VOL (IO_speed = MAX) VOH (IO_speed = MAX) VOH Low level output voltage for an IO Pin (IIO = +8 mA) Low level output voltage for an IO Pin (IIO = +20 mA) High level output voltage for an IO Pin (IIO = +8 mA) High level output Conditions Min Typ Max Unit 1.8 V ≤ VDD ≤ 3.6 V — — 0.3 VDD V 1.8 V ≤ VDD ≤ 3.6 V — — 0.3 VDD V 1.8 V ≤ VDD ≤ 3.6 V 0.7 VDD — — V 1.8 V ≤ VDD ≤ 3.6 V 0.7 VDD — — V VDD = 1.8V — 0.14 — V VDD = 2.7V — 0.11 — VDD = 3.3V — 0.10 — VDD = 3.6V — 0.10 — VDD = 1.8V — 0.41 — VDD = 2.7V — 0.27 — VDD = 3.3V — 0.25 — VDD = 3.6V — 0.25 — VDD = 1.8V — 1.59 — VDD = 2.7V — 2.56 — VDD = 3.3V — 3.17 — VDD = 3.6V — 3.47 — VDD = 1.8V — 1.17 — V V V V V V 54 GD32VW553xx Datasheet Symbol Parameter Conditions Min Typ Max (IO_speed = MAX) voltage for an IO Pin VDD = 2.7V — 2.32 — (IIO = +20 mA) VDD = 3.3V — 2.96 — VDD = 3.6V — 3.28 — VDD = 1.8V — 0.20 — VDD = 2.7V — 0.14 — VDD = 3.3V — 0.13 — VDD = 3.6V — 0.13 — VDD = 1.8V — 0.70 — VDD = 2.7V — 0.37 — VDD = 3.3V — 0.33 — VDD = 3.6V — 0.32 — VDD = 1.8V — 1.50 — VDD = 2.7V — 2.51 — VDD = 3.3V — 3.12 — VDD = 3.6V — 3.43 — VDD = 1.8V — 0.94 — VOL (IO_speed = 25 MHz) VOL (IO_speed = 25 MHz) VOH (IO_speed = 25 MHz) Low level output voltage for an IO Pin (IIO = +8 mA) Low level output voltage for an IO Pin (IIO = +20 mA) High level output voltage for an IO Pin (IIO = +8 mA) Unit V V V V V V V High level output voltage for an IO Pin VOH (IIO = +17 mA) (IO_speed = 25 MHz) High level output VDD = 2.7V — 2.16 — voltage for an IO Pin VDD = 3.3V — 2.83 — (IIO = +20 mA) VDD = 3.6V — 3.16 — VDD = 1.8V — 0.40 — VDD = 2.7V — 0.25 — VDD = 3.3V — 0.23 — VDD = 3.6V — 0.22 — VDD = 1.8V — 0.9 — VOL (IO_speed = 10 MHz) Low level output voltage for an IO Pin (IIO = +8 mA) V V V V Low level output voltage for an IO Pin VOL (IIO = +12 mA) (IO_speed = 10 MHz) Low level output VDD = 2.7V — 0.54 — voltage for an IO Pin VDD = 3.3V — 0.47 — (IIO = +16 mA) VDD = 3.6V — 0.46 — VDD = 1.8V — 1.21 — VDD = 2.7V — 2.36 — VDD = 3.3V — 3.00 — VDD = 3.6V — 3.32 — VDD = 1.8V — 0.88 — VOH (IO_speed = 10 MHz) High level output voltage for an IO Pin (IIO = +8 mA) V V V V High level output voltage for an IO Pin VOH (IIO = +10 mA) (IO_speed = 10 MHz) High level output VDD = 2.7V — 1.92 — voltage for an IO Pin VDD = 3.3V — 2.66 — (IIO = +16 mA) VDD = 3.6V — 3.00 — Low level output VDD = 1.8V — 0.22 — VOL V V V 55 GD32VW553xx Datasheet Symbol Parameter Conditions Min Typ Max VDD = 2.7V — 0.15 — VDD = 3.3V — 0.14 — VDD = 3.6V — 0.13 — VDD = 1.8V — 0.56 — Low level output VDD = 2.7V — 0.70 — voltage for an IO Pin VDD = 3.3V — 0.59 — VDD = 3.6V — 0.57 — VDD = 1.8V — 1.49 — VDD = 2.7V — 2.51 — VDD = 3.3V — 3.13 — VDD = 3.6V — 3.44 — VDD = 1.8V — 0.99 — (IO_speed = 2 MHz) voltage for an IO Pin (IIO = +1 mA) Unit V Low level output voltage for an IO Pin (IIO = +2 mA) VOL (IO_speed = 2 MHz) (IIO = +4 mA) VOH (IO_speed = 2 MHz) V High level output voltage for an IO Pin (IIO = +1 mA) V V V High level output voltage for an IO Pin VOH (IIO = +2 mA) (IO_speed = 2 MHz) High level output VDD = 2.7V — 1.73 — voltage for an IO Pin VDD = 3.3V — 2.55 — (IIO = +4 mA) VDD = 3.6V — 2.90 — All pins — — 40 — PU — — 10 — All pins — — 40 — PU — — 10 — Internal RPU (2) Internal RPD V kΩ pull-up resistor (2) V pull-down resistor kΩ (1) Based on characterization, not tested in production. (2) Guaranteed by design, not tested in production. (3) All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which can only be obtained by a small current(typical source capability:3 mA shared between these IOs, but sink capability is same as other IO), the speed of GPIOs PC13 to PC15 should not exceed 2 MHz when they are in output mode (maximum load: 30 pF). Table 4-24. I/O port AC characteristics (1)(2) GPIOx_MDy[1:0] bit value(3) Parameter GPIOx_CTL->MDy[1:0]=10 Maximum (IO_Speed = 2 MHz) frequency(4) GPIOx_CTL->MDy[1:0] = 01 Maximum (IO_Speed = 10 MHz) frequency(4) GPIOx_CTL->MDy[1:0]=11 Maximum (IO_Speed = 25 MHz) frequency(4) Conditions Max Unit 1.8 V ≤ VDD ≤ 3.6 V , CL = 10pF 3.47 1.8 V ≤ VDD ≤ 3.6 V , CL = 30pF 3.15 1.8 V ≤ VDD ≤ 3.6 V , CL = 50pF 2.77 1.8 V ≤ VDD ≤ 3.6 V , CL = 10pF 24.33 1.8 V ≤ VDD ≤ 3.6 V , CL = 30pF 20.41 MHz 1.8 V ≤ VDD ≤ 3.6 V , CL = 50pF 15.63 1.8 V ≤ VDD ≤ 3.6 V , CL = 10pF 142.45 1.8 V ≤ VDD ≤ 3.6 V , CL = 30pF 100.55 MHz 1.8 V ≤ VDD ≤ 3.6 V, CL = 50pF 48.38 MHz 56 GD32VW553xx Datasheet GPIOx_MDy[1:0] bit value(3) GPIOx_CTL->MDy[1:0]=11(IO_S peed = MAX) (1) (2) (3) (4) Parameter Maximum frequency(4) Conditions Max Unit 1.8 V ≤ VDD ≤ 3.6 V, CL = 10pF 246.91 1.8 V ≤ VDD ≤ 3.6 V , CL = 30pF 159.87 MHz 1.8 V ≤ VDD ≤ 3.6 V , CL = 50pF 117.79 Based on characterization, not tested in production. Unless otherwise specified, all test results given for TA = 25 ℃. The I/O speed is configured using the GPIOx_OSPD0->OSPDy [1:0] bits. Refer to the GD32VW553xx user manual which is selected to set the GPIO port output speed. The maximum frequency is defined in Figure 4-3, and maximum frequency cannot exceed 100 MHz. Figure 4-3. I/O port AC characteristics definition 90% EXTERNAL OUTPUT ON 50pF 90% 50% 50% 10% tr(IO)out 10% tf(IO)out T If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved. The duty cycle is (45%-55%) when loaded by 50 pF. 4.13. ADC characteristics Table 4-25. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA(2) Operating voltage — 1.62 3.3 3.6 V VIN(2) ADC input voltage range — 0 — VDDA V fADC(2) ADC clock(3) 2.4 V ≤ VDDA ≤ 3.6 V — — 42 1.62 V ≤ VDDA ≤ 2.4 V — — 14 fS(2) Sampling rate 12-bit 0.007 — 3 MSPS VAIN(2) Analog input voltage 9 external; 2 internal 0 — VDDA V RAIN(2) External input impedance See Equation 1 — — 178.8 kΩ — — — 0.2 kΩ — — 6.57 pF RADC(2) CADC(2) ts(2) Input sampling switch resistance MHz Input sampling No pin / pad capacitance capacitance included Sampling time fADC(3) = 42 MHz 0.036 — 11.42 μs 12-bit 14 — 492 1 / fADC — — — 1 μs Total conversion tCONV(2) time(including sampling time) tSU(2) (1) (2) (3) Startup time Based on characterization, not tested in production. Guaranteed by design, not tested in production. When the supply voltage of VDDA is 2.4V to 3.6V, the maximum frequency of fADC is 42 MHz, and when the supply voltage of VDDA is 1.62V to 2.4V, the maximum frequency of fADC is 14 MHz. 57 GD32VW553xx Datasheet Equation 1: RAIN max formula R AIN < Ts fADC *CADC *ln(2N+2 ) -R ADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 4-26. ADC RAIN max for fADC = 42 MHz (1) (1) Ts(cycles) ts(μs) RAINmax(kΩ) 1.5 0.036 0.36 2.5 0.06 0.73 14.5 0.345 5.21 27.5 0.655 10.07 55.5 1.32 20.52 83.5 1.99 30.9 111.5 2.655 41.44 143.5 3.416 53.39 479.5 11.42 178.8 Based on characterization, not tested in production. Table 4-27. ADC dynamic accuracy at f ADC = 42 MHz (1) Symbol Parameter Test conditions Min Typ Max Unit ENOB Effective number of bits fADC = 42 MHz, — 11 — bits Signal-to-noise and distortion ratio VDDA = 3.3 V, — 68.21 — Signal-to-noise ratio Input Frequency = 20 — 68.39 — — -81.5 — SNDR SNR kHz, THD (1) Total harmonic distortion Temperature = 25℃ dB Based on characterization, not tested in production. Table 4-28. ADC static accuracy at fADC = 42 MHz Symbol Parameter Offset Offset error DNL Differential linearity error INL Integral linearity error (1) 4.14. Test conditions Typ(1) Max fADC = 42 MHz, VDDA = 3.3 V ±1 — ±0.9 — ±1.1 — Unit LSB Based on characterization, not tested in production. Temperature sensor characteristics Table 4-29. Temperature sensor characteristics (1) Symbol Parameter Min Typ Max Unit TL VSENSE linearity with temperature — ±1 — ℃ Avg_Slope Average slope — 4.3 — mV/℃ V25 Voltage at 25 °C — 1.42 — V Startup time — 8 — μs ADC sampling time when reading the temperature — 13.7 — μs tSTART tS_temp (1) (2) (2) Based on characterization, not tested in production. Shortest sampling time can be determined in the application by multiple iterations. 58 GD32VW553xx Datasheet 4.15. I2C characteristics Table 4-30. I2C characteristics (1)(2)(3) Standard Symbol Parameter Conditions SCL clock high tSCL(H) time mode Fast mode Fast mode plus Unit Min Max Min Max Min Max — 4.0 — 0.6 — 0.2 — μs tSCL(L) SCL clock low time — 4.7 — 1.3 — 0.5 — μs tsu(SDA) SDA setup time — 250 — 100 — 50 — ns — 0(3) 3450 0 900 0 450 ns — — 1000 — 300 — 120 ns — — 300 3(4)(5) 300 3(4)(6) 120 ns — 4.0 — 0.6 — 0.26 — μs — 4.7 — 0.6 — 0.26 — μs — 4.0 — 0.6 — 0.26 — μs — 4.7 — 1.3 — 0.5 — μs th(SDA) SDA data hold time SDA and SCL rise tr(SDA/SCL) time SDA and SCL fall tf(SDA/SCL) time Start condition hold th(STA) time Repeated Start ts(STA) condition setup time Stop condition ts(STO) setup time Stop to Start tbuff condition time (bus free) (1) (2) (3) (4) (5) (6) Guaranteed by design, not tested in production. To ensure the standard mode I2C frequency, fPCLK1 must be at least 2 MHz. To ensure the fast mode I2C frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode plus I2C frequency, f PCLK1 must be at least a multiple of 10 MHz. The external device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the falling edge of SCL. Based on characterization, not tested in production. In the condition of I2C frequency = 400 kHz, IO_Speed = 50 MHz and Pull-up resistor = 1 kΩ. In the condition of I2C frequency = 1 MHz, IO_Speed = 50 MHz and Pull-up resistor = 1 kΩ. Figure 4-4. I2C bus timing diagram tsu(STA) SDA 70% 30% tf(SDA) tr(SDA) tSCL(H) th(STA) SCL tbuff th(SDA) tsu(SDA) 70% 30% tSCL(L) tr(SCL) tf(SCL) tsu(STO) 59 GD32VW553xx Datasheet 4.16. SPI characteristics Table 4-31. Standard SPI characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency — — — 40 MHz tSCK(H) SCK clock high time 12.5 14.5 ns 12.5 14.5 ns Master mode, fPCLKx = 160 MHz, 10.5 presc = 4 tSCK(L) Master mode, fPCLKx = 160 MHz, 10.5 SCK clock low time presc = 4 SPI master mode tV(MO) Data output valid time — — — TBD ns tSU(MI) Data input setup time — 4.4 — — ns Data input hold time — 0 — — ns tH(MI) SPI slave mode (1) tSU(NSS) NSS enable setup time — 0 — — ns tH(NSS) NSS enable hold time — 2.3 — — ns tA(SO) Data output access time — — TBD — ns tDIS(SO) Data output disable time — — TBD — ns tV(SO) Data output valid time — — TBD — ns tSU(SI) Data input setup time — 0 — — ns tH(SI) Data input hold time — 1.6 — — ns Based on characterization, not tested in production. Figure 4-5. SPI timing diagram - master mode tSCK SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) tSCK(H) tSCK(L) SCK (CKPH=1 CKPL=1) tSU(MI) MISO D[0] LF=1,FF16=0 D[7] tH(MI) MOSI D[0] D[7] tV(MO) tH(MO) 60 GD32VW553xx Datasheet Figure 4-6. SPI timing diagram - slave mode NSS tSCK tSU(NSS) SCK (CKPH=0 CKPL=0) tSCK(H) SCK (CKPH=0 CKPL=1) tSCK(L) tH(NSS) tH(SO) tDIS(SO) tV(SO) tA(SO) MISO D[0] D[7] tSU(SI) D[0] MOSI D[7] tH(SI) 4.17. USART characteristics Table 4-32. USART characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency fPCLKx = 80MHz — — 40 MHz tSCK(H) SCK clock high time fPCLKx = 80 MHz 12.50 — — ns tSCK(L) SCK clock low time fPCLKx =80 MHz 12.50 — — ns (1) 4.18. Guaranteed by design, not tested in production. TIMER characteristics Table 4-33. TIMER characteristics (1) Symbol Parameter tres Timer resolution time fEXT Conditions Min Max Unit — 1 — tCK_TIMERx fCK_TIMERx = 160 MHz 6.25 — ns Timer external clock — 0 fTIMERxCLK/2 MHz frequency fCK_TIMERx = 160 MHz 0 80 MHz TIMERx except RES Timer resolution 16-bit counter clock period tCOUNTER when internal clock is selected (TIMER1& TIMER2) — 16 bit TIMER1& TIMER2 — 32 — 1 65536 0.00625 409.6 fCK_TIMERx = 160 MHz tCK_TIMERx μs 61 GD32VW553xx Datasheet Symbol Parameter Conditions Min 32-bit counter clock period — 1 fCK_TIMERx = 160 MHz — — — fCK_TIMERx = 160 MHz — when internal clock is selected tMAX_COUNT (1) 4.19. Maximum possible count (32-bit) Max Unit 65536 × 65536 tCK_TIMERx 26.84 65536 × 65536× 65536 s tCK_TIMERx 488.6 s Guaranteed by design, not tested in production. WDGT characteristics Table 4-34. FWDGT min/max timeout period at 32 kHz (IRC32K) Min timeout Max timeout RLD[11:0] =0x000 RLD[11:0] = 0xFFF 000 0.03125 511.90625 1/8 001 0.03125 1023.78125 1/16 010 0.03125 2047.53125 1/32 011 0.03125 4095.03125 1/64 100 0.03125 8190.03125 1/128 101 0.03125 16380.03125 1/256 110 or 111 0.03125 32760.03125 Prescaler divider PSC[2:0] bits 1/4 (1) (1) Unit ms Guaranteed by design, not tested in production. Table 4-35. WWDGT min-max timeout value at 40 MHz (fPCLK1) (1) PSC[2:0] 1/1 00 102.4 1/2 01 204.8 1/4 10 409.6 1/8 11 819.2 (1) 4.20. Min timeout value Prescaler divider CNT[6:0] = 0x40 Unit Max timeout value CNT[6:0] = 0x7F Unit 6.55 μs 13.10 ms 26.21 52.42 Guaranteed by design, not tested in production. Wi-Fi Radio characteristics Below data are measured at GD32VW553xx RF pin. Table 4-36. Transmitter power characteristics (1)(2) Parameter Tx Power Rate Typ 11b,1Mbps 22.3 11b,11Mbps 22.3 11g,6Mbps 20.9 11g,54Mbps 18.7 11n,HT20,MCS0 20.3 Unit dBm 62 GD32VW553xx Datasheet Parameter (1) (2) Rate Typ 11n,HT20,MCS7 18 11ax,HE20,MCS0 20.8 11ax,HE20,MCS9 15.6 Unit Tx Power level is Limited by 802.11 Mask & EVM spec. Based on characterization, not tested in production. Table 4-37. Receiver sensitivity characteristics (1) Parameter Rx Sensitivity Rate Typ 11b,1Mbps -100.3 11b,2Mbps -96.9 11b,5.5Mbps -94.8 11b,11Mbps -91.8 11g,6Mbps -95.2 11g,9Mbps -94.5 11g,12Mbps -93.4 11g,18Mbps -90.5 11g,24Mbps -87.8 11g,36Mbps -84.8 11g,48Mbps -80 11g,54Mbps -78.7 11n,HT20,MCS0 -95.1 11n,HT20,MCS1 -92.6 11n,HT20,MCS2 -90.3 11n,HT20,MCS3 -87.2 11n,HT20,MCS4 -83.9 11n,HT20,MCS5 -79.5 11n,HT20,MCS6 -77.9 11n,HT20,MCS7 -76.2 11ax,HE20,MCS0 -94.9 11ax,HE20,MCS1 -92.1 11ax,HE20,MCS2 -89.7 11ax,HE20,MCS3 -86.3 11ax,HE20,MCS4 -83.2 11ax,HE20,MCS5 -78.7 11ax,HE20,MCS6 -77.5 11ax,HE20,MCS7 -76.2 11ax,HE20,MCS8 -71.5 11ax,HE20,MCS9 -69.7 11ax,HE20,MCS0-DCM -95.1 11ax,HE20,MCS1-DCM -94.6 11ax,HE20,MCS3-DCM -89.9 11ax,HE20,MCS4-DCM -86.8 Unit dBm 63 GD32VW553xx Datasheet Parameter (1) Rate Typ Unit 11ax,HE20,MCS0-ER -95.6 11ax,HE20,MCS0-ER-106 -96.5 11ax,HE20,MCS0-ER-DCM -96.5 11ax,HE20,MCS0-ER-DCM-106 -96.7 11ax,HE20,MCS1-ER -92.6 11ax,HE20,MCS1-ER-DCM -95.2 11ax,HE20,MCS2-ER -90.1 Based on characterization, not tested in production. Table 4-38. Rx Maximum Input Level (1) Parameter Rx Maximum Level Input (1) Rate Typ Unit 11b,1Mbps >8.5 11b,11Mbps >8.5 11g,6Mbps >8.5 11g,54Mbps TBD 11n,HT20,MCS0 >8.5 11n,HT20,MCS7 TBD 11ax,HE20,MCS0 >8.5 11ax,HE20,MCS9 TBD dBm Based on characterization, not tested in production. Table 4-39. Adjacent Channel Rejection (1)(4) Typ Parameter Interference pattern Rate by IQxel(2) interference 45 TBD 11g, 6Mbps 30 TBD 11g, 54Mbps 11.5 TBD 11n, HT20,MCS0 27 TBD 11n,HT20,MCS7 10 TBD 11ax,HE20,MCS0 25 TBD 11ax,HE20,MCS9 -0.5 TBD Rejection Unit pattern(3) 11b, 11Mbps Adjacent Channel 4.21. In-house (1) (2) (3) ACR result depends on interference source. Waveform generated by LitePoint IQxel series instrument, gap = SIFS Waveform generated by GD32VW553xx baseband, gap = SIFS (4) Based on characterization, not tested in production. dB Bluetooth LE Radio characteristics Table 4-40. Transmitter Characteristics - Bluetooth LE 1 Mbps Parameter Conditions RF transmit power RF power control range Min -30 Typ Max Unit 5 15 dBm 64 GD32VW553xx Datasheet Gain control step — 1 — dB Max |fn|n=0, 1, 2, ..k — 0.89 — kHz Carrier frequency Max |f0 − fn| — 1.53 — kHz offset and drift Max |fn − fn−5| — 0.74 — kHz |f1 − f0| — 0.85 — kHz ∆ f1avg — 250.61 — kHz — 216.5 — kHz ∆ f2avg/∆ f1avg — 0.88 — — ±2 MHz offset — -47 — dBm ±3 MHz offset — -50 — dBm >±3 MHz offset — -51 — dBm Modulation Min ∆f2max (for at least characteristics 99.9% of all ∆f2max) In-band spurious emissions Table 4-41. Transmitter Characteristics - Bluetooth LE 2 Mbps Parameter RF transmit power Conditions Min Typ Max -30 5 15 dBm Gain control step — 1 — dB Max |fn|n=0, 1, 2, ..k — 1.06 — kHz RF power control range Unit Carrier frequency offset Max |f0 − fn| — 1.58 — kHz and drift Max |fn − fn−5| — 0.78 — kHz |f1 − f0| — 0.72 — kHz ∆ f 1avg — 499.8 — kHz — 436 — kHz ∆ f2avg/∆ f1avg — 0.89 — — ±4 MHz offset — -48 — dBm ±5 MHz offset — -51 — dBm >±5 MHz offset — -53 — dBm Modulation Min ∆f2max (for at least characteristics 99.9% of all ∆f2max) In-band spurious emissions Table 4-42. Transmitter Characteristics - Bluetooth LE 125 Kbps Parameter RF transmit power Carrier frequency offset and drift Modulation characteristics Conditions Min Typ Max Unit -30 5 15 dBm Gain control step — 1 — dB Max |fn|n=0, 1, 2, ..k — 0.47 — kHz Max |f0 − fn| — 1.55 — kHz |fn − fn−3| — 1.19 — kHz ∆f1avg — 251.38 — kHz — 248.18 — kHz RF power control range Min ∆f1max (for at least 99.9% of all ∆f1max) Table 4-43. Receiver Characteristics - Bluetooth LE 1 Mbps Parameter Conditions Min Typ Max Unit Sensitivity @30.8% — — -100.5 — dBm 65 GD32VW553xx Datasheet Parameter Conditions Min Typ Max Unit — — 10 — dBm — — 9 — dB F = F0 + 1 MHz — -2 — dB F = F0 – 1 MHz — -4 — dB F = F0 + 2 MHz — -31 — dB Adjacent channel F = F0 – 2 MHz — -36 — dB selectivity C/I F = F0 + 3 MHz — -37 — dB F = F0 – 3 MHz — -44 — dB F ≥ F0 + 4 MHz — -37 — dB F ≤ F0 – 4 MHz — -56 — dB Image frequency + 4 MHz — -37 — dB Adjacent channel to F = Fimage + 1 MHz — -47 — dB image frequency F = Fimage - 1 MHz — -37 — dB 30 MHz ~ 2000 MHz — -5.5 — dBm Out-of-band blocking 2003 MHz ~ 2399 MHz — -8.5 — dBm performance 2484 MHz ~ 2997 MHz — -7.5 — dBm 3000 MHz ~ 12.75 GHz — -5.5 — dBm — — -27 — dBm PER Maximum received signal @30.8% PER Co-channel C/I Intermodulation Table 4-44. Receiver Characteristics - Bluetooth LE 2 Mbps Parameter Conditions Min Typ Max Unit — — -97.5 — dBm — — 10 — dBm — — 8 — dB F = F0 + 2 MHz — -4 — dB F = F0 – 2 MHz — -7 — dB F = F0 + 4 MHz — -35 — dB Adjacent channel F = F0 – 4 MHz — -48 — dB selectivity C/I F = F0 + 6 MHz — -45 — dB F = F0 – 6 MHz — -53 — dB F ≥ F0 + 8 MHz — -53 — dB F ≤ F0 – 8 MHz — -55 — dB Image frequency + 4 MHz — -35 — dB Adjacent channel to F = Fimage + 2 MHz — -45 — dB image frequency F = Fimage - 2 MHz — -4 — dB 30 MHz ~ 2000 MHz — -5.5 — dBm 2003 MHz ~ 2399 MHz — -18.5 — dBm 2484 MHz ~ 2997 MHz — -15.5 — dBm Sensitivity @30.8% PER Maximum received signal @30.8% PER Co-channel C/I Out-of-band blocking performance 66 GD32VW553xx Datasheet Parameter Intermodulation Conditions Min Typ Max Unit 3000 MHz ~ 12.75 GHz — -15.5 — dBm — — -27 — dBm Table 4-45. Receiver Characteristics - Bluetooth LE 125 Kbps Parameter Conditions Min Typ Max Unit — — -107.5 — dBm — — 10 — dBm — — 2 — dB F = F0 + 1 MHz — -14 — dB F = F0 – 1 MHz — -14 — dB F = F0 + 2 MHz — -30 — dB Adjacent channel F = F0 – 2 MHz — -34 — dB selectivity C/I F = F0 + 3 MHz — -32 — dB F = F0 – 3 MHz — -46 — dB F ≥ F0 + 4 MHz — -42 — dB F ≤ F0 – 4 MHz — -65 — dB Image frequency + 4 MHz — -42 — dB Adjacent channel to F = Fimage + 1 MHz — -53 — dB image frequency F = Fimage - 1 MHz — -32 — dB Sensitivity @30.8% PER Maximum received signal @30.8% PER Co-channel C/I Table 4-46. Receiver Characteristics - Bluetooth LE 500 Kbps Parameter Conditions Min Typ Max Unit — — -102 — dBm — — 10 — dBm — — 5 — dB F = F0 + 1 MHz — -9 — dB F = F0 – 1 MHz — -10 — dB F = F0 + 2 MHz — -29 — dB Adjacent channel F = F0 – 2 MHz — -32 — dB selectivity C/I F = F0 + 3 MHz — -32 — dB F = F0 – 3 MHz — -46 — dB F ≥ F0 + 4 MHz — -39 — dB F ≤ F0 – 4 MHz — -61 — dB Image frequency + 4 MHz — -39 — dB Adjacent channel to F = Fimage + 1 MHz — -52 — dB image frequency F = Fimage - 1 MHz — -32 — dB Sensitivity @30.8% PER Maximum received signal @30.8% PER Co-channel C/I 67 GD32VW553xx Datasheet 4.22. Parameter conditions Unless otherwise specified, all values given for VDD = VDDA = AVDD33_ANA = AVDD33_PA = AVDD33_CLK = 3.3 V, TA = 25 ℃. 68 GD32VW553xx Datasheet 5. Package information 5.1. QFN40 package outline dimensions Figure 5-1. QFN40 package outline D2 L D 40 1 1 PIN 1 Laser Mark Ne E2 2 E 2 h h 40 K DETAIL A b e Nd TOP VIEW EXPOSED THERMAL PAD ZONE c A1 A b1 BOTTOM VIEW SIDE VIEW DETAIL A Table 5-1. QFN40 package dimensions Symbol Min Typ Max A 0.70 0.75 0.80 A1 — 0.02 0.05 b 0.15 0.20 0.25 b1 — 0.14 — c 0.18 0.20 0.25 D 4.90 5.00 5.10 D2 3.30 3.40 3.50 E 4.90 5.00 5.10 E2 3.30 3.40 3.50 e — 0.40 — h 0.30 0.35 0.40 K 0.20 — — L 0.35 0.40 0.45 Nd — 3.60 — Ne — 3.60 — (Original dimensions are in millimeters) 69 GD32VW553xx Datasheet Figure 5-2. QFN40 recommended footprint 5.70 31 40 4.10 1 0.125 3.85 5.70 3.35 0.25 30 3.35 10 11 20 21 0.40 0.80 (Original dimensions are in millimeters) 70 GD32VW553xx Datasheet QFN32 package outline dimensions Figure 5-3. QFN32 package outline D2 eee C A B b1 32 L 32 eee C A B D A 1 h 1 PIN 1# (Lasermark) 2 K E2 Ne h E 2 2X aaa C 2X aaa b e B C Nd TOP VIEW BOTTOM VIEW ddd M C A B EXPOSED THERMAL PAD ZONE A bbb C C A1 ccc c 5.2. C SIDE VIEW Table 5-2. QFN32 package dimensions Symbol Min Typ Max A 0.80 0.85 0.90 A1 0 0.02 0.05 b 0.15 0.20 0.25 b1 — 0.14 — c — 0.152 — D 3.90 4.00 4.10 D2 2.60 2.70 2.80 E 3.90 4.00 4.10 E2 2.60 2.70 2.80 e — 0.40 — h 0.30 0.35 0.40 K — 0.35 — L 0.25 0.30 0..35 Nd — 2.80 — Ne — 2.80 — aaa — 0.10 — bbb — 0.10 — ccc — 0.08 — ddd — 0.10 — eee — 0.10 — (Original dimensions are in millimeters) 71 GD32VW553xx Datasheet Figure 5-4. QFN32 recommended footprint 4.70 25 32 3.30 R 0.125 1 3.05 4.70 2.65 0.25 24 2.65 8 16 9 17 0.70 0.40 (Original dimensions are in millimeters) 72 GD32VW553xx Datasheet 5.3. Thermal characteristics Thermal resistance is used to characterize the thermal performance of the package device, which is represented by the Greek letter “θ”. For semiconductor devices, thermal resistance represents the steady-state temperature rise of the chip junction due to the heat dissipated on the chip surface. θJA: Thermal resistance, junction-to-ambient. θJB: Thermal resistance, junction-to-board. θJC: Thermal resistance, junction-to-case. ᴪJB: Thermal characterization parameter, junction-to-board. ᴪJT: Thermal characterization parameter, junction-to-top center. θJA =(TJ -TA )/PD (5-1) θJB =(TJ -TB )/PD (5-2) θJC =(TJ -TC )/PD (5-3) Where, TJ = Junction temperature. TA = Ambient temperature TB = Board temperature TC = Case temperature which is monitoring on package surface PD = Total power dissipation θJA represents the resistance of the heat flows from the heating junction to ambient air. It is an indicator of package heat dissipation capability. Lower θJA can be considerate as better overall thermal performance. θJA is generally used to estimate junction temperature. θJB is used to measure the heat flow resistance between the chip surface and the PCB board. θJC represents the thermal resistance between the chip surface and the package top case. θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat dissipation methods outside the device package). Table 5-3. Package thermal characteristics(1) Symbol Condition θJA Natural convection, 2S2P PCB θJB Cold plate, 2S2P PCB θJC Cold plate, 2S2P PCB Package Value QFN40 47.85 QFN32 51.44 QFN40 17.97 QFN32 18.71 QFN40 16.85 Unit °C/W °C/W °C/W 73 GD32VW553xx Datasheet Symbol Condition ᴪJB Natural convection, 2S2P PCB ᴪJT Natural convection, 2S2P PCB Package Value QFN32 21.85 QFN40 18.15 QFN32 17.69 QFN40 1.55 QFN32 0.99 Unit °C/W °C/W (1): Thermal characteristics are based on simulation, and meet JEDEC specification. 74 GD32VW553xx Datasheet 6. Ordering information Table 6-1. Part ordering code for GD32VW553xx devices Ordering code Flash (KB) Package Package type GD32VW553HMQ7 4096 QFN40 Green GD32VW553HMQ6 4096 QFN40 Green GD32VW553HIQ7 2048 QFN40 Green GD32VW553HIQ6 2048 QFN40 Green GD32VW553KMQ7 4096 QFN32 Green GD32VW553KMQ6 4096 QFN32 Green GD32VW553KIQ7 2048 QFN32 Green GD32VW553KIQ6 2048 QFN32 Green Temperature operating range Industrial -40 °C to +105 °C Industrial -40 °C to +85 °C Industrial -40 °C to +105 °C Industrial -40 °C to +85 °C Industrial -40 °C to +105 °C Industrial -40 °C to +85 °C Industrial -40 °C to +105 °C Industrial -40 °C to +85 °C 75 GD32VW553xx Datasheet 7. Revision history Table 7-1. Revision history Revision No. Description Date 1.0 Initial Release Oct. 13, 2023 1.1 1. Update the flash size of GD32VW553HMQ6 in Table 2-1. GD32VW553xx devices features and peripheral list. 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