FC4150F1MBS

FC4150F1M_B Data Sheet Rev. A0 FC4150F1M_B Data Sheet Table of Contents Table of Contents ............................................................................................................................................... 2 Chapter 1 Introduction ....................................................................................................................................... 7 1.1 Part Ordering .................................................................................................................................................... 7 1.1.1 1.1.2 1.2 1.3 Ordering Information................................................................................................................................... 7 Orderable Part Number ............................................................................................................................... 7 Marking Rule..................................................................................................................................................... 8 Abbreviations ................................................................................................................................................... 8 Chapter 2 Features ........................................................................................................................................... 11 Chapter 3 General ............................................................................................................................................. 14 3.1 Absolute Maximum Ratings........................................................................................................................... 14 3.3 Thermal Operating Condition ....................................................................................................................... 15 3.2 3.4 3.5 3.6 3.7 3.8 3.9 Operation Condition ...................................................................................................................................... 14 Clock Operating Condition ............................................................................................................................ 15 LVR, LVD, HVD, and POR Operating Requirements ...................................................................................... 16 Power Mode Transition ................................................................................................................................. 17 Chip IDD .......................................................................................................................................................... 17 PMC Internal LDO ........................................................................................................................................... 18 ESD Ratings .................................................................................................................................................... 19 Chapter 4 I/O Parameter ................................................................................................................................... 20 4.1 4.2 IO DC Specification ........................................................................................................................................ 20 IO AC Specification......................................................................................................................................... 21 Chapter 5 Clock Specification ........................................................................................................................... 22 5.1 FOSC Specification ........................................................................................................................................ 22 5.3 FIRC96M Specification ................................................................................................................................... 23 5.2 5.4 5.5 5.6 SOSC Specification ........................................................................................................................................ 23 SIRC12M Specification ................................................................................................................................... 23 SIRC32k Specification .................................................................................................................................... 24 PLL0 Specification ......................................................................................................................................... 24 2 FC4150F1M_B Data Sheet Chapter 6 Non-Volatile Memory (NVM) ............................................................................................................. 25 6.1 NVM Retention ............................................................................................................................................... 25 6.3 NVM Max Read Timing ................................................................................................................................... 25 6.2 NVM Program/Erase Time ............................................................................................................................. 25 Chapter 7 Analog .............................................................................................................................................. 26 7.1 7.2 12-bit SAR ADC ............................................................................................................................................... 26 CMP Specification .......................................................................................................................................... 27 Chapter 8 Peripherals ....................................................................................................................................... 28 8.1 8.2 FCSPI Specification ........................................................................................................................................ 28 OSPI Specification ......................................................................................................................................... 34 Chapter 9 Debug Modules ................................................................................................................................. 36 9.1 SWD Specification .......................................................................................................................................... 36 9.3 JTAG Interface ................................................................................................................................................ 37 9.2 Trace Block ..................................................................................................................................................... 37 Chapter 10 Package .......................................................................................................................................... 39 10.1 10.2 Thermal Data.................................................................................................................................................. 39 Package Dimension ....................................................................................................................................... 40 Chapter 11 Pinout ............................................................................................................................................. 43 Revision History ................................................................................................................................................ 55 3 FC4150F1M_B Data Sheet List of Figures Figure 1. Ordering information ....................................................................................................................................... 7 Figure 2. FC4150F1M_B block diagram ........................................................................................................................ 11 Figure 3. Crystal connection diagram ........................................................................................................................... 22 Figure 4. FCSPI master mode timing (SCK_PHA=0) ..................................................................................................... 28 Figure 5. FCSPI master mode timing (SCK_PHA=1) ..................................................................................................... 28 Figure 6. FCSPI slave mode timing (SCK_PHA=0) ........................................................................................................ 29 Figure 7. FCSPI slave mode timing (SCK_PHA=1) ........................................................................................................ 29 Figure 8. OSPI SDR/DDR in mode .................................................................................................................................. 34 Figure 9. OSPI SDR/DDR out mode ............................................................................................................................... 34 Figure 10. HyperRAM mode ........................................................................................................................................... 35 Figure 11. SWD clock timing diagram ........................................................................................................................... 36 Figure 12. SWD data timing diagram ............................................................................................................................ 36 Figure 13. Trace block timing diagram ......................................................................................................................... 37 Figure 14. JTAG clock timing diagram .......................................................................................................................... 37 Figure 15. Boundary timing diagram ............................................................................................................................ 37 Figure 16. JTAG TAP timing diagram ............................................................................................................................ 38 Figure 17. 144LQFP package ......................................................................................................................................... 40 Figure 18. 100LQFP package ......................................................................................................................................... 41 Figure 19. 64LQFP package ........................................................................................................................................... 42 Figure 20. 144LQFP pinout ............................................................................................................................................ 43 Figure 21. 100LQFP pinout ............................................................................................................................................ 44 Figure 22. 64LQFP pinout .............................................................................................................................................. 44 4 FC4150F1M_B Data Sheet List of Tables Table 1. Absolute maximum ratings ............................................................................................................................. 14 Table 2. Operating requirements .................................................................................................................................. 14 Table 3. Thermal operating condition .......................................................................................................................... 15 Table 4. Max. functional clock of modules ................................................................................................................... 15 Table 5. LVR/LVD/HVD and POR .................................................................................................................................... 16 Table 6. Power mode transition time ........................................................................................................................... 17 Table 7. Chip RUN IDD ................................................................................................................................................... 17 Table 8. Chip low power IDD ......................................................................................................................................... 18 Table 9. V25 LDO specification ...................................................................................................................................... 18 Table 10. Core LDO specification .................................................................................................................................. 18 Table 11. ESD ratings ..................................................................................................................................................... 19 Table 12. 3V IO DC specification .................................................................................................................................... 20 Table 13. 5V IO DC specification .................................................................................................................................... 20 Table 14. 3V IO AC specification .................................................................................................................................... 21 Table 15. 5V IO AC specification .................................................................................................................................... 21 Table 16. FOSC specification ......................................................................................................................................... 22 Table 17. SOSC specification......................................................................................................................................... 23 Table 18. FIRC96M specification ................................................................................................................................... 23 Table 19. SIRC12M specification ................................................................................................................................... 23 Table 20. SIRC32k specification .................................................................................................................................... 24 Table 21. PLL0 specification .......................................................................................................................................... 24 Table 22. NVM retention specification .......................................................................................................................... 25 Table 23. NVM program/erase time .............................................................................................................................. 25 Table 24. ADC specification ........................................................................................................................................... 26 Table 25. CMP specification .......................................................................................................................................... 27 Table 26. FCSPI 3V specification ................................................................................................................................... 30 Table 27. FCSPI 5V specification ................................................................................................................................... 32 Table 28. OSPI timing .................................................................................................................................................... 34 5 FC4150F1M_B Data Sheet Table 29. SWD electrical specification .......................................................................................................................... 36 Table 30. Trace block electrical specification .............................................................................................................. 37 Table 31. JTAG electrical specification ......................................................................................................................... 38 Table 32. Thermal package simulation data ................................................................................................................ 39 Table 33. FC4150F1M_B pin functions .......................................................................................................................... 45 6 FC4150F1M_B Data Sheet Chapter 1 Introduction This data sheet provides the ordering information, electrical specifications, package information, and pinout data of the Flagchip FC4150F1M_B microcontroller (MCU). 1.1 Part Ordering 1.1.1 Ordering Information The ordering of the Flagchip MCU follows the rules below. For detailed part information, refer to the Flagchip company. Figure 1. Ordering information Note: 1. 2. 1.1.2 Not all part number combinations are available. The technical information for 64LQFP devices in the data sheet is preliminary until this package option achieves qualification. Orderable Part Number Refer to the attached FC4150F1M_B_Orderable_Part_Number_List_A0.xlsx for a list of standard orderable part numbers. 7 1.2 Marking Rule FC4150F1M_B Data Sheet The followings are the schematic diagram and the picture of a FC4150F1M_B chip. Marking rules of the FC4150F1M_B are listed in the table below. Row Step 2 1 1 3 4 4 4 Content 1 logo (LL006758.LOG) 1 XXXXXXXXXXX 1 2 Logo Fixed/Dynamic Fixed Align Center XXXXXXXXXXX Part number Dynamic Center YYWW Date code Dynamic Left FGXX 3 Description X Part number Dynamic Lot schedule number Engineering information Dynamic Optional Center Left Left 1.3 Abbreviations The following abbreviations are used in this document. No. Abbreviation Description 2. AFCB Advanced Flagchip Bus (APB Bridge) 1. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. ADC AONTIMER Analog-to-Digital Converter Always-on Timer APB Advanced Peripheral Bus CAN Controller Area Network CGC Clock Gating Control AVB CBC CRC CORDIC Audio Video Bridging Cipher Block Chaining Cyclic Redundancy Check Coordinate Rotation Digital Computer DAC Digital-to-Analog Converter DP Debug Port DMA DSP DWT ECB ECC Direct Memory Access Digital Signal Processing Data Watchpoint and Trace Electronic Codebook Book Error Correction Code 8 No. Abbreviation FC4150F1M_B Data Sheet Description 18. ERM 20. FCIIC Flagchip (FC) Inter-Integrated Circuit FCSPI Flagchip (FC) Serial Peripheral Interface FIRC Fast Internal Reference Clock 19. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. ESD FCPIT FCUART FMC Error Reporting Module Electrostatic Discharge Flagchip (FC) Programmable Interrupt Timer Flagchip (FC) Universal Asynchronous Receiver Transmitter Flash Memory Controller FOSC Fast Oscillator FPM Full Performance Mode FREQM Frequency Measurement FPB FPU Flash Patch and Breakpoint Floating Point Unit FTU Flexible Timer Unit GPIO General-Purpose Input/Output FWM HMI Function Safety Watchdog Monitor Human-Machine Interface HSM Hardware Secure Module IIC/I2C Inter-Integrated Circuit HVD High-Voltage Detect IRC Internal Reference Cock ITM Instrumentation Trace Macrocell ISM Interface Safety Monitor LDO Low Dropout LVD Low-Voltage Detect MAP Memory Access Protection NMI Non-maskable Interrupt OSC Oscillator PCC Peripheral Clock Controller LIN LVR MPU NVM OSPI PIT PLL PMC Local Interconnect Network Low-Voltage Reset Memory Protection Unit Non-Volatile Memory Octal Serial Peripheral Interface Programmable Interrupt Timer Phase-Locked Loop Power Management Controller POR Power-on Reset RCM Reset Control Module PWM RPM Pulse Width Modulation Reduce Power Mode 9 No. Abbreviation 59. RTC 61. SCG 60. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. SAR SIRC FC4150F1M_B Data Sheet Description Real-Time Clock Successive Approximation System Clock Generator Slow Internal Reference Clock SOSC Slow Oscillator SWD Serial Wire Debug SPI SWJ-DP TAP TCM TPIU Serial Peripheral Interface Serial Wire/JTAG Debug Port Test Access Port Tightly-Coupled Memory Trace Port Interface Unit TRGSEL Trigger Select UART Universal Asynchronous Receiver and Transmitter TSTMP VCO WDOG WKU Timer Stamp Voltage-Controlled Oscillator Watchdog Wake-up Unit 10 Chapter 2 Features FC4150F1M_B Data Sheet This chapter summarizes the FC4150F1M_B features. For detailed information, refer to the Reference Manual. Figure 2. FC4150F1M_B block diagram ARM Cortex-M� @ ���MHz FPU/DSP DMA Debug �K CACHE Up to � MB + ��� KB Flash Up to ��� KB SRAM ��� KB ROM OSPI LQFP ��/���/��� � x PWM � x SPI OSC � x UART CRC Timers � x WDOG ISM � x IIC CMP � x CAN* PLL FIRC � x ADC ECC TRGSEL GPIO MAP � x CMU PMC RTC � x TSTMP CORDIC ASIL-B HSM_Lite * Optional CAN FD support Note: Not all features in this block diagram are available on all parts, refer to the Reference Manual for details. Operating Environment • Voltage range: 3.0 V to 5.5 V – – Arm Cortex-M4F Core • – – – – – Ambient temperature (TA) range: - 40°C to + 125°C; junction temperature (TJ) range: - 40°C to + 150°C 150 MHz frequency with 2.66 Dhrystone MIPS per MHz Armv7 Architecture and Thumb-2 ISA Digital Signal Processing (DSP) instruction Single-Precision Floating Point Unit (FPU) Support Memory Protection Unit (MPU) with 8 regions CORDIC accelerator for mathematical operations such as angles • 16-channel Direct Memory Access (DMA) with selected DMA source • Clock Sources • – – – – – 16 ~ 48 MHz Fast Oscillator (FOSC) with up to 50 MHz DC external input clock in bypass mode 32 kHz Slow Oscillator (SOSC) 96 MHz Fast Internal RC Oscillator (FIRC96M) 12 MHz Slow Internal RC Oscillator (SIRC12M) 32 kHz Slow Internal RC Oscillator (SIRC32k) – Up to 200 MHz Phased Lock Loop (PLL0) with reference from FIRC48M or FOSC – Four power modes: RUN, WAIT, STOP and Standby. Optional 64 KB RAM retention in standby mode. – Up to 1 MB program flash memory with Error Correction Code (ECC) Power Management • Memory • – – Up to 128 KB data flash memory with ECC Up to 128 KB SRAM with ECC 11 8 KB instruction cache for Flash – FC4150F1M_B Data Sheet Octal Serial Peripheral Interface (OSPI) with up to 50 MHz DDR support (Refer to Table 27. OSPI timing in Section – – 8.2 OSPI Electrical Specification for details.) 128 KB ROM with CM4 core self-test/Flash program & erase/ Secure Boot & ISP Analog • Two 12-bit Successive Approximation (SAR) Analog-to-Digital Converters (ADCs) with up to 32 channel analog – inputs per module One Analog Comparator (CMP) with internal 8-bit Digital-to-Analog Converter (DAC) – Debug Functionality • Serial Wire/JTAG Debug Port (SWJ-DP) combines – Data Watchpoint and Trace (DWT) – Instrumentation Trace Macrocell (ITM) – Trace Port Interface Unit (TPIU) – Flash Patch and Breakpoint (FPB) Unit – JTAG Test Access Port (TAP) and boundary scan support – • – Human-Machine Interface (HMI) Up to 124 GPIO pins with interrupt support Non-maskable Interrupt (NMI) – – GPIO input/output interface – Up to six FC Universal Asynchronous Receiver/Transmitter (FCUART) modules with LIN support Communications Interfaces • Up to four FC Serial Peripheral Interface (FCSPI) modules; support 1/2/4 data lines and master/slave mode – Up to two FC Inter-Integrated Circuit (FCIIC) modules – Up to three FLEXCAN modules with CAN FD (optional) and PNET support – Four TRGSELs for on-chip bus connection – – Lookup Unit (LU) module with 4 lookup tables – Hardware Secure Module (HSM) with crypto algorithms including AES and SM4 Safety and Security • CCM/GCM/ECB/CTR/CBC etc. mode – Support random number generation and pseudo random number generation – Key import/export management – ECC on flash and SRAM memories – Memory Access Protection (MAP) on system SRAM – Peripheral Access Protection on APB bridge (AFCB) – One Cyclic Redundancy Check (CRC) module – – – – – • – – – – Up to two Internal watchdogs (WDOG) with window function FunSa Watchdog Monitor (FWM) module One Interface Safety Monitor (ISM) module to monitor the critical signals' delay/period/duty etc. CM4 core self-test API in ROM code Timers Up to six Flexible Timer Unit (FTU) modules with IC/OC/PWM function One Always-on Timer (AONTIMER) with standby wake up capability Two Programmable Timers (PTIMERs) One FC Programmable Interrupt Timer (FCPIT) with 4 channels 12 One Real-Time Clock (RTC) – FC4150F1M_B Data Sheet Two 56-bit Timer Stamps (TSTMPs) with four 32-bit compare channels. The TSTMP0 runs at 1MHz divided from – SIRC12M; and the TSTMP1 runs at Core clock. – One Frequency Measurement (FREQM) Module; with up to 64 input clock sources. – 64LQFP, 100LQFP and 144LQFP package options. Package • • – – Qualification: ASIL B certified according to ISO 26262 AEC-Q100/Q006 Grade 1 (-40°C to 125°C) 13 Chapter 3 General FC4150F1M_B Data Sheet 3.1 Absolute Maximum Ratings The table below lists the maximum allowed conditions for the chip. To avoid the chip damage, the user needs to make sure the conditions are met. Symbol Description VDD_HV Table 1. Absolute maximum ratings 3.0 V - 5.5 V input supply voltage VREFH 3.3 V - 5.0 V high reference voltage IINJPAD_DC_ABS VIN_DC Continuous DC input current (positive / negative) that can be injected into an I/O pin Continuous DC Voltage on any I/O pin with respect to VSS IINJSUM_DC_ABS Tramp_MCU Sum of injected currents on all the pins (Continuous DC limit, positive / negative) MCU supply ramp rate Min. Max. Unit 6.01 V -0.3 6.01 - 3 mA -0.8 6.01 V - 252 mA - 100 V/ms - -0.3 V TA Ambient temperature -40 125 °C VIN_TRANSIENT Transient overshoot voltage allowed on I/O pin beyond VIN_DC limit - 6.8 V TSTG 1. 2. Storage temperature Operation with the 6.0 V maximum is allowed for 10 hours over lifetime. -55 165 °C The maximum value is based on VDD_HV_A = VDD_HV_B = 5V condition and continuous pins DC injection current includes sum of injection currents of 16 continuous pins. Note: For inject current, the user needs to make sure that it won't cause issue if the inject current is above the chip self-power consumption (like standby/stop mode). Otherwise, it may cause damage. 3.2 Operation Condition The table below lists the chip operation condition. To meet the design specifications, these conditions need to be met. Note: VDD_HV means the supply such as VDD_HV_A/VDD_HV_B. Symbol VDD_HV VDD_OFF VDDA VDD_HV – VDDA VREFH VREFL IINJPAD_DC_OP IINJSUM_DC_OP Description Table 2. Operating requirements Supply voltage Voltage allowed to be developed on VDD_HVA pin when it is not powered from any external power supply source. Analog supply voltage Min. Max. Unit 0 0.1 V 3.0 5.5 V 3.0 5.5 V VDD_HV to VDDA differential voltage -0.1 0.1 V ADC reference voltage low -0.1 0.1 V -1 +1 mA - 5 mA ADC reference voltage high Continuous DC input current (positive / negative) that can be injected into an I/O pin Continuous total DC input current that can be injected across all I/O pins 3.0 VDDA + 0.1 V 14 FC4150F1M_B Data Sheet Symbol Table 2. Operating requirements (continued) Description Tpulse Reset/NMI input analog filter pulse width 3.3 Thermal Operating Condition Symbol Description TJ Junction temperature TA 42 Table 3. Thermal operating condition Ambient temperature Min. Min. Typ. Max. Unit -40 - 150 ℃ -40 - 125 ℃ Max. - Unit ns Notes 3.4 Clock Operating Condition The table below lists the maximum functional clocks of modules. For the IO-related max clock frequency, refer to each IPs electrical specification. For the SCG DIVH/M/L output, it should be not above the 150 MHz/75 MHz/37.5 MHz range. Table 4. Max. functional clock of modules Module/Peripheral Max. Functional Clock (for STA) CM4 150 MHz FWM 75 MHz DMA 150 MHz WDOGx 75 MHz RCM 75 MHz WKU 75 MHz SCG - TRGSELx 75 MHz PCC - ROM 150 MHz FMC 150 MHz OSPI 50 MHz TCM FC CRC 150 MHz 150 MHz 75 MHz FCSPIx 75 MHz FCIICx 75 MHz FLEXCAN0-2 Memory Modules 150 MHz HSM FCUARTx CPU & System Modules Notes Security Modules Communication Modules 75 MHz 150 MHz 15 FC4150F1M_B Data Sheet Table 4. Max functional clock of modules (continued) Module/Peripheral Max. Functional Clock (for STA) Timer Modules AONTIMER0 75 MHz FTU0-5 150 MHz FCPIT0 Notes 75 MHz TSTMP0 1 MHz TSTMP1 150 MHz RTC 32 kHz PTIMER0-1 150 MHz GPIOx 150 MHz PORTx 75 MHz ADCx Analog Modules 30 MHz CMP HMI Modules 75 MHz PMC 75 MHz 3.5 LVR, LVD, HVD, and POR Operating Requirements The chip supports monitors including Power-on Reset (POR)/ Low-Voltage Reset (LVR)/ Low-Voltage Detect (LVD) on the VDD_HV supply. Symbol Description Table 5. LVR/LVD/HVD and POR VDD_HV_A/B supply HVD, LVD and POR Operating Ratings Min. Typ. Max. Unit 2.75 2.85 2.95 V 4.2 4.35 VPOR POR re-arm voltage VHVD_VDD_HV HVD on VDD_HV_A/B 5.7 VHYS Hysteresis Voltage - VLVR_VDD_HV VLVD_VDD_HV VBG LVR on VDD_HV_A/B LVD on VDD_HV_A/B Bandgap voltage reference voltage 1.1 1.164 1.6 2.1 V 5.85 6 V 0.04 0.1 V 1.2 4.5 1.236 Notes V V 16 FC4150F1M_B Data Sheet 3.6 Power Mode Transition The table below lists the different power mode transition time. Symbol tPOR Description Table 6. Power mode transition time Min. Typ. Max. Unit VDD reaches 2.7 V to execution of the first instruction - 200 - μs Standby → RUN (First code) - 130 - μs - 3 - μs - μs After a POR event, the amount of time from the point across the operating temperature range of the chip. tSTBtoR STOP → RUN (FIRC and SIRC are enabled in Stop tSTtoR mode) tRtoST RUN → STOP - 5 tREStoR Pin reset →RUN (First code) - 2 tRtoSTB RUN → Standby - 12 - - μs μs 3.7 Chip IDD The chip supports four power modes: RUN/WAIT/STOP/Standby. During standby mode, the V25 Low Dropout (LDO) and SIRC12M/FOSC etc. can be optionally on. Both code RAM and data RAM can optionally retain 32 KB SRAM during standby mode. Refer to the Reference Manual for detailed settings. The table below lists the chip RUN IDD current. The peripheral enabled/disabled here means enabling/disabling the peripherals' clock gating control (CGC). Symbol Description Table 7. Chip RUN IDD Active mode current - all peripherals disabled, while1, 150 MHz/75 MHz for Core/Bus, Cache enable, 25℃ Idd_active Active mode current - all peripherals enabled and clock switch 150 MHz PLL0 output, while1, 150 MHz/75 MHz for Core/Bus, Cache enable, 25℃ Active mode current - all peripherals enabled and clock switch 150 MHz PLL0 output, while1, 150 MHz/75 MHz for Core/Bus, Cache enable, 125℃ Wait mode – all peripherals enable and clock switch 150 MHz PLL0 output, 25℃ Idd_wait Wait mode – all peripherals enable and clock switch 150 MHz PLL0 output, 105℃ Wait mode – all peripherals enable and clock switch 150 MHz PLL0 output, 125℃ Min. Typ.1 Max. Unit - 24.5 26.2 mA - 36.3 38.0 mA - 42.2 98.1 mA - 27.1 28.8 mA - 30.0 85.9 mA - 33.0 88.9 mA Notes 1. Typical value indicates the typical silicon process and the average current values at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0 V, and VDD_HV_B = 5.0 V. 17 FC4150F1M_B Data Sheet Symbol Idd_stop Description Table 8. Chip low power IDD Min. Max. Unit 22.3 mA 135.8 μA STOP Mode, 25℃ - 2.6 4.2 STOP Mode, 125℃ - 9.3 36.7 STOP Mode, 105℃ - Standby Mode, all 64K RAM retention, 25℃ Standby Mode, only 32K RAM retention, 25℃ Idd_standby Typ.1 Standby Mode, no RAM retention, 25℃ Standby Mode, no RAM retention, 125℃ Standby Mode, no RAM retention, SIRC12M Enable, 25℃ Standby Mode, no RAM retention, SIRC32k Enable, 25℃ - - 6.1 69.2 mA 125.9 μA 476.7 3644.1 μA - 161.8 228.4 μA - 53.2 119.8 μA - 59.3 mA 49.3 Notes 115.9 μA 1. Typical value indicates the typical silicon process and the average current values at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0 V, and VDD_HV_B = 5.0 V. 3.8 PMC Internal LDO The chip contains two LDO supply outputs: V25 and V11. Both V25 and V11 support the Full Performance Mode (FPM) and Reduce Power Mode (RPM). External cap needs to be put on the V25/V11 pin to make sure LDO function works as expected. Symbol VDD_HV_A V25 Cout Symbol Description V25 input supply voltage V25 regulator output voltage External output capacitor Description Table 9. V25 LDO specification Min. 3 2.25 - Table 10. Core LDO specification Min. Typ. - Max. 5.5 2.75 - nF Typ. Max. Unit 1.21 V 220 V11 input supply voltage 3 - 5.5 Cout External output capacitor - 1.1 2.2 V11 regulator output voltage 1.06 V - VDD_HV_A V11 Unit - Notes V V Notes μF 18 FC4150F1M_B Data Sheet 3.9 ESD Ratings The Electrostatic Discharge (ESD) result follows the industry test standard. Symbol VHBM VCDM ILAT 1. 2. 3. 4. 5. Table 11. ESD ratings Description Electrostatic discharge voltage, human body model (HBM) Electrostatic discharge All pins except the corner model (CDM) Corner pins only voltage, charged-device pins Latch-up current at ambient temperature of 125°C Min. Max. Unit Notes -2000 2000 V 1, 2, 3 -500 500 V -750 750 V -100 100 mA 1, 3, 4 1, 3, 5 Device failure is defined as the situation where the device fails to meet the specification requirements after being exposed to ESD pulses. This parameter is tested in compliance with AEC-Q100-002. All ESD tests comply with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. This parameter is tested in compliance with AEC-Q100-011. This parameter is tested in compliance with AEC-Q100-004. 19 FC4150F1M_B Data Sheet Chapter 4 I/O Parameter 4.1 IO DC Specification The IO can work with supplies from 3.0 V to 5.5 V. The tables below list specifications for the supplies. Symbol VIH VIL VHYS Voh_normal Vol_normal Voh_fast Vol_fast Voh_fast Vol_fast IPU IPD Symbol Description Table 12. 3V IO DC specification Min. Typ. Max. Unit Input high voltage 0.65*VDD_IO - - V Input hysteresis 0.07*VDD_IO - - V Input low voltage - I/O current source capability with Ioh=4mA I/O current sink capability with Iol=4mA I/O current source capability with Ioh=4mA and DSE=0 I/O current sink capability with Iol=4mA and DSE=0 I/O current source capability with Ioh=8mA and DSE=1 I/O current sink capability with Iol=8mA and DSE=1 Internal pullup current (Rload=0, output tie to VSS) Internal pulldown current (Rload=0, output tie to VDD_IO) Description - 0.35*VDD_IO V VDD_IO - 0.68 - - V - - 0.712 V VDD_IO - 0.78 - - V - - 0.751 V VDD_IO - 0.78 - - V - - 0.751 V 65 - 124 μA 68 - 133 μA Table 13. 5V IO DC specification Min. Typ. Max. Unit - 0.35*VDD_IO V VIH Input high voltage 0.65*VDD_IO - VHYS Input hysteresis 0.07*VDD_IO - - V VDD_IO - 0.68 - - V - - 0.46 V VDD_IO - 0.5 - - V - - 0.444 V VIL Voh_normal Vol_normal Voh_fast Vol_fast Input low voltage I/O current source capability with Ioh=4mA I/O current sink capability with Iol=4mA I/O current source capability with Ioh=4mA and DSE=0 I/O current sink capability with Iol = 4mA and DSE = 0 - - Notes V Notes 20 FC4150F1M_B Data Sheet Symbol Voh_fast Vol_fast IPU IPD Table 13. 5V IO DC specification (continued) Description I/O current source capability with Ioh = 8mA and DSE = 1 I/O current sink capability with Iol = 8mA and DSE = 1 Internal pullup current (Rload = 0, output tie to VSS) Internal pulldown current (Rload = 0, output tie to VDD_IO) Min. Typ. Max. Unit VDD_IO - 0.5 - - V - - 0.444 V 107 - 213 μA 110 - 210 μA Notes 4.2 IO AC Specification The below is the IO AC specification, wherein the minimum value is based on 3.6 V/5.5 V/150℃ condition and the maximum value is based on 3.0 V/4.5 V/-40℃ condition. Note: The specification is based on simulation data. Table 14. 3V IO AC specification Symbol SRE tRFnormal 0 tRFnormal tRFfast 1 tRFfast DSE 1 0 Rise Time (ns) Fall Time (ns) 2.12 8.82 2.3 1.52 4.63 Min. 3.3 2.77 Max. Capacitance (pF) Min. Max. 10.98 3.1 10.32 25, 20%-80% r/f 8.04 2.75 8.39 25, 20%-80% r/f 1.39 8.64 4.53 25, 20%-80% r/f 25, 20%-80% r/f Table 15. 5V IO AC specification Symbol SRE tRFnormal 0 tRFnormal tRFfast tRFfast 1 DSE 1 0 Rise Time (ns) Min. Max. Min. Max. 7.82 2.43 7.19 2.16 6.41 1.14 3.18 2.67 2.16 Fall Time (ns) 6.7 2.15 1.11 2.31 Capacitance (pF) 6.08 25, 20%-80% r/f 3.09 25, 20%-80% r/f 6.06 25, 20%-80% r/f 25, 20%-80% r/f 21 FC4150F1M_B Data Sheet Chapter 5 Clock Specification 5.1 FOSC Specification The Fast Oscillator (FOSC) supports the range of 16 - 48 MHz. To avoid the startup noise impact, software should wait enough time before using the clock. The FOSC can keep enabled during standby/stop mode. Figure 3. Crystal connection diagram Gain Amplifier With Loop control EXTAL XTAL C� Symbol Description fosc GND� Y� C� Table 16. FOSC specification Oscillator crystal or resonator frequency Min. 16 Rs Typ. 40 GND� Max. Unit 48 MHz Tst_osc Startup time - 600 - μs GM Gain Amplifier transconductance 11.07 - 26.24 mA/V Idd_osc Current consumption - 1200 - μA Notes Select max GM setting For crystal selection, usually require gm > 5*gmcrit. • Formula gainmargin = gm / gmcrit, where: ­ gm is the oscillator transconductance specified in the data sheet. Note that the oscillator transconductance is in ­ gmcrit is defined as the minimal transconductance of an oscillator required to maintain a stable oscillation when ­ • the range of a dozen of mA/V. it is a part of the oscillation loop for which this parameter is relevant. gmcrit is computed from oscillation-loop passive components parameters (Rs is 0 here). gmcrit = 4 × ESR (2πF)2 × (C0 + CL)2, where: ­ ­ ­ ­ ESR is the equivalent series resistance. C0 is the crystal shunt capacitance. CL is the crystal nominal load capacitance, CL = Cs+ [C1*C2/(C1+C2)] (Note: C1 should be equal to C2). F is the crystal nominal oscillation frequency. 22 FC4150F1M_B Data Sheet 5.2 SOSC Specification The Slow Oscillator (SOSC) supports the 32.768 kHz crystal. To avoid the startup noise impact, software should wait enough time before using the clock. The SOSC will keep enabled during system reset. Only POR/LVD will reset the SOSC. Symbol fosc32k Table 17. SOSC specification Description Oscillator crystal or resonator frequency Min. - Typ. 32.768 Max. - Unit kHz Tst_osc32k Startup time - 1 - s GM Gain Amplifier transconductance 26 - 54.5 μA/V Idd_osc32k Current consumption - 1.8 - Notes μA 5.3 FIRC96M Specification The FIRC96M is the default system clock after reset. FIRC96M provides two clock sources, one is 96 MHz and the other is 48 MHz. The 96 MHz clock can be selected as the system clock. The 48 MHz clock can be selected as the PLL reference clock and Flash program/erase clock. Software needs to make sure FIRC is enabled and 48 MHz clock output is enabled before a flash program/erase operation or selecting the FIRC as the PLL reference clock. After reset, the FIRC is enabled and both 96 MHz and 48 MHz clock output are enabled. Symbol ffirc96m Δffirc96m Tst_firc96m Description Table 18. FIRC96M specification firc96m clock frequency range Frequency Deviation with 1T trim Startup time (