APS6408L-3OBM-BA

APS6408L-3OBMx DDR OPI Xccela PSRAM Double-Data-Rate OPI Xccela PSRAM Specifications Features • • • • • • • • Single Supply Voltage o VDD = 2.7 to 3.6V o VDDQ = 2.7 to 3.6V Interface: Octal SPI with DDR Xccela mode, two bytes transfers per one clock cycle Performance: Clock rate up to 133MHz, 266MB/s read/write throughput Organization: 64Mb, 8M x 8bits with 1024 bytes page size o Column address: AY0 to AY9 o Row address: AX0 to AX12 Refresh: Self-managed Operating Temperature Range o Tc = -40°C to +85°C(standard range) o Tc= -40°C to +105°C (extended range) Maximum Standby Current o 350µA @ 105°C (extended range) o 250µA @ 85°C o 140µA @ 25°C APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 • • • • • • • • • • 1 of 26 Low Power Features o Partial Array Self-Refresh (PASR) o Auto Temperature Compensated SelfRefresh (ATCSR) by built-in temperature sensor o User configurable refresh rate Software Reset Reset Pin Available Output Driver LVCMOS with programmable drive strength Data Mask (DM) for write data Data Strobe (DQS) enabled highspeed read operation Register Configurable write and read initial latencies Write Burst Length, maximum 1024 Byte, minimum 2 Byte. Wrap & Hybrid Burst in 16/32/64/1K lengths. Linear Burst Command Row Boundary Crossing (RBX) o read operations can be enabled via Mode Register o RBX Write is NOT supported. AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM Table of Contents 1 Table of Contents 1 Table of Contents ............................................................................................................. 2 2 Package Information ........................................................................................................ 3 3 Package Outline Drawing ................................................................................................. 4 4 Ordering Information ....................................................................................................... 5 5 Signal Table ...................................................................................................................... 6 6 Power-Up Initialization .................................................................................................... 7 7 8 9 6.1 Power-Up Initialization Method 1 (via. RESET# pin) ............................................... 7 6.2 Power-Up Initialization Method 2 (via. Global Reset) ............................................ 8 Interface Description ....................................................................................................... 9 7.1 Address Space ......................................................................................................... 9 7.2 Burst Type & Length................................................................................................ 9 7.3 Command/Address Latching ................................................................................... 9 7.4 Command Truth Table ............................................................................................ 9 7.5 Read Operation ..................................................................................................... 10 7.6 Write Operation .................................................................................................... 13 7.7 Control Registers ................................................................................................... 14 Electrical Specifications: ................................................................................................ 20 8.1 Absolute Maximum Ratings .................................................................................. 20 8.2 Pin Capacitance ..................................................................................................... 20 8.3 Decoupling Capacitor Requirement ...................................................................... 21 8.4 Operating Conditions ............................................................................................ 21 8.5 DC Characteristics ................................................................................................. 22 8.6 ISB Partial Array Refresh Current .......................................................................... 23 8.7 AC Characteristics ................................................................................................. 24 Change Log ..................................................................................................................... 26 APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 2 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 2 Package Information The APS6408L-3OBMx is available in miniBGA 24L package 6 x 8 x 1.2mm, ball pitch 1.0mm,ball size 0.4mm , package code “BA”.  Ball Assignment for MINIBGA 24L 1 A 2 3 4 5 NC CE# RST# NC B NC CLK VSS VDD NC C VSSQ RSU DQS/ DM ADQ2 NC D VDDQ ADQ1 ADQ0 ADQ3 ADQ4 E ADQ7 ADQ6 ADQ5 VDDQ VSSQ Top View (Ball Down) (6x8x1.2mm)(P1.0)(B0.4) Note: 1. Part Number APS6408L-3OBM-BA for 64Mb. 2. RFU: Reserved for future use, which is reserved for 2nd CE#. 3. NC: No internal connection. APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 3 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 3 Package Outline Drawing TOP VIEW BOTTOM VIEW A1 INDEX A1 INDEX A 1 2 3 4 5 5 4 3 2 1 DIMENSION (mm) SYM. NOM. MIN. A A B D C D1 SD B C - - 1.20 A1 0.25 0.30 0.35 A2 - 0.79 - b 0.35 0.40 0.45 D 7.90 8.00 8.10 D1 E D e D E E e E B d 0.10 4.00 BSC 5.90 6.00 E1 4.00 BSC SE 1.00 TYP SD 1.00 TYP e 1.00 BSC 6.10 NOTE: 1. CONTROLLING DIMENSION : MILLIMETER. 2. REFERENCE DOCUMENT : JEDEC MO-207. 3. THE DIAMETER OF PRE-REFLOW SOLDER BALL IS Ø0.40mm.(0.35mm SMO) SE DETAIL B E1 (4X) MAX. A SOLDER BALL Øb (24x PLACES) f DETAIL A 0.10 C j j . A2 A 0.15 m C A B 0.08 m C SEATING PLANE d 0.08 C A1 C SIDE VIEW APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 DETAIL A 4 of 26 DETAIL B AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 4 Ordering Information Table 1: Ordering Information Part Number APS6408L-3OBM-BA Temperature Range Tc= -40°C to +85°C Max Frequency 133 MHz Note 24b Package APS6408L-3OBMX-BA Tc= -40°C to +105°C 133 MHz 24b Package Note  OBM is standard part to support RBX read operation only. A P S 64 08 L 3 OB 128 256 Die Gen. 32 16 IO Config. S: Sync PSRAM AP Memory X Package Type Blank: KGD Temperature grade Blank: default option X: extended temp. 16: x16 08: x8 04: x1/x4 Density 256: 256M 128: 128M 64: 64M 32: 32M 16: 16M APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 Die Option Interface VCC Blank: 1.8V 3: 3V 5 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 5 Signal Table All signals are listed in Table 2. Table 2: Signals Table Symbol VDD VDDQ VSS VSSQ A/DQ[7:0] DQS/DM Type Power Power Ground Ground IO IO Description Core supply 3.0V IO supply 3.0V Core supply ground IO supply ground Address/DQ bus [7:0] DQ strobe clock during reads, Data mask during writes. DM is active high. DM=1 means “do not write”. CE# CLK RESET# Input Input Input Chip select, active low. When CE#=1, chip is in standby state. Clock signal Reset signal, active low. Optional, as the pad is internally tied to a weak pull-up and can be left floating. APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 6 of 26 Comments AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 6 Power-Up Initialization Octal DDR products include an on-chip voltage sensor used to start the self-initialization process. VDD and VDDQ must be applied simultaneously. When they reach a stable level at or above minimum VDD, the device is in Phase 1 and will require 150μs to complete its self-initialization process. The user can then proceed to Phase 2 of the initialization described in this section. During Phase 1 CE# should remain HIGH (track VDD within 200mV); CLK should remain LOW. After Phase 2 is complete the device is ready for operation. 6.1 Power-Up Initialization Method 1 (via. RESET# pin) The RESET# pin can be used to initialize the device during Phase 2 as follows: Phase 1 Phase 2 VDDmin Device ready for normal operation tPU ≥ 150µs VDD/VDDQ Device Initialization CE# tRP RESET# tRST ≥ 2µs Don’t Care Figure 1. Power-Up Initialization Method 1 RESET# The RESET# pin can also be used at any time after the device is initialized to reset all register contents. Memory content is not guaranteed. Timing requirements for RESET# usage are shown below. CE# tRP RESET# tRST Figure 2. RESET# Timing APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 7 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 6.2 Power-Up Initialization Method 2 (via. Global Reset) As an alternate power-up initialization method, After the Phase 1 150μs period the Global Reset command is used to reset the device in Phase 2 as follows: Phase 1 Phase 2 VDDmin tPU ≥ 150µs VDD/VDDQ Device Initialization tRST ≥ 2µs Write Global Reset Device ready for normal operation Figure 3. Power-Up Initialization Method 2 Timing with Global Reset The Global Reset command resets all register contents. Memory content is not guaranteed. The command frame is made of 4 clocked CE# lows. Clocking is optional during tRST. The Global Reset command sequence is shown below. Note that Global Reset command can be used ONLY as Power-up initialization. Clocking Optional CLK t t CSP CHD t RST CE# Global Reset begins t A/DQ[7:0] SP INST t HD DQS/DM Don’t Care Global Reset Identified (INST[7:0] = `hFF) Figure 4: Global Reset APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 8 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 7 7.1 Interface Description Address Space Octal DDR PSRAM device is byte-addressable. Memory accesses are required to start on even addresses (A[0]=’0). Mode Register accesses allow both even and odd addresses. 7.2 Burst Type & Length Read and write operations are default Hybrid Wrap 32 mode. Other burst lengths of 16, 32, 64 or 1K bytes in standard or Hybrid wrap modes are register configurable (see Table 18) The device also includes command for Linear Bursting. Bursts can start on any even address. Write burst length has a minimum of 2 bytes. Read has no minimum length. Both write and read have no restriction on maximum burst length as long as tCEM is met. 7.3 Command/Address Latching After CE# goes LOW, instruction code is latched on 1st CLK rising edge. Access address is latched on the 3rd, 4th, 5th & 6th CLK edges (2nd CLK rising edge, 2nd CLK falling edge, 3rd CLK rising edge, 3rd CLK falling edge). 7.4 Command Truth Table The Octal DDR PSRAM recognizes the following commands specified on the INST (Instruction) cycle defined by the Address/DQ pins. 1st CLK Command Sync Read Sync Write Sync Read (Linear Burst) Sync Write (Linear Burst) Mode Register Read Mode Register Write Global Reset 00h 80h 20h A0h 40h C0h FFh Remarks: APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 × A3 A2 A1 A0 MA 2nd CLK A3 A3 A3 A3 3rd CLK A2 A2 A2 A2 × × A1 A1 A1 A1 A0 A0 A0 A0 MA MA × = don't care (VIH/VIL) = unused address bits are reserved = 1'bx, RA[12:6], unused address bit is reserved = RA[5:0],CA[9:8] = CA[7:0] = Mode Register Address 9 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 7.5 Read Operation After address latching, the device initializes DQS/DM to ‘0 from next CLK rising edge of the 3rd clock cycle (A1). See Figure 5 below. Output data is available after LC latency cycles, as shown in Figure 7 & Figure 8, LC is defined in Table 5 and Table 6. When data is valid, A/DQ[7:0] and DQS/DM follow the timing specified in Figure 9. Synchronous timing parameters are shown in Table 28 & Table 29. In case of internal refresh insertion, variable latency output data may be delayed by up to (LC*2) latency cycles as shown in Figure 7. True variable refresh pushout latency can be anywhere between LC to LCx2. The 1st DQS/DM rising edge after read pre-amble indicates the beginning of valid data. t RC CLK t t CSP CHD Latency Count 5 CE# t CPH t t HZ SP A/DQ[7:0] A3 INST t A2 A1 A0 D0 High-Z HD t D1 D2 D3 High-Z INST DQSCK t CQLZ DQS/DM High-Z High-Z A3=Addr[31:24] A2=Addr[23:16] A1=Addr[15:8] A0=Addr[7:0] READ Burst Identified (INST[7:6] = `b00) Don’t Care Undefined Figure 5: Synchronous Read If RBX has been enabled (MR8[3] written to 1) and a Linear Burst Command issued, then Wrap settings (MR8[2:0] are ignored and Read operations are allowed to cross row boundaries as shown in Figure 6. CLK t CSP Latency Count 3 CE# t A/DQ[7:0] SP INST A3 A2 A1 A0 D0 High-Z D1 D2 D3 t HD t t DQS/DM CQLZ t DQSCK RBXwait High-Z Linear READ Burst Identified (INST[7:0] = `h20) A3=Addr[31:24] A2=Addr[23:16] A1=Addr[15:8] A0=Addr[7:0] Don’t Care Undefined Figure 6: Synchronous Read with RBX (Starting address ‘3FE) APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 10 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 1 2 3 4 5 6 CLK A/DQ[7:0] INST A3 DQS/DM A/DQ[7:0] A2 A1 A3 D0 High-Z D1 D2 D3 D4 D5 D6 D7 D8 D0 D1 D2 Variable Latency Code 3, no refresh High-Z INST A0 A2 A1 A0 High-Z Variable Latency Code 3, maximum refresh pushout DQS/DM High-Z Figure 7: Variable Read Latency Refresh Pushout 1 2 3 4 5 CLK Latency Code 5 A/DQ[7:0] INST A3 A2 A1 A0 D0 High-Z D1 D2 D3 t DQSCKMIN DQS/DM A/DQ[7:0] High-Z INST A3 A2 A1 A0 D0 High-Z D1 D2 D3 t DQSCKMAX DQS/DM High-Z Figure 8: Read Latency & tDQSCK APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 11 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM t t CL t CH CLK CLK t A/DQ[7:0] DQSQ D0 High-Z t DQSCKMIN t D1 QH D2 D3 t QH t DQSCKMIN DQS/DM t A/DQ[7:0] DQSQ D0 High-Z t t DQSCKMAX D1 D2 D3 t QH t QH DQSCKMAX DQS/DM Note: All DQ are valid tDQSQ after the DQS edge, regardless of tDQSCK Undefined Figure 9: Read DQS/DM & DQ timing APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 12 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 7.6 Write Operation A minimum of 2 bytes of data must be input in a write operation. In the case of consecutive short burst writes, tRC must be met by issuing additional CE# high time between operations. Single-byte write operations can be performed by masking the un-written byte with DQS/DM as shown in Figure 10. t RC CLK t CSP t CHD Latency Count 3 CE# t CPH t SP A/DQ[7:0] INST A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 High-Z INST t HD DQS/DM High-Z High-Z WRITE Burst Identified (INST[7:6] = `b10) A3=Addr[31:24] A2=Addr[23:16] A1=Addr[15:8] A0=Addr[7:0] D1, D3, D4 & D6 masked Don’t Care Figure 10: Synchronous Write followed by any Operation tCH tCL tCLK CLK tDH tDS DQS/DM DM0 DM1 DM2 tDH tDS DQ D0 D1 DM3 D2 D3 Don’t Care Figure 11: Write DQS/DM & DQ Timing APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 13 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 7.7 Control Registers Register Read is shown below. Mode Address in command determines which Mode Register is read from as Data0 (see chart in the Figure below). t RC CLK t t CSP CHD Latency Count 5 CE# t t t A/DQ[7:0] SP INST MA D0 High-Z t HD t D1 D0 CPH HZ D1 INST High-Z DQSCK t DQS/DM CQLZ High-Z High-Z MA `h00 `h01 `h02 `h03 `h04 `h08 Register READ Identified (INST[7:0] = `h40) D0 MR0 MR1 MR2 MR3 MR4 MR8 Don’t Care D1 MR1 MR2 MR3 MR4 MR8 MR0 Undefined Figure 12: Register Read t RC CLK t t CHD CSP CE# t t A/DQ[7:0] CPH t DS SP INST MA# t MR# t HD High-Z INST DH DQS/DM Don’t Care Register WRITE Identified (INST[7:0] = `hC0) Figure 13: Register Write Register Writes are Latency 1, whereas Register Reads use the same MR0[4:2] settings as burst reads (see Table 5). Registers 0, 4 & 8 are read and writable, and Registers 1, 2 and 3 are read-only. Register mapping is shown in Table 3. Note that MR0[6], MR0[7], MR4[4] and MR8[7] must be written to b'0. APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 14 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM Table 3: Mode Register Table MR No. MA[7:0] 0 `h00 1 `h01 2 `h02 3 `h03 4 `h04 8 `h08 Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 '00' Drive Str. R/W LT Read Latency Code rsvd. Vendor ID R rsvd. Dev ID Density R GB rsvd. R RBXen VCC SRF Write Latency Code PASR R/W '0' RF rsvd. BL R/W '0' RBX BT Table 4: Read Latency Type (MR0[5]) Latency Type MR0[5] LT 0 Variable (default) 1 Fixed Table 5: Read Latency Codes MR0[5:2] MR0[4:2] 000 001 010 others VL Codes (MR0[5]=0) Latency (LC) Max push out (LCx2) 3 6 4 8 5 (default) 10 reserved FL Codes (MR0[5]=1) Latency (LCx2) 6 8 10 Max Input CLK Freq (MHz) Standard Extended 66 66 109 109 133 133 - Table 6: Operation Latency Code Table VL (default) No Refresh Refresh Read LC Up to LCx2 Memory Write WLC Read LC Register Write 1 *Note: see Table 15 for WLC settings. Type Operation APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 15 of 26 FL LCx2 WLC LC 1 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM Table 7: Drive Strength Codes MR0[1:0] Codes ‘00 ‘01 ‘10 ‘11 Drive Strength Half (50Ω) 1/4 (100Ω default) 1/8 (200Ω) 1/16 (400Ω) Table 8: Vendor ID mapping MR1[4:0] Vendor ID 01101: APM Table 9: Good-Die Bit MR2[7]* Codes Good Die ID ‘1 PASS ‘0 FAIL *Note: Default is FAIL die, and only mark PASS after all tests passed. Table 10: Device ID MR2[4:3] Codes ‘00 ‘01 ‘10 others Device ID Generation 1 Generation 2 Generation 3 (default) reserved Table 11: Device Density mapping MR2[2:0] MR2[2:0] ‘001 ‘011 ‘101 ‘111 others Density 32Mb 64Mb 128Mb 256Mb reserved Table 12: Row Boundary Crossing Enable (MR3[7]) MR3[7] (read-only) 0 1 APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 RBXen RBX not supported RBX supported via MR8[3]=1 16 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM Table 13: Operating Voltage Range (MR3[6]) MR3[6] 0 1 VCC 1.8V 3V (default) Table 14: Self Refresh Flag (MR3[5]) MR3[5] (read-only) Self Refresh Flag 0 Slow Refresh (allowed via MR4[3]=1, otherwise Fast Refresh) 1 Fast Refresh MR3[5] is a refresh indicator that corresponds to device internal temperature. This bit will indicate 0 when the temperature is low enough to allow a slow frequency refresh rate. Table 15: Write Latency MR4[7:5] Default powered up behavior is WL 5 MR4[7:5] 000 100 010 others Write Latency Codes (WLC) 3 4 5 (default) reserved Fmax (MHz) 66 109 133 - Table 16: Refresh Frequency MR4[3] MR4[3] 0 1 Refresh Frequency Fast Refresh (default) Enables Slow Refresh when temperature allows APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 17 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM Table 17: PASR MR4[2:0] The PASR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. Codes ‘000 ‘001 ‘010 ‘011 ‘100 ‘101 ‘110 ‘111 Refresh Coverage Full array (default) Bottom 1/2 array Bottom 1/4 array Bottom 1/8 array None Top 1/2 array Top 1/4 array Top 1/8 array APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 64Mb Address Space 000000h-7FFFFFh 000000h-3FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 400000h-7FFFFFh 600000h-7FFFFFh 700000h-7FFFFFh 18 of 26 Size 8M x8 4M x8 2M x8 1M x8 0M 4M x8 2M x8 1M x8 Density 64Mb 32Mb 16Mb 8Mb 0Mb 32Mb 16Mb 8Mb AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM Table 18: Burst Type MR8[2], Burst Length MR8[1:0] By default the device powers up in 32 Byte Hybrid Wrap. In non-Hybrid burst (MR8[2]=0), MR8[1:0] sets the burst address space in which the device will continually wrap within. If Hybrid burst wrap is selected (MR8[2]=1), the device will burst through the initial wrapped burst length once, then continue to burst incrementally up to maximum column address (1K) before wrapping around within the entire column address space. Burst length (MR8[1:0]) can be set to 16,32,64 & 1K lengths. MR8[2] ‘0 ‘0 ‘0 ‘0 ‘1 ‘1 ‘1 ‘1 MR8[1:0] ‘00 ‘01 ‘10 ‘11 ‘00 ‘01 ‘10 ‘11 Burst Length 16 Byte Wrap 32 Byte Wrap 64 Byte Wrap 1K Byte Wrap 16 Byte Hybrid Wrap 32 Byte Hybrid Wrap (default) 64 Byte Hybrid Wrap 1K Byte Wrap Example of Sequence of Bytes During Wrap Starting Address Byte Sequence 4 [4,5,6,…15,0,1,2,…] 4 [4,5,6,…31,0,1,2,…] 4 [4,5,6,…63,0,1,2,…] 4 [4,5,6,…1023,0,1,2,…] 2 [2,3,4,…15,0,1],16,17,18,…1023,0,1,… 2 [2,3,4,…31,0,1],32,33,34,…1023,0,1,… 2 [2,3,4,…63,0,1],64,65,66,…1023,0,1,… 2 [2,3,4,…1023,0,1,2,…] The Linear Burst Commands (INST[5:0]=6’b100000) override MR8[2:0] settings and forces the current array read or write command to do 1K Byte Wrap (equivalent to having MR8[1:0] set to 2’b11). The burst continues linearly from the starting address and at the end of the page, then wraps back to the beginning of the page. This special burst instruction can be used on both array write and read. Table 19: Row Boundary Crossing Read Enable MR8[3] This register setting applies to Linear Burst reads only on RBX enabled devices (MR3[7]=1). Default write and read burst behavior is limited within the 1K (CA=’h000 -> ‘h3FF) column address space. Setting this bit high will allow Linear Burst reads to cross over into the next Row (RA+1). MR8[3] 0 1 RBX Read Reads stay within the 1K column address space Reads cross row at 1K boundaries APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 19 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 8 Electrical Specifications: 8.1 Absolute Maximum Ratings Table 20: Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage to any ball except VDD, VDDQ relative to VSS VT VDD Voltage on VDDQ supply relative to VSS VDDQ -0.4 to VDD/VDDQ+0.4 -0.4 to +4 -0.4 to +4 V Voltage on VDD supply relative to VSS Storage Temperature TSTG -55 to +150 °C Notes Notes V V 1 1: Storage temperature refers to the case surface temperature on the center/top side of the PSRAM. Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 8.2 Pin Capacitance Table 21: Bare Die Pin Capacitance Parameter Input Pin Capacitance Output Pin Capacitance Note 1: spec’d at 25°C. Symbol CIN COUT Min Symbol CIN COUT Min Parameter Symbol Load Capacitance CL Note 1: System CL for the use of package Min Max 2 3 Unit pF pF Notes Max 6 8 Unit pF pF Notes Max 15 Unit pF Notes VIN=0V VOUT=0V Table 22: Package Pin Capacitance Parameter Input Pin Capacitance Output Pin Capacitance Note 1: spec’d at 25°C. VIN=0V VOUT=0V Table 23: Load Capacitance APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 20 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 8.3 Decoupling Capacitor Requirement It is required to have a decoupling capacitor on VDD pin for IO switchings and psram internal transient events. A low ESR 1μF ceramic cap is recommended. To minimize parasitic inductance, place the cap as close to VDD pin as possible. An optional 0.1μF can further improve high frequency transient response. CE# VDD C0 = 100nF CLK A/DQ 8.4 C1= 1µF VSS Operating Conditions Table 24: Operating Characteristics Parameter Min Max Unit Notes °C Operating Temperature (extended) -40 105 1 Operating Temperature (standard) -40 85 °C Note 1: Extended temp range of -40 to 105°C is only characterized; test condition is -32 to 105°C. APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 21 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 8.5 DC Characteristics Table 25: DC Characteristics Symbol VDD VDDQ VIH VIL VOH VOL ILI ILO Parameter Min Supply Voltage 2.7 I/O Supply Voltage 2.7 Input high voltage VDDQ-0.4 Input low voltage -0.2 Output high voltage (IOH=-0.2mA) 0.8 VDDQ Output low voltage (IOL=+0.2mA) Input leakage current Output leakage current Read/Write @ 13MHz ICC Read/Write @133MHz ISBEXT Standby current (extended temp) ISBSTD Standby current (standard temp) ISBSTDroom Standby current (standard room temp) Note 1: Spec’d up to 105°C. 2: Current is only characterized. 3: Without CLK toggling. ISB will be higher if CLK is toggling. 4: Slow Refresh. 5: Typical ISBSTDroom 100µA APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 22 of 26 Max 3.6 3.6 VDDQ+0.2 0.4 0.2 VDDQ 1 1 3 14 350 250 140 Unit V V V V V V µA µA mA mA µA µA µA Notes 2 2 1,3 3 3,4,5 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 8.6 ISB Partial Array Refresh Current Table 26: Typical PASR Current @ 25°C Standby Current @ 25°C PASR ISB –typical mean Full 100 1/2 90 1/4 85 1/8 80 Unit µA µA µA µA Notes 1,2 1,2 1,2 1,2 Unit µA µA µA µA Notes 2 2 2 2 Table 27: Typical PASR Current @ 85°C Standby Current @ 85°C PASR ISB –typical mean Full 195 1/2 169 1/4 156 1/8 150 Note Note 1: Slow Refresh current is only attainable by enabling Slow Refresh Frequency (see Table 16) 2: PASR Current is only characterized based on 64M density without CLK toggling. APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 23 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 8.7 AC Characteristics Table 28: READ/WRITE Timing -7 (133MHz) Symbol tCLK tCH/tCL tKHKL tCPH tCEM tCEM tCSP tCHD tSP tHD tRBXwait tHZ tRC tRC tPU tRP tRST Parameter CLK period Clock high/low width CLK rise or fall time CE# HIGH between subsequent burst operations Min 7.5 0.45 APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 0.55 1.0 18 CE# low pulse width CE# low pulse width CE# setup time to CLK rising edge CE# hold time from CLK falling edge Setup time to active CLK edge Hold time from active CLK edge Row Boundary Crossing Wait Time Chip disable to DQ/DQS output high-Z Write Cycle Read Cycle Device Initialization RESET# low pulse width Reset to CMD valid Max 3 2.5 2.5 1.1 1.1 30 60 60 150 1 2 24 of 26 -9 (109MHz) Min 9.2 0.45 Max 0.55 1.2 18 Unit ns tCLK ns Notes ns 4 4 µs Standard temp 1 1 µs Extended temp Minimum 3 clocks 65 6 tCLK ns ns ns ns ns ns ns ns µs µs µs 65 6 3 2.5 2.5 1.1 1.1 30 60 60 150 1 2 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM Table 29: DDR timing parameters Symbol tCQLZ Parameter Clock rising edge to DQS low tDQSCK tDQSQ tDS tDH tHP tQHS tQH DQS output access time from CLK DQS – DQ skew DQ and DM input setup time DQ and DM input hold time Half Period Datahold skew factor DQ output hold time from DQS APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 -7 (133MHz) Min Max 1 6 2 1.1 1.1 25 of 26 5.5 0.6 -9 (109MHz) Min Max 1 6 2 1.1 1.1 = min (tCH, tCL) 0.75 = tHP - tQHS 5.5 0.6 0.9 Unit ns Notes ns ns ns ns ns ns ns AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. All rights reserved APS6408L-3OBMx DDR OPI Xccela PSRAM 9 Change Log Version Date Description 1.0 Aug 24, 2017 Initial Version 1.5 Oct 31, 2017 Removed Hybrid 64, modified Write 4 bytes & absolute voltage, VIL/VIH 1.6 Nov 13, 2017 Modified spec of ISB, PASR, ICC 1.7 Dec 21, 2017 Revised RLC, WLC tables 1.8 Jan 01, 2018 Revised Fmax of bare die to 200MHz 1.9 Jun 13, 2018 Added part APS6408L-3OBM 2.0 Nov 26, 2018 Updated some latency wording; added operation latency table 2.1 Jan 17, 2019 Updated temperature; ordering information; unified part number to OBM for RBX read & special parts of STM32L4+ family 3.1a Aug 23 2019 Updated section 2, 4, 8.5, 8.7, Table 23 and Table 25 from OBM v3.1a, Updated section 6 from OBM BA v2.0; Updated section 6 from OC v1.7; Updated Table 5, Table 13, Table 15 3.2 Sep 28, 2019 Updated header and page 1; updated Table 26 and Table 27 3.3 Oct 24, 2019 Updated defaults setting in Table 7 3.4 Nov 07, 2019 Updated notes for Table 3, Table 14, Table 18, Table 25, section 7.5 and section 8.3 3.5 Nov 14, 2019 Updated notes in section 7.5, Table 15, Table 17 and Table 28 3.5a Nov 20, 2019 Update typo in section 7.7, 8.3 and 8.6 3.5b Dec 13, 2019 Revised the typo in section 7.7 APM Octal PSRAM Datasheet.pdf - Rev. 3.5b Dec 13, 2019 26 of 26 AP Memory reserves the right to change products and/or specifications without notice @2019 AP Memory. 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