SN74LS393M

SN74LS393 Dual 4−Stage Binary Counter The SN74LS393 contains a pair of high-speed 4-stage ripple counters. Each half of the LS393 operates as a Modulo-16 binary divider, with the last three stages triggered in a ripple fashion. In the LS393, the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs. Each half of each circuit type has a Master Reset input which responds to a HIGH signal by forcing all four outputs to the LOW state. • Dual Versions • Individual Asynchronous Clear for Each Counter • Typical Max Count Frequency of 50 MHz • Input Clamp Diodes Minimize High Speed Termination Effects http://onsemi.com LOW POWER SCHOTTKY 14 1 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current − High −0.4 mA IOL Output Current − Low 8.0 mA PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A 14 1 SOEIAJ M SUFFIX CASE 965 ORDERING INFORMATION Device Package Shipping SN74LS393N 14 Pin DIP 2000 Units/Box SN74LS393D SOIC−14 55 Units/Rail SN74LS393DR2 SOIC−14 2500/Tape & Reel SN74LS393M SOEIAJ−14 See Note 1 SN74LS393MEL SOEIAJ−14 See Note 1 1. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 2 1 Publication Order Number: SN74LS393/D SN74LS393 CONNECTION DIAGRAM DIP (TOP VIEW) VCC CP MR Q0 Q1 Q2 Q3 14 13 12 11 10 9 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 5 6 7 CP MR Q0 Q1 Q2 Q3 GND LOADING (Note a) PIN NAMES CP CP0 CP1 MR Q0 − Q3 Clock (Active LOW Going Edge) Input to +16 (LS393) Clock (Active LOW Going Edge) Input to ÷2 (LS390) Clock (Active LOW Going Edge) Input to ÷ 5 (LS390) Master Reset (Active HIGH) Input Flip−Flop Outputs NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. http://onsemi.com 2 HIGH LOW 0.5 U.L. 1.0 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 1.5 U.L. 0.25 U.L. 5 U.L. SN74LS393 FUNCTIONAL DESCRIPTION not occur simultaneously. This means that logic signals derived from combinations of these outputs will be subject to decoding spikes and, therefore, should not be used as clocks for other counters, registers or flip-flops. A HIGH signal on MR forces all outputs to the LOW state and prevents counting. Each half of the SN74LS393 operates in the Modulo 16 binary sequence, as indicated in the ÷ 16 Truth Table. The first flip-flop is triggered by HIGH-to-LOW transitions of the CP input signal. Each of the other flip-flops is triggered by a HIGH-to-LOW transition of the Q output of the preceding flip-flop. Thus state changes of the Q outputs do SN74LS393 LOGIC DIAGRAM (one half shown) CP K CP CD K CP J Q J CD K CP CD Q J K CP Q CD J Q MR Q0 Q1 Q2 TRUTH TABLE COUNT OUTPUTS Q3 Q2 Q1 Q0 0 1 2 3 L L L L L L L L L L H H L H L H 4 5 6 7 L L L L H H H H L L H H L H L H 8 9 10 11 H H H H L L L L L L H H L H L H 12 13 14 15 H H H H H H H H L L H H L H L H H = HIGH Voltage Level L = LOW Voltage Level http://onsemi.com 3 Q3 SN74LS393 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current Typ Max Unit 2.0 0.8 −0.65 2.7 −1.5 3.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = − 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 μA VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V 0.1 mA MR −0.4 mA CP, CP0 −1.6 mA CP1 −2.4 mA −100 mA VCC = MAX 26 mA VCC = MAX IOS Short Circuit Current (Note 2) ICC Power Supply Current VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 −20 VCC = MAX, VIN = 0.4 V 2. Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ 35 fMAX Maximum Clock Frequency CP0 to Q0 25 fMAX Maximum Clock Frequency CP1 to Q1 20 tPLH tPHL Propagation Delay, CP to Q0 tPLH tPHL tPHL CP to Q3 MR to Any Output Max Unit Test Conditions MHz MHz 12 13 20 20 ns 40 40 60 60 ns 24 39 ns CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit tW Clock Pulse Width 20 ns tW MR Pulse Width 20 ns trec Recovery Time 25 ns http://onsemi.com 4 Test Conditions VCC = 5.0 V SN74LS393 AC WAVEFORMS *CP 1.3 V 1.3 V tW tPLH tPHL Q 1.3 V 1.3 V Figure 1. MR & MS 1.3 V 1.3 V tW trec CP 1.3 V tPHL Q 1.3 V Figure 2. *The number of Clock Pulses required between tPHL and tPLH measurements can be determined from the appropriate Truth Table. http://onsemi.com 5 SN74LS393 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646−06 ISSUE M 14 8 B 1 7 A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10_ 0.38 1.01 SN74LS393 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A−03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− 1 0.25 (0.010) 7 G D 14 PL 0.25 (0.010) T B B M F J M K M M R X 45 _ C −T− SEATING PLANE P 7 PL S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SN74LS393 PACKAGE DIMENSIONS M SUFFIX SOEIAJ PACKAGE CASE 965−01 ISSUE O 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE M_ L 7 1 DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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