RTL8153-VC-CG
INTEGRATED 10/100/1000M ETHERNET
CONTROLLER FOR USB APPLICATIONS
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.2
29 September 2015
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8153-VC
Datasheet
COPYRIGHT
©2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
1.1
1.2
Release Date
2015/02/17
2015/04/01
2015/09/29
Summary
First release.
Revised section 8 Mechanical Dimensions, page 29.
Revised note in Table 7 LED Pins, page 7.
Revised section 5.5 Clock Pins, page 6.
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Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................3
3.
SYSTEM APPLICATIONS...............................................................................................................................................4
4.
PIN ASSIGNMENTS .........................................................................................................................................................4
4.1.
5.
PIN DESCRIPTIONS.........................................................................................................................................................5
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
6.
PACKAGE IDENTIFICATION ...........................................................................................................................................4
POWER MANAGEMENT PIN ..........................................................................................................................................5
SPI (SERIAL PERIPHERAL INTERFACE) FLASH PINS .....................................................................................................5
EEPROM PINS ............................................................................................................................................................5
TRANSCEIVER INTERFACE PINS....................................................................................................................................6
CLOCK PINS .................................................................................................................................................................6
REGULATOR AND REFERENCE PINS..............................................................................................................................6
LED PINS .....................................................................................................................................................................7
POWER AND GROUND PINS ..........................................................................................................................................7
GPIO PIN .....................................................................................................................................................................7
USB INTERFACE PINS ..................................................................................................................................................8
FUNCTIONAL DESCRIPTION.......................................................................................................................................9
6.1.
USB INTERFACE ..........................................................................................................................................................9
6.1.1. USB Configurations................................................................................................................................................9
6.1.2. Endpoint 0 ..............................................................................................................................................................9
6.1.3. Endpoint 1 Bulk-IN.................................................................................................................................................9
6.1.4. Endpoint 2 Bulk-OUT.............................................................................................................................................9
6.1.5. Endpoint 3 Interrupt-IN..........................................................................................................................................9
6.2.
CUSTOMIZABLE LED CONFIGURATION ......................................................................................................................10
6.3.
PHY TRANSCEIVER ...................................................................................................................................................12
6.3.1. PHY Transmitter...................................................................................................................................................12
6.3.2. PHY Receiver .......................................................................................................................................................12
6.3.3. Link Down Power Saving Mode ...........................................................................................................................13
6.3.4. Next Page .............................................................................................................................................................13
6.4.
EEPROM INTERFACE ................................................................................................................................................13
6.5.
SPI (SERIAL PERIPHERAL INTERFACE) FLASH............................................................................................................14
6.6.
POWER MANAGEMENT...............................................................................................................................................14
6.7.
LINK POWER MANAGEMENT (LPM) ..........................................................................................................................15
6.8.
PROTOCOL OFFLOAD .................................................................................................................................................15
6.9.
WAKE PACKET DETECTION (WPD) ...........................................................................................................................16
6.10.
‘REALWOW!’ (WAKE-ON-WAN) TECHNOLOGY ......................................................................................................16
6.11.
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................16
6.12.
LAN DISABLE MODE .................................................................................................................................................16
6.13.
ALWAYS ON ALWAYS CONNECTED ...........................................................................................................................17
6.14.
SWITCHING REGULATOR ............................................................................................................................................17
6.15.
LDO REGULATOR ......................................................................................................................................................17
6.16.
DRIVER AUTO-INSTALL MODE ..................................................................................................................................18
7.
CHARACTERISTICS......................................................................................................................................................19
7.1.
7.2.
7.3.
7.4.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................19
RECOMMENDED OPERATING CONDITIONS .................................................................................................................19
CRYSTAL REQUIREMENTS ..........................................................................................................................................20
OSCILLATOR REQUIREMENTS ....................................................................................................................................20
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7.5.
ENVIRONMENTAL CHARACTERISTICS ........................................................................................................................21
7.6.
DC CHARACTERISTICS ...............................................................................................................................................21
7.7.
REFLOW PROFILE RECOMMENDATIONS .....................................................................................................................22
7.8.
AC CHARACTERISTICS ...............................................................................................................................................22
7.8.1. SPI EEPROM Interface Timing............................................................................................................................22
7.8.2. TWSI EEPROM Interface Timing.........................................................................................................................23
7.8.3. SPI Flash Commands ...........................................................................................................................................25
7.8.4. SPI Flash Interface Timing...................................................................................................................................27
7.8.5. SPI Flash Type Supported ....................................................................................................................................28
8.
MECHANICAL DIMENSIONS......................................................................................................................................29
9.
ORDERING INFORMATION........................................................................................................................................30
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List of Tables
TABLE 1.
TABLE 2.
TABLE 3.
TABLE 4.
TABLE 5.
TABLE 6.
TABLE 7.
TABLE 8.
TABLE 9.
TABLE 10.
TABLE 11.
TABLE 12.
TABLE 13.
TABLE 14.
TABLE 15.
TABLE 16.
TABLE 17.
TABLE 18.
TABLE 19.
TABLE 20.
TABLE 21.
TABLE 22.
TABLE 23.
TABLE 24.
TABLE 25.
TABLE 26.
TABLE 27.
TABLE 28.
TABLE 29.
TABLE 30.
TABLE 31.
POWER MANAGEMENT PIN ...........................................................................................................................................5
SPI FLASH PINS ............................................................................................................................................................5
EEPROM PINS .............................................................................................................................................................5
TRANSCEIVER INTERFACE PINS ....................................................................................................................................6
CLOCK PINS ..................................................................................................................................................................6
REGULATOR AND REFERENCE PINS ..............................................................................................................................6
LED PINS......................................................................................................................................................................7
POWER AND GROUND PINS ...........................................................................................................................................7
GPIO PIN ......................................................................................................................................................................7
USB INTERFACE PINS ..................................................................................................................................................8
LED SELECT (OCP REGISTER OFFSET DD90H~DD91H)...........................................................................................10
CUSTOMIZED LEDS ...................................................................................................................................................10
FIXED LED MODE .....................................................................................................................................................10
LED FEATURE CONTROL-1........................................................................................................................................11
LED FEATURE CONTROL-2........................................................................................................................................11
LED OPTION 1 & OPTION 2 SETTINGS .......................................................................................................................11
EEPROM INTERFACE ................................................................................................................................................13
SPI FLASH INTERFACE ...............................................................................................................................................14
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................19
RECOMMENDED OPERATING CONDITIONS .................................................................................................................19
CRYSTAL REQUIREMENTS ..........................................................................................................................................20
OSCILLATOR REQUIREMENTS ....................................................................................................................................20
ENVIRONMENTAL CHARACTERISTICS ........................................................................................................................21
DC CHARACTERISTICS ...............................................................................................................................................21
REFLOW PROFILE RECOMMENDATIONS .....................................................................................................................22
SPI EEPROM ACCESS TIMING PARAMETERS ............................................................................................................23
TWSI EEPROM ACCESS TIMING PARAMETERS ........................................................................................................24
SPI FLASH COMMANDS..............................................................................................................................................25
SPI FLASH ACCESS TIMING PARAMETERS .................................................................................................................27
SPI FLASH TYPES SUPPORTED ...................................................................................................................................28
ORDERING INFORMATION ..........................................................................................................................................30
List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
FIGURE 8.
FIGURE 9.
FIGURE 10.
FIGURE 11.
FIGURE 12.
PIN ASSIGNMENTS .......................................................................................................................................................4
SPI EEPROM INTERFACE TIMING ............................................................................................................................22
TWSI EEPROM INTERFACE TIMING-1 .....................................................................................................................23
TWSI EEPROM INTERFACE TIMING-2 .....................................................................................................................23
TWSI EEPROM INTERFACE TIMING-3 .....................................................................................................................24
TWSI EEPROM INTERFACE TIMING-4 .....................................................................................................................24
WREN/WRDI COMMAND SEQUENCE .......................................................................................................................25
READ COMMAND SEQUENCE .....................................................................................................................................25
PAGE PROGRAM COMMAND SEQUENCE ....................................................................................................................26
SECTOR/BLOCK ERASE COMMAND SEQUENCE .........................................................................................................26
CHIP ERASE COMMAND SEQUENCE ..........................................................................................................................26
SPI FLASH INTERFACE TIMING .................................................................................................................................27
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1.
General Description
The Realtek RTL8153-VC-CG 10/100/1000M Ethernet controller combines a triple-speed IEEE 802.3
compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, USB 3.0 bus
controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal
technology, the RTL8153-VC offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP
(10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction, polarity correction,
adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented to provide robust transmission and reception capabilities. The RTL8153-VC features
embedded One-Time-Programmable (OTP) memory that can replace the external EEPROM
(93C46/93C56/93C66/TWSI).
The RTL8153-VC features USB 3.0 to provide higher bandwidth and improved protocols for data
exchange between the host and the device. USB 3.0 also offers more advanced power management
features for energy saving.
Advanced Configuration Power management Interface (ACPI)—power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM)—is
supported to achieve the most efficient power management possible. In addition to the ACPI feature,
remote wake-up (including AMD Magic Packet and Microsoft Wake-Up Frame) is supported in both
ACPI and APM (Advanced Power Management) environments.
The RTL8153-VC supports Microsoft Wake Packet Detection (WPD) to provide Wake-Up Frame
information to the OS, e.g., PatternID, OriginalPacketSize, SavedPacketSize, SavedPacketOffset, etc.
WPD helps prevent unwanted/unauthorized wake-up of a sleeping computer.
The RTL8153-VC supports ‘RealWoW!’ technology to enable remote wake-up of a sleeping PC through
the Internet. This feature allows PCs to reduce power consumption by remaining in low power sleeping
state until needed.
Note: The ‘RealWoW!’ service requires registration on first time use.
The RTL8153-VC supports Protocol offload. It offloads some of the most common protocols to NIC
hardware in order to prevent spurious wake-up and further reduce power consumption. The RTL8153-VC
can offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving state.
The RTL8153-VC supports the ECMA (European Computer Manufacturers Association) proxy for
sleeping hosts standard. The standard specifies maintenance of network connectivity and presence via
proxies in order to extend the sleep duration of higher-powered hosts. It handles some network tasks on
behalf of the host, allowing the host to remain in sleep mode for longer periods. Required and optional
behavior of an operating proxy includes generating reply packets, ignoring packets, and waking the host.
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The RTL8153-VC supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE). IEEE
802.3az-2010 operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation
in Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on
both sides of the link to save power.
The RTL8153-VC is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum
features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local
Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting
performance when in operation on a network server.
The RTL8153-VC is suitable for multiple market segments and emerging applications, such as desktop,
mobile, workstation, server, communications platforms, docking station, and embedded applications.
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2.
Features
Hardware
Software Offload
Integrated 10/100/1000M transceiver
Auto-Negotiation with Next Page capability
Supports USB 3.0, 2.0, and 1.1
Microsoft NDIS5, NDIS6 Checksum
Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send v1
and Large send v2) support
Supports CDC-ECM
Supports jumbo frame to 9K bytes
Supports LPM (Link Power Management),
U1/U2/U3 at SuperSpeed, and L1/L2 at
HighSpeed
IEEE
Supports Full Duplex flow control
(IEEE 802.3x)
Supports pair swap/polarity/skew correction
Crossover Detection & Auto-Correction
Supports Wake-On-LAN and ‘RealWoW!’
(Wake-On-WAN) Technology (see note 1)
Fully compliant with IEEE 802.3,
IEEE 802.3u, and IEEE 802.3ab
Supports IEEE 802.1P Layer 2 Priority
Encoding
Supports IEEE 802.1Q VLAN tagging
Supports IEEE 802.3az-2010 (EEE)
Supports ECMA-393 ProxZzzy Standard for
sleeping hosts (see note 1)
Note 1. Select between RealWoW! or ECMA,
only one feature can be active at a time.
Supports power down/link down power
saving
Transmit/Receive on-chip buffer support
Microsoft AOAC (Always On Always
Connected)
Supports 16-set 128-byte Wake-Up Frame
pattern exact matching
EEPROM Interface
Supports link change wake up
Embedded OTP memory can replace
external EEPROM
Built-in switching regulator and LDO
regulator
Supports Microsoft WPD (Wake Packet
Detection)
Supports Customizable LEDs
Supports Protocol Offload (ARP & NS) at
all speeds
Supports hardware CRC (Cyclic
Redundancy Check) function
Intel CPPM (Converged Platform Power
Management)
LAN disable with GPIO pin
Supports L1 with 3ms BESL (USB 2.0)
Supports 25MHz or 48MHz clock source
SPI Flash Interface
Dynamic LTM messaging (USB 3.0)
Supports Legacy PXE (eHCI and xHCI) &
UEFI PXE
Supports U1/U2/U3 (USB 3.0)
Supports selective suspend
48-pin QFN ‘Green’ package
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3.
4.
System Applications
USB 10/100/1000M Ethernet on Motherboard, Dongle, Notebook, Docking station, or Embedded
system
Pin Assignments
Figure 1.
Pin Assignments
4.1. Package Identification
Green package is indicated by the ‘G’ in GXXXV (Figure 1). The version number is shown in the
location marked ‘V’.
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5.
Pin Descriptions
The signal type codes below are used in the following tables:
I: Input
O: Output
P: Power
5.1. Power Management Pin
Symbol
LANWAKEB
Type
O
Pin No
39
Table 1. Power Management Pin
Description
Power Management Event Output Pin (Active Low).
5.2. SPI (Serial Peripheral Interface) Flash Pins
Symbol
SPICSB
SPISDO
SPISDI
SPISCK
Type
O
I
O
O
Pin No
30
41
38
32
Table 2. SPI Flash Pins
Description
SPI Flash Chip Select.
Input from SPI Flash Serial Data Output Pin.
Output to SPI Flash Serial Data Input Pin.
SPI Flash Serial Data Clock.
5.3. EEPROM Pins
Table 3. EEPROM Pins
Symbol
Type
Pin No Description
EESK
O
32
Serial Data Clock for 93C46/93C56/93C66.
EEDI: Output to serial data input pin of EEPROM (93C46/93C56/93C66)
SDA: Data interface for TWSI EEPROM
Refer to the reference schematic for strapping pin information.
EEDI/SDA
IO
38
All strapping pins are power-on latch pins.
Power-on latch high voltage: TWSI EEPROM
Power-on latch low voltage: SPI EEPROM
Input from Serial Data Output Pin of EEPROM (93C46/93C56/93C66).
Refer to the reference schematic for strapping pin information.
EEDO
I
41
All strapping pins are power-on latch pins.
Power-on latch high voltage: 93C46
Power-on latch low voltage: 93C56/93C66
EECS: EEPROM (93C46/93C56/93C66) Chip Select
EECS/SCL
O
40
SCL: Serial Data Clock for TWSI EEPROM
Note: The RTL8153-VC will complete eFUSE auto-load before EEPROM auto-load, and determine the type of EEPROM
(93C46/93C56) by the ‘select 93C46/56/66’ eFUSE auto-load value. 1 indicates 93C46; 0 indicates 93C56/93C66.
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5.4. Transceiver Interface Pins
Symbol
Type
Pin No
MDIP0
IO
2
MDIN0
IO
3
MDIP1
IO
5
MDIN1
IO
6
MDIP2
MDIN2
MDIP3
MDIN3
IO
IO
IO
IO
7
8
10
11
Table 4. Transceiver Interface Pins
Description
In MDI mode, this is the first pair in 1000Base-T, i.e., the BI_DA+/- pair, and is
the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair
in 10Base-T and 100Base-TX.
In MDI mode, this is the second pair in 1000Base-T, i.e., the BI_DB+/- pair, and is
the receive pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit
pair in 10Base-T and 100Base-TX.
In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
5.5. Clock Pins
Table 5. Clock Pins
Description
Input of 25MHz Clock Reference.
CKXTAL1
I
Connect to GND if an external clock source drives CKXTAL2.
Output of 25MHz Clock Reference.
CKXTAL2
IO
45
Input of 25MHz or 48MHz External Clock Source.
Power-Up Strapping Pin.
XTALDET
I
37
Power-on latch high voltage: 25MHz clock source
Power-on latch low voltage: 48MHz clock source
Note: When a 25MHz clock is used the XTALDET pin must be pulled high by a resistor during power-up. When a 48MHz
clock is used the XTALDET pin must be pulled low by a resistor during power-up.
Symbol
Type
Pin No
44
5.6. Regulator and Reference Pins
Symbol
REGOUT
Type
O
ENSWREG
I
VDDREG
P
AVDD33
P
DVDD10_UPS
P
RSET
I
Table 6. Regulator and Reference Pins
Description
Switching Regulator 1.2V Output.
3.3V: Enable switching regulator
33
0V: Disable switching regulator, and enable external 1.2V input mode
34, 35
Digital 3.3V Power Supply for Switching/LDO Regulator.
Linear Regulator (LDO) 3.3V Output.
25
Note: The embedded LDO is designed for RTL8153-VC internal use only. Do not
provide this power source to other devices.
Linear Regulator (LDO) 1.2V Output.
27
Note: The embedded LDO is designed for RTL8153-VC internal use only. Do not
provide this power source to other devices.
47
Reference (External Resistor Reference).
Pin No
36
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5.7. LED Pins
Table 7. LED Pins
Description
See Section 6.2 Customizable LED Configuration, Page 10 for Details.
Symbol
Type
Pin No
LED0
O
30
LED1
O
32
LED2
O
41
Note: In pre-link suspend state (power-on and USB disconnected), the LED pin output voltage depends on both the
Ethernet connection (link up/link down) and the LED setting (high active/low active).
In LAN disabled state, the LED pin output voltage is 0V.
5.8. Power and Ground Pins
Table 8. Power and Ground Pins
Symbol
Type
Pin No
Description
VDD5
P
26
Analog 5.0V Power Supply.
AVDD33
P
1, 12, 25, 48 Analog 3.3V Power Supply.
DVDD33
P
28, 43
Digital 3.3V Power Supply.
AVDD10
P
4, 9, 46
Analog 1.2V Power Supply.
DVDD10
P
31, 42
Digital 1.2V Power Supply.
DVDD10_UPS
P
27
Digital 1.2V Uninterruptible Power Supply.
U3VDD10
P
13, 20
USB 3.0 1.2V Power Supply.
U2VDD10
P
24
USB 2.0/USB 1.1 1.2V Power Supply.
U3GND
P
16, 17
USB 3.0 Ground.
U2GND
P
21
USB 2.0/USB 1.1 Ground.
GND
P
49
Ground (Exposed Pad).
Note: Refer to the most updated schematic circuit for correct configuration.
5.9. GPIO Pin
Symbol
GPIO
Type
Pin No
IO
29
Table 9. GPIO Pin
Description
General Purpose Input/Output Pin.
Link OK feature: Output Pin (Active High)
Power Saving Feature: Output Pin (Active Low)
LAN Disable Mode: Input pin (Active Low)
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5.10. USB Interface Pins
Symbol
U3SSRXP
U3SSRXN
U3SSTXP
U3SSTXN
U2DP
U2DM
Type
I
I
O
O
IO
IO
Table 10. USB Interface Pins
Pin No
Description
14
USB 3.0 Super-Speed Receive Differential Pair.
15
USB 3.0 Super-Speed Receive Differential Pair.
18
USB 3.0 Super-Speed Transmit Differential Pair.
19
USB 3.0 Super-Speed Transmit Differential Pair.
23
USB 2.0/USB 1.1 Differential Signal Pair.
22
USB 2.0/USB 1.1 Differential Signal Pair.
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6.
Functional Description
6.1. USB Interface
The SIE (Serial Interface Engine) employs a robust hardwired USB protocol implementation so that the
entire USB interface operation can be done without firmware intervention. For all three types of End
Points (Bulk-IN, Bulk-OUT, and Interrupt-IN), appropriate responses and handshake signals are
generated by the SIE. The SIE analog transceiver complies fully with driver and receiver characteristics
defined in USB Specification Rev. 3.0.
6.1.1.
USB Configurations
The RTL8153-VC supports two networking configurations; ECM (Ethernet Control Model) configuration
and in-house configuration. The ECM configuration complies with CDC-ECM, and is a general Ethernet
networking model that enables network communication without installing additional vendor specific
drivers. The in-house configuration requires a vendor specific driver to support enhanced features and
optimized performance.
6.1.2.
Endpoint 0
All USB devices support a common access mechanism for accessing information through this control
pipe. Associated with the control pipe at endpoint 0 is the information required to completely describe the
USB device. This pipe also provides the register read and write to the RTL8153-VC.
6.1.3.
Endpoint 1 Bulk-IN
The maximum Bulk-IN packet size is 1024 bytes. Each Ethernet packet is transferred to the HOST by this
Endpoint. If the Ethernet packet is larger than 1024 bytes, the RTL8153-VC splits the Ethernet packet
into multiples of 1024 bytes. The HOST treats USB packets that are less than 1024 bytes or are equal to
zero as End of Ethernet packets.
6.1.4.
Endpoint 2 Bulk-OUT
The HOST sends the USB packet to Ethernet. If the Ethernet packet is larger than 1024 bytes, the Host
will send the Ethernet packet in multiples of 1024 bytes. A USB packet that is less than 1024 bytes or is
equal to zero is treated as an End of Ethernet packet.
The Ethernet packet (containing multiple USB packets) will be queued in the TX FIFO and transmitted
when possible. If the Ethernet packet is transmitted without error, the TX FIFO space that was occupied
by the transmitted Ethernet packet will be released. If the TX FIFO is full, the RTL8153-VC will respond
with a NRDY when the host tries to Bulk-OUT more USB packets.
It is possible to have multiple Ethernet packets in the TX FIFO simultaneously. If an Ethernet packet is to
be transmitted but experiences collisions more than 16 times (default), this is called a transmit abort and
the packet will be skipped for transmission by the RTL8153-VC.
6.1.5.
Endpoint 3 Interrupt-IN
The Interrupt Endpoint (EP3) can be used to poll the current ALDPS state, EEE capability, TX/RX flow
control enable, Connection Speed, Duplex mode, and link status of the RTL8153-VC.
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Datasheet
6.2. Customizable LED Configuration
The RTL8153-VC supports customizable LED operation modes via OCP address DD90h~DD91h. Table
11 describes the different LED actions.
Bit
15:12
11:8
7:4
3:0
Table 11. LED Select (OCP Register Offset DD90h~DD91h)
Symbol
RW
Description
LEDCntl
RW
LED Feature Control.
LEDSEL2
RW
LED Select for PINLED2.
LEDSEL1
RW
LED Select for PINLED1.
LEDSEL0
RW
LED Select for PINLED0.
When implementing customized LEDs:
Configure OCP address DD90h to support your own LED signals. For example, if the value in the OCP
address DD90h is 0CA9h (0000110010101001b), the LED actions are:
•
LED 0: On only in 10M mode, with blinking during TX/RX
•
LED 1: On only in 100M mode, with blinking during TX/RX
•
LED 2: On only in 1000M mode, with blinking during TX/RX
Speed
LED 0
LED 1
LED 2
Feature Control
Link 10M
Bit 0
Bit 4
Bit 8
Bit 12
Table 12. Customized LEDs
LINK
Link 100M
Link 1000M
Bit 1
Bit 2
Bit 5
Bit 6
Bit 9
Bit 10
Bit 13
Bit 14
ACT/Full
Bit 3
Bit 7
Bit 11
Bit 15
Note: There are two special modes:
LED OFF Mode: Set all bits to 0. All LED pin output become floating (power saving).
Fixed LED Mode: Set Option 1 LED table Mode: LED0=LED1=LED2=1 or 2 (see Table 13).
Bit31~Bit0 Value
1XXX 0001 0001 0001
1XXX 0010 0010 0010
Note: ‘X’ indicates ‘irrelevant’.
Table 13. Fixed LED Mode
LED0
LED1
ACT
LINK
Transmit
LINK
Integrated 10/100/1000M Ethernet Controller for USB Applications
10
LED2
Full Duplex + Collision
Receive
Track ID: JATR-8275-15
Rev. 1.2
RTL8153-VC
Datasheet
Feature Control
0
Bit12
LED0 Low Active
1
LED0 High Active
LED Pin
LINK=0
LINK>0
10
ACT=0
Floating
Selected Speed LINK
Link Bit
100
1000
Table 14. LED Feature Control-1
Bit13
Bit14
LED1 Low Active
LED2 Low Active
LED1 High Active
LED2 High Active
Bit15
Indicates Option 1 of Table 16
is Selected
Indicates Option 2 of Table 16
is Selected
Table 15. LED Feature Control-2
ACT=1
All Speed ACT
Option 1 (see Table 16): Selected Speed LINK+ Selected Speed ACT
Option 2 (see Table 16): Selected Speed LINK+ All Speed ACT
Table 16. LED Option 1 & Option 2 Settings
Active Bit
Description
Link
Option 1 LED
Activity
0
LED Off
1
Act10+Act100+Act1000
0
Link1000
1
Link1000
Act1000
0
Link100
1
Link100
Act100
0
Link100+Link1000
1
Link100+Link1000
Act100+Act1000
0
Link10
1
Link10
Act10
0
Link10+Link1000
1
Link10+Link1000
Act10+Act1000
0
Link10+Link100
1
Link10+Link100
Act10+Act100
0
Link10+Link100+Link1000
1
Link10+Link100+Link1000
Act10+Act100+Act1000
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Note:
Act10 = LED blinking when Ethernet packets transmitted/received at 10Mbps.
Act100 = LED blinking when Ethernet packets transmitted/received at 100Mbps.
Act1000 = LED blinking when Ethernet packets transmitted/received at 1000Mbps.
Link10 = LED lit when Ethernet connection established at 10Mbps.
Link100 = LED lit when Ethernet connection established at 100Mbps.
Link1000 = LED lit when Ethernet connection established at 1000Mbps.
Integrated 10/100/1000M Ethernet Controller for USB Applications
11
Option 2 LED
Activity
Act10+Act100+Act1000
Act10+Act100+Act1000
Act10+Act100+Act1000
Act10+Act100+Act1000
Act10+Act100+Act1000
Act10+Act100+Act1000
Act10+Act100+Act1000
Act10+Act100+Act1000
Track ID: JATR-8275-15
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RTL8153-VC
Datasheet
6.3. PHY Transceiver
6.3.1.
PHY Transmitter
Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the
RTL8153-VC operates at 10/100/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), or CAT.3
UTP cable (10Mbps).
GMII (1000Mbps) Mode
The RTL8153-VC’s PCS layer receives data bytes from the MAC through the GMII interface and
performs the generation of continuous code-groups through 4D-PAM5 coding technology. These code
groups are passed through a waveform-shaping filter to minimize EMI effects, and are transmitted onto
the 4-pair CAT5 cable at 125MBaud/s through a D/A converter.
MII (100Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into
5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are
converted to 125MHz NRZ and NRZI signals. The NRZI signals are passed to the MLT3 encoder, then to
the D/A converter and transmitted onto the media.
MII (10Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into
10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is
transmitted onto the media by the D/A converter.
6.3.2.
PHY Receiver
GMII (1000Mbps) Mode
Input signals from the media pass through the sophisticated on-chip hybrid circuit to separate the
transmitted signal from the input signal for effective reduction of near-end echo. The received signal is
processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.
The RX MAC retrieves the packet data from the receive MII/GMII interface and sends it to the RX
Buffer Manager.
MII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII
interface in 4-bit-wide nibbles at a clock speed of 25MHz.
MII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the MII interface at a clock speed of 2.5MHz.
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6.3.3.
Link Down Power Saving Mode
The RTL8153-VC implements link-down power saving, greatly cutting power consumption when the
network cable is disconnected. The RTL8153-VC automatically enters link down power saving mode ten
seconds after the cable is disconnected from it. Once it enters link down power saving mode, it transmits
normal link pulses on its TX pins and continues to monitor the RX pins to detect incoming signals. After
it detects an incoming signal, it wakes up from link down power saving mode and operates in normal
mode according to the result of the connection.
6.3.4.
Next Page
If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the
two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and
Reg8 as defined in IEEE 802.3ab.
6.4. EEPROM Interface
Both SPI and TWSI EEPROM interfaces are supported. The SPI interface utilizes a
93C46/93C56/93C66, which is 1K-bit/2K-bit/4K-bit, respectively, EEPROM. The EEPROM interface
permits the RTL8153-VC to read from, and write data to, an external serial EEPROM device.
Values in the internal eFUSE memory or external EEPROM allow default register values to be overridden
following a power-on or software EEPROM auto-load command. The RTL8153-VC will auto-load
values from the eFUSE or EEPROM. If the EEPROM is not present and eFUSE auto-load is bypassed,
the RTL8153-VC initialization uses default values for the appropriate Configuration and Operational
Registers. Software can read and write to the EEPROM using bit-bang accesses via the 9346CR Register.
The EEPROM SPI interface consists of EESK, EECS, EEDO, and EEDI. The TWSI interface shares
SCL/SDA with EECS/EEDI.
The correct EEPROM (i.e., 93C46/93C56/93C66) must be used in order to ensure proper LAN function.
Table 17. EEPROM Interface
Description
EECS: EEPROM (93C46/93C56/93C66) chip select
SCL: Serial data clock for TWSI EEPROM
EESK
Serial Data Clock for EEPROM (93C46/93C56/93C66).
EEDI/SDA
EEDI: Output to serial data input pin of EEPROM (93C46/93C56/93C66)
SDA: Data interface for TWSI EEPROM
EEDO
Input from Serial Data Output Pin of EEPROM (93C46/93C56/93C66).
Note: The TWSI interface should comply with the specifications shown in section 7.8.2.
EEPROM
EECS/SCL
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6.5. SPI (Serial Peripheral Interface) Flash
SPI Flash is enabled by the RTL8153-VC through the Chip Select pin, and accessed via a 3-wire interface
consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SPI flash
utilizes an 8-bit instruction register. All instructions, addresses, and data are transferred with the MSB
first and start with a high-to-low transition.
Compared to a parallel bus interface, the Serial Peripheral Interface provides simpler wiring and much
less interaction (crosstalk) among the conductors in the cable. This minimizes the number of conductors,
pins, and the IC package size, reducing the cost of making, assembling, and testing the electronics.
SPI Flash
SO
SI
SCK
CSB
Table 18. SPI Flash Interface
Description
Input Data Bus.
Output Data Bus.
SPI Flash Serial Data Clock.
SPI Flash Chip Select.
6.6. Power Management
The RTL8153-VC complies with ACPI (Rev 1.0, 1.0b, 2.0), Network Device Class Power Management
Reference Specification (V1.0a), such as to support an Operating System-directed Power Management
(OSPM) environment.
The RTL8153-VC can monitor the network for a Wake-Up Frame or a Magic Packet, and notify the
system via the USB interface when such a packet or event occurs. The system is then restored to a normal
state to process incoming jobs.
When the RTL8153-VC is in power down mode:
•
The RX state machine is stopped. The RTL8153-VC monitors the network for wake-up events such as
a Magic Packet and Wake-Up Frame in order to wake-up the system. When in power down mode, the
RTL8153-VC will not reflect the status of any incoming packets in the ISR register and will not
receive any packets into the RX on-chip buffer.
•
The on-chip buffer status and packets that have already been received into the RX on-chip buffer
before entering power down mode are held by the RTL8153-VC.
•
Transmission is stopped. USB transactions are stopped. The TX on-chip buffer is held.
•
After being restored to D0 state, the RTL8153-VC transmits data that was not moved into the TX
on-chip buffer during power down mode. Packets that were not transmitted completely last time are
re-transmitted.
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Magic Packet Wake-Up occurs only when the following conditions are met:
•
The destination address of the received Magic Packet is acceptable to the RTL8153-VC, e.g., a
broadcast, multicast, or unicast packet addressed to the current RTL8153-VC adapter.
•
The received Magic Packet does not contain a CRC error.
•
The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID)
in any part of a valid Ethernet packet.
A Wake-Up Frame event occurs only when the following conditions are met:
•
The destination address of the received Wake-Up Frame is acceptable to the RTL8153-VC, e.g., a
broadcast, multicast, or unicast address to the current RTL8153-VC adapter.
•
The received Wake-Up Frame does not contain a CRC error.
•
The 16-bit CRC of the received Wake-Up Frame matches the 16-bit CRC of the sample Wake-Up
Frame pattern given by the local machine’s OS. Or, the RTL8153-VC is configured to allow direct
packet wake-up, e.g., a broadcast, multicast, or unicast network packet.
Note: 16-bit CRC: The RTL8153-VC supports 16-set 16-bit CRC wake-up frames (covering 128 mask
bytes from offset 0 to 127 of any incoming network packet). CRC16 polynomial=x16+x12+x5+1.
6.7. Link Power Management (LPM)
The RTL8153-VC supports full USB Link Power Management (LPM). It provides an efficient way for
the host to manage power consumption. The four power management states are L0, L2, L3 in USB 2.0,
and L1 in extended USB 2.0.
USB 3.0 also defines four power management states: U0, U1, U2, and U3. If host and hub support LPM,
the host/hub can put the device into a low power state. The RTL8153-VC will deactivate some of its
circuits to reduce power consumption in the low power state, and go back to full functionality in active
state.
Refer to http://www.usb.org/developers/docs/.
6.8. Protocol Offload
Protocol offload is a task offload supported by Microsoft Windows 7. It maintains a network presence for
a sleeping higher power host. Protocol offload prevents spurious wake-up and further reduces power
consumption. It maintains connectivity while hosts are asleep, including receiving requests from other
nodes on the network, ignoring packets, generating packets while in the sleep state (e.g., the Ethernet
Controller will generate ARP responses if the same MAC and IPv4 address are provided in the
configuration data), and intelligently waking up host systems. The RTL8153-VC supports the ECMA
(European Computer Manufacturers Association) specification including proxy configuration and
management, IPv4 ARP, IPv6 NDP, and wake-up packets. The RTL8153-VC also supports optional
ECMA items such as QoS tagged packets and duplicate address detection.
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Track ID: JATR-8275-15
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6.9. Wake Packet Detection (WPD)
The RTL8153-VC supports Microsoft Wake Packet Detection (WPD) to provide Wake-Up Frame
information to the OS, e.g., PatternID, OriginalPacketSize, SavedPacketSize, SavedPacketOffset, etc.
WPD helps prevent unwanted/unauthorized wake-up of a sleeping computer.
Refer to the Microsoft Wake Packet Detection (WPD) Interface Specification for details
(http://msdn.microsoft.com/en-us/library/hh440160(v=vs.85).aspx).
6.10. ‘RealWoW!’ (Wake-On-WAN) Technology
The RTL8153-VC supports Realtek 'RealWoW!' technology that allows the RTL8153-VC to
send keep-alive packets to the Wake Server when the PC is in sleeping mode. Realtek
'RealWoW!' can pass wake-up packets through a NAT (Network Address Translation) device.
This feature allows PCs to reduce power consumption by remaining in low power sleeping
state until needed.
Users can login into the Wake Server via the Internet to wake the selected sleeping PC. Registration of
Account information to the Wake Server is required on first time use.
6.11. Energy Efficient Ethernet (EEE)
The RTL8153-VC supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE), at
10Mbps, 100Mbps, and 1000Mbps. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being
transmitted, the system goes to Low Power Idle mode to save power. Once packets need to be
transmitted, the system returns to normal mode, and does this without changing the link status and
without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode most of the circuits are disabled, however,
the transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer
protocols and applications.
EEE also specifies a negotiation method to enable link partners to determine whether EEE is supported
and to select the best set of parameters common to both devices.
Refer to http://www.ieee802.org/3/az/index.html for more details.
6.12. LAN Disable Mode
The RTL8153-VC supports ‘LAN Disable Mode’ that can use an external signal to control whether the
NIC is enabled or disabled.
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6.13. Always On Always Connected
The RTL8153-VC supports Microsoft’s AOAC (Always On Always Connected) model. The AOAC
platform can enter the system state ‘Connected Standby’ and allow the RTL8153-VC to enter a
low-power state. The RTL8153-VC will maintain Layer 2 connectivity and generate a wake signal when
one of the following conditions is satisfied:
•
Link status becomes ‘connected’
•
Link status becomes ‘disconnected’
•
Receives a WOL pattern
•
Receives a wildcard pattern
6.14. Switching Regulator
The RTL8153-VC incorporates a state-of-the-art switching regulator that requires a well-designed PCB
layout in order to achieve good power efficiency and lower the output voltage ripple and input overshoot.
Note that the switching regulator 1.2V output pin (REGOUT) must be connected only to DVDD10,
AVDD10, U3VDD10, and U2VDD10 (do not provide this power source to other devices).
6.15. LDO Regulator
The RTL8153-VC incorporates two linear Low-Dropout (LDO) regulators that feature high power supply
ripple rejection and low output noise. The RTL8153-VC embedded LDO regulators do not require power
inductors on the PCB; only an output capacitor between its output and analog ground for phase
compensation, which saves cost and PCB real estate.
The output capacitors (and bypass capacitors) should be placed as close as possible to the power pins for
adequate filtering.
Note 1: The embedded LDO is designed for the RTL8153-VC internal use only. Do not provide this power
source to other devices.
Note 2: The digital LDO output pin (DVDD10_UPS) should be separated from the other 1.2V SWR output
pin (REGOUT).
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6.16. Driver Auto-Install Mode
Realtek’s auto-install mode solves the problem of a lack of network connection or CD-ROM hardware on
some recent computer platforms making driver installation difficult. With auto-install mode configured,
attach the driver-less RTL8153 to a system. The RTL8153 will disconnect, switch to auto-install mode,
and reconnect as a USB CD-ROM with a programmed driver installer. The driver will install itself and
the RTL8153 will switch back to USB NIC mode after installation.
The mechanism for identifying driver existence has inherent limitations due to the USB protocol. The
general USB enumeration flow consists of SetAddress and SetConfiguration control transfer. The
SetAddress is done by the operating system, the SetConfiguration is done by the device driver (see
note1).
The RTL8153 detects the driver existence by starting the auto-install mode timer when it receives
SetAddress. If the driver exists, the driver will do SetConfiguration within a short time (millisecond scale
after the driver has loaded). The timer will stop upon receipt of SetConfiguration. If a driver is not present,
the device will not receive SetConfiguration and the timer will timeout (default timeout value is 8
seconds).
Note 1: For Linux and OSX, the USB SetConfig is handled by the system USB framework (USB host
controller driver and/or USB bus driver); this behavior cannot trigger RTL8153 switching to auto-install
mode. As a result, RTL8153 supports auto-install mode in Windows only.
For Linux, Realtek supports a built-in in-house/ECM driver.
For OSX, Realtek supports a built-in ECM driver; users can also install an in-house driver.
Note 2: For more technical information, refer to the auto-install mode application note.
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7.
Characteristics
7.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 19. Absolute Maximum Ratings
Description
Minimum
Maximum
5.0V Supply Voltage
-0.3
5.5
3.3V Supply Voltage
-0.3
3.63
Symbol
VDD5
DVDD33, AVDD33
DVDD10, AVDD10,
U3VDD10, U2VDD10, 1.2V Supply Voltage
-0.3
1.32
DVDD10_UPS
Dcinput
Input Voltage
-0.3
Corresponding Supply Voltage + 10%
Dcoutput
Output Voltage
-0.3
Corresponding Supply Voltage + 10%
N/A
Storage Temperature
-55
+125
Note: Refer to the most updated schematic circuit for correct configuration.
Unit
V
V
V
V
V
°C
7.2. Recommended Operating Conditions
Table 20. Recommended Operating Conditions
Description
Symbol
Minimum
Typical
VDD5
4.5
5.0
DVDD33, AVDD33
3.14
3.3
Supply Voltage VDD
DVDD10, AVDD10,
U3VDD10, U2VDD10,
1.14
1.2
DVDD10_UPS
Ambient Operating Temperature TA 0
Maximum Junction Temperature
Note: Refer to the most updated schematic circuit for correct configuration.
Integrated 10/100/1000M Ethernet Controller for USB Applications
19
Maximum
5.5
3.46
Unit
V
V
1.26
V
70
125
°C
°C
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Datasheet
7.3. Crystal Requirements
Table 21. Crystal Requirements
Symbol
Description/Condition
Minimum
Typical
Maximum
Unit
Parallel resonant crystal reference frequency,
Fref
25/48
MHz
fundamental mode, AT-cut type
Parallel resonant crystal frequency stability,
-30
+30
ppm
Fref Stability
fundamental mode, AT-cut type. Ta=0°C ~ +70°C
Parallel resonant crystal frequency tolerance,
-50
+50
ppm
Fref Tolerance
fundamental mode, AT-cut type. Ta=25°C
Fref Duty Cycle Reference Clock Input Duty Cycle
40
60
%
ESR
Equivalent Series Resistance
70
Ω
CL
Load Capacitance
16
20
pF
Jitter
Broadband Peak-to-Peak Jitter
200
ps
DL
Drive Level
0.3
mW
Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above.
Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps.
Note 3: The ESR maximum value of 70ohm is based on shunt capacitance (Co) less than 7pF.
Note 4: The accuracy of the crystal resonance frequency can be achieved by matching the load capacitance correctly to
the designed-in circuit. The latest schematic circuit recommends two external capacitors of 27pF connected between the
crystal and ground. To match this use the load capacitance specified by the crystal manufacturer of 16~20pF.
7.4. Oscillator Requirements
Table 22. Oscillator Requirements
Parameter
Condition
Minimum
Typical
Maximum
Unit
Frequency
25/48
MHz
Frequency Stability
-30
+30
ppm
Ta = 0°C ~ +70°C
-50
+50
ppm
Frequency Tolerance
Ta = 25°C
Duty Cycle
40
60
%
Broadband Peak-to-Peak Jitter
200
ps
Vih
1.4
V
Vil
0.4
V
Rise Time
10
ns
Fall Time
10
ns
0
70
Operation Temp Range
°C
Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above.
Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps.
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7.5. Environmental Characteristics
Parameter
Storage Temperature
Ambient Operating Temperature
Moisture Sensitivity Level (MSL)
Table 23. Environmental Characteristics
Minimum
Maximum
-55
+125
0
Units
°C
°C
N/A
70
Level 3
7.6. DC Characteristics
Symbol
VDD5
DVDD33,
AVDD33
DVDD10,
AVDD10,
U3VDD10,
U2VDD10,
DVDD10_UPS
Voh
Vol
Vih
Vil
Iin
Parameter
5.0V Supply Voltage
Table 24. DC Characteristics
Conditions
Minimum
4.5
Typical
5.0
Maximum
5.5
Units
V
3.3V Supply Voltage
-
3.14
3.3
3.46
V
1.2V Supply Voltage
-
1.14
1.2
1.26
V
Ioh = -4mA
0.9*VDD33
-
VDD33
V
Iol = 4mA
0
-
0.1*VDD33
V
-
2.0
-
-
V
-
-
-
0.8
V
Vin = VDD33 or
GND
0
-
0.5
µA
Minimum High Level Output
Voltage
Maximum Low Level Output
Voltage
Minimum High Level Input
Voltage
Maximum Low Level Input
Voltage
Input Current
Average Operating Supply
At 1000Mbps with
Current from 5.0V (does
Icc5
0.5
mA
NOT include 3.3V and 1.2V heavy network traffic
power consumption)
Average Operating Supply
At 1000Mbps with
Current from 3.3V (does
90
mA
Icc33
heavy network traffic
NOT include 1.2V power
consumption)
Average Operating Supply
At 1000Mbps with
350
mA
Icc10
Current from 1.2V
heavy network traffic
Average Operating Supply
At 1000Mbps with
Current for total system 5V
Note3
mA
Isys5
heavy network traffic
(includes 3.3V and 1.2V
power consumption)
Note 1: Refer to the most updated schematic circuit for correct configuration.
Note 2: All Supply Voltage power noise
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