FSEIASLD-128G

Rev. 1.1 FSEIASLD-xxG Co ongsys L l tia 1.1 nfiden Version: Co 2019.01.04 INFORMATION PRODUCTS, LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE WITHOUT AND SPECIFICATIONS NOTICE. s and specifications are herein gsypurposes only. All discussed for reference n Products o L information discussed herein of any kind. on an “AS IS” basis, without warranties is provided and exclusive This document and the sole all information discussed herein remain Electronics. of property Longsys No license of any patent, copyright, mask work, trademark l the other a or any other intellectual property right is granted by one party to party under this ti estoppel or other-wise. ys n s e g document, by implication, d nfi Lon o C safety Longsys products are not intended for use critical care, medical, in life support, product failure could equipment, or similar applications where in loss of life or personal result or physical harm, or any military defense application, any governmental procurement or orl a terms to which special or provisions may apply. identi products, f your o For updates orn additional information about Longsys contact nearest C office. Longsys All brand names, trademarks and registered trademarks belong to their respective owners. ys s g Lon Shenzhen rights Longsys Electronics Co., Ltd. All reserved. ⓒ 2018 sys ial t n e nfid Long o C Electronics www.longsys.com Longsys Electronics al ti FORESEE eMMC FSEIASLD-xxG Datasheet  Rev. 1.1 FSEIASLD-xxG Revision History: Rev. Date Changes Co Remark 1.0 2018/08/13 Basic spec and architecture Preliminary 1.1 2019/01/04 Revise some descriptions ongsys L l tia nfiden Co s y Longs l a ys nti s e g d Lon fi n o C l a denti Confi ys s g Lon sys ial t n e nfid Long o C Electronics www.longsys.com Longsys Electronics al ti  Rev. 1.1 FSEIASLD-xxG CONTENTS 1. Introduction .......................................................................................................................... Co 1 2. Product List ........................................................................................................................... 1 3. Features ................................................................................................................................ 1 4. Functional Description ........................................................................................................... 2 sys g n 5. Product Specifications ........................................................................................................... 3 Lo 5.1 Performance ...................................................................................................................... 3 3 5.2 Power Consumption ............................................................................................................ 4 l .................................................................................................................... 6. Pin Assignments tia n e d Ball Array 4 view ................................................................................................................... Confi6.1 7. 6 ..................................................................................................................... Usage Overview 7.1 General description............................................................................................................. 6 7.2 Partition 6 ......................................................................................................... Management s sy g ........................................................................................................ n Automatic Sleep Mode 7.3 o 8 L 8 7.4 Sleep .................................................................................................................... (CMD5) 7.5 H/W 9 Reset operation........................................................................................................... l 7.6 High-speed mode selection .................................................................................................. 9 a ti ys n s 7.7 e g d Bus width i 9 Lon fselection............................................................................................................. n o C 7.8 Partition configuration ......................................................................................................... 9 ................................................................................................................... 7.9 CID register 10 CSD register .................................................................................................................. 10 tial 7.10 n 10 CSDnfregister Extended ide .................................................................................................... 7.11 o C ................................................................................................................. 7.12 OCR Register 22 update(FFU) 23 .............................................................................................. 7.13 Field firmware S.M.A.R.T. Health Report ................................................................................................. 25 7.14 ys s 8. Package g .............................................................................................................. Lon 25 Dimension 9 Guide Connection .................................................................................................................. 26 26 9.1 Schematic Diagram .......................................................................................................... 10. Processing Guide ............................................................................................................... 27 ys al i t n e gs d n i o f L Con www.longsys.com Longsys Electronics Electronics l a i t  Rev. 1.1 FSEIASLD-xxG 1. Introduction The FORESEE FORESEE eMMC is an embedded storage solution designed in the BGA package. eMMC Co consists of NAND flash and eMMC controller. The controller could manage the interface protocols， wear-leveling，bad block management and ECC. quality and low power consumption, and FORESEE eMMC has high performance at a competitive cost, high 5.1 eMMC is compatible with JEDEC standard eMMC specifications. s ngsy 2. Product List o L Type Density Part Number NAND Flash Type Capacity Package Size(mm) Package 153FBGA 11.5x13x1.0 256Gb x1 28.8GB 32GB FSEIASLD-32G 256Gb x2 57.6GB 153FBGA 11.5x13x1.0 64GB FSEIASLD-64G 153FBGA 11.5x13x1.2 tFSEIASLD-128G al 256Gb x4 115.2GB 128GB i den n3.fiFeatures Co compatibility  eMMC5.1 specification  Global-wear-leveling (Backward  Supported to eMMC4.41/4.5/5.0) features. compatible  Bus mode HS200 - HS400, - Data bus 1 bit (default), 4 bits, Partitioning, RPMB 8 bits width: s - Data transfer rate: up to 400MB/s (HS400) boot sypartition - Boot feature, g n - MMC o I/F Clock frequency : 0~200MHz HW Reset/SW Reset L  Operating voltage range Discard, Trim, Erase, Sanitize : 2.7 - 3.6V Background operations, HPI - Vcc(NAND) - Vccq(Controller) - 1.95V / 2.7 - 3.6V Enhanced reliable : 1.7 write Health  l Temperature S.M.A.R.T. Report a - Command ti (-25℃ ~n+85℃) queuing ys s - Operation e g d without on - Storage n - FFU fi operation (-40℃ ~ +85℃) L o C  Sudden-Power-Loss safeguard Sleep / awake  Others  Hardware ECC engine backup RoHS  Unique mechanism - Compliance with the Directive firmware ntial onfide C ys s g Lon sys ial t n e nfid Long o C Electronics www.longsys.com Longsys al ti Page 1  4. Functional Description FORESEE eMMC with powerful L2P (Logical to Physical) NAND Flash management algorithm provides o C unique functions:  Host independence from details of operating NAND flash  Internal ECC to correct defect in NAND flash  Sudden-Power-Loss safeguard To prevent from data loss, a mechanism Sudden-Power-Loss safeguard is added in the eMMC. named properly the cycling. In the case of sudden power-failure, eMMC would power ys after work s g n  Global-wear-leveling Lo To achieve the and device endurance, this eMMC equips the Global Wear Leveling best stability accessed not only normal area, algorithm. It ensures that but also the frequently area, such as FAT, and erased evenly. be programmed would Data  IDA(Initial Acceleration) l customer had with IDA, data iaprevents t The n eMMC the pre-burned from data-loss in case of our e d data to eMMC, eMMC the being SMT. before Confipre-burned Cache eMMC enhanced the data written performance with Cache, with which our customer would get The more endurance and reliability. TYPE  DEVICE s Device Type Supportability Bit sy g n o 7 Dual eMMC at 200 MHz – 1.2 V I/OL Not support Data Rate HS400 eMMC at 200 MHz – 1.8 V I/O Data Rate 6 Support HS400 Dual HS200 Single Data Rate eMMC at 200 MHz - 1.2 V I/O Not support 5 HS200 Single Data Rate eMMC at 200 MHz - 1.8 V I/O Support 4 3 High-Speed Dual Data Rate eMMC at 52 MHz - 1.2 V I/O Not support l a MHz - i ys 1.8 V or 3 V I/O Support s 2 idHigh-Speed at 52 ent Dual Data Rate eMMC g n LoSupport 1f High-Speed eMMC at 52 MHz - at rated device voltage(s) n o C 0 High-Speed eMMC at 26 MHz - at rated device voltage(s) Support l a denti Confi ys s g Lon sys ial t n e nfid Long o C Electronics www.longsys.com Longsys al ti Rev. 1.1 FSEIASLD-xxG Page 2  5. Product Specifications 5.1 Performance Co Part Number Write Read FSEIASLD-32G Up to 120MB/s Up to 220MB/s Up FSEIASLD-64G Up to 145MB/s to 230MB/s FSEIASLD-128G 150MB/s Up to 230MB/s Up to • Test Condition: Bus width x8, 200MHz DDR, 512KB data transfer, w/o file system overhead, measured on sys internal board g n Lo • Test tool: uBOOT (Without O/S) size: 1MB, • Chunk area: Full-range of LBA. 100MB/ • Test l Poweri Consumption a 5.2 t n 5.2.1d Active power consumption during operation e Number Confi Part Icc Iccq FSEIASLD-32G 100mA 150mA FSEIASLD-64G 150mA 120mA 150mA 150mA FSEIASLD-128G • Power Measurement conditions: Bus configuration =x8 @200MHz DDR, 23℃. s & • Vcc:3.3V sy g Vccq：1.8V. n o L for max • The measurement RMS current is the average RMS current consumption over a period of 100ms. Low 5.2.2 power mode (stand-by) Part Number Icc Iccq l a FSEIASLD-32G 70uA 150uA ys nti s e g FSEIASLD-64G 100uA 160uA d Lon fi FSEIASLD-128G n o 130uA 160uA C configuration • Power Measurement conditions: Bus =x8 @200MHz DDR, 23℃. • Standby: Nand Vcc & Controller Vccq power supply is switched on. • The measurement for max RMS current is the average RMS current consumption over a period of 100ms. l a denti 5.2.3 Low power mode (sleep) i Icc ConfPart Number Iccq 0 150uA FSEIASLD-32G 160uA 0 FSEIASLD-64G FSEIASLD-128G 0 160uA • Power Measurement conditions: Bus configuration =x8 @200MHz DDR, 23℃. ys s • Sleep: g supply Nand Vcc power is switched off（Controller Vccq on） Lon • RMS current consumption over a period of 100ms. The measurement max RMS current is the average for sys ial t n e nfid Long o C Electronics www.longsys.com Longsys al ti Rev. 1.1 FSEIASLD-xxG Page 3  6. Pin Assignments 6.1 Ball Array view Co ongsys L l tia nfiden Co s y Longs l a i - Ball Array (Top View through package) ys ntFBGA153 s e g d Lon fi n o C l a denti Confi ys s g Lon sys ial t n e nfid Long o C Electronics www.longsys.com Longsys al ti Rev. 1.1 FSEIASLD-xxG Page 4  6.2 Ball Array view Signal Description and on the data Co CLOCK Each cycle of the clock directs a transfer on the command line (CLK) lines. channel This signal is a bidirectional command used for device initialization and command transfer. has COMMAND The CMD Signal 2 operation modes: open drain, for initialization, and s (CMD) push-pull, command ngsy transfer. for Commands are sent from the host L too the device, and responses are sent from the to the device host. signals These are bidirectional data signal. The DAT operate in push-pull mode. or RESET, only The default, after power-up DAT0 is used for data transfer. l By transfer bus a wider can configure data for data using DAT wither tia controller mode)or DAT[7:0](8bit mode). after den [3:0](4bit nfDATA i Includes internal pull-up resistors for data lines DAT[7:1].Immediately Co (DAT0-DAT7) the on entering the 4-bit mode, device disconnects the internal pull-up resistors DAT3 line internal the DAT1 and DAT2 lines.(The pull-up is left connected.)Upon the disconnects mode, the 8bit the device internal pull-up on the DAT1, entering DAT[7:4]lines. and DAT2, s Strobe Newly assigned pin for HS400 mode. Strobe is generated sy from e.MMC to Data g n Data o host. L data and CRC response are synchronized with Data (DS) mode, Strobe. In HS400 read RESET Hardware Reset Input (RSTN) Vccq is thel power supply line for host interface, have two power mode: High power a ys nti mode:2.7V~3.6V; Lower power mode:1.7V~1.95V s Vccq e g d n voltage Lopower line for internal fi Vcc is the power supply flash memory, its range n o C Vcc is:2.7V~3.6V is internal power Connect 1uF capacitor VDDi to node, not the power supply. VDDi VDDi ground Vss,Vssq Ground lines. al denti Note: NC: No Connect, fi to ground or nconnected shall be left floating. o C Reserved for Future RFU: use. floating Use, must be left for future VSF: Vendor Specific Function, must be left floating. ys s g Lon sys ial t n e nfid Long o C Electronics www.longsys.com Longsys al ti Rev. 1.1 FSEIASLD-xxG Page 5  7. Usage Overview 7.1 General description by a controller Co The eMMC can be operated in 1, 4, or 8-bit mode. NAND flash memory is managed inside, provides which manages ECC, wear leveling and bad block management. The eMMC integration with easy the host process that all flash management hassles are invisible host. to the ongsys L l tia nfiden Co s sy g n o 7.2 Partition Management L of configuring by the host additional split local memory The embedded device offers also the possibility starting from logical address with independent addressable space 0x00000000 for different partitions Default can be changed by Vendor Command size of each Boot Area Partition is 4096 KB and models. usage as multiple of 128KB. Boot area partition size is calculated as ( 128KB * BOOT_SIZE_MULTI ) The size of l a Boot area ypartition Boot Area Partition 1 andn2tcannot i be set independently s which and is set as same value s e g d partition. on is classified is enhanced block area scan as follows: fi Therefore memory L n o C configuration supplies  Factory boot partitions.  The RPMB partition is 4MB. in the User Data segment  The host is free to configure one Area to be implemented as enhanced terms of Write Protect Groups. its lstarting The and storage media, to specify location and size in a only of this Area can be programmed once during life-cycle ti Data Enhanced the device nUser attributes e d (one-time programmable). nfi o C  Up to four General Purpose Area Partitions can be configured to store user data or sensitive data, or for other host usage models. The size of these partitions is a multiple of the write protect group. Size programmable). life-cycle in device Each and attributes can be programmed once (one-time of the Area Partitions can General Purpose with be implemented technological features. enhanced ys s g Lon sys ial t n e nfid Long o C Electronics www.longsys.com Longsys al ti Rev. 1.1 FSEIASLD-xxG Page 6  Co ongsys L l Partitions user data area configuration and tia (The size of RPMB area partition is 4MB) n can read the line low or deoperation nInfboot i mode, master boot data from the slave (device) by keeping CMD Co sending CMD0 with argument issuing before + 0xFFFFFFFA, from either boot The data can be read CMD1. setting. on register or user area depending area Factor Value Timing Boot ACK Time < 50 ms s Boot Data Time sy < 1 s g n Initialization o Time