MOD5270-200IR

MOD5270 Ethernet Core Module 100 Version with RJ-45 | 200 Version with 10-pin header DATASHEET Key Points • Use as a high-performance single board computer or add Ethernet connectivity to a new or existing design • Customize with a development kit and begin writing application code immediately! • Industrial temperature range (-40°C to 85°C) Device Connectivity • 10/100Mbps Ethernet • 47 digital I/Os • 3 UARTs, I C, and SPI • 16-bit address bus and 32-bit data bus with 3 chip selects 2 • SD/MMC flash card ready Performance and memory • 32-bit 147.5 MHz Processor • 8MB SDRAM and 512KB Flash Companion development kit The following is available with the development kit: • Customize any aspect of operation including web pages, data filtering, or custom network applications • Development software: NB Eclipse IDE, Graphical debugger, deployment tools, and examples • Communication software: TCP/IP stack, SSL/TLS 1.3, HTTP web server, FTP, E-mail, and flash file system • System software: NBRTOS, ANSI C/C++ compiler and linker Updated: November 7, 2023 | Page 1 of 8 © 2023 NetBurner Inc. All Rights Reserved. MOD5270 Specifications Processor and Memory 32-bit Freescale ColdFire 5270 running at 147.5MHz with 8MB SDRAM, 512KB Flash, and 64Kb SRAM. Network Interface 10/100 BaseT with RJ-45 connector (100 Version) 10-pin header (200 Version) Data I/O Interface (J1 and J2) • Up to 3 UARTs • I2C interface • Up to 47 digital I/O • SPI interface • Up to 3 external timer in and up to 4 timer outputs • SD/MMC flash card ready • Up to 4 external IRQs • 16-bit address bus and 32-bit data bus with 3 chip selects Flash Card Support FAT32 support for SD Cards up to 8GB (requires exclusive use of SPI signals). Card types include SD/MMC (up to 2GB) and SDHC. Serial Configurations The UARTs can be configured in the following way: • 3 TTL ports • Add external level shifter for RS-232 • Add external level shifter for RS-422/485 (up to three ports) Note: UART 0/1/2 also provides RTS/CTS hardware handshaking signals. LEDs Link and Speed (100 Version only, on RJ-45) Physical Characteristics Dimensions (inches): 2.60” x 2.00” Weight: 1 oz. Mounting Holes: 2 x 0.125” dia. Power DC Input Voltage: 3.3V @ 380mA typical Environmental Operating Temperature -40° to 85° C RoHS Compliance The Restriction of Hazardous Substances guidelines ensure that electronics are manufactured with fewer environment harming materials. Updated: November 7, 2023 | Page 2 of 8 © 2023 NetBurner Inc. All Rights Reserved. MOD5270 Part Numbers MOD5270 Ethernet Core Module (100 Version, with RJ-45) Part Number: MOD5270-100IR MOD5270 Ethernet Core Module (200 Version, with 10-pin header) Part Number: MOD5270-200IR MOD5270 LC Development Kit Part Number: NNDK-MOD5270LC-KIT Kit includes all the hardware and software you need to customize the included platform hardware. See NetBurner Store product page for package contents. Note: Includes the MOD-DEV-70 development board. MOD5270 Development Kit Part Number: NNDK-MOD5270-KIT Kit includes all the hardware and software you need to customize the included platform hardware. See NetBurner Store product page for package contents. Note: Includes the MOD-DEV-100 development board. Ordering Information E-mail: sales@netburner.com Online Store: www.NetBurner.com Telephone: 1-800-695-6828 Updated: November 7, 2023 | Page 3 of 8 © 2023 NetBurner Inc. All Rights Reserved. MOD5270 Pinout and Signal Description The 200 version board has a 10-pin header instead of an RJ-45 jack. This header enables you to relocate the jack to another location or to add a different jack with power over ethernet (PoE) capabilities to your module. Table 1 provides descriptions of pin function of the 10-pin header. Refer to the application note, “Adding an External Ethernet RJ-45 Connector and PCB Layout Guidlines for NetBurner -200 Version Modules”, for details and examples. Table 1: Pinout and Signal Descriptions for JP2 Header (1) Pin Signal Description 1 2 3 4 5 6 7 8 9 10 TXTX+ TXCT1 RX+ RXRXCT1 GND N/C LED LED Transmit Transmit + Transmit Data Center Tap Receive + Receive Receive Data Center Tap Ground Not Connected LED control sink, link/activity LED control sink, speed Note: 1. Ethernet magnetics center tap voltage provided by NetBurner device Updated: November 7, 2023 | Page 4 of 8 © 2023 NetBurner Inc. All Rights Reserved. MOD5270 The module has two dual in-line 50 pin headers which enable you to connect to one of our standard NetBurner Carrier Boards, or a board you create on your own. Table 2-3 provides descriptions of pin function of the module header. Table 2: Pinout and Signal Descriptions for J1 Connector (1) J1 Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CPU Pin J13 B10 C9 A9 N6 C6 B6 L2 H11 K4 L1 K2 K3 J4 K1 J2 J3 H4 J1 H2 H3 Function 1 GND GND VCC3V R/W CS1 CS2 CS3 OE BS2 BS3 TIP D16 TA D18 D17 D20 D19 D22 D21 D24 D23 D26 D25 D28 D27 Function 2 General Description Purpose I/O PCS1 PCS2 PCS3 CAS2 CAS3 PBUSCTL6 Max Voltage Ground Ground Input Power 3.3 VDC Read / NOT Write1 Chip Select 11 Chip Select 21 Chip Select 31 Output Enable Byte Strobe for D16 to D23 (8 bits)1 or Column Address Strobe 21 Byte Strobe for D24 to D31 (8 bits)1 or Column Address Strobe 31 Transfer in Progress1,2 Data Bus - Data 164 Transfer Acknowledge1 Data Bus - Data 18 Data Bus - Data 17 Data Bus - Data 20 Data Bus - Data 19 Data Bus - Data 22 Data Bus - Data 21 Data Bus - Data 24 Data Bus - Data 23 Data Bus - Data 26 Data Bus - Data 25 Data Bus - Data 28 Data Bus - Data 27 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC Note: 1. Active low signals, such as RESET, are indicated with an overbar 2. The TIP signal is the logical AND of *CS1, *CS2 and *CS3. TIP can be used to control an external data bus buffer for the data bus signals. An example circuit design can be found on the Module Development Board schematic. An external data bus buffer is recommended for any designs that use data bus signals D16 - D31. 3. The CLKOUT signal is 1/2 the system frequency of 147.456 MHz. 4. This is the LSB (Least-significant bit). This bit is unused for 16-bit ports 5. This is the MSB (Most-significant bit) 6. Each UART can be clocked from an internal or external source. For external clocks, each UARTn,can be clocked by the corresponding DTn_IN input pin. 7. If using I2C, pull-up resistors must be added to SDA/SCL. 8. The Mod5270 provides QSPI chip selects QSPI_CS0, QSPI_CS1 & QSPI_CS3. 9. 32-bit mode only Updated: November 7, 2023 | Page 5 of 8 © 2023 NetBurner Inc. All Rights Reserved. MOD5270 J1 Connector (continued) Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CPU Pin G2 H1 N13 G1 P13 K14 G13 G12 G11 F14 F13 F12 E14 E13 E12 E11 D14 D13 D12 C14 C13 B14 Function General Purpose I/O D30 D29 RESET D31 RSTOUT CLK_OUT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VCC3V GND GND Description Max Voltage Data Bus - Data 30 Data Bus - Data 295 Processor Reset Input1 Data Bus - Data 31 Processor Reset Output1 Buffer Clock Out (CLKOUT-73.728 Mhz)3 Data Bus - Address 04 Data Bus - Address 1 Data Bus - Address 2 Data Bus - Address 3 Data Bus - Address 4 Data Bus - Address 5 Data Bus - Address 6 Data Bus - Address 7 Data Bus - Address 8 Data Bus - Address 9 Data Bus - Address 10 Data Bus - Address 11 Data Bus - Address 12 Data Bus - Address 13 Data Bus - Address 14 Data Bus - Address 155 Input Power 3.3 VDC Ground Ground 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC - Note: 1. Active low signals, such as RESET, are indicated with an overbar 2. The TIP signal is the logical AND of *CS1, *CS2 and *CS3. TIP can be used to control an external data bus buffer for the data bus signals. An example circuit design can be found on the Module Development Board schematic. An external data bus buffer is recommended for any designs that use data bus signals D16 - D31. 3. The CLKOUT signal is 1/2 the system frequency of 147.456 MHz. 4. This is the LSB (Least-significant bit). This bit is unused for 16-bit ports 5. This is the MSB (Most-significant bit) 6. Each UART can be clocked from an internal or external source. For external clocks, each UARTn,can be clocked by the corresponding DTn_IN input pin. 7. If using I2C, pull-up resistors must be added to SDA/SCL. 8. The Mod5270 provides QSPI chip selects QSPI_CS0, QSPI_CS1 & QSPI_CS3. 9. 32-bit mode only Updated: November 7, 2023 | Page 6 of 8 © 2023 NetBurner Inc. All Rights Reserved. MOD5270 Table 3: Pinout and Signal Descriptions for J2 Connector (1) J2 Connector Pin CPU Pin Function 1 1 GND 2 VCC3V 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 F2 F1 N1 M2 M1 P2 N2 L3 M3 N3 P5 N5 P4 M5 N4 M4 D8 D9 L5 P3 C5 UART0_RX UART0_TX NC D14 D13 D15 D11 D12 D10 D9 D8 GND D0 D1 D4 D2 D5 D6 UART1_RX UART1_TX D3 D7 SPI_CLK Function 2 General Description Purpose I/O Ground PUARTL0 PUARTL1 PDATAH14 PDATAH13 PDATAH15 PDATAH11 PDATAH12 PDATAH10 PDATAH9 PDATAH8 I2C_SCL PDATAL0 PDATAL1 PDATAL4 PDATAL2 PDATAL5 PDATAL6 PUARTL4 PUARTL5 PDATAL3 PDATAL7 PQSPI2 Max Voltage - Input Power 3.3 VDC 3.3VDC UART 0 Receive6 UART 0 Transmit6 No Connect Data Bus - Data 14 Data Bus - Data 13 Data Bus - Data 15 Data Bus - Data 11 Data Bus - Data 12 Data Bus - Data 10 Data Bus - Data 9 Data Bus - Data 8 Ground Data Bus - Data 0 Data Bus - Data 1 Data Bus - Data 4 Data Bus - Data 2 Data Bus - Data 5 Data Bus - Data 6 UART 1 Receive6 UART 1 Transmit6 Data Bus - Data 3 Data Bus - Data 7 SPI Clock8 or I2C Serial Clock7 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC Note: 1. Active low signals, such as RESET, are indicated with an overbar 2. The TIP signal is the logical AND of *CS1, *CS2 and *CS3. TIP can be used to control an external data bus buffer for the data bus signals. An example circuit design can be found on the Module Development Board schematic. An external data bus buffer is recommended for any designs that use data bus signals D16 - D31. 3. The CLKOUT signal is 1/2 the system frequency of 147.456 MHz. 4. This is the LSB (Least-significant bit). This bit is unused for 16-bit ports 5. This is the MSB (Most-significant bit) 6. Each UART can be clocked from an internal or external source. For external clocks, each UARTn,can be clocked by the corresponding DTn_IN input pin. 7. If using I2C, pull-up resistors must be added to SDA/SCL. 8. The Mod5270 provides QSPI chip selects QSPI_CS0, QSPI_CS1 & QSPI_CS3. 9. 32-bit mode only Updated: November 7, 2023 | Page 7 of 8 © 2023 NetBurner Inc. All Rights Reserved. MOD5270 J2 Connector (continued) Pin CPU Pin Function 1 Function 2 Function 3 26 G14 T3OUT UART2_RTS SPI_CS3 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 B5 A5 F3 A6 E4 C8 B8 M6 M9 F4 L6 G3 J12 B7 A7 J11 L8 A8 N8 SPI_DIN SPI_DOUT UART0_CTS SPI_CS0 T0IN UART1_RTS UART1_CTS T1OUT T2IN T0OUT T1IN UART0_RTS I2C_SDA SPI_CS1 UART2_RX I2C_SCL IRQ1 UART2_TX IRQ3 GND IRQ5 IRQ7 GND VCC3V I2C_SDA L7 N7 DREQ0 U2_RTS U2_CTS DACK1 DREQ2 DACK0 DREQ1 T2OUT T1OUT SD_CKE General Description Purpose I/O PTIMER6 PQSPI1 PQSPI0 PUARTL3 PQSPI3 PTIMER1 PUARTL6 PUARTL7 PTIMER2 PTIMER5 PTIMER0 PTIMER3 PUARTL2 PFECI2C1 PQSPI4 PUARTH0 PFECI2C0 PIRQ1 PUARTH1 PIRQ3 PIRQ5 PIRQ7 Max Voltage Timer Output 3 or UART 2 Request To Send1,6 or SPI Chip Select 3 SPI Data In or I2C Serial Data7 SPI Data Out UART 0 Clear To Send1,6 SPI Chip Select 08 Timer Input 0 or DMA Request 01 UART 11,6 or UART 2 Request to Send1,6 UART 11,6 or UART 2 Clear to Send1,6 Timer Output 1 or DMA Acknowledge 1 Timer Input 2 or DMA Request 21 or Timer Output 2 Timer Output 0 or DMA Acknowledge 0 Timer Input 1 or DMA Request 11 or Timer Output 1 UART 0 Request To Send1,6 I2C Serial Data7 SPI Chip Select 18 or SDRAM Clock Enable UART 2 Receive6 I2C Serial Clock External Interrupt 11 UART 2 Transmit6 External Interrupt 31 Ground External Interrupt 51 External Interrupt 71 Ground Input power 3.3 VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC Note: 1. Active low signals, such as RESET, are indicated with an overbar 2. The TIP signal is the logical AND of *CS1, *CS2 and *CS3. TIP can be used to control an external data bus buffer for the data bus signals. An example circuit design can be found on the Module Development Board schematic. An external data bus buffer is recommended for any designs that use data bus signals D16 - D31. 3. The CLKOUT signal is 1/2 the system frequency of 147.456 MHz. 4. This is the LSB (Least-significant bit). This bit is unused for 16-bit ports 5. This is the MSB (Most-significant bit) 6. Each UART can be clocked from an internal or external source. For external clocks, each UARTn,can be clocked by the corresponding DTn_IN input pin. 7. If using I2C, pull-up resistors must be added to SDA/SCL. 8. The Mod5270 provides QSPI chip selects QSPI_CS0, QSPI_CS1 & QSPI_CS3. 9. 32-bit mode only Updated: November 7, 2023 | Page 8 of 8 © 2023 NetBurner Inc. All Rights Reserved.