XN3700
8Bit Single-Chip Microcontroller
1. FEATURES
Embedded MCU
Motor Controller (MOC)
MCS®-51 Compatible
Space Vector PWM (SVPWM)
1T 8052 Central Processing Unit
Supports Sin-Wave and Square-Wave Solutions
4.5V to 5.5V Operation Range
Supports Hall Latch and Hall Element Input
4 Level Priority Interrupt
Supports Digital OCP and Analog OCP (Over
14 Interrupt Sources
━ Two External Interrupts (INT0N, INT1N)
Current Protection)
Programmable Deadband
Programmable Angle Shift Control (0° to 58° in
━ 8KB Flash Program Memory
32steps)
━ 256 x 8-bit IRAM
Memory Size:
━ 256 x 8-bit XRAM
Up to 25 General-Purpose Input / Output (GPIO)
Pins
Three 16-bit Timer/Counters
Watchdog (WD) Timer
1 Channel 16-bit Capture
8 Channels 10-bit Analog-to-Digital Converter
(ADC)
Full Duplex UART Serial Channel
Fast Multiplication-Division Unit (MDU): 16*16,
32/16, 16/16,32-bit L/R shifting and 32-bit
normalization
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
2. Block Diagram
Figure 2.1 HALL LATCH
Figure 2.2 HALL ELEMENT
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
3. XN3700 Series Product Selection Guide
I/O
Part No
UART
PWM
ADC
[*1]
XN3700
25
1
6
8
HALL
Ext.
Ext.
Customer
[*2]
Crystal
Reset
Code
3L/3E
√
√
√
A10
Package
LQFP-32
TQPF-32
-xxxx0A
A1/7
XN3700
25
1
8
3L/3E
√
√
x
A100AA
LQFP-32
TQPF-32
1/7
A10
-xxxxA
D4
XN3700
A100A
D4
XN3700
A10
-xxxxA
D2
XN3700
8KB Flash, 256B IRAM, 258B XRA M
XN3700
22
1
8
3L
√
√
√
SSOP-28
22
1
8
3L
√
√
x
SSOP-28
15
0
2
3L / 3E
x
x
√
SSOP-20
15
0
2
3L / 3E
x
x
x
SSOP-20
15
1
3
3L
x
x
√
QFN-20
15
1
3
3L
x
x
x
QFN-20
A100A
D2
XN3700
A10
-xxxxAB
2
XN3700
A100
-AB2
Note:
1. xxxx is customer code number.
2. 3L / 3E : support 3 hall latch or 3 hall element.
3L : support 3 hall latch.
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
4. Ordering Information
4.1 Including Customer Code
Code 1
8
9
A
B
Year 2018 2019 2020 2021
Code 2
1
Month Jan.
2
Feb.
3
Mar.
4
Apr.
●
●
●
G
2026
H
2027
I
2028
J
2029
9
Sep.
A
Oct.
B
Nov.
C
Dec.
5. Pin Assignments
5.1 SSOP-28(AD4)
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
5.2 SSOP-20(AD2)
5.3 LQFP-32 7x7mm(AA1) / TQFP-32 7x7mm(AA7)
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
6. Pin Definitions
SSOP-28
SSOP-20
L/TQFP32
7x7
Name
Pin #
Type
Description
8
---
1
RSTN
I
System Reset.
25
---
2
CH7
I
Analog Input Ch7.
CAP2
I
Capture Input 2
P2.7
I/O
Bit 7 of Port 2.
CH6
I
Analog Input Ch6.
P2.6
I/O
Bit 6 of Port 2.
CH5
I
Analog Input Ch5.
P2.5
I/O
Bit 5 of Port 2.
CH4
I
Analog Input Ch4.
P2.4
I/O
Bit 4 of Port 2.
CH3
I
Analog Input Ch3.
P2.3
I/O
Bit 3 of Port 2.
RX
I
Serial Data Transmit
24
23
22
9
13
---
---
---
---
---
3
4
5
6
7
(UART)
14
---
8
P3.0
I/O
Bit 0 of Port 3.
TX
O
Serial Data Receive
(UART)
P3.1
15
11
9
I/O
SDAICE
Bit 1 of Port 3.
For ICE (In Circuit
Emulator).
16
12
10
SCLICE
For ICE (In Circuit
Emulator).
17
---
11
XTALI
I
Crystal input pin.
Connect the crystal
12MHz between this
pin and XTALO and a
22pF capacitor to
VSS.
T1
I
TIMER1 External
Input.
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
18
---
12
P3.5
I/O
Bit 5 of Port 3.
XTALO
O
Crystal output pin.
Connect the crystal
12MHz between this
pin and XTALI and a
22pF capacitor to
VSS.
T0
I
TIMER0 External
Input.
P3.4
---
---
13
NC
19
13
14
VDD5
I/O
Bit 4 of Port 3.
No connect.
Power
5.0V Voltage Input. A
0.1uF and 10uF
(minimum) capacitor
should be connected
between this pin and
VSS.
20
14
15
V25
O
2.5V Voltage Output.
A 0.1uF and 1uF
(minimum) capacitor
should be connected
between this pin and
VSS.
21
15
16
VSS
Ground
Power Ground.
12
16
17
CH0
I
Analog Input Ch0.
CAP1
I
Capture Input 1
GPWM
O
General PWM output.
P1.6
I/O
Bit 6 of Port 1.
CH1
I
Analog Input Ch1.
INT0N
I
External Interrupt 0.
11
17
18
Low level trigger or
falling edge trigger.
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
10
---
19
P3.2
I/O
Bit 2 of Port 3.
CH2
I
Analog Input Ch2.
INT1N
I
External Interrupt 1.
Low level trigger or
falling edge trigger.
---
10
20
P3.3
I/O
Bit 3 of Port 3.
HWN
I
Hall Element negative
input. (HALL W)
26
9
21
P0.6
I/O
Bit 6 of Port 0.
HWP
I
Hall Latch input or
HALL Element
positive input. (HALL
W)
---
8
22
P0.2
I/O
Bit 2 of Port 0.
HVN
I
Hall Element negative
input. (HALL V)
27
7
23
P0.5
I/O
Bit 5 of Port 0.
HVP
I
Hall Latch input or
HALL Element
positive input. (HALL
V)
---
6
24
P0.1
I/O
Bit 1 of Port 0.
HUN
I
Hall Element negative
input. (HALL U)
28
5
25
P0.4
I/O
Bit 4 of Port 0.
HUP
I
Hall Latch input or
HALL Element
positive input.(HALL
U)
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
1
18
26
P0.0
I/O
Bit 0 of Port 0.
OCPN
I
Over current
protection. Active-low.
2
19
27
P0.3
I/O
Bit 3 of Port 0.
U
O
PWM output.
High-side PWM of
phase U.
3
20
28
P1.0
I/O
Bit 0 of Port 1.
X
O
PWM output. Low-side
PWM of phase U.
4
1
29
P1.1
I/O
Bit 1 of Port 1.
V
O
PWM output.
High-side PWM of
phase V.
5
2
30
P1.2
I/O
Bit 2 of Port 1.
Y
O
PWM output. Low-side
PWM of phase V.
6
3
31
P1.3
I/O
Bit 3 of Port 1.
W
O
PWM output.
High-side PWM of
phase W.
7
4
32
P1.4
I/O
Bit 4 of Port 1.
z
O
PWM output.
Low-side PWM of
phase W.
P1.5
---
---
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Bit 5 of Port 1.
No connect.
Datasheet
XN3700
8Bit Single-Chip Microcontroller
7. Absolute Maximum Ratings
Supply Voltage............................ ............ ............ ................................VSS-0.3V to VSS+6.0V
Input Voltage............................ ............ ............ ................................... VSS -0.3V to VDD+0.3V
Storage Temperature.................... ...... ...... ...... ...... ...... ...................................-50°C to 150°C
Operating Temperature..................... ...... ...... ...... ...... ...... ..............................-40°C to 125°C
IOH Total........................ ...... ...... ...... ...... ...... ...... .........................................................-80mA
IOL Total................... ...... ...... ...... ...... ...... ...... ...............................................................80mA
ΘJA Thermal Resistance, Junction-to-ambient (SSOP-28L).... ...... ...... ...... ...... .........82°C/W
ΘJA Thermal Resistance, Junction-to-ambient (SSOP-20L).. ...... ...... ...... ...... ......114.5°C/W
ΘJA Thermal Resistance, Junction-to-ambient (LQFP7x7-32) ..... ............ ..... ...... ......80℃/W
Total Power Dissipation.................................... ...... ...... ...... ...... ...... ...... ....................500mW
Electrostatic Discharge Capability – Human Body Mode......... ...... ...... ...... ...... ............2000V
Electrostatic Discharge Capability – Machine Mode...... ...... ...... ...... ...... ........................200V
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
8. D.C. Characteristics
Symbol
Parameter
Ta=25℃
Test Conditions
VDD
Min.
Typ.
Max.
Unit
Conditions
VDD
Operating Voltage
―
fsys=48MHz
4.5
5.0
5.5
V
V25
V25 Output Range
―
Load Current < 10mA
2.35
2.50
2.65
V
IDD
Operating Current
5V
No load, fsys=48Mhz, ADC
―
9
12
mA
off, MOC off
VIL
Input Low Voltage
―
―
0
―
0.3 VDD
V
―
―
0.7
―
VDD
V
for I/O Ports.
VIH
Input High Voltage
for I/O Ports.
VDD
VLVD
LVD Voltage Level
―
―
VOL
Output Low Voltage
5V
IOL=5mA
―
―
0.5
V
5V
IOH=-3.8mA
4.5
―
―
V
5V
―
10
35
50
KΩ
5V
―
10
35
50
KΩ
for I/O Ports.
VOH
Output High
Voltage for I/O
Ports.
RPU
Pull-up Resistance
for I/O Ports
RPD
Pull-down
Resistance for I/O
Ports
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
9. A.C. Characteristics Ta=25℃
Symbol
fSYS
Parameter
System
Test Conditions
Timer Input Pin
Typ.
Max.
Unit
VDD
Conditions
4.5V~5.5V
Ta=-40℃ to 125℃
TBD
48.0
TBD
MHz
Ta=-20℃ to 85℃
TBD
48.0
TBD
MHz
Ta=25℃
-1%
48.0
+1%
MHz
―
―
―
―
4
fsys
―
―
1
5
10
tsys
―
―
120
240
480
us
Frequency
fTIMER
Min.
Frequency
tINT
Interrupt Pulse
Width
tLVD
Low Voltage
Width to interrupt
tV25
V25 Stable Time
―
―
60
120
240
us
tRSDT
System Reset
―
―
25
50
100
ms
Delay Time
(Power On Reset)
10.
A/D Converter Characteristics
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
Ta=25℃
Symbol
IAD
Parameter
Additional Power
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Conditions
5V
―
―
4.5
―
mA
―
Load Current <
―
―
4
uA
Consumption if A/D
Converter is Used
IADSTB
A/D Converter Standby
Current
tADCCLK
tCONV
tSHCLK
tSH
DNL
INL
GERR
10mA
A/D Converter Clock
―
4MHz
―
0.25
―
us
Time
―
2MHz
―
0.5
―
us
A/D Conversion Time
―
4MHz
―
3.25
―
us
―
2MHz
―
6.5
―
us
A/D Sample and Hold
―
1MHz
―
1
―
us
Clock Time
―
500KHz
―
2
―
us
―
400KHz
―
2.5
―
us
―
333KHz
―
3
―
us
A/D Sample and Hold
―
1MHz
1
―
2
us
Time
―
500KHz
2
―
4
us
―
400KHz
2.5
―
5
us
―
333KHz
3
―
6
us
Differential
4.5V
No load,
-1
―
+3
LSB
Non-linearity
5.5V
tCONV=2.5us
-1
―
+3
LSB
4.5V
No load,
-1
―
+3
LSB
5.5V
tCONV=5us
-1
―
+3
LSB
4.5V
No load,
-4
―
+4
LSB
5.5V
tCONV=2.5us
-4
―
+4
LSB
4.5V
No load,
-4
―
+4
LSB
5.5V
tCONV=5us
-4
―
+4
LSB
―
―
-10
―
+10
LSB
Integral Non-linearity
Gain Error
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
11. Special Function Registers (SFR)
11.1 SFRs Memory Map
F8
8
9
A
B
C
D
E
F
PINCONG1
PINCONG
PINCONG
PINCONG4
PINCONG5
PINCONG6
RSTS
TAKEY
FF
2
3
F0
B
PINSET1
PINSET2
PINSET3
PINSET4
PINSET5
PINSET6
PINSET7
F7
E8
ASUD1_1
ASUD1_2
ASUD1_3
ASUD1_4
ASUD2_1
ASUD2_2
ASUD2_
ASUD2_4
EF
3
E0
ACC
AS_MD_C
MD0
MD1
MD2
MD3
MD4
MD5
E7
SVPWMA
MD_CONT
ASUR1
ASUR2
ASUR3
ASUR4
DF
ONT
D8
CAPCONT
VRHALL
MPFT
D0
PSW
PFCON
ADCCONT
ADCSTR
-----
ADCD1
ADCD2
SYNC
D7
C8
T2CON
CAPT_H
CAPT_L
CAPH_H
CAPH_L
-----
-----
-----
CF
C0
IRCON1
SVPWMA
-----
SVPWMAM
SVPWMAM
-----
-----
PINCONG
C7
PL
PH
GPWMCO
GPWMMAX
GPWMMAX
NT
L
H
MPWMCO
MPWMCO
MPWMINV
TL2
TH2
NT1
NT2
IP0
MPWMDY
MPWMDYV
-----
VL
H
MCONT2
MPWMMAX
NG
B8
B0
A8
A0
98
IEN1
P3
IEN0
P2
SCON
IP1
OCPCONT
SBUF
SRELL
7
-----
BF
WDTC
WDTK
B7
MPWMDYW
MPWMD
-----
AF
L
YWH
MPWMMAX
MPWMDYU
MPWMD
MPWMD
A7
L
H
L
YUH
B
SRELH
HALLDBT
MCONT1
AOCPCO
-----
9F
ROTORS
ROTORS
97
PEEDL
PEEDH
GPWMDYL
GPWMD
YH
NT
90
P1
HALLSET1
HALLSET2
HALLSET3
HALLST
-----
88
TCON
TMOD
TL0
TL1
TH0
TH1
AUX
AS
8F
80
P0
SP
DP0L
DP0H
DP1L
DP1H
RCON
PCON
87
0
1
2
3
4
5
6
7
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
11.2 XN3700 SFRs and Reset Value
SYMBOL
DESCRIPTION
DIRECT
RESET
ADDRESS
VALUE
ACC
Accumulator
E0H
00H
ADCCONT
ADC Control Register
D2H
80H
ADCD1
ADC Data Register 1
D5H
00H
ADCD2
ADC Data Register 2
D6H
00H
ADCSTR
ADC Start Convert and Setting Register
D3H
00H
AOCPCONT
Analog OCP Control Register
9EH
0FH
AS
Angle Shift Control Register
8FH
00H
AS_MD_CONT
ASU and MDU Control Register
E1H
10H
ASUD1_1
ASU Data 1 byte 1
E8H
00H
ASUD1_2
ASU Data 1 byte 2
E9H
00H
ASUD1_3
ASU Data 1 byte 3
EAH
00H
ASUD1_4
ASU Data 1 byte 4
EBH
00H
ASUD2_1
ASU Data 2 byte 1
ECH
00H
ASUD2_2
ASU Data 2 byte 2
EDH
00H
ASUD2_3
ASU Data 2 byte 3
EEH
00H
ASUD2_4
ASU Data 2 byte 4
EFH
00H
ASUR1
ASU Result Register 1
DCH
00H
ASUR2
ASU Result Register 2
DDH
00H
ASUR3
ASU Result Register 3
DEH
00H
ASUR4
ASU Result Register 4
DFH
00H
AUX
Auxiliary
8EH
11H
B
B Register
F0H
00H
CAPCONT
Capture Control Register
D8H
03H
CAPH_H
Capture High-level Count High
CBH
00H
CAPH_L
Capture High-level Count Low
CCH
00H
CAPT_H
Capture Total Count High
C9H
00H
CAPT_L
Capture Total Count Low
CAH
00H
DPTR0:
Data Pointer (2 bytes)
DP0H
Data Pointer 0 High
83H
00H
DP0L
Data Pointer 0 Low
82H
00H
DPTR1:
Data Pointer 1 (2 bytes)
DP1H
Data Pointer 1 High
85H
00H
DP1L
Data Pointer 1 Low
84H
00H
GPWMCONT
General PWM Control Register
BAH
00H
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
GPWMDYH
General PWM Duty Register High
BEH
FFH
GPWMDYL
General PWM Duty Register Low
BDH
FFH
GPWMMAXH
General PWM Max Register High
BCH
00H
GPWMMAXL
General PWM Max Register Low
BBH
02H
HALLDBT
Hall De-bounce Time Register
9CH
0EH
HALLSET1
Hall Setting Register 1
91H
45H
HALLSET2
Hall Setting Register 2
92H
26H
HALLSET3
Hall Setting Register 3
93H
13H
HALLST
Hall Status Register
94H
XXH
IEN0
Interrupt Enable Register 0
A8H
00H
IEN1
Interrupt Enable Register 1
B8H
00H
IP0
Interrupt Priority Register 0
A9H
00H
IP1
Interrupt Priority Register 1
B9H
00H
IRCON1
Interrupt Request Register 1
C0H
00H
MCONT1
Motor Control Register 1
9DH
X011
0000B
MCONT2
Motor Control Register 2
A2H
00H
MD_CONT
MDU Control Register
DBH
00H
MD0
Multiplication Division Register 0
E2H
00H
MD1
Multiplication Division Register 1
E3H
00H
MD2
Multiplication Division Register 2
E4H
00H
MD3
Multiplication Division Register 3
E5H
00H
MD4
Multiplication Division Register 4
E6H
00H
MD5
Multiplication Division Register 5
E7H
00H
MPWMCONT1
MPWM Control Register 1
B1H
00H
MPWMCONT2
MPWM Control Register 2
B2H
00H
MPWMDB
Motor PWM Deadband Register
A7H
00H
MPWMDYUH
Motor PWM Duty Register U High (Phase U)
A6H
07H
MPWMDYUL
Motor PWM Duty Register U Low (Phase U)
A5H
FFH
MPWMDYVH
Motor PWM Duty Register V High (Phase V)
ABH
07H
MPWMDYVL
Motor PWM Duty Register V Low (Phase V)
AAH
FFH
MPWMDYWH
Motor PWM Duty Register W High (Phase W)
AEH
07H
MPWMDYWL
Motor PWM Duty Register W Low (Phase W)
ADH
FFH
MPWMINV
MPWM Inverse Selection Register
B3H
00H
MPWMMAXH
Motor PWM Max Register High
A4H
00H
MPWMMAXL
Motor PWM Max Register Low
A3H
02H
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
OCPCONT
OCP Control Register
A1H
04H
P0
Port 0
80H
FFH
P1
Port 1
90H
FFH
P2
Port 2
A0H
FFH
P3
Port 3
B0H
FFH
PCON
Power Control Register
87H
00H
PFCON
Peripheral Frequency Control Register
D1H
00H
PINCONG1
Pin Configure Register 1
F8H
AAH
PINCONG2
Pin Configure Register 2
F9H
AAH
PINCONG3
Pin Configure Register 3
FAH
A0H
PINCONG4
Pin Configure Register 4
FBH
AAH
PINCONG5
Pin Configure Register 5
FCH
AAH
PINCONG6
Pin Configure Register 6
FDH
A0H
PINCONG7
Pin Configure Register 7
C7H
20H
PINSET1
Pin I/O Setting Register 1
F1H
AAH
PINSET2
Pin I/O Setting Register 2
F2H
AAH
PINSET3
Pin I/O Setting Register 3
F3H
0AH
PINSET4
Pin I/O Setting Register 4
F4H
00H
PINSET5
Pin I/O Setting Register 5
F5H
80H
PINSET6
Pin I/O Setting Register 6
F6H
2AH
PINSET7
Pin I/O Setting Register 7
F7H
FFH
PSW
Program Status Word Register
D0H
00H
RCON
Internal RAM Control Register
86H
F0H
ROTORSPEE
Rotor Speed Count Register High
97H
FFH
Rotor Speed Count Register Low
96H
FFH
RSTS
Reset Source Register
FEH
0AH
SBUF
Serial Port Data Buffer
99H
00H
SCON
Serial Port Control Register
98H
00H
SP
Stack Pointer
81H
07H
SRELH
Serial Port Reload Register High
9BH
00H
SRELL
Serial Port Reload Register Low
9AH
00H
SVPWMAMPF
SVPWM Amplitude Fine-Tune Register
DAH
00H
SVPWM Amplitude Register High
C4H
00H
DH
ROTORSPEE
DL
T
SVPWMAMPH
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XN3700
8Bit Single-Chip Microcontroller
SVPWMAMPL
SVPWM Amplitude Register Low
C3H
00H
SVPWMANG
SVPWM Angle Register
C1H
00H
SYNC
MOC Sync Register
D7H
00H
T2CON
Timer2 Control Register
C8H
00H
TAKEY
Time Access Key Register
FFH
00H
TCON
Timer 0/1 Control Register
88H
00H
TH0
Timer0 High byte
8CH
00H
TH1
Timer1 High byte
8DH
00H
TH2
Timer2 High byte
B5H
00H
TL0
Timer0 Low byte
8AH
00H
TL1
Timer1 Low byte
8BH
00H
TL2
Timer2 Low byte
B4H
00H
TMOD
Timer 0/1 Mode Register
89H
00H
VRHALL
Virtual Hall Register
D9H
05H
WDTC
Watchdog Timer Control Register
B6H
04H
WDTK
Watchdog Timer Refresh Key
B7H
00H
12. Memory
The XN3700 memory structure follows the general 8052 structure. There are three memory
areas: Program Memory (Flash), External Data Memory (XRAM) and Internal Data Memory
(IRAM). In addition, XN3700 integrates 8Kbytes Flash, 256bytes IRAM and 256bytes XRAM.
12.1. Program Memory
The XN3700 contains 8Kbytes of on-chip Flash memory for program storage.
12.2. Data Memory
The XN3700 contains 256bytes of general internal data memory (IRAM) and 256bytes of
external data memory (XRAM).
12.2.1 Data Memory (IRAM)(00H~FFH)
The lower 128 bytes of IRAM may be accessed through both direct and indirect addressing.
The upper 128 bytes of IRAM and the 128 bytes of SFR registers share the same address
space. The upper 128 bytes of data memory may only be accessed using indirect addressing.
The SFR registers can only be accessed through direct addressing. The lowest 32 bytes (00H
-1FH) of data memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits
(PSW.3 and PSW.4) select which register bank is in use. Instructions using register
addressing will only access the currently specified bank.
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XN3700
8Bit Single-Chip Microcontroller
12.2.2 Data Memory (XRAM)(F000H~F0FFH)
External addresses F000H to F0FFh contain the on-chip expanded SRAM. This memory can
be accessed via external direct addressing mode (with MOVX instructions). The address
space of instruction MOVX @Ri,A (i=0,1) is determined by RCON [7:0] of SFR 86H RCON
(internal RAM control register). The default setting of RCON [7:0] is F0h (page0). One page of
XRAM is 256 bytes.
13. Instruction Set
The XN3700 is fully binary compatible with the MCS-51 instruction set.
Arithmetic
Description
Bytes
Cycles
Hex Code
ADD A,Rn
Add register to accumulator
1
1
0x28-0x2F
ADD A,direct
Add directly addressed data to accumulator
2
2
0x25
ADD A,@Ri
Add indirectly addressed data to accumulator
1
2
0x26-0x27
ADD A,#data
Add immediate data to accumulator
2
2
0x24
ADDC A,Rn
Add register to accumulator with carry
1
1
0x38-0x3F
operations
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XN3700
8Bit Single-Chip Microcontroller
ADDC A,direct
Add directly addressed data to accumulator
2
2
0x35
1
2
0x36-0x37
with carry
ADDC A,@Ri
Add indirectly addressed data to accumulator
with carry
ADDC A,#data
Add immediate data to accumulator with carry
2
2
0x34
SUBB A,Rn
Subtract register from accumulator with
1
1
0x98-0x9F
2
2
0x95
1
2
0x96-0x97
2
2
0x94
borrow
SUBB A,direct
Subtract directly addressed data from
accumulator with borrow
SUBB A,@Ri
Subtract indirectly addressed data from
accumulator with borrow
SUBB A,#data
Subtract immediate data from accumulator
with borrow
INC A
Increment accumulator
1
1
0x04
INC Rn
Increment register
1
2
0x08-0x0F
INC direct
Increment directly addressed location
2
3
0x05
INC @Ri
Increment indirectly addressed location
1
3
0x06-0x07
INC DPTR
Increment data pointer
1
1
0xA3
DEC A
Decrement accumulator
1
1
0x14
DEC Rn
Decrement register
1
2
0x18-0x1F
DEC direct
Decrement directly addressed location
2
3
0x15
DEC @Ri
Decrement indirectly addressed location
1
3
0x16-0x17
MUL AB
Multiply A and B
1
5
0xA4
DIV
Divide A by B
1
5
0x84
DA A
Decimally adjust accumulator
1
1
0xD4
Logicoperations
Description
Bytes
Cycles
Hex Code
ANL A,Rn
AND register to accumulator
1
1
0x58-0x5F
ANL A,direct
AND directly addressed data to accumulator
2
2
0x55
ANL A,@Ri
AND indirectly addressed data to accumulator
1
2
0x56-0x57
ANL A,#data
AND immediate data to accumulator
2
2
0x54
ANL direct,A
AND accumulator to directly addressed
2
3
0x52
3
4
0x53
location
ANL direct,#data
AND immediate data to directly addressed
location
ORL A,Rn
OR register to accumulator
1
1
0x48-0x4F
ORL A,direct
OR directly addressed data to accumulator
2
2
0x45
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XN3700
8Bit Single-Chip Microcontroller
ORL A,@Ri
OR indirectly addressed data to accumulator
1
2
0x46-0x47
ORL A,#data
OR immediate data to accumulator
2
2
0x44
ORL direct,A
OR accumulator to directly addressed location
2
3
0x42
ORL direct,#data
OR immediate data to directly addressed
3
4
0x43
location
XRL A,Rn
Exclusive OR register to accumulator
1
1
0x68-0x6F
XRL A,direct
Exclusive OR directly addressed data to
2
2
0x65
1
2
0x66-0x67
accumulator
XRL A,@Ri
Exclusive OR indirectly addressed data to
accumulator
XRL A,#data
Exclusive OR immediate data to accumulator
2
2
0x64
XRL direct,A
Exclusive OR accumulator to directly
2
3
0x62
3
4
0x63
addressed location
XRL direct,#data
Exclusive OR immediate data to directly
addressed location
CLR A
Clear accumulator
1
1
0xE4
CPL A
Complement accumulator
1
1
0xF4
RL A
Rotate accumulator left
1
1
0x23
RLC A
Rotate accumulator left through carry
1
1
0x33
RR A
Rotate accumulator right
1
1
0x03
RRC A
Rotate accumulator right through carry
1
1
0x13
SWAP A
Swap nibbles within the accumulator
1
1
0xC4
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XN3700
8Bit Single-Chip Microcontroller
Data transfer
Description
Bytes
Cycles
Hex Code
MOV A,Rn
Move register to accumulator
1
1
0xE8-0xEF
MOV A,direct
Move directly addressed data to
2
2
0xE5
1
2
0xE6-0xE7
operations
accumulator
MOV A,@Ri
Move indirectly addressed data to
accumulator
MOV A,#data
Move immediate data to accumulator
2
2
0x74
MOV Rn,A
Move accumulator to register
1
2
0xF8-0xFF
MOV Rn,direct
Move directly addressed data to register
2
4
0xA8-0xAF
MOV Rn,#data
Move immediate data to register
2
2
0x78-0x7F
MOV direct,A
Move accumulator to direct
2
3
0xF5
MOV direct,Rn
Move register to direct
2
3
0x88-0x8F
MOV direct1,direct2
Move directly addressed data to directly
3
4
0x85
2
4
0x86-0x87
3
3
0x75
1
3
0xF6-0xF7
2
5
0xA6-0xA7
2
3
0x76-0x77
addressed location
MOV direct,@Ri
Move indirectly addressed data to directly
addressed location
MOV direct,#data
Move immediate data to directly
addressed location
MOV @Ri,A
Move accumulator to indirectly addressed
location
MOV @Ri,direct
Move directly addressed data to indirectly
addressed location
MOV @Ri,#data
Move immediate data to in directly
addressed location
MOV DPTR,#data16
Load data pointer with a 16-bit immediate
3
3
0x90
MOVC A,@A+DPTR
Load accumulator with a code byte
1
3
0x93
1
3
0x83
1
3
0xE2-0xE3
1
3
0xE0
1
4
0xF2-0xF3
relative to DPTR
MOVC A,@A+PC
Load accumulator with a code byte
relative to PC
MOVX A,@Ri
Move external RAM (8-bit addr.) to
accumulator
MOVX A,@DPTR
Move external RAM (16-bit addr.) to
accumulator
MOVX @Ri,A
Move accumulator to external RAM (8-bit
addr.)
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XN3700
8Bit Single-Chip Microcontroller
MOVX @DPTR,A
Move accumulator to external RAM (16-bit
1
4
0xF0
addr.)
PUSH direct
Push directly addressed data onto stack
2
4
0xC0
POP direct
Pop directly addressed location from
2
3
0xD0
stack
XCH A,Rn
Exchange register with accumulator
1
2
0xC8-0xCF
XCH A,direct
Exchange directly addressed location with
2
3
0xC5
accumulator
XCH A,@Ri
Exchange indirect RAM with accumulator
1
3
0xC6-0xC7
XCHD A,@Ri
Exchange low-order nibbles of indirect
1
3
0xD6-0xD7
and accumulator
Program branches
Description
Bytes
Cycles
Hex Code
ACALL addr11
Absolute subroutine call
2
6
xxx10001b
LCALL addr16
Long subroutine call
3
6
0x12
RET
Return from subroutine
1
4
0x22
RETI
Return from interrupt
1
4
0x32
AJMP addr11
Absolute jump
2
3
xxx00001b
LJMP addr16
Long jump
3
4
0x02
SJMP rel
Short jump (relative address)
2
3
0x80
JMP @A+DPTR
Jump indirect relative to the DPTR
1
2
0x73
JZ rel
Jump if accumulator is zero
2
3
0x60
JNZ rel
Jump if accumulator is not zero
2
3
0x70
JC rel
Jump if carry flag is set
2
3
0x40
JNC
Jump if carry flag is not set
2
3
0x50
JB bit,rel
Jump if directly addressed bit is set
3
4
0x20
JNB bit,rel
Jump if directly addressed bit is not set
3
4
0x30
JBC bit,rel
Jump if directly addressed bit is set and
3
4
0x10
3
4
0xB5
3
4
0xB4
3
4
0xB8-0xBF
3
4
0xB6-0xB7
clear bit
CJNE A,direct,rel
Compare directly addressed data to
accumulator and jump if not equal
CJNE A,#data,rel
Compare immediate data to accumulator
and jump if not equal
CJNE Rn,#data,rel
Compare immediate data to register and
jump if not equal
CJNE @Ri,#data,rel
Compare immed. to ind. and jump if not
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XN3700
8Bit Single-Chip Microcontroller
equal
DJNZ Rn,rel
Decrement register and jump if not zero
2
3
0xD8-0xDF
DJNZ direct,rel
Decrement directly addressed location
3
4
0xD5
and jump if not zero
NOP
No operation
1
1
0
Boolean
Description
Bytes
Cycles
Hex Code
CLR C
Clear carry flag
1
1
0xC3
CLR bit
Clear directly addressed bit
2
3
0xC2
SETB C
Set carry flag
1
1
0xD3
SETB bit
Set directly addressed bit
2
3
0xD2
CPL C
Complement carry flag
1
1
0xB3
CPL bit
Complement directly addressed bit
2
3
0xB2
ANL C,bit
AND directly addressed bit to carry flag
2
2
0x82
ANL C,/bit
AND complement of directly addressed bit
2
2
0xB0
mainpulation
to carry
ORL C,bit
OR directly addressed bit to carry flag
2
2
0x72
ORL C,/bit
OR complement of directly addressed bit
2
2
0xA0
to carry
MOV C,bit
Move directly addressed bit to carry flag
2
2
0xA2
MOV bit,C
Move carry flag to directly addressed bit
2
3
0x92
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XN3700
8Bit Single-Chip Microcontroller
14. MCU
14.1 8051 Engine
SFR
Description
address
Reset value
ACC
Accumulator
E0H
00H
B
B Register
F0H
00H
PSW
Program Status Word Register
D0H
00H
SP
Stack Pointer
81H
07H
DP0H
Data Pointer 0 High
83H
00H
DP0L
Data Pointer 0 Low
82H
00H
DP1H
Data Pointer 1 High
85H
00H
DP1L
Data Pointer 1 Low
84H
00H
AUX
Auxiliary
8EH
11H
RCON
Internal RAM Control Register
86H
F0H
14.1.1 ACC (Accumulator)
The most important of all special function registers, that‟s the first comment about
Accumulator which is also known as ACC or A. The Accumulator(sometimes referred to as
Register A also) holds the result of most of arithmetic and logic operations.
14.1.2 B (B Register)
The B register is used during multiplying and division instructions. It can also
be used as a scratch-pad register to hold temporary data.
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8Bit Single-Chip Microcontroller
14.1.3 PSW (Program Status Word Register)
The PSW register contains status bits that reflect the current state of the CPU.Note that the
Parity bit can only be modified by hardware upon the state of ACC register.
The state of RS1and RS0bits selects the working register bank as follows:
RS1
RS0
Selected Register Bank
Location
0
0
Bank 0
00H –07H
0
1
Bank 1
08H –0FH
1
0
Bank 2
10H –17H
1
1
Bank 3
18H –1FH
14.1.4 SP (Stack Pointer)
This register points to the top of stack in internal data memory space. It is used to store the
return address of program before executing interrupt routine or subprograms. The SP is
incremented before executing PUSH or CALL instruction and it is decremented after executing
POP or RET(I) instruction (it always points the top of stack). A reset initializes the stack pointer
to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08.
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XN3700
8Bit Single-Chip Microcontroller
14.1.5 DP0 (Data Pointer 0)
These registers are intended to hold 16-bit address in the indirect addressing mode used by
MOVX (move external memory), MOVC (move program memory) or JMP (computed branch)
instructions. They may be manipulated as16-bit register or as two separate 8-bit registers.
DP0H holds higher byte and DP0L holds lower byte of indirect address.
It is generally used to access external code or data space, e.g.:
MOVC A,@A+DPTR (code space)
MOV A,@DPTR (data space)
14.1.6 DP1 (Data Pointer 1)
The dual data pointer accelerates the movement of block data. The standard DPTR is a 16-bit
register that is used to address external memory, or peripherals. The standard data pointer is
called DPTR0 and the second data pointer is called DPTR1. The data pointer select bit
chooses the active pointer. The data pointer select bit (DPS) is located in the LSB of AUX
register(AUX.1).
The user switches between DPTR0 and DPTR1 by toggling the DPS bit. All DPTR-related
instructions use the currently selected DPTR for any activity.
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XN3700
8Bit Single-Chip Microcontroller
14.1.7 AUX (Auxiliary Register)
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XN3700
8Bit Single-Chip Microcontroller
14.1.8 RCON (Internal RAM Control Register)
256 bytes of on-chip expanded RAM are provided and can be accessed by external memory
addressing method only (instruction MOVX). The address space of instruction MOVX @Ri,A
(i= 0,1) is determined by RCON [7:0] of RCON. The default setting of RCON [7:0] is F0H.
14.2 GPIO
Four I/O ports are available: Port0, Port1, Port2, and Port3.
All 25 port pins on XN3700 can configure to one of four modes : quasi-bidirectional (standard
8051 port outputs), push-pull output, open drain output, or input-only. All port pins default to
input-only mode after reset.Two configuration registers (PINSETx, PINCONFGx) for each port
select the output mode for each port pin.
SFR
Description
address
Reset value
P0
Port 0
80H
FFH
P1
Port 1
90H
FFH
P2
Port 2
A0H
FFH
P3
Port 3
B0H
FFH
PINCONG1
Pin Configure Register 1
F8H
AAH
PINCONG2
Pin Configure Register 2
F9H
AAH
PINCONG3
Pin Configure Register 3
FAH
A0H
PINCONG4
Pin Configure Register 4
FBH
AAH
PINCONG5
Pin Configure Register 5
FCH
AAH
PINCONG6
Pin Configure Register 6
FDH
A0H
PINCONG7
Pin Configure Register 7
C7H
20H
PINSET1
Pin I/O Setting Register 1
F1H
AAH
PINSET2
Pin I/O Setting Register 2
F2H
AAH
PINSET3
Pin I/O Setting Register 3
F3H
0AH
PINSET4
Pin I/O Setting Register 4
F4H
00H
PINSET5
Pin I/O Setting Register 5
F5H
80H
PINSET6
Pin I/O Setting Register 6
F6H
2AH
PINSET7
Pin I/O Setting Register 7
F7H
FFH
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XN3700
8Bit Single-Chip Microcontroller
14.2.1 Port
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XN3700
8Bit Single-Chip Microcontroller
14.2.2 PINCONG (Pin Configure Register)
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XN3700
8Bit Single-Chip Microcontroller
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XN3700
8Bit Single-Chip Microcontroller
14.2.3 PINSET (Pin I/O Setting Register)
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XN3700
8Bit Single-Chip Microcontroller
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XN3700
8Bit Single-Chip Microcontroller
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XN3700
8Bit Single-Chip Microcontroller
14.3 Clock Structure
The clock source of the device may be either external, or internal. The external crystal (12MHz)
is connect to pins XTALIand XTALO. The internal clock source (on-chip oscillator) is run at
12MHz. The choice of internal, or external, clock source is setting by Writer.
14.4 Timer
The XN3700 has three 16-bit timer/counter registers: Timer0, Timer1 and Timer2. All can be
configured for counter, or timer, operations.In addition to the “timer” or “counter” selection,
Timer0 and Timer1 have four operating modes from which to select which are selected by
bit-pairs (M1, M0) in TMOD. Modes 0, 1,and 2 are the same for both timer/counters. Mode 3 is
different.
Two Special Function registers (TMOD and TCON) are used to select the appropriate
mode.
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XN3700
8Bit Single-Chip Microcontroller
SFR
Description
address
Reset value
PFCON
Peripheral Frequency control Register
D1H
00H
TMOD
Timer 0/1 Mode Register
89H
00H
TCON
Timer 0/1 Control Register
88H
00H
T2CON
Timer2 Control Register
C8H
00H
TH0
Timer0 High byte
8CH
00H
TL0
Timer0 Low byte
8AH
00H
TH1
Timer1 High byte
8DH
00H
TL1
Timer1 Low byte
8BH
00H
TH2
Timer2 High byte
B5H
00H
TL2
Timer2 Low byte
B4H
00H
14.4.1 PFCON (Peripheral Frequency Control Register)
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XN3700
8Bit Single-Chip Microcontroller
14.4.2 TMOD (Timer 0/1 Mode Register)
TMOD register is used in configuration of MCU Timer0 and Timer1.
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XN3700
8Bit Single-Chip Microcontroller
14.4.3 TCON (Timer 0/1 Control Register)
TCON register is used to control operation of these modules. XN3700 includes two external
digital interrupt sources INT0N and INT1N), with dedicated interrupt sources. INT0N and
INT1N are configurable as falling edge or low level. The IT0 and IT1 bits in TCON select levelor edge-sensitive. IE0 and IE1 in the TCON register serve as the interrupt-pending flags for
the INT0N and INT1N external interrupts, respectively.
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XN3700
8Bit Single-Chip Microcontroller
The TF0, TF1 (Timer0 and Timer1 overflow flags), IE0 and IE1 (External interrupt 0 and 1
flags) will be automatically cleared by hardware when the corresponding service routine is
called.
14.4.4 T2CON (Timer2 Control Register)
T2CON is used to control Timer2 run/stop, mode, prescaler.
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XN3700
8Bit Single-Chip Microcontroller
14.4.5 Timer0 Mode 0
14.4.6 Timer0 Mode 1
14.4.7 Timer0 Mode 2
14.4.8 Timer0 Mode 3
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XN3700
8Bit Single-Chip Microcontroller
14.4.9 Timer1 Mode 0
14.4.10 Timer1 Mode 1
14.4.11 Timer1 Mode 2
14.4.12 Timer2 Mode 0
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XN3700
8Bit Single-Chip Microcontroller
14.4.13 Timer2 Mode 1
14.4.14 Timer2 Mode 2
14.4.15 Timer2 Mode 3
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XN3700
8Bit Single-Chip Microcontroller
14.5 Watchdog Timer
The Watchdog Timer (WDT) is a 8-bit free-running counter that generates a reset signal or
interrupt (WDTC.6) if it overflows. It can help the application software to recover from an
abnormal condition. The WDT is independent from Timer0, Timer1, or Timer2. The F_WDT is
375KHz, it is from on-chip RC oscillator.
Figure 12.5.1 WDT block diagram
SFR
Description
address
Reset value
RSTS
Reset Source Register
FEH
0AH
TAKEY
Time Access Key Register
FFH
00H
WDTC
Watchdog Timer Control
B6H
04H
B7H
00H
Register
WDTK
Watchdog Timer Refresh Key
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8Bit Single-Chip Microcontroller
14.5.1 WDTC (Watchdog Timer Control Register)
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14.5.2 TAKEY (Time Access Key Register)
14.5.3 WDTK (Watchdog Timer Refresh Key)
For example, enable the watchdog with a time-out reset period of 5.461ms.
Following write sequence:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah ; WDTC write is available.
MOV WDTC, #23h ; WDTM [3:0] = 0011b. WDTE =1 to enable the WDT.
MOV WDTK, #55h ; Refresh WDT.
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8Bit Single-Chip Microcontroller
14.6 Serial Port (UART)
The Serial Port provides a flexible full-duplex synchronous/asynchronous receiver/transmitter,
called UART. The communication rate can be set by configuring the baud rate in SFRs. The
two serial buffers consist of two separate registers, a transmit buffer and a receive buffer.
Writing data to the SFR SBUF, transfers the data to the serial output buffer and starts the
transmission. Reading from the SBUF, reads data from the serial receive buffer. The serial
port can simultaneously transmit and receive data. It can also buffer 1 byte at receive, which
prevents the receive data from being lost if the CPU reads the second byte before the
transmission of the first byte is completed.
SFR
Description
address
Reset value
AUX
Auxiliary
8EH
11H
PFCON
Peripheral Frequency Control
D1H
00H
Register
SCON
Serial Port Control Register
98H
00H
SBUF
Serial Port Data Buffer
99H
00H
SRELH
Serial Port Reload Register High
9BH
00H
SRELL
Serial Port Reload Register Low
9AH
00H
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14.6.1 SCON (Serial Port Control Register)
The SCON register controls the function of Serial Port (UART).
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8Bit Single-Chip Microcontroller
Serial Port working in modes 1 or mode 3:
When BRS = 0 (AUX.2)
TIPS[1:0] = 00b
TIPS[1:0] = 01b
TIPS[1:0] = 10b
When BRS = 1 (AUX.2)
SRELPS[1:0] = 00b
SRELPS [1:0] = 01b
SRELPS [1:0] = 10b
SRELPS [1:0] = 11b
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14.6.2 SBUF (Serial Port Data Buffer)
Writing data to this register sets data in serial output buffer and starts the transmission through
Serial Port. Reading from the SBUF, reads data from the serial receive buffer.
14.6.3 SREL (Serial Port Reload Register)
Serial Port Reload Register is used for Serial Port baud rate generation. Only 10 bits are used,
where 8 bits from the SRELL as lower bits and 2 bits from the SRELH (SRELH.1, SRELH.0)
as higher bits.
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14.7 Power Management
The Power Control Register (PCON) is used to control the XN3700 STOP and IDLE power
management modes.
14.7.1 STOP MODE
Setting the STOP Mode Select bit (PCON.1) causes the controller core to enter STOP mode
as soon as the instruction that sets the bit completes execution. In STOP mode the CPU,
GPIO, UART, and Timers are stopped, but the ADC, MOC, and WDT is still work.
STOP mode can terminate by an internal or external reset. On reset, the device performs the
normal reset sequence and begins program execution at address 0x0000. The assertion of an
enabled interrupt will cause the STOP Mode Selection bit (PCON.1) to be cleared and the
CPU to resume operation.
14.7.2 IDLE MODE
Setting the IDLE Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter
IDLE mode as soon as the instruction that sets the bitcompletes execution.
In IDLE mode only the CPU is stop. All internal registers and memory maintain their original
data.
IDLE mode can terminate by an internal or external reset. On reset, the device performs the
normal reset sequence and begins program execution at address 0x0000. The assertion of an
enabled interrupt will cause the IDLE Mode Selection bit (PCON.0) to be cleared and the CPU
to resume operation.
14.8 Reset
The reset logic is used to place the device into a known state.
XN3700 provides Power-on Reset flag, External Reset RSTN flag and Watchdog timer Reset
flag to monitor reset status. The source of the reset can be monitor.
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14.8.1 RSTS (Reset Source Register)
14.9 Interrupt Controller
The ISR - Interrupt Service Routine unit, is a subcomponent responsible for interrupt handling.
It receives up to 14 interrupt requests. Each interrupt source has its own request flag that is
located in devices which is a source of interrupt. No interrupt request flags are located directly
in ISR. All interrupts are requested by high level on correspondent inputs to ISR. Each of the
interrupt sources can be individually enabled or disabled by corresponding enable flag in IEN0,
IEN1 SFR registers.. Additionally all interrupts can be globally enabled or disabled by the
―EA flag in the IEN0 SFR. All interrupt sources are divided into 6 interrupts groups. Each of
the interrupt groups can have one of four interrupt priority levels assigned. The interrupt
priority level is defined by flags located in the IP0 and IP1 SFR registers.
Interrupt Number Interrupt Vector Address
Interrupt Request Flags
(use Keil C Tool)
0
0003H
IE0 –External interrupt 0
1
000BH
TF0 –Timer0 interrupt
2
0013H
IE1 –External interrupt1
3
001BH
TF1 –Timer1 interrupt
4
0023H
SPIF(TI, RI)–Serial port interrupt
5
002BH
TF2 –Timer2 interrupt
6
0033H
-----
7
003BH
-----
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8
0043H
OCPSIF –OCP Short interrupt
9
004BH
HALLIF –HALL interrupt
10
0053H
MPWMMINIF–MPWM MIN interrupt
11
005BH
MPWMMAXIF–MPWM MAX interrupt
12
0063H
GPWMMAXIF –GPWM MAX interrupt
13
006BH
LVDIF –Low voltage detect interrupt
14
0073H
WDTIF –Watchdog timer interrupt
15
007BH
OCPLIF –OCP Limit interrupt
Table14.9.1 Interrupt vectors
Group priority
Highest
Lowest
Interrupt
Highest priority
Lowest priority
Group
in group
in group
Group0
LVDIF
IE0
-----
Group1
WDTIF
TF0
-----
Group2
OCPSIF
HALLIF
IE1
Group3
MPWMMINIF
MPWMMAXIF
TF1
Group4
GPWMMAXIF
SPIF(TI, RI)
-----
Group5
OCPLIF
2TF2
-----
Table14.9.2 Interrupt Priority Groups
SFR
Description
address
Reset value
IEN0
Interrupt Enable Register 0
A8H
00H
IEN1
Interrupt Enable Register 1
B8H
00H
IRCON1
Interrupt Request Register 1
C0H
00H
IP0
Interrupt Priority Register 0
A9H
00H
IP1
Interrupt Priority Register 1
B9H
00H
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14.9.1 IEN0 (Interrupt Enable Register 0)
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14.9.2 IEN1 (Interrupt Enable Register 1)
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14.9.3 IRCON1 (Interrupt Request Register 1)
14.9.4 IP (Interrupt Priority Register)
The 14 interrupt sources are grouped into 6 priority groups. For each of the groups, one of four
priority levels can be selected. It is achieved by setting appropriate values in IP0 and IP1
registers. The contents of the Interrupt Priority Registers define the priority levels for each
interrupt source according to the tables below.
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Level
Priority
GxIP1
GxIP0
Level 0
Lowest
0
0
Level 1
0
1
Level 2
1
0
1
1
Level 3
Highest
15.10-bit Analog-to-Digital Converter (ADC)
The XN3700 provides eight channels 10-bit ADC. The result of the conversion is provided at
ADCD [9:0].
SFR
Description
address
Reset value
ADCCONT
ADC Control Register
D2H
80H
ADCSTR
ADC Start Convert and Setting Register
D3H
00H
ADCD1
ADC Data Register 1
D5H
00H
ADCD2
ADC Data Register 2
D6H
00H
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Figure15.1 ADC conversion timing
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15.1 ADCCONT (ADC Control Register)
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15.2 ADCSTR (ADC Start Convert and Setting Register)
15.3 ADCD1 (ADC Data Register 1)
15.4 ADCD2 (ADC Data Register 2)
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16 General PWM (GPWM)
XN3700 have one 16-bit general PWM output (PINSET6.4 = „1‟) and six 11-bit PWM
(compensation with Deadband) for Motor Controller.
GPWM is count up and down timer. (fixed)
SFR
Description
address
Reset value
GPWMCONT
General PWM Control Register
BAH
00H
GPWMMAXH
General PWM Max Register High
BCH
00H
GPWMMAXL
General PWM Max Register Low
BBH
02H
GPWMDYH
General PWM Duty Register High
BEH
FFH
GPWMDYL
General PWM Duty Register Low
BDH
FFH
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16.1 GPWMCONT (General PWM Control Register)
16.2 GPWMMAX (General PWM Max Register)
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16.3 GPWMDY (General PWM Duty Register)
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17. Capture
SFR
Description
address
Reset value
CAPCONT
Capture Control Register
D8H
03H
CAPH_H
Capture High-level Count High
CBH
00H
CAPH_L
Capture High-level Count Low
CCH
00H
CAPT_H
Capture Total Count High
C9H
00H
CAPT_L
Capture Total Count Low
CAH
00H
17.1 CAPCONT (Capture Control Register)
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17.2 CAPT (Capture Total Count)
17.3 CAPH (Capture High-level Count)
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18. Addition and Subtraction Unit (ASU)
ASU provides 32-bit Addition and Subtraction calculation.
SFR
Description
address
Reset value
AS_MD_CONT
ASU and MDU Control Register
E1H
10H
ASUD1_1
ASU Data 1 byte 1
E8H
00H
ASUD1_2
ASU Data 1 byte 2
E9H
00H
ASUD1_3
ASU Data 1 byte 3
EAH
00H
ASUD1_4
ASU Data 1 byte 4
EBH
00H
ASUD2_1
ASU Data 2 byte 1
ECH
00H
ASUD2_2
ASU Data 2 byte 2
EDH
00H
ASUD2_3
ASU Data 2 byte 3
EEH
00H
ASUD2_4
ASU Data 2 byte 4
EFH
00H
ASUR1
ASU Result Register 1
DCH
00H
ASUR2
ASU Result Register 2
DDH
00H
ASUR3
ASU Result Register 3
DEH
00H
ASUR4
ASU Result Register 4
DFH
00H
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18.1 AS_MD_CONT (ASU and MDU Control Register)
18.2 ASUD1 (ASU Data 1)
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18.3 ASUD2 (ASU Data 2)
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18.4 ASUR (ASU Result Register)
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19. Multiplication and Division Unit (MDU)
The MDU is an on-chip arithmetic co-processor which enables the XN3700 to perform
additional extended arithmetic operations. All operations are singed/unsigned integer
operations. Operands and results are stored in MD0 – MD5 registers. The module is
controlled by the AS_MD_CONT and MD_CONT register. Any calculation of the MDU
overwrites its operands. The MDU support five operations: Division 32-bit/16-bit, Division
16-bit/16-bit,Multiplication, Shift and Normalize.
SFR
Description
address
Reset value
AS_MD_CONT
ASU and MDU Control Register
E1H
10H
MD_CONT
MDU Control Register
DBH
00H
MD0
Multiplication Division Register 0
E2H
00H
MD1
Multiplication Division Register 1
E3H
00H
MD2
Multiplication Division Register 2
E4H
00H
MD3
Multiplication Division Register 3
E5H
00H
MD4
Multiplication Division Register 4
E6H
00H
MD5
Multiplication Division Register 5
E7H
00H
19.1 AS_MD_CONT (ASU and MDU Control Register)
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19.2 MD_CONT (MDU Control Register)
19.2.1 MDEF
The MDEF error flag indicates an improperly performed operation (when one of the arithmetic
operations has been restarted or interrupted by a new operation). The error flag mechanism is
automatically enabled with the first write operation to MD0 and disabled with the final read
instruction from MD3 (multiplication or shift/norm) or MD5 (division) in phase three.
The error flag is set when:
There is a write access to MDx registers (any of MD0 - MD5 and MD_CONT) during phase
two of MDU operation (restart or calculations interrupting) There is a read access to one of
MDx registers during phase two of MDU operation when the error flag mechanism is enabled.
In such condition error flag is set but the calculation is not interrupted. The error flag is reset
only after read access to MD_CONT register. The error flag is read only.
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19.2.2 MDOV
The MDOV overflow flag is set when one of the following conditions occurs: Division by zero
Multiplication with a result greater than FFFFH
Start of normalizing if the („MD3.7‟ = „1‟) most significant bit of MD3 is set Any operation of
the MDU that does not match the above conditions clears the overflow flag. Note that the
overflow flag is exclusively controlled by hardware. lt cannot be written.
19.3 MD0 – MD5 (Multiplication Division Register)
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19.4 MDU Operation Description
The operation of the MDU consists of three phases:
19.4.1 Loading the MDx registers
The type of calculation the MDU has to perform is selected by the order in which the MDx
registers are written to. A write to MD0 is the first transfer to be done in any case. Next writes
must be done as shown in the table below to determine the MDU operation. The last write will
start the selected operation.
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19.4.2 Executing calculation
During the calculation period, the MDU works in parallel to the CPU. When the
calculation is complete, the hardware will set the MDUF bit to one (MDUF = „1‟).
The flag will be cleared at the next calculation.
The following table provides the execution time for each mathematical operation.
19.4.3 Reading the result from the MDx registers
The Read-out sequence of the first “MDx” registers is not critical.
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19.4.4 Shifting
In shift operation, 32-bit integer variable stored in MD0 to MD3 registers (the latter contains
the most significant byte) is shifted left or right by a specified number of bits. The SLR bit
(MD_CONT.5) defines the shift direction, and bits SC[4:0] (MD_CONT.4 – MD_CONT.0)
specifies the shift count (which must not be 0). During shift operation, zeroes come into the left
end of MD3 for shifting right or right end of the MD0 for shifting left.
19.4.5 Normalizing
All leading zeroes of 32-bit integer variable stored in MD0 to MD3 registers, the latter contains
the most significant byte are removed by shift left operations. The whole operation is
completed when the MSB (most significant bit) of MD3 register contains a „1„. After
normalizing, bits SC[4:0] (MD_CONT.4 – MD_CONT.0) contain the number of shift left
operations, which were done.
20. Motor Controller (MOC)
20.1 HALL Interface
SFR
Description
address
Reset value
HALLDBT
Hall De-bounce Time Register
9CH
0EH
HALLSET1
Hall Setting Register 1
91H
45H
HALLSET2
Hall Setting Register 2
92H
26H
HALLSET3
Hall Setting Register 3
93H
13H
HALLST
Hall Status Register
94H
XXH
ROTORSPEEDH
Rotor Speed Count Register
97H
FFH
96H
FFH
D9H
05H
High
ROTORSPEEDL
Rotor Speed Count Register
Low
VRHALL
Virtual Hall Register
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20.1.1 HALLDBT (Hall De-bounce Time Register)
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20.1.2 HALLSET (Hall Setting Register 1, 2, 3)
HALLSET define forward direction HALL sequence.
1 Hall alignment select HALLALS = 0 (MCONT1)
○
Line Voltage (Line to Line) sequence is Vuv leads Vvw by 120 degrees and
Vvw leads Vwu by 120 degrees. (Forward direction define in XN3700)
Hall signal is alignment with Line Voltage.
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2 Hall alignment select HALLALS = 1 (MCONT1)
○
Phase Voltage sequence is Vu leads Vv by 120 degrees and Vv leads Vw
by 120 degrees. (Forward direction define in XN3700)
Hall signal is alignment with Phase Voltage.
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20.1.3 HALLST (Hall Status Register)
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20.1.4 ROTORSPEED (Rotor Speed Count Register)
ROTORSPEED is a 16-bit counter (counter is limit at FFFFH). Clock source is
depends on HCKS (MCONT1 reg.). The counter input is HALL U.
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20.1.5 VRHALL(Virtual Hall Register)
20.2 Motor PWM Engine
MPWM is count up and down timer. (fixed)
SFR
Description
address
MCONT1
Motor Control Register 1
9DH
Reset value
X011
0000B
MCONT2
Motor Control Register 2
A2H
00H
MPWMMAXH
Motor PWM Max Register High
A4H
00H
MPWMMAXL
Motor PWM Max Register Low
A3H
02H
MPWMDYUH
Motor PWM Duty Register U High
A6H
07H
A5H
FFH
ABH
07H
AAH
FFH
AEH
07H
ADH
FFH
(Phase U)
MPWMDYUL
Motor PWM Duty Register U Low
(Phase U)
MPWMDYVH
Motor PWM Duty Register V High
(Phase V)
MPWMDYVL
Motor PWM Duty Register V Low
(Phase V)
MPWMDYWH
Motor PWM Duty Register W High
(Phase W)
MPWMDYWL
Motor PWM Duty Register W Low
(Phase W)
MPWMDB
Motor PWM Deadband Register
A7H
00H
MPWMCONT1
MPWM Control Register 1
B1H
00H
MPWMCONT2
MPWM Control Register 2
B2H
00H
MPWMINV
MPWM Inverse Selection Register
B3H
00H
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20.2.1 MCONT1 (Motor Control Register 1)
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20.2.2 MCONT2 (Motor Control Register 2)
20.2.3 MPWMMAX (Motor PWM Max Register)
MPWM is 11-bit timer. The frequency of MPWM timer is 48MHz. (fixed)
MPWM is count up and down timer. (fixed)
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20.2.4 MPWMDY (Motor PWM Duty Register)
MPWM is 11-bit timer.
MPWMDYU is phase U PWM duty. MPWMDYV is phase V PWM duty.
MPWMDYW is phase W PWM duty.
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20.2.5 MPWMDB (Motor PWM Deadband Register)
Compensation PWM output with Deadband is use to prevent short-though between high-side
and low-side power device.
The frequency of MPWMDB is 48MHz. (fixed)
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20.2.6 MPWMCONT1 (MPWM Control Register 1)
Motor High-side PWM output mode select :
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20.2.7 MPWMCONT2 (MPWM Control Register 2)
Motor Low-side PWM output mode select :
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20.2.8 MPWMINV (MPWM Inverse Selection Register)
Motor six PWM output Inverse select :
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20.3 Space Vector PWM (SVPWM)
SFR
Description
address
Reset value
SVPWMAMPH
SVPWM Amplitude Register High
C4H
00H
SVPWMAMPL
SVPWM Amplitude Register Low
C3H
00H
SVPWMAMPFT
SVPWM Amplitude Fine-Tune
DAH
00H
Register
SVPWMANG
SVPWM Angle Register
C1H
00H
AS
Angle Shift Control Register
8FH
00H
2019.05 v1.0 Xindamao Micro-Electronics
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
20.3.1 SVPWMAMP (SVPWM Amplitude Register)
SVPWMAMP is control by user.
20.3.2 SVPWMAMPFT (SVPWM Amplitude Fine-Tune Register)
20.3.3 SVPWMANG (SVPWM Angle Register)
1.875∘/bit
0∘~ 358.125∘= 0 ~ 191(SVPWMANG)
When MWPMA = „1‟ (auto mode), SVPWMANG is control by MOC.
When MWPMA = „0‟, SVPWMANG is control by user.
2019.05 v1.0 Xindamao Micro-Electronics
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
20.3.4 AS (Angle Shift Control Register)
AS is used to compensate phase lag between current and voltage
1.875∘/bit
When MWPMA = „1‟ (auto mode), AS is active. Control by user.
2019.05 v1.0 Xindamao Micro-Electronics
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
20.4 Over Current Protect (OCP)
2019.05 v1.0 Xindamao Micro-Electronics
www.xindamao.com.cn
Datasheet
XN3700
8Bit Single-Chip Microcontroller
2019.05 v1.0 Xindamao Micro-Electronics
www.xindamao.com.cn
Datasheet
XN3700
8Bit Single-Chip Microcontroller
2019.05 v1.0 Xindamao Micro-Electronics
www.xindamao.com.cn
Datasheet
XN3700
8Bit Single-Chip Microcontroller
2019.05 v1.0 Xindamao Micro-Electronics
www.xindamao.com.cn
Datasheet
XN3700
8Bit Single-Chip Microcontroller
2019.05 v1.0 Xindamao Micro-Electronics
www.xindamao.com.cn
Datasheet
XN3700
8Bit Single-Chip Microcontroller
20.5 SYNC
MOC behavior is synchronized with MPWM, many MOC SFRs have shadow register that is
used to update these SFRs at the same time with SYNC register. Write SYNC any value will
synchronization update these SFRs at the same time.
Shadow register : (need SYNC)
HALLSET1
HALLSET2
HALLSET3
AS
MPWMMAXH, MPWMMAXL
MPWMDYUH, MPWMDYUL
MPWMDYVH, MPWMDYVL
MPWMDYWH, MPWMDYWL
MPWMDB
MPWMINV
MPWMCONT1
MPWMCONT2
GPWMMAX
GPWMDY
GPWMOCNT.GPMS, GPWMOCNT.GPCT, GPWMOCNT.GPCKS
SVPWMAMP
2019.05 v1.0 Xindamao Micro-Electronics
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
21. Package Information
21.1 SSOP-28 150mil(AD4) Outline Dimensions
2019.05 v1.0 Xindamao Micro-Electronics
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
21.2 SSOP-20 150mil(AD2) Outline Dimensions
2019.05 v1.0 Xindamao Micro-Electronics
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Datasheet
XN3700
8Bit Single-Chip Microcontroller
21.3 LQFP-32 7x7mm(AA1) Outline Dimensions
2019.05 v1.0 Xindamao Micro-Electronics
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Datasheet
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