FM25Q128AI3-SOB-T-G

FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY Datasheet Sep. 2022 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 1 INFORMATION IN THIS DOCUMENT IS INTENDED AS A REFERENCE TO ASSIST OUR CUSTOMERS IN THE SELECTION OF SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCT BEST SUITED TO THE CUSTOMER'S APPLICATION AND SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD DOES NOT GUARANTEE THE AUTHENTICITY AND INTEGRITY OF THE INFORMATION. INFORMATION DO NOT CONVEY ANY LICENSE UNDER ANY INTELLECTUAL PROPERTY RIGHTS, OR ANY OTHER RIGHTS, BELONGING TO SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD OR A THIRD PARTY. WHEN USING THE INFORMATION CONTAINED IN THIS DOCUMENTS, PLEASE BE SURE TO EVALUATE ALL INFORMATION AS A TOTAL SYSTEM BEFORE MAKING A FINAL DECISION ON THE APPLICABILITY OF THE INFORMATION AND PRODUCTS. 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Description The FM25Q128AI3 is a 128M-bit (16,384K-byte) Serial Flash memory, operating in wide voltage range. The FM25Q128AI3 supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O as well as 2-clock instruction cycle Quad Peripheral Interface (QPI). The FM25Q128AI3 can be programmed 1 to 256 bytes at a time, using the Page Program instruction. It is designed to allow either single Sector/Block at a time or full chip erase operation. The FM25Q128AI3 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. 2. Features  128Mbit of Flash memory – 4096 uniform sectors with 4K-byte each – 256 uniform blocks with 64K-byte each or – 512 uniform blocks with 32K-byte each – 256 bytes per programmable page  Serial Interface – Standard SPI: CLK, CS#, DI, DO, WP# – Dual SPI: CLK, CS#, DQ0, DQ1, WP# – Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3 – QPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3 – Continuous READ mode support – Program / Erase Suspend and Resume support – Allow true XIP (execute in place) operation  High Performance – Max FAST_READ clock frequency: 100MHz – Max READ clock frequency: 50MHz – Typical page program time: 0.7ms – Typical sector erase time: 45ms – Typical block erase time: 200/250ms – Typical chip erase time: 50s  Supply Voltage: 2.3V to 3.6V  Industrial Temperature Rage FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY  Flexible Architecture with 4KB Sectors – Uniform Sector Erase(4K-bytes) – Uniform Block Erase(32K and 64Kbytes) – Program 1 to 256 bytes per programmable page – Erase/Program Suspend & Resume  Advanced Security Features – Software and hardware write protection – Top/Bottom, 4KB complement array protection – Power Supply Lock-Down and OTP protection – Individual Block/Sector array protection – Lockable 4X256-Byte OTP Security Register – Discoverable Parameters (SFDP) Register – 64-Bit Unique ID for each device – Volatile & Non-volatile Status Register Bits  Green Package – 8-pin SOP (208mil) – 8-pad TDFN (6x5mm) – 24-ball BGA (8x6mm) – All Packages are RoHS Compliant and Halogen-free V1.0 Datasheet 3 3. Packaging Type And Pin Configurations FM25Q128AI3 is offered in an 8-pin SOP (208mil)，an 8-pad TDFN (6x5mm) and a 24-ball BGA (8x6mm) packages as shown in Figure 1-3 respectively. Package diagrams and dimensions are illustrated at the end of this datasheet. 3.1. Pin Configuration SOP8 (208-mil) Top View CS# DO(DQ1) WP#(DQ2) VSS 1 2 8 7 3 4 6 5 VCC HOLD#/RESET# (DQ3) CLK DI(DQ0) Figure 1 FM25Q128AI3 pin assignments, 8-pin SOP(208mil) 3.2. Pin Configuration TDFN8 (6x5mm) Top View CS# 1 DO(DQ1) 2 WP#(DQ2) 3 VSS 4 8 VCC HOLD#/RESET# 7 (DQ3) 6 CLK 5 DI(DQ0) Figure 2 FM25Q128AI3 pad assignments, 8-pad TDFN(6x5mm) 3.3. Ball Configuration BGA24 (8x6mm) (6x4 Ball Array) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 4 Top View A1 A2 A3 A4 NC NC NC NC B1 B2 B3 B4 NC CLK VSS VCC C1 C2 C3 C4 NC CS# NC D1 D2 D3 NC DO(DQ1) E1 E2 E3 E4 NC NC NC NC F1 F2 F3 F4 NC NC NC NC WP#(DQ2) D4 DI(DQ0) HOLD#/RESET# (DQ3) Figure 3 FM25Q128AI3 pad assignments, 24-ball BGA (8x6mm) 3.4. Pin Configuration PIN NAME CLK VSS VCC CS# WP# (DQ2) DO (DQ1) DI (DQ0) HOLD#/RESET# (DQ3) NC I/O FUNCTION I Serial Clock Input Ground Power Supply I Chip Select Input I/O Write Protect Input (Data Input Output 2)(2) I/O Data Output (Data Input Output 1)(1) I/O Data Input (Data Input Output 0)(1) I/O Hold Input (Data Input Output 3)(2) No connect Note: 1 DQ0 and DQ1 are used for Dual SPI instructions. 2 DQ0 – DQ3 are used for Quad SPI and QPI instructions 3 WP#(DQ2), HOLD#/RESET#(DQ3) will remain internal pull up function while this pin is not physically connected in system confguration. However, the internal pull up function will be disabled if the system has physical connection to WP#(DQ2) or HOLD#/RESET#(DQ3). FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 5 4. Pin Descriptions 4.1. Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2, DQ3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When CS# is brought low, the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. The CS# input must track the VCC supply level at power-up (see “8 Write Protection” and Figure 81). If needed a pull-up resister on CS# can be used to accomplish this. 4.2. Serial Data Input, Output and I/Os (DI, DO and DQ0, DQ1, DQ2, DQ3) The FM25Q128AI3 supports standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual/Quad SPI and QPI instructions use the bidirectional DQ pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the WP# pin becomes DQ2 and HOLD# pin becomes DQ3. 4.3. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Registers from being written. The WP# pin is active low. However, when the QE bit of Status Register-2 is set for Quad I/O, the WP# pin function is not available since this pin is used for DQ2. 4.4. HOLD (HOLD#) The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the HOLD# pin function is not available since this pin is used for DQ3. 4.5. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. 4.6. Reset(RESET#) The RESET# pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the DQ3 pin can be configured either as a HOLD# pin or as a RESET# pin depending on Status Register setting. When QE=1, the HOLD# or RESET# function is not available. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 6 5. Block Diagram Address Generator r e d o c e D r X e d o c e D HV Generator Memory Array ic g lo t u tp HOLD/RESET# u (DQ3) O l ia r e WP#(DQ ) 2 S Y WP# CS# c i g o L t u p n Il ia r e S Y-Gating DO(DQ1) CLK DI SRAM DI(DQ0) Sense Amplifier DO HOLD/R ESET# Clock Generator State Machine Figure 4 FM25Q128AI3 Serial Flash Memory Block Diagram FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 7 6. Memory Organization The FM25Q128AI3 array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed (bits are programmed from 1 to 0) at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The FM25Q128AI3 has 4,096 erasable sectors, 512 erasable 32-k byte blocks and 256 erasable 64-k byte blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. Table 1 Block (64KB) 255 Block (32KB) 511 | 510 ...... ...... 248 497 | 496 ...... ...... 15 31 | 30 ...... ...... 8 7 ...... 2 1 0 17 | 16 15 | 14 ...... 5 | 4 3 | 2 1 | 0 Memory Organization Sector (4KB) 4095 … 4080 ...... ...... ...... 3983 … 3968 ...... ...... ...... 255 … 240 ...... ...... ...... 143 … 128 127 … 112 ...... ...... ...... 47 … 32 31 … 16 15 … 2 1 0 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY Address Range FFF000h … FF0000h ...... ...... ...... F8F000h … F80000h ...... ...... ...... 0FF000h … 0F0000h ...... ...... ...... 08F000h … 080000h 07F000h … 070000h ...... ...... ...... 02F000h … 020000h 01F000h … 010000h 00F000h … 002000h 001000h 000000h V1.0 FFFFFFh … FF0FFFh ...... ...... ...... F8FFFFh … F80FFFh ...... ...... ...... 0FFFFFh … 0F0FFFh ...... ...... ...... 08FFFFh … 080FFFh 07FFFFh … 070FFFh ...... ...... ...... 02FFFFh … 020FFFh 01FFFFh … 010FFFh 00FFFFh … 002FFFh 001FFFh 000FFFh Datasheet 8 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 9 7. Device Operations Power On Reset (66h + 99h)/ Hardware Reset Reset (66h + 99h)/ Hardware Reset Device Initialization Standard SPI Dual SPI Quad SPI operations Enable QPI (38h) Disable QPI (FFh) QPI operations Figure 5 FM25Q128AI3 Serial Flash Memory Operation Diagram 7.1. Standard SPI The FM25Q128AI3 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device. The DO output pin is used to read data or status from the device. Commands, write instructions, addresses or data are latched on the rising edge of CLK, read data or status are available on the falling edge of CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of CS#. For Mode 3, the CLK signal is normally high on the falling and rising edges of CS#. CS# CLK MODE3 MODE3 MODE0 MODE0 DI DO DONT CARE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB HIGH IMPEDANCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB Figure 6 The difference between Mode 0 and Mode 3 7.2. Dual SPI The FM25Q128AI3 supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” , “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (codeshadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: DQ0 and DQ1. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 10 7.3. Quad SPI The FM25Q128AI3 supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)”, “Octal Word Read Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional DQ0 and DQ1 and the WP # and HOLD# pins become DQ2 and DQ3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 7.4. QPI The FM25Q128AI3 supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four DQ pins to input the instruction code, thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enable QPI (38h)” and “Disable QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction or hardware reset, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional DQ0 and DQ1, and the WP# and HOLD# pins become DQ2 and DQ3 respectively. See Figure 5 for the device operation modes. 7.5. Hold For Standard SPI and Dual SPI operations, the HOLD# signal allows the FM25Q128AI3 operation to be paused while it is actively selected (when CS# is low). The HOLD# function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the HOLD# function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The HOLD# function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI. To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD# condition will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition will terminate after the next falling edge of CLK. During a HOLD# condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic state of the device. Active Hold FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY Active V1.0 Hold Active Datasheet 11 Figure 7 Hold Condition Waveform 7.6. Software Reset & Hardware Reset The FM25Q128AI3 can be reset to the initial power-on sate by a Software Reset sequence, either in SPI or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). No command will be accepted during the reset period. FM25Q128AI3 can also be configured to utilize a hardware RESET# pin. The HOLD/RST bit in the Status Register-2 is the configuration bit for HOLD# pin function or RESET# pin function. When HOLD/RST=0 (factory default), the pin acts as a HOLD# pin as described above; when HOLD/RST=1, the pin acts as a RESET# pin. Drive the RESET# pin low for a minimum period of ~1us will reset the device to its initial power-on state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While RESET# is low, the device will not accept any command input. If QE bit is set to 1, the HOLD# or RESET# function will be disabled, the pin will become one of the four data I/O pins. Hardware RESET# pin has the highest priority among all the input signals. Drive RESET# low for a minimum period of ~1us will interrupt any on-going external/internal operations, regardless the status of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#). Note: 1. While a faster RESET# pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum time is recommended to ensure reliable operation. 2. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when software/hardware reset is accepted by the device. It is recommended to check the WIP bit and the SUS bit in Status Register before issuing the software reset command or hardware reset. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 12 8. Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the FM25Q128AI3 provides several means to protect the data from inadvertent writes. Write Protect Features         Device resets when VCC is below threshold during WRITE operation Time delay write disable after Power-up Write enable/disable instructions and automatic write disable after erase or program Software and Hardware (WP# pin) write protection using Status Register Advanced Sector Protection Write Protection using Power-down instruction Lock Down write protection for Status Register until the next power-up One Time Program (OTP) write-protection for array and Security Sectors using Status Register. At power-up and power-down, the device must not be selected; that is, CS# must follow the voltage applied on VCC until VCC reaches the correct values: VCC (min) at power-up and Vss at power-down. To avoid data corruption and inadvertent WRITE operations during power-up, a power-on reset circuit is included. The logic inside the device is held to RESET while VCC is less than the poweron reset threshold voltage of VCC (low); all operations are disabled, and the device does not respond to any instruction. During a standard power-up phase, the device ignores all commands. After power-up, the device is in standby power mode. In the event Power-on Reset (POR) did not complete correctly after power up, the assertion of the RESET# signal or receiving a software reset command (RESET) will restart the POR process. At power-down, when VCC drops from the operating voltage to below the threshold voltage VCC (low), all operations are disabled and the device does not respond to any command. Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress, data corruption may result. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP[3:0]) bits. These settings allow a portion as small as a 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. The FM25Q128AI3 also provides another Write Protect method using the individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 254 blocks) and each 4KB sector within the top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block. The WPS bit in Status Register-2 is used to decide which Write Protect scheme should be used. When WPS=0(factory default), the device will only utilize CMP,SEC,TB, BP[2:0] to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection, each protect scheme for the corresponding is available. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 13 9. Status Register Three Status Registers are provided for FM25Q128AI3. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the Flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Sector lock status, Erase/Program Suspend status and output driver strength. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Sector OTP lock, Hold/RESET functions and output driver strength. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the WP# pin. Factory default for all Status Register bits are 0. 9.1. Status Register-1(SR1) Related Commands: Read Status Register (RDSR1 05h), Write Status Register (WRSR 01h), Write Enable (WREN 06h), Write Disable (WRDI 04h), Write Enable for Volatile Status Register (50h). S7 S6 SRP0 SEC S5 S4 S3 S2 S1 S0 TB BP2 BP1 BP0 WEL WIP STATUS REGISTER PROTECT 0 (Volatile/Non-Volatile writable) SECTOR PROTECT BIT (Volatile/Non-Volatile writable should be set to 0) TOP/BOTTOM PROTECT (Volatile/Non-Volatile writable) BLOCK PROTECT BITS (Volatile/Non-Volatile writable) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS Figure 8 Status Register-1 9.1.1. Write In Progress (WIP) WIP is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Sector instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in “11.6 AC Electrical Characteristics”). When the program, erase or write status register (or security sector) instruction has completed, the WIP bit will be cleared to a 0 state indicating the device is ready for further instructions. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 14 9.1.2. Write Enable Latch (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Sector and Program Security Sector. 9.1.3. Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in “11.6 AC Electrical Characteristics”). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection). The factory default setting for the Block Protection Bits is 0, none of the array protected. 9.1.4. Top/Bottom Block Protect (TB) The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits. 9.1.5. Sector/Block Protect (SEC) The non-volatile Sector/Block Protect bit (SEC) should be set to 0. The factory default setting is SEC=0. 9.2. Status Register-2 (SR2) Related Commands: Read Status Register-2 (RDSR2 35h), Write Status Register-2 (WRSR2 31h), Write Enable (WREN 06h), Write Disable (WRDI 04h), Write Enable for Volatile Status Register (50h). S15 HOLD or RESET function (Volatile/Non-Volatile Writable) COMPLEMENT PROTECT (Volatile/Non-Volatile Writable) S14 S13 S12 S11 HOLD DRV DRV WPS CMP /RST 1 0 S10 S9 S8 LB QE SRP1 OUTPUT DRIVE STRENGTH (Volatile/Non-Volatile Writable) WRITE PROTECT SELECTION (Volatile/Non-Volatile Writable) SECURITY REGISTER LOCK BIT (Volatile/Non-Volatile writable) QUAD ENABLE (Volatile/Non-Volatile writable) STATUS REGISTER PROTECT 1 (Volatile/Non-Volatile writable) Figure 9 Status Register-2 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 15 9.2.1. Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. Table 2 SRP1 SRP0 WP# 0 0 X 0 1 0 0 1 1 1 0 X 1 1 X Status Register Protect bits Status Register Description WP# pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. (Factory Default) Hardware When WP# pin is low the Status Register locked and can Protected not be written to. Hardware When WP# pin is high the Status register is unlocked and Unprotected can be written to after a Write Enable instruction, WEL=1. Power Supply Status Register is protected and can not be written to Lock-Down again until the next power-down, power-up cycle.(1) One Time Status Register is permanently protected and can not be Program written to. Software Protection Note: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 9.2.2. HOLD# or RESET# pin function(HOLD/RST) The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0 (factory default), the pin acts as HOLD#; when HOLD/RST=1, the pin acts as RESET#. However, HOLD# or RESET# functions are only available when QE=0. If QE is set to 1, the HOLD# and RESET# functions are disabled, the pin acts as a dedicated data I/O pin. 9.2.3. Complement Protect (CMP) The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP[2:0] bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to Status Register Memory Protection table for details. The default setting is CMP=0. 9.2.4. Write Protect Selection (WPS) The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, TB, SEC, BP[2:0] to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset. 9.2.5. Output driver strength (DRV1, DRV0) The DRV1 & DRV0 bits are used to determine the output driver strength. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 16 Table 3 Driver strength configuration DRV1, DRV0 0,0 0,1 1,0 1,1 9.2.6. Driver Strength 100% 75% 50% 25% Security Sector Lock Bit (LB) The Security Register Lock Bit (LB) is non-volatile One Time Program (OTP) bits in Status Register (S10) that provide the write protect control and status to the Security Registers. The default state of LB is 0, Security Registers are unlocked. LB can be set to 1 individually using the Write Status Register instruction. LB is One Time Programmable (OTP), once it’s set to 1, the corresponding 1024-Byte Security Register will become read-only permanently. 9.2.7. Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI and QPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# are enabled. When the QE bit is set to a 1, the Quad DQ2 and DQ3 pins are enabled, and WP# and HOLD# functions are disabled. QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from Standard/Dual/Quad SPI to QPI; otherwise the command will be ignored. When the device is in QPI mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a 1 to a 0. WARNING: If the WP# or HOLD# pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1. 9.3. Status Register-3 (SR3) Related Commands: Read Status Register-3 (RDSR3 15h), Write Enable (06h). Write Enable (06h) can be used to clear ERR bit of SR3 if ERR is set to 1 by the last operation. S23 S22 S21 S20 S19 S18 S17 S16 SUS RFU RFU RFU ERR RFU RFU RFU SUSPEND STATUS (Volatile, Read Only) Reserved Program/Erase Fail Bit (Volatile,Read Only) Reserved Figure 10 Status Register-3 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 17 9.3.1. Erase/Program Suspend Status (SUS) The Suspend Status bit is a read only bit in the status register (S23) that is set to 1 after executing an Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. 9.3.2. Write Fail Bit (ERR) The Write Fail bit is a status flag, which shows the status of last write operation. It will be set to 1, if the program or erase or write status register operation fails. It is cleard to 0 by WREN (06h) or Reset operation. 9.4. Status Register Memory Protection (WPS=0, CMP=0) Table 4 Status Register Memory Protection (WPS=0, CMP=0) STATUS REGISTER SEC FM25Q128AI3 (128M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED PROTECTED DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 252 thru 255 FC0000h – FFFFFFh 256KB Upper 1/64 0 0 0 1 0 248 thru 255 F80000h – FFFFFFh 512KB Upper 1/32 0 0 0 1 1 240 thru 255 F00000h – FFFFFFh 1MB Upper 1/16 0 0 1 0 0 224 thru 255 E00000h – FFFFFFh 2MB Upper 1/8 0 0 1 0 1 192 thru 255 C00000h – FFFFFFh 4MB Upper 1/4 0 0 1 1 0 128 thru 255 800000h – FFFFFFh 8MB Upper 1/2 0 1 0 0 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/64 0 1 0 1 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/32 0 1 0 1 1 0 thru 15 000000h – 0FFFFFh 1M Lower 1/16 0 1 1 0 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/8 0 1 1 0 1 0 thru 63 000000h – 3FFFFFh 4MB Lower 1/4 0 1 1 1 0 0 thru 127 000000h – 7FFFFFh 8MB Lower 1/2 0 X 1 1 1 0 thru 255 000000h – FFFFFFh 16MB ALL 1 0 0 0 1 255 FFF000h – FFFFFFh 4KB Top Block 1 0 0 1 0 255 FFE000h – FFFFFFh 8KB Top Block 1 0 0 1 1 255 FFC000h – FFFFFFh 16KB Top Block 1 0 1 0 X 255 FF8000h – FFFFFFh 32KB Top Block 1 0 1 1 0 255 FF8000h – FFFFFFh 32KB Top Block 1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block 1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block 1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 18 STATUS REGISTER SEC 9.5. FM25Q128AI3 (128M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED PROTECTED DENSITY PORTION 1 1 1 0 X 0 000000h – 007FFFh 32KB Bottom Block 1 1 1 1 0 255 000000h – 007FFFh 32KB Bottom Block Status Register Memory Protection (WPS=0, CMP=1) Table 5 Status Register Memory Protection (WPS=0, CMP=1) STATUS REGISTER SEC FM25LQ128 (128M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED PROTECTED DENSITY PORTION 0 X 0 0 0 0 to 255 000000h – FFFFFFh ALL ALL 0 0 0 0 1 0 to 255 000000h – FBFFFFh 16128KB Lower 63/64 0 0 0 1 0 0 to 255 000000h – F7FFFFh 15872KB Lower 31/32 0 0 0 1 1 0 to 255 000000h – EFFFFFh 15MB Lower 15/16 0 0 1 0 0 0 to 255 000000h – DFFFFFh 14MB Lower 7/8 0 0 1 0 1 0 to 255 000000h – BFFFFFh 12MB Lower 3/4 0 0 1 1 0 0 to 255 000000h – 7FFFFFh 8MB Lower 1/2 0 1 0 0 1 4 to 255 040000h – FFFFFFh 16128KB Upper 63/64 0 1 0 1 0 8 to 255 080000h – FFFFFFh 15872KB Upper 31/32 0 1 0 1 1 16 to 255 100000h – FFFFFFh 15MB Upper 15/16 0 1 1 0 0 32 to 255 200000h – FFFFFFh 14MB Upper 7/8 0 1 1 0 1 64 to 255 400000h – FFFFFFh 12MB Upper 3/4 0 1 1 1 0 128 to 255 800000h – FFFFFFh 8MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 to 255 000000h – FFEFFFh 16380KB L-4095/4096 1 0 0 1 0 0 to 255 000000h – FFDFFFh 16376KB L-2047/2048 1 0 0 1 1 0 to 255 000000h – FFBFFFh 16368KB L-1023/1024 1 0 1 0 X 0 to 255 000000h – FF7FFFh 16352KB L-511/512 1 0 1 1 0 0 to 255 000000h – FF7FFFh 16352KB L-511/512 1 1 0 0 1 0 to 255 001000h – FFFFFFh 16380KB U-4095/4096 1 1 0 1 0 0 to 255 002000h – FFFFFFh 16376KB U-2047/2048 1 1 0 1 1 0 to 255 004000h – FFFFFFh 16368KB U-1023/1024 1 1 1 0 X 0 to 255 008000h – FFFFFFh 16352KB U-511/512 1 1 1 1 0 0 to 255 001000h – FFFFFFh 16352KB U-511/512 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 19 Status Register Memory Protection (WPS=1) Block 255 (64KB) 9.6. Sector 15(4KB) ... Sector 14(4KB) . Individual Block Locks: 32 Sectors(Top/Bottom) 254 Blocks . Sector 1(4KB) Sector 0(4KB) Individual Block Lock: 36h + Address Block 254(64KB) .. .. ... .. . Individual Block Unlock: 39h + Address Read Block Lock: 3Dh + Address Block 0 (64KB) Block 1(64KB) Global Block Lock: 7Eh Sector 15(4KB) .. Sector 14(4KB) .. Global Block Unlock: 98h . Sector 1(4KB) Sector 0(4KB) Figure 11 Individual Sector/Block Locks FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 20 10. Instructions The Standard/Dual/Quad SPI instruction set of the FM25Q128AI3 consists of 44 basic instructions that are fully controlled through the SPI bus (see Table 7 ~ Table 10 Instruction Set). Instructions are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. The QPI instruction set of the FM25Q128AI3 consists of 30 basic instructions that are fully controlled through the SPI bus (see Table 10 Instruction Set). Instructions are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked through DQ[3:0] pins provides the instruction code. Data on all four DQ pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions, addresses, data and dummy bytes are using all four DQ pins to transfer every byte of data with every two serial clocks (CLK). Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of CS#. Clock relative timing diagrams for each instruction are included in Figure 12 through Figure 85. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (CS# driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 10.1. Device ID and Instruction Set Tables 10.1.1. Manufacture and Device Identification Table 6 OP Code ABh 90h, 92h, 94h 9Fh Manufacturer and Device Identification MF7-MF0 ID15-ID0 17h 17h A1h A1h FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY ID7-ID0 4018h V1.0 Datasheet 21 10.1.2. Standard SPI Instructions Set Table 7 Standard SPI Instructions Set (1) CLOCK NUMBER Write Enable Volatile SR Write Enable Write Disable Read Status Register-1 Write Status Register-1(3) Read Status Register-2 Write Status Register-2 BYTE 1 (0-7) 06h 50h 04h 05h 01h 35h 31h Read Status Register-3 15h Page Program Sector Erase (4KB) Block Erase (32KB) Block Erase (64KB) 02h 20h 52h D8h C7h/60 h 75h 7Ah B9h 03h 0Bh INSTRUCTION NAME Chip Erase Erase / Program Suspend Erase / Program Resume Power-down Read Data Fast Read BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (8-15) (16-23) (24-31) (32-39) (40-47) (S7-S0)(2) (S7-S0) (3) (S15-S8)(2) (S15-S8) (S23S16)(2) A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 D7-D0 D7-D0(4) A23-A16 A23-A16 A15-A8 A15-A8 A7-A0 A7-A0 (D7-D0) dummy (ID7ID0)(2) (MF7MF0) (5) ABh dummy dummy Dummy Manufacturer/Device ID(5)(6) 90h dummy dummy 00h (ID15ID8) Memory Type 00h (ID7ID0) Capacit y A7-A0 dummy dummy Release Powerdown / ID (D7-D0) (ID7-ID0) Read SFDP Register 5Ah (MF7MF0) Manufactur er 00h Read Unique ID(6) 4Bh dummy dummy dummy 44h A23-A16 A15-A8 A7-A0 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 48h A23-A16 A15-A8 A7-A0 dummy (D7-D0) 38h 66h 99h 36h 39h 3Dh 7Eh 98h A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 JEDEC ID (6) Erase Security Sectors(7) Program Security Sectors(7) Read Security Sectors(7) Enable QPI Enable Reset Reset Individual Block Lock Individual Block Unlock Read Block Lock Global Block Lock Global Block Unlock 9Fh FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 (D7-D0) (UID63UID0) Datasheet 22 10.1.3. Dual SPI Instructions Set Table 8 INSTRUCTION NAME BYTE 1 Dual SPI Instructions Set BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (40-47) (D7D0, …)(9) CLOCK NUMBER (0-7) (8-15) (16-23) (24-31) (32-39) Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 Dummy Fast Read Dual I/O BBh A23-A8(8) A7-A0, M7-M0 (8) Dummy Manufacturer/Device ID by Dual I/O(5)(6) 92h A23-A8(8) A7-A0, M7-M0(8) (MF7-MF0, ID7-ID0) (D7-D0, …)(9) 10.1.4. Quad SPI Instructions Set Table 9 Quad SPI Instructions Set CLOCK NUMBER BYTE 1 (0-7) Quad Page Program 32h A23-A16 A15-A8 A7-A0 Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 Fast Read Quad I/O EBh Dummy (D7D0, …)(11) Word Read Quad I/O(12) E7h Dummy (D7D0, …)(11) Octal Word Read Quad I/O(13) E3h Dummy (D7D0, …)(11) Set Burst with Wrap 77h Manufacture/Device ID by Quad I/O(5)(6) 94h xxxx, (MF7-MF0, ID7-ID0) (MF7-MF0, ID7ID0, …) INSTRUCTION NAME BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (8-15) (16-23) (24-31) (32-39) D7D0, …(11) (40-47) D7D0, …(11) (D7D0, …)(11) A23-A0, M7M0(10) A23-A0, M7M0(10) A23-A0, M7M0(10) xxxxx, W6W4(10) A23-A0, M7M0(10) Dummy 10.1.5. QPI Instructions Set Table 10 QPI Instructions Set (14) INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 CLOCK NUMBER Write Enable Volatile SR Write Enable Write Disable (0,1) 06h 50h 04h (2,3) (4,5) (6,7) (8,9) (10,11) Read Status Register-1 05h Write Status Register-1(3) 01h FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY (S7S0)(2) (S7-S0) (3) V1.0 Datasheet 23 INSTRUCTION NAME BYTE 1 Read Status Register-2 35h Write Status Register-2 31h Read Status Register-3 15h BYTE 2 (S15S8)(2) (S15-S8) (S23S16)(2) BYTE 3 BYTE 4 Erase / Program Suspend Erase / Program Resume Power-down Set Read Parameters Enable Reset Reset Disable QPI Fast Read Burst Read with Wrap Fast Read Quad I/O(16) C7h/60 h 75h 7Ah B9h C0h 66h 99h FFh 0Bh 0Ch EBh A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 Release Powerdown / ID(5) ABh dummy dummy dummy Manufacturer/Device ID(5)(6) 90h dummy dummy 00h (5)(6) 9Fh (MF7MF0) Manufac turer (ID15ID8) Memory Type (ID7ID0) Capacit y Page Program 02h A23-A16 A15-A8 A7-A0 Sector Erase (4KB) Block Erase (32KB) Block Erase (64KB) Individual Block Lock Individual Block Unlock Read Block Lock Global Block Lock Global Block Unlock 20h 52h D8h 36h 39h 3Dh 7Eh 98h A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 Chip Erase JEDEC ID BYTE 5 BYTE 6 P7-P0 dummy(15) dummy(15) M7-M0(15) (ID7ID0)(2) (MF7MF0) D7D0(11) (D7-D0) (D7-D0) (D7-D0) (ID7-ID0) D7-D0(4) (D7-D0) (2) Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device on either 1, 2 or 4 DQ pins. 2. The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction. 3. Write Status Register-1(01h) can also be used to program Status Register-1&2, see section 10.2.5 4. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Sectors, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 5. See Table 6 Manufacturer and Device Identification table for device ID information. 6. Please contact Shanghai Fudan Microelectronics Group Co., Ltd for details. 7. Security Sector Address: Security Sector 0: A23-A16 = 00h; A15-A8 = 00h; A7-A0 = byte address Security Sector 1: A23-A16 = 00h; A15-A8 = 01h; A7-A0 = byte address FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 24 8. 9. 10. 11. 12. 13. 14. Security Sector 2: A23-A16 = 00h; A15-A8 = 10h; A7-A0 = byte address Security Sector 3: A23-A16 = 00h; A15-A8 = 11h; A7-A0 = byte address Dual SPI address input format: DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 Dual SPI data output format: DQ0 = (D6, D4, D2, D0) DQ1 = (D7, D5, D3, D1) Quad SPI address input format: Set Burst with Wrap input format: DQ0 = A20, A16, A12, A8, A4, A0, M4, M0 DQ0 = x, x, x, x, x, x, W4, x DQ1 = A21, A17, A13, A9, A5, A1, M5, M1 DQ1 = x, x, x, x, x, x, W5, x DQ2 = A22, A18, A14, A10, A6, A2, M6, M2 DQ2 = x, x, x, x, x, x, W6, x DQ3 = A23, A19, A15, A11, A7, A3, M7, M3 DQ3 = x, x, x, x, x, x, x, x Quad SPI data input/output format: DQ0 = (D4, D0 …) DQ1 = (D5, D1…) DQ2 = (D6, D2…) DQ3 = (D7, D3…) For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0) For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0) QPI Command Address, Data input/output format: CLK# 0 1 2 3 4 5 6 7 8 9 10 11 DQ0 C4 C0 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 DQ1 C5 C1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 DQ2 C6 C2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 DQ3 C7 C3 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 15. The number of dummy clocks is controlled by read parameter P6-P4. 16. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P1-P0 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 25 10.2. Instruction Description 10.2.1. Write Enable (WREN) (06h) The Write Enable (WREN) instruction (Figure 12) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register , Erase/Program Security Sectors and Block/Sector Lock/Unlock instruction. The Write Enable (WREN) instruction is entered by driving CS# low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving CS# high. CS# CS# Mode 3 CLK Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 Mode 3 0 1 Mode 0 Mode 3 Mode 0 Instruction (06h) Mode 0 DQ0 Instruction (06h) DI (DQ0) DQ1 DQ2 High Impedance D0 (DQ1) DQ3 Figure 12 Write Enable Instruction for SPI Mode (left) or QPI Mode (right) 10.2.2. Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 9.1, 9.2, 9.3 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 13) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values. CS# CS# Mode 3 CLK Mode 3 CLK 0 1 2 3 4 5 Mode 0 6 7 Mode 3 Mode 0 0 1 Mode 0 Mode 3 Mode 0 Instruction( 50h) DQ0 Instruction (50h) DI (DQ0) DQ1 DQ2 D0 (DQ1) High Impedance DQ3 Figure 13 Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 26 10.2.3. Write Disable (WRDI) (04h) The Write Disable (WRDI) instruction (Figure 14) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable (WRDI) instruction is entered by driving CS# low, shifting the instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Sectors, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase , Block/Sector Lock/Unlock and Reset instructions. CS# CS# Mode 3 CLK Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 0 Mode 3 1 Mode 0 Mode 0 Instruction (04h) Mode 0 DQ0 Instruction (04h) DI (DQ0) DQ1 DQ2 High Impedance D0 (DQ1) DQ3 Figure 14 Write Disable Instruction for SPI Mode (left) or QPI Mode (right) 10.2.4. Read Status Register-1 (RDSR1) (05h), Status Register-2 (RDSR2) (35h) & Status Register-3 (RDSR3) (15h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2 or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 15. Refer to section 9.1, 9.2 and 9.3 for Status Register description. The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the WIP status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 16. The instruction is completed by driving CS# high. CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 0 Mode 0 Instruction (05h/35h/15h) DI (DQ0) Status Register 1/2/3 out Status Register 1/2/3 out D0 (DQ1) High Impedance 7 =MSB 6 5 4  3 2 1 0 7 6 5 4 3 2 7  Figure 15 Read Status Register Instruction (SPI Mode) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 27 CS# Mode 3 CLK 0 1 2 4 3 5 Mode 0 Instruction 05h/35h/15h DQ0 4 0 4 0 4 DQ1 5 1 5 1 5 DQ2 6 2 6 2 6 DQ3 7 3 7 3 7 SR1/2/3 out SR1/2/3 out Figure 16 Read Status Register Instruction (QPI Mode) 10.2.5. Write Status Register-1 (WRSR1) (01h), Status Register-2 (WRSR2) (31h) The Write Status Register instruction allows the Status Register to be written. The writable Status Register bits include: SRP0, TB, SEC, BP2, BP1 and BP0 in Status Register-1; HOLD/RST, CMP, LB, QE, SRP1, DRV1, DRV0 and WPS in Status Register-2. All other Status Register bit locations are read-only and will not be affected by Write Status Register instruction. LB is a non-volatile OTP bit, once it is set to 1, it cannot be cleared to 0. To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code “01h/31h”, and then writing the status register data byte as illustrated inFigure 17 & Figure 18. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP1 and LB cannot be changed from 1 to 0 because of the OTP protection for these bits. Upon power off or the execution of Software Reset, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored. During non-volatile Status Register write operation (06h combined with 01h/31h), after CS# is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See “11.6 AC Electrical Characteristics”). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. During volatile Status Register write operation (50h combined with 01h/31h), after CS# is driven high, the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See “11.6 AC Electrical Characteristics”). WIP bit will remain 0 during the Status Register bit refresh period. The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit cannot be written to 0 when the device is in the QPI mode, because QE=1 is required FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 28 for the device to enter and operate in the QPI mode. Refer to section 9.1, 9.2, 9.3 for Status Register description. Factory default for all status Register bits are 0. CS# 0 Mode 3 CLK 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 Mode 3 Mode 0 Mode 0 Status Register 1/2 in Instruction (01h/31h) DI (DQ0) D0 (DQ1) 7 6 5 4 3 2 1 0  High Impedance =MSB Figure 17 Write Status Register-1/2 Instruction (SPI Mode) CS# Mode 3 CLK 0 1 2 Mode 3 3 Mode 0 Mode 0 Instruction 01h/31h SR1/2 in DQ0 4 0 DQ1 5 1 DQ2 6 2 DQ3 7 3 Figure 18 Write Status Register-1/2 Instruction (QPI Mode) The FM25Q128AI3 is also backward compatible to FMSH’s previous generations of serial flash memories, in which the Status Register-1&2 can be written using a single “Write Register-1(01h)” command. To complete the Write Status Register1&2, the CS# pin must be driven high after the sixteenth bit of data that is clocked in as shown in Figure 19. If CS# is driven high after the eighth clock, the Write Status Register (WRSR) instruction will only program the Status Register-1 and the Status Register-2 will not be affected. CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Mode 0 Instruction (01h) DI (DQ0) D0 (DQ1) Mode 3 Status Register 1 in 7 6 5 4 3  2 Status Register 2 in 1 0 15 14 13 12 11 10 9 8  High Impedance =MSB Figure 19 Write Status Register-1/2 Instruction (backward compatible,SPI Mode) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 29 CS# Mode 3 CLK 0 1 2 4 3 Mode 3 5 Mode 0 Mode 0 Instruction 01h SR1 in SR2 in DQ0 4 0 12 8 DQ1 5 1 13 9 DQ2 6 2 14 10 DQ3 7 3 15 11 Figure 20 Write Status Register-1/2 Instruction (backward compatible,QPI Mode) 10.2.6. Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a 24-bit address A23-A0 into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving CS# high. The Read Data instruction sequence is shown in Figure 21. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP =1) the instruction is ignored and will not have any effect on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see “11.6 AC Electrical Characteristics”). The Read Data (03h) instruction is only supported in Standard SPI mode. CS# Mode3 CLK Mode0 0 1 2 3 4 5 6 8 9 10 7 24-Bit Addess Instruction (03h) DI (DQ0) DO (DQ1) 28 29 30 31 32 33 34 35 36 37 38 39 23 22 21 ▲ 3 2 1 0 Data Out1 HIGH IMPEDANCE 7 ▲ 6 5 4 3 2 Data Out2 1 0 7 ▲ = MSB Figure 21 Read Data Instruction (SPI Mode only) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 30 10.2.7. Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see “11.6 AC Electrical Characteristics”). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 22. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DI pin is a “don’t care”. CS# Mode 3 CLK 0 1 Mode 0 2 3 4 5 6 8 7 9 10 Instruction (0Bh) 28 29 30 31 3 2 1 0 45 46 47 48 49 50 0 7 6 5 24-Bit Address DI (DQ0) 23 22 21 42 43  High Impedance D0 (DQ1) =MSB CS# 31 32 33 34 35 36 37 38 39 40 41 44 51 52 53 54 55 2 1 0 CLK Dummy Clocks DI (DQ0) 0 Data Out 2 Data Out 1 D0 (DQ1) High Impedance 7 6 5 4 3 2 1 4 3 7   Figure 22 Fast Read Instruction (SPI Mode) Fast Read (0Bh) in QPI Mode The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate wide range applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 31 CS# Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Mode 0 Instruction IOs switch from Input to Output A23-16 A15-8 A7-0 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 0Bh Dummy Byte1 Byte2 *the number of dummy clocks is controlled by LC[1:0] Figure 23 Fast Read Instruction (QPI Mode) 10.2.8. Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; DQ0 and DQ1. This allows data to be transferred from the FM25Q128AI3 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see “11.6 AC Electrical Characteristics”). For Fast Read Dual Output instruction, there are eight dummy cycles required after the last address bit is shifted into DI before data begins shifting out of DQ0 and DQ1. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the DQ0 pin should be high-impedance prior to the falling edge of the first data out clock. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 32 CS# 0 Mode 3 CLK 1 2 3 4 5 6 8 7 9 10 Instruction (3Bh) 29 30 31 2 1 0 24-Bit Address DI (DQ0) D0 (DQ1) 28 Mode 0 23 22 21 3  High Impedance =MSB CS# 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 CLK IO0 switches from Input to Output Dummy Clocks DI (DQ0) 0 6 4 2 0 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 6 7 5 3 1 7  High Impedance D0 (DQ1) 7   Data Out 1 Figure 24   Data Out 2 Data Out 3 Data Out 4 Fast Read Dual Output Instruction (SPI Mode only) 10.2.9. Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, DQ0, DQ1, DQ2, and DQ3. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the FM25Q128AI3 at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see “11.6 AC Electrical Characteristics”). For Fast Read Quad Output instruction, there are eight dummy cycles required after the last address bit is shifted into DI before data begins shifting out of DQ0, DQ1, DQ2 and DQ3. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the DQ pins should be high-impedance prior to the falling edge of the first data out clock. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 33 CS# 0 Mode 3 CLK 1 2 3 4 5 6 7 8 9 10 28 29 30 31 2 1 0 Mode 0 Instruction (6Bh) 24-Bit Address DQ0 23 22 21 3  High Impedance DQ1 High Impedance DQ2 High Impedance DQ3 =MSB CS# 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 CLK IO0 switches from Input to Output Dummy Clocks DQ0 DQ1 DQ2 DQ3 0 High Impedance High Impedance High Impedance 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 3 7 3 7 3 7 3 7 7 Byte1 Byte2 Byte3 Byte4 Figure 25 Fast Read Quad Output Instruction (SPI Mode only) 10.2.10. Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two I/O pins, DQ0 and DQ1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits A23-A0 two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 26. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after CS# is raised and then lowered) does not require the BBh instruction code, as shown in Figure 27. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on DQ0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 34 CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (BBh) A23-16 DI (DQ0) D0 (DQ1) A15-8 A7-0 M7-0 22 20 18 16 14 12 10 8 6 4 2 0 23 21 19 17 15 13 11 9 7 5 3 1 4 2 0 7 5 3 1   =MSB 6 CS# 23 24 25 26 27 28 29 31 30 32 33 34 35 36 37 38 39 CLK IOs switch from Input to Output DI (DQ0) 0 D0 (DQ1) 1 6 4 2 0 7 5 3 1  6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1   Byte 1 6 4 2 0 6 7 5 3 1 7  Byte 2 Byte 3 Byte 4 Figure 26 Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only) CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 Mode 0 A23-16 A15-8 A7-0 M7-0 DI (DQ0) 22 20 18 16 14 12 10 8 6 4 2 0 D0 (DQ1) 23 21 19 17 15 13 11 9 7 5 3 1 6 4 2 0 7 5 3 1 30 31   =MSB CS# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 CLK IOs switch from Input to Output DI (DQ0) 0 D0 (DQ1) 1 6 4 2 0 7 5 3 1  6 4 2 0 7 5 3 1 4 2 0 7 5 3 1   Byte 1 6 Byte 2 6 4 2 0 6 7 5 3 1 7  Byte 3 Byte 4 Figure 27 Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 35 10.2.11. Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins DQ0, DQ1, DQ2 and DQ3 and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 28. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is raised and then lowered) does not require the EBh instruction code, as shown in Figure 29. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1, 0), the next instruction (after CS# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on DQ0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (EBh) IOs switch from Input to Output A23-16 A15-8 A7-0 M7-0 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 Dq3 23 19 15 11 7 3 7 3 7 3 7 3 7 Dummy Dummy Byte1 Byte2 Byte3 Figure 28 Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, SPI Mode) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 36 CS# Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 IOs switch from Input to Output A23-16 A15-8 A7-0 M7-0 Dummy Dummy DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Figure 29 Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See “Set Burst with Wrap (77h)” for detail descriptions. Fast Read Quad I/O (EBh) in QPI Mode The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 30. When QPI mode is enabled, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. “Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please refer to the description on previous pages for details. “Wrap Around” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please refer to the description on previous pages for details. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 37 CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 Mode 0 Instruction IOs switch from Input to Output A23-16 A15-8 A7-0 M7-0 Dummy DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 EBh Byte1 Byte2 * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. Figure 30 Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, QPI Mode) 10.2.12. Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O Instruction. Word Read Quad I/O with “Continuous Read Mode” The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 31. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is raised and then lowered) does not require the E7h instruction code, as shown in Figure 32. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1, 0), the next instruction (after CS# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on DQ0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 38 CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 16 15 17 18 19 20 21 Mode 0 Instruction (E7h) IOs switch from Input to Output A23-16 A15-8 A7-0 M7-0 Dummy DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Figure 31 Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only) CS# Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Mode 0 IOs switch from Input to Output A23-16 A15-8 A7-0 M7-0 Dummy DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Figure 32 Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See “Set Burst with Wrap (77h)” for detail descriptions. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 39 10.2.13. Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read Quad I/O Instruction. Octal Word Read Quad I/O with “Continuous Read Mode” The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits M7-M0 after the input Address bits A23-A0, as shown in Figure 33. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is raised and then lowered) does not require the E3h instruction code, as shown in Figure 34. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1, 0), the next instruction (after CS# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on DQ0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 Mode 0 IOs switch from Input to Output A23-16 A15-8 A7-0 M7-0 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 Instruction (E3h) Byte2 Byte1 Byte3 Byte4 Figure 33 Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only) CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 Mode 0 IOs switch from Input to Output A23-16 A15-8 A7-0 M7-0 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 Figure 34 Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 40 10.2.14. Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance. Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the CS# pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction sequence is shown in Figure 35. Wrap bit W7 and the lower nibble W3-0 are not used. W4 = 0 Wrap Around Wrap Length W6, W5 00 01 10 11 Yes Yes Yes Yes W4 =1 (default) Wrap Around Wrap Length 8-byte 16-byte 32-byte 64-byte No No No No N/A N/A N/A N/A Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case of a system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap instruction to reset W4 = 1 prior to any normal Read instructions since FM25Q128AI3 does not have a hardware Reset Pin. CS# Mode 3 CLK 0 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 Mode 3 Mode 0 Mode 0 Instruction (77h) don’t care don’t care DQ0 X X X X DQ1 X X X X DQ2 X X X DQ3 X X X don’t care Wrap Bit X W4 X X X W5 X X X X W6 X X X X X X X Figure 35 Set Burst with Wrap Instruction for SPI Mode 10.2.15. Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the CS# pin low then shifting the instruction code “02h” followed by a 24-bit address A23-A0 and at least one data byte, into the DI pin. The CS# pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 36 and Figure 37. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 41 address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After CS# is driven high, the self-timed Page Program instruction will commence for a time duration of tPP (See “11.6 AC Electrical Characteristics”). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits or the Individual Block/Sector Locks. CS# 0 Mode 3 CLK 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 2 1 0 Mode 0 Instruction (02h) Data Byte 1 24-Bit Address DI (DQ0) 23 22 21 3 2 1 7 0 =MSB 6 5 4 3   46 47 48 49 50 51 52 53 54 55 2079 45 2078 44 2077 43 2076 42 2075 41 2074 40 2073 39 2072 CS# CLK Mode 0 Data Byte 2 DI (DQ0) Mode 3 0 7 6 5 4 3 Data Byte 256 Data Byte 3 2 1 0 7  6 5 4 3 2 1 0 7 6 5 4 3 2 1 0   Figure 36 Page Program Instruction (SPI Mode) 2 3 4 5 6 8 7 9 10 11 12 13 519 1 518 0 517 Mode 3 CLK 516 CS# Mode 3 Mode 0 Mode 0 Instruction A23-16 02h A15-8 A7-0 Byte1 Byte2 Byte3 Byte 255 Byte 256 DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 Figure 37 Page Program Instruction (QPI Mode) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 42 10.2.16. Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: DQ0, DQ1, DQ2, and DQ3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds = 1 / FCLK ; 2. This parameter is characterized and is not 100% tested. SPEC TYP MAX UNIT 4 5 5 5 5 3 ns ns ns ns ns ns ns ns ns ns µs 3 µs 1.8 µs 400 15 50 3 500 1500 2000 100 µs ms us ms ms ms ms s us 12 7 8 20 100 10 30 0.7 50 200 250 50 1 CS# tCH CLK I/O OUTPUT tCLQX tCLQV tCLQX tCLQV tCL tSHQZ LSB OUT tQLQH tQHQL Figure 83 Serial Output Timing FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 74 tSHSL CS# tCHSL tCHSH tSLCH tSHCH CLK tDVCH I/O INPUT tCHDX tCLCH MSB IN I/O OUTPUT tCHCL LSB IN (High Impedance) Figure 84 Serial Input Timing CS# tHLCH tCHHL tHHCH CLK tCHHH tHLQZ tHHQX I/O OUTPUT I/O INPUT HOLD# Figure 85 Hold Timing CS# tSHWL tWHSL WP# CLK I/O INPUT Write Status Register is allowed Write Status Register is not allowed Figure 86 WP# Timing FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 75 12. Ordering Information FM 25Q 128 AI3 -XXX -C -H M Company Prefix FM = Fudan Microelectronics Group Co.,ltd Product Family 25Q =2.3~3.6V Serial Flash with 4KB Uniform-Sector, Dual/Quad SPI & QPI Product Density 128 = 128M-bit Product Version Package Type SOB = 8-pin SOP (208mil） DNA = 8-pin TDFN (5x6mm) BGB = 24-ball BGA (8x6mm) Product Carrier U = Tube T = Tape and Reel A = Tray HSF ID Code G = RoHS Compliant, Halogen-free, Antimony-free Moisture Sensitivity Level 1 = MSL1 3 = MSL3 FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 76 13. Part Marking Scheme 13.1. SOP8 (208mil) FM25Q128AI3 YYWWALHM Product Density Moisture Sensitivity Level 1 = MSL1 Blank=MSL3 HSF ID Code G = RoHS Compliant, Halogen-free, Antimony-free Lot Number（just with 0~9、A~Z） Assembly’s Code Work week during which the products was molded (eg..week 12) The last two digits of the year In which the products was seal / molded. 13.2. TDFN8 (5x6mm) FM25Q128AI3 YYWWALHM Product Density Moisture Sensitivity Level 1 = MSL1 Blank=MSL3 HSF ID Code G = RoHS Compliant, Halogen-free, Antimony-free Lot Number（just with 0~9、A~Z） Assembly’s Code Work week during which the product was molded (eg..week 12) The last two digits of the year In which the product was sealed / molded. 13.3. BGA24 (8x6mm) FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 77 FM25Q128AI3 Product Density YYWWALHM Moisture Sensitivity Level 1 = MSL1 Blank=MSL3 HSF ID Code G = RoHS Compliant, Halogen-free, Antimony-free Package Lot Number (just with 0~9, A~Z) Assembly’s Code Work week during which the product was molded (eg..week 12) The last two digits of the year in which the product was sealed/molded FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 78 14. Packaging Information 14.1. SOP8 (208mil) SOP 8 (208mil) Symbol MIN A –– A1 0.050 b 0.350 c 0.100 D 5.130 E1 5.180 E 7.700 e L 0.500 θ 0° NOTE: 1. Dimensions are in Millimeters. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY MAX 2.150 0.250 0.500 0.250 5.330 5.380 8.100 1.270(BSC) 0.850 8° V1.0 Datasheet 79 14.2. TDFN8 (5x6mm) TDFN 8 (5x6mm) Symbol A A1 D D1 E E1 b e L MIN 0.700 0.000 4.900 3.900 5.900 3.300 0.350 MAX 0.800 0.050 5.100 4.300 6.100 3.500 0.450 1.270TYP 0.550 0.650 NOTE: 1 Dimensions are in Millimeters. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 80 14.3. BGA24 (8x6mm) BGA24 (8x6mm) Symbol A A1 A2 D D1 E E1 e b MIN --0.17 0.69 7.90 MAX 1.20 0.25 0.79 8.10 5.00 BSC 5.90 6.10 3.00 BSC 1.00 BSC 0.350 0.450 Note: 1. Dimensions are in Millimeters. FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 81 15. Revision History Version 1.0 Publication Pages date Sep. 2022 83 Paragraph or Illustration FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY Revise Description Initial Document Release. V1.0 Datasheet 82 Sales and Service Shanghai Fudan Microelectronics Group Co., Ltd. Address: Bldg No. 4, 127 Guotai Rd, Shanghai City China. Postcode: 200433 Tel: (86-021) 6565 5050 Fax: (86-021) 6565 9115 Shanghai Fudan Microelectronics (HK) Co., Ltd. Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (852) 2116 3288 2116 3338 Fax: (852) 2116 0882 Beijing Office Address: Room 423, Bldg B, Gehua Building, 1 QingLong Hutong, Dongzhimen Alley north Street, Dongcheng District, Beijing City, China. Postcode: 100007 Tel: (86-010) 8418 6608 Fax: (86-010) 8418 6211 Shenzhen Office Address: Room.2306-2308, Building A7, Chuangzhi Cloud City, Liuxian Avenue, Xili Street, Nanshan District, Shenzhen, China. Postcode: 518000 Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611 Fax: (86-0755) 8335 9011 Shanghai Fudan Microelectronics (HK) Ltd Taiwan Representative Office Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist., Taipei City 114, Taiwan Tel : (886-2) 7721 1889 Fax: (886-2) 7722 3888 Shanghai Fudan Microelectronics (HK) Ltd Singapore Representative Office Address : 47 Kallang Pudding Road, #08-06,The Crescent @ Kallang ,Singapore 349318 Tel : (65) 6443 0860 Fax: (65) 6443 1215 Fudan Microelectronics（USA）Inc. Address : 97 E Brokaw Road, Suite 320,San Jose,CA 95112 Tel : (+1)408-335-6936 Web Site: http://www.fmsh.com/ FM25Q128AI3 128M-BIT SERIAL FLASH MEMORY V1.0 Datasheet 83