GD5F1GM7UEYIGR

SPI-NAND GD5F1GM7 GD5F1GM7xExxG DATASHEET DS-GD5F1GM7xExxG-Rev1.3 1 December 2023 SPI-NAND GD5F1GM7 Contents 1 FEATURE ........................................................................................................................................................... 4 2 GENERAL DESCRIPTION ............................................................................................................................... 5 2.1 VALID PART NUMBERS ........................................................................................................................................ 6 2.2 CONNECTION DIAGRAM ..................................................................................................................................... 6 2.3 PIN DESCRIPTION ................................................................................................................................................ 7 2.4 BLOCK DIAGRAM ................................................................................................................................................ 7 3 MEMORY MAPPING ......................................................................................................................................... 8 4 ARRAY ORGANIZATION ................................................................................................................................. 9 5 DEVICE OPERATION ..................................................................................................................................... 10 5.1 SPI MODES.......................................................................................................................................................... 10 5.2 HOLD MODE ....................................................................................................................................................... 11 5.3 WRITE PROTECTION............................................................................................................................................... 11 5.4 POWER OFF TIMING .............................................................................................................................................. 12 5.5 DATA STROBE (DQS) SIGNAL ................................................................................................................................... 12 6 COMMANDS DESCRIPTION ......................................................................................................................... 13 7 WRITE OPERATIONS .................................................................................................................................... 15 8 9 7.1 WRITE ENABLE (WREN) (06H) ............................................................................................................................... 15 7.2 WRITE DISABLE (WRDI) (04H) ............................................................................................................................... 15 READ OPERATIONS ...................................................................................................................................... 16 8.1 PAGE READ .......................................................................................................................................................... 16 8.2 PAGE READ TO CACHE (13H) ................................................................................................................................... 17 8.3 READ FROM CACHE (03H OR 0BH) ........................................................................................................................... 18 8.4 READ FROM CACHE X2 (3BH).................................................................................................................................. 19 8.5 READ FROM CACHE X4 (6BH).................................................................................................................................. 20 8.6 READ FROM CACHE DUAL IO (BBH) ......................................................................................................................... 21 8.7 READ FROM CACHE QUAD IO (EBH) ........................................................................................................................ 22 8.8 READ FROM CACHE QUAD I/O DTR (EEH) ................................................................................................................ 23 8.9 READ ID (9FH) ..................................................................................................................................................... 24 8.10 READ UID ........................................................................................................................................................... 25 8.11 READ PARAMETER PAGE ......................................................................................................................................... 26 PROGRAM OPERATIONS ............................................................................................................................. 31 9.1 PAGE PROGRAM ................................................................................................................................................... 31 9.2 PROGRAM LOAD (PL) (02H) ................................................................................................................................... 32 9.3 PROGRAM LOAD X4 (PL X4) (32H) .......................................................................................................................... 33 9.4 PROGRAM EXECUTE (PE) (10H)............................................................................................................................... 34 9.5 INTERNAL DATA MOVE ........................................................................................................................................... 35 9.6 PROGRAM LOAD RANDOM DATA (84H) ..................................................................................................................... 36 DS-GD5F1GM7xExxG-Rev1.3 2 December 2023 SPI-NAND 9.7 10 PROGRAM LOAD RANDOM DATA X4 (C4H/34H) ......................................................................................................... 37 ERASE OPERATIONS ................................................................................................................................... 38 10.1 11 GD5F1GM7 BLOCK ERASE (D8H) .............................................................................................................................................. 38 RESET OPERATIONS .................................................................................................................................... 39 11.1 SOFT RESET(FFH) .................................................................................................................................................. 39 11.2 ENABLE POWER ON RESET (66H) AND POWER ON RESET (99H) ..................................................................................... 40 12 FEATURE OPERATIONS ............................................................................................................................... 41 12.1 GET FEATURES (0FH) AND SET FEATURES (1FH) .......................................................................................................... 41 12.2 STATUS REGISTER AND DRIVER REGISTER.................................................................................................................... 45 12.3 OTP REGION ........................................................................................................................................................ 46 12.4 ASSISTANT BAD BLOCK MANAGEMENT ...................................................................................................................... 47 12.5 BLOCK PROTECTION ............................................................................................................................................... 48 12.6 POWER LOCK DOWN PROTECTION............................................................................................................................ 49 12.7 INTERNAL ECC...................................................................................................................................................... 50 12.8 DEEP POWER-DOWN (B9H) (1.8V ONLY) ................................................................................................................. 51 12.9 RELEASE FROM DEEP POWER-DOWN (ABH)(1.8V ONLY) ............................................................................................. 52 13 POWER ON TIMING ....................................................................................................................................... 53 14 ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 54 15 CAPACITANCE MEASUREMENT CONDITIONS ........................................................................................ 55 16 DC CHARACTERISTIC .................................................................................................................................. 56 17 AC CHARACTERISTICS................................................................................................................................ 58 18 PERFORMANCE AND TIMING ..................................................................................................................... 59 19 ORDERING INFORMATION .......................................................................................................................... 61 20 PACKAGE INFORMATION ............................................................................................................................ 62 21 REVISION HISTORY....................................................................................................................................... 65 DS-GD5F1GM7xExxG-Rev1.3 3 December 2023 SPI-NAND 1 GD5F1GM7 FEATURE 1Gb SLC NAND Flash ◆ Advanced security Features ◆ - 20K-Byte OTP Region Page Size ◆ - Internal ECC On (ECC_EN=1, default): ◆ Program/Erase/Read Speed Page Size：2048-Byte+64-Byte - Page Program time: 320us typical - Internal ECC Off (ECC_EN=0): - Block Erase time: 3ms typical Page Size：2048-Byte+128-Byte - Page read time: 120us maximum Standard, Dual, Quad SPI,DTR ◆ ◆ Low Power Consumption - Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# - 30mA maximum active current - Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD# - 50uA maximum standby current - Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3 - DTR(Double Transfer Rate) Read : SCLK, CS#, SIO0, ◆ SIO1, SIO2, SIO3 - 2KByte cache for fast random read High Speed Clock Frequency ◆ Enhanced access performance ◆ Advanced Feature for NAND - 3.3V: - Factory good block0 133MHz for Standard/Dual/Quad SPI - Deep Power Down(1.8V only) 104MHz for DTR Quad SPI - 1.8V: ◆ Reliability 104MHz for Standard/Dual/Quad SPI - P/E cycles with ECC: Typical 80K(2) 80MHz for DTR Quad SPI - Data retention: 10 Years Software/Hardware Write Protection ◆ ◆ - Write protect all/portion of memory via software Internal ECC - 8bits /528byte - Register protection with WP# Pin - Power Lock Down Protection ◆ Single Power Supply Voltage - Full voltage range for 1.8V: 1.7V ~ 2.0V - Full voltage range for 3.3V: 2.7V ~ 3.6V Note: 1. ECC is on default, which can be disabled by user. 2. The P/E cycles with ECC will be 60K at 105℃ operation temperature. DS-GD5F1GM7xExxG-Rev1.3 4 December 2023 SPI-NAND 2 GD5F1GM7 GENERAL DESCRIPTION SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memory storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive alternative to SPI-NOR and standard parallel NAND Flash, with advanced features. • Total pin count is 8, including VCC and GND • Density is 1Gb • Superior write performance and cost per bit over SPI-NOR • Significant low cost than parallel NAND This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash memory, with specified designed features to ease host management: • User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The 64-bytes spare area is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status. • Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage collection task, without need of shift in and out of data. • Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power on, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when ECC enabled. It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the status of device operation. DS-GD5F1GM7xExxG-Rev1.3 5 December 2023 SPI-NAND GD5F1GM7 2.1 VALID PART NUMBERS Please contact GigaDevice regional sales for the latest product selection and available form factors Product Number Density Voltage GD5F1GM7REYIG GD5F1GM7REBIG 1.7V to 2.0V GD5F1GM7REWIG Package Type Temperature WSON8(8*6mm) -40℃ to 85℃ TFBGA24(5*5 Ball Array) -40℃ to 85℃ WSON8(6*5mm) -40℃ to 85℃ WSON8(8*6mm) -40℃ to 85℃ TFBGA24(5*5 Ball Array) -40℃ to 85℃ WSON8(6*5mm) -40℃ to 85℃ 1Gbit GD5F1GM7UEYIG GD5F1GM7UEBIG 2.7V to 3.6V GD5F1GM7UEWIG GD5F1GM7REYJG 1Gbit 1.7V to 2.0V WSON8(8*6mm) -40℃ to 105℃ GD5F1GM7UEYJG 1Gbit 2.7V to 3.6V WSON8(8*6mm) -40℃ to 105℃ 2.2 CONNECTION DIAGRAM Figure 2-1. Connect Diagram Top View CS# 1 8 VCC SO/ SIO1 2 7 HOLD#/ SIO3 WP#/ SIO2 VSS Top View 3 4 5 SCLK SI/ SIO0 8–LEAD WSON DS-GD5F1GM7xExxG-Rev1.3 A3 A4 A5 NC NC NC B1 B2 B3 B4 B5 NC SCLK VSS VCC NC C1 C2 C3 C4 C5 NC CS# DQS D1 D2 D3 NC 6 A2 NC WP#(IO2) NC D4 D5 HOLD#/ SO(IO1) SI(IO0) (IO3) NC E1 E2 E3 E4 E5 NC NC NC NC NC 24-BALL TFBGA (5x5 ball array) 6 December 2023 SPI-NAND GD5F1GM7 2.3 PIN DESCRIPTION Pin Name I/O Description CS# I Chip Select input, active low SO/SIO1 I/O Serial Data Output / Serial Data Input Output 1 WP#/SIO2 I/O Write Protect, active low / Serial Data Input Output 2 VSS Ground Ground SI/SIO0 I/O Serial Data Input / Serial Data Input Output 0 SCLK I Serial Clock input HOLD# /SIO3 I/O Hold Input/Serial Data Input Output 3 VCC Supply Power Supply NC Not Connect, Not internal connection; can be driven or floated. DQS (only for BGA24) O Data Strobe Signal Output Note： 1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. 2. If the DQS Function is not used, this pin must be floating. 3. If WP# and HOLD# are unused, they must be driven high by the host, or an external pull-up resistor must be placed on the PCB in order to avoid allowing WP# and HOLD# input to float. 2.4 BLOCK DIAGRAM Figure 2-2. Block Diagram DQS SCLK SI/SIO0 SO/SIO1 CS# HOLD#/ SIO3 WP#/ SIO2 Serial NAND controller Vcc Vss Cache memory NAND memory core Status register DS-GD5F1GM7xExxG-Rev1.3 7 December 2023 SPI-NAND 3 GD5F1GM7 MEMORY MAPPING For 1G Blocks RA 0 1 Pages RA 0 1 Bytes CA 0 1 2 1023 63 2 2175 Note: 1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0 through 2175/2111 are valid. Bytes 2176/2112 through 4095 of each page are “out of bounds,” do not exist in the device, and cannot be addressed. 2. RA: Row Address. RAselects a page inside a block, and RAselects a block. DS-GD5F1GM7xExxG-Rev1.3 8 December 2023 SPI-NAND 4 GD5F1GM7 ARRAY ORGANIZATION Table 4. Array Organization Each device has Each block has Each page has 128M+8M 128K+8K 2K+128 bytes 1024 x 64 64 - pages 1024 - - blocks 1Gb Figure 4. Array Organization Cache Register 2048 128 Data Register 2048 128 IO 1 page = (2K + 128)bytes 1 block = (2K + 128)bytes x 64 pages = (128K + 8K)bytes Per device: 1G: 1024 Blocks 1 device: For 1G: = (128K +8K)bytes x 1024 blocks = 1Gb 1 block Internal ECC = OFF Cache Register 2048 64 Data Register 2048 64 IO 1 page = (2K + 64)bytes 1 block = (2K + 64)bytes x 64 pages = (128K + 4K)bytes Per device: 1G: 1024 Blocks 1 device: For 1G: = (128K +4K)bytes x 1024 blocks = 1Gb 1 block Internal ECC = ON Note: 1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area. 2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area. DS-GD5F1GM7xExxG-Rev1.3 9 December 2023 SPI-NAND 5 GD5F1GM7 DEVICE OPERATION 5.1 SPI Modes SPI NAND supports two SPI modes: • CPOL = 0, CPHA = 0 (Mode 0) • CPOL = 1, CPHA = 1 (Mode 3) Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing diagrams shown in this data sheet are mode 0. See Figure 5-1 for more details. Figure 5-1. SPI Modes Sequence Diagram CPOL CPHA 0 0 SCLK 1 1 SCLK SI MSB LSB SO MSB LSB CS# Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS# is driven LOW. We recommend that the user pull CS# to high when user don’t use SPI flash, otherwise the flash is always in the read state, which is damage for flash. When CS# is high and SCLK at VCC or GND state, the device is in idle state. Standard SPI SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Dual SPI SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1. Quad SPI SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3. DS-GD5F1GM7xExxG-Rev1.3 10 December 2023 SPI-NAND GD5F1GM7 DTR Quad SPI The device supports DTR Quad SPI operation when using the “DTR Quad I/O Fast Read” command. These command allow data to be transferred to or from the device at eight times the rate of the standard SPI, and data output will be latched on both rising and falling edges of the serial clock. When using the DTR Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. DTR Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be enable. 5.2 HOLD Mode The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated data I/O pin. The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of reading, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure 5-2. Hold Condition CS# SCLK HOLD# HOLD HOLD 5.3 Write Protection SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the block protect bits cannot be altered. To enable the Write Protection, the Quad Enable bit (QE) of feature (B0[0]) must be set to 0. DS-GD5F1GM7xExxG-Rev1.3 11 December 2023 SPI-NAND GD5F1GM7 5.4 Power Off Timing Please do not turn off the power before Write/Erase operation is completed. Avoid using the device when the battery is low. Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or damage to data. 5.5 Data Strobe (DQS) signal The DQS signal is an active output pin for the Data Strobe (DQS) signal during Read operations. The DQS signal is typically used in high speed applications to indicate when the output data is ready to be fetched by the controllers. To achieve such high frequency for specific DTR command, DQS pin is enabled on BGA24 package of this device. DQS is only available in EEh command. DQS signal is driven to ground once EEh command is accepted, and will start to toggle when the output data is ready on the I/O pins under DTR mode. The toggling frequency is the same as the CLK frequency. For DTR Read operations, the data should be latched on both rising edge and falling edge of the DQS signal. If the DQS Function is not used, this pin must be floating. DS-GD5F1GM7xExxG-Rev1.3 12 December 2023 SPI-NAND 6 GD5F1GM7 COMMANDS DESCRIPTION Table 6-1. Commands Set Command Name Byte1 Byte2 Byte3 Byte4 Write Enable 06h Write Disable 04h Get Features 0Fh A7-A0 D7-D0 Wrap(7) Set Feature 1Fh A7-A0 D7-D0 Page Read (to cache) 13h A23-A16 A15-A8 A7-A0 Read From Cache 03h/0Bh(8) A15-A8 A7-A0(2) Dummy(1) D7-D0 A15-A8 A7-A0 (2) (1) Dummy D7-D0 A15-A8 A7-A0(2) Dummy(1) D7-D0 A15-A8 A7-A0(2) Dummy(1) D7-D0 EBh A15-A8 A7-A0(2) Dummyx2(1) D7-D0 EEh A31-A24 A23-A16 A15-A8 A7-A0(2) Read ID(4) 9Fh Dummy MID DID Read parameter page 13h 00h 00h 01h Read UID 13h 00h 00h 00h Program Load 02h A15-A8 A7-A0(3) D7-D0 Next byte Program Load x4 32h A15-A8 A7-A0(3) D7-D0 Next byte Program Execute 10h A23-A16 A15-A8 A7-A0 Program Load Random Data 84h A15-A8 A7-A0(3) D7-D0 Next byte D7-D0 Next byte A7-A0 (8) Read From Cache x 2 3Bh Read From Cache x 4 6Bh(8) Read From Cache Dual IO Read From Cache Quad IO Read From Cache Quad I/O DTR BBh Program Load Random Data x4 C4h/34h A15-A8 A7-A0(3) Block Erase(128K) D8h A23-A16 A15-A8 Reset(5) FFh Enable Power on Reset Power on Reset(6) Deep Power Down(1.8V Only) Release Deep Power Down(1.8V Only) DS-GD5F1GM7xExxG-Rev1.3 Byte5 Byte6 Dummy x8(1) Byte 7 D7-D0 66h 99h B9h ABh 13 December 2023 SPI-NAND GD5F1GM7 Note: 1.03h/0Bh/3Bh/6Bh has 8 clock, 1 byte dummy. BBh has 4 clock, 1 byte dummy. EBh has 4 clock, 2 bytes dummy. EEh has 8 clock, 8 bytes dummy. 2. The A15-A0 (03h/0Bh/3Bh/6Bh) has 16 clock, include 4 clock dummy. The A15-A0 (BBh) has 8 clock, include 2 clock dummy. The A15-A0 (EBh) has 4 clock, include 1 clock dummy. The A31-A0 (EEh) has 4 clock, include 2.5 clock dummy. 3. The A15-A0 has 16 clock, include 4 clock dummy. 4. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID. 5. Reset command: • Reset will reset PAGE READ/PROGRAM/ERASE operation. • Reset will reset status register bits P_FAIL/E_FAIL/WEL/OIP/ECCS/ECCSE. 6. Power on reset: Retrieve status register and data in cache to power on status. 7. The output would be updated by real-time, until CS# is driven high. 8. Read UID/parameter page are same as page read to cache. DS-GD5F1GM7xExxG-Rev1.3 14 December 2023 SPI-NAND 7 GD5F1GM7 WRITE OPERATIONS 7.1 Write Enable (WREN) (06h) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to following operations that change the contents of the memory array: • Page program • OTP program/OTP protection • Block erase The WEL bit can be cleared after a reset command. Figure 7-1. Write Enable Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 06h High-Z SO 7.2 Write Disable (WRDI) (04h) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is reset by following condition: • Page program • OTP program/OTP protection • Block erase Figure 7-2. Write Disable Sequence Diagram CS# SCLK SI SO DS-GD5F1GM7xExxG-Rev1.3 0 1 2 3 4 5 6 7 Command 04h High-Z 15 December 2023 SPI-NAND 8 GD5F1GM7 READ OPERATIONS 8.1 Page Read The PAGE READ (13h) command transfers the data from the NAND Flash array to the cache register. The command sequence is as follows: • 13h (PAGE READ to cache) • 0Fh (GET FEATURES command to read the status) • 03h or 0Bh (Read from cache)/3Bh (Read from cache x2)/6Bh (Read from cache x4)/ BBh (Read from cache dual IO)/EBh (Read from cache Quad IO)/EEh(Read from cache Quad IO DTR) The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0Fh) command can be issued to monitor the status. Followed the page read operation, the RANDOM DATA READ (03h/0Bh/3Bh/6Bh/BBh/EBh/EEh) command must be issued in order to read out the data from cache. The output data starts at the initial address specified in the command, once it reaches the ending boundary of whole page section, the output will wrap around from the beginning boundary until CS# is pulled high to terminate this operation. Refer waveforms to view the entire READ operation. Note:(1) The command 6Bh (Read from cache x4)/EBh (Read from cache Quad IO)/EEh (Read from cache Quad IO DTR) is only available with the QE enable. (2) When user read to the end of 64-Byte spare area, it won’t wrap around from the beginning boundary and an additional 64Byte ECC code will be read. (Internal ECC enabled) DS-GD5F1GM7xExxG-Rev1.3 16 December 2023 SPI-NAND GD5F1GM7 8.2 Page Read to Cache (13h) The command page read to cache is read the data from flash array to cache register. Figure 8-1. Page Read to cache Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 13h 23 22 21 3 2 1 0 High-Z SO CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLK tCS 0Fh 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 1 byte address Get Feature SI 16 17 18 19 20 21 22 23 24 SCLK SI Data byte SO 7 6 5 4 3 2 1 0 7 MSB DS-GD5F1GM7xExxG-Rev1.3 17 December 2023 SPI-NAND GD5F1GM7 8.3 Read From Cache (03h or 0Bh) The command sequence is shown below. Figure 8-2. Read From Cache Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 23 SCLK Command SI SO Dummy 03h or 0Bh 0 0 A11- A0 3 2 1 0 0 11 10 0 High-Z CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Dummy byte SI SO DS-GD5F1GM7xExxG-Rev1.3 7 6 5 4 3 2 1 0 7 6 MSB 18 Data byte 0 5 4 3 2 1 0 7 MSB Data byte 1 6 5 December 2023 SPI-NAND GD5F1GM7 8.4 Read From Cache x2 (3Bh) The command sequence is shown below. Figure 8-3. Read From Cache x2 Sequence Diagram CS# 0 1 2 3 4 5 6 7 9 10 11 12 13 14 8 22 23 SCLK Dummy Command SI/SIO0 3Bh 0 A11-A0 0 11 10 0 0 3 2 1 0 High-Z SO/SIO1 CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Dummy byte SI/SIO0 SO/SIO1 7 6 5 4 3 2 1 0 6 7 4 6 4 2 Data byte 0 Data byte 1 5 3 1 7 5 3 1 7 5 3 MSB DS-GD5F1GM7xExxG-Rev1.3 2 0 6 4 2 0 MSB 19 December 2023 SPI-NAND GD5F1GM7 8.5 Read From Cache x4 (6Bh) The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. The command sequence is shown below. Figure 8-4. Read From Cache x4 Sequence Diagram CS# 0 1 2 3 4 5 8 7 6 9 10 11 12 13 14 22 23 SCLK Command SO(SIO1) High-Z WP#(SIO2) High-Z HOLD#(SIO3) High-Z CS# 3 0 11 10 0 0 0 6Bh SI(SIO0) A11- A0 Dummy 2 1 0 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Dummy byte 0 4 0 4 0 4 0 4 0 4 SO(SIO1) 5 1 5 1 5 1 5 1 5 WP#(SIO2) 6 2 6 2 6 2 6 2 6 HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 Byte0 Byte1 Byte2 Byte3 SI(SIO0) DS-GD5F1GM7xExxG-Rev1.3 7 6 5 4 3 2 1 20 December 2023 SPI-NAND GD5F1GM7 8.6 Read From Cache Dual IO (BBh) The Read from Cache Dual I/O command (BBh) is similar to the Read form Cache x2 command (3Bh) but with the capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and 4 clock dummy by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted out until the boundary wrap bit. Figure 8-5. Read From Cache Dual IO Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 Dummy A11-A0 0 0 10 8 6 4 2 Command SI(SIO0) 7 BBh SO(SIO1) 0 0 11 9 7 5 Dummy 3 0 6 4 2 0 1 7 5 3 1 CS# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SCLK SI(SIO0) 6 SO(SIO1) 7 DS-GD5F1GM7xExxG-Rev1.3 4 2 0 6 4 2 0 6 4 0 6 4 0 6 5 3 Data byte 0 1 7 5 3 1 Data byte 1 7 5 3 1 Data byte 2 7 5 3 1 Data byte 3 7 21 2 2 December 2023 SPI-NAND GD5F1GM7 8.7 Read From Cache Quad IO (EBh) The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input the 4 dummy bits, followed a 12-bit column address for the starting byte address and dummy bytes by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out until the boundary wrap bit. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache quad IO command. Figure 8-6. Read From Cache Quad IO Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Dummy 0 8 4 0 4 0 4 0 4 0 4 0 4 SO(SIO1) 0 5 1 5 1 5 1 5 1 5 1 5 WP#(SIO2) 0 10 6 2 6 2 6 2 6 2 6 2 6 HOLD#(SIO3) 0 11 7 3 7 3 7 3 7 3 7 3 7 Command SI(SIO0) EBh 9 A11 - A0 DS-GD5F1GM7xExxG-Rev1.3 22 Dummy Byte0 Byte1 December 2023 SPI-NAND GD5F1GM7 8.8 Read From Cache Quad I/O DTR (EEh) The DTR Quad IO command enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to “1” before sending the DTR Quad IO command. The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The first address Byte can be at any location. The address is automatically increased to the next higher address after each Byte data is shifted out, so the whole page can be read out at a single DTR Quad IO command. The address counter rolls over to 0 when the highest address has been reached. Figure 8-7.a Read From Cache Quad I/O DTR Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 9 10 11 19 20 Dummy Command SI(IO0) 8 EEh Dummy 0 0 0 0 0 8 4 0 4 0 4 0 0 0 0 0 0 9 5 1 5 1 5 1 IO2 0 0 0 0 0 10 6 2 6 2 6 2 IO3 0 0 0 0 0 11 7 3 SO(IO1) 7 3 7 3 Byte 0Byte 1 A11- A0 Figure 8-7.b Read From Cache Quad I/O DTR with DQS Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 8 9 10 11 Dummy Command SI(IO0) 7 EEh 19 20 Dummy 0 0 0 0 0 8 4 0 4 0 4 0 0 0 0 0 0 9 5 1 5 1 5 1 IO2 0 0 0 0 0 10 6 2 6 2 6 2 IO3 0 0 0 0 0 11 7 3 SO(IO1) A11- A0 High-Z 7 3 7 3 Byte 0Byte 1 DQS Note: Please contact GigaDevice when there is a need to use the EEh command for DTR. DS-GD5F1GM7xExxG-Rev1.3 23 December 2023 SPI-NAND GD5F1GM7 8.9 Read ID (9Fh) The READ ID command is used to identify the NAND Flash device. • the READ ID command outputs the Manufacturer ID and the device ID. See Table 8-1 for details. Figure 8-8. Read ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI 9Fh 7 6 5 4 3 2 1 0 High-Z SO CS# Dummy 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI SO 7 Manufacturer ID 6 5 4 3 2 1 MSB Device ID 0 7 6 5 4 3 2 1 0 MSB Table 8-1. READ ID Table Part No MID DID1 GD5F1GM7UExxG C8h 91h GD5F1GM7RExxG C8h 81h DS-GD5F1GM7xExxG-Rev1.3 24 December 2023 SPI-NAND GD5F1GM7 8.10 Read UID The Read Unique ID function is used to retrieve the 16 bytes unique ID (UID) for the device. The unique ID when combined with the device manufacturer shall be unique. The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID is returned with its complement. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid. To accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding complement are stored by the target. For example, reading bytes 32-63 returns to the host another copies of the UID and its complement. Bytes Value 0-15 UID 16-31 UID complement (bit-wise) Sequence is as follows: 1. Use Set Feature command to set B0 register, to enable OTP_EN. 2. Use Get Feature command to get data from B0 register and check if the OTP_EN is enable. 3. Use page read to cache (13h) command with address 24’h000000h, read data from array to cache. 4. Use 0Fh (GET FEATURES command) read the status. 5. User can use Read from cache command (03h/0Bh), read 16 bytes UID from cache. Figure 8-9. Read UID to cache and Get Feature Command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 13h 000000h High-Z SO CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLK tCS 0Fh 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 1 byte address Get Feature SI 16 17 18 19 20 21 22 23 24 SCLK SI Data byte SO 7 6 5 4 3 2 1 0 7 MSB DS-GD5F1GM7xExxG-Rev1.3 25 December 2023 SPI-NAND GD5F1GM7 8.11 Read Parameter Page The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features, timing and other behavioral parameters. This data structure enables the host processor to automatically recognize the SPI-NAND Flash configuration of a device. The whole data structure is repeated at least three times. The Read from Cache command can be issued during execution of the read parameter page to read specific portion-soft the parameter page. Sequence is as follows: 1. Use Set Feature command to set B0 register, to enable OTP_EN. 2. Use Get Feature command to get data from B0 register and check if the OTP_EN is enable. 3. Use Page Read to Cache (13h) command with address 24’h000001h. Load parameter page from array to cache. 4. Use 0Fh (GET FEATURES command) read the status 5. User can use Read from cache command (03h/0Bh), read parameter page from cache. Figure 8-10. Read parameter page to cache and Get Feature Command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 13h 000001h High-Z SO CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLK 0Fh 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 1 byte address Get Feature tCS SI 16 17 18 19 20 21 22 23 24 SCLK SI Data byte SO 7 6 5 4 3 2 1 0 7 MSB DS-GD5F1GM7xExxG-Rev1.3 26 December 2023 SPI-NAND GD5F1GM7 Parameter page table as follow (1G) Byte O/M Description 3.3V/1.8V 0-3 M Parameter page signature 4Fh Byte 0: 4Fh, “O” 4Eh Byte 1: 4Eh, “N” 46h Byte 2: 46h, “F” 49h Byte 3: 49h, “I” 4-5 6-7 8-9 M M M Revision number 00h 0-15 Reserved (0) 00h Features supported 00h 0-15 Reserved (0) 00h Reserved (0) 00h 00h 10-31 Reserved (0) 00h … 00h Manufacturer Information block 32-43 M Device manufacturer (12 ASCII characters)“GIGADEVICE ” 47h 49h 47h 41h 44h 45h 56h 49h 43h 45h 20h 20h 44-63 M Device model (20 ASCII characters) 47h Device Model ORGANIZATION VCC RANGE 44h “GD5F1GM7U” X4 2.7v ~ 3.6v 35h “GD5F1GM7R” X4 1.7v ~ 2.0v 46h 31h 47h 4Dh 37h 55h/52h 20h 20h 20h 20h 20h 20h DS-GD5F1GM7xExxG-Rev1.3 27 December 2023 SPI-NAND GD5F1GM7 20h 20h 20h 20h 20h 64 M JEDEC manufacturer ID“C8” C8h 65-66 O Date code 00h 00h 67-79 Reserved 00h 00h 00h Memory organization block 80-83 M Number of data bytes per page 00h 08h 00h 00h 84-85 M Number of spare bytes per page 80h 00h 86-89 M Number of data bytes per partial page 00h 02h 00h 00h 90-91 M Number of spare bytes per partial page 20h 00h 92-95 M Number of pages per block 40h 00h 00h 00h 96-99 M Number of blocks per logical unit (LUN) 00h 04h 00h 00h 100 M Number of logical units (LUNs) 01h 101 M Reserved 00h 102 M Number of bits per cell 01h 103-104 M Bad blocks maximum 14h 00h 105-106 M Block endurance 05h 04h 107 M Guaranteed valid blocks at beginning of target 01h 108-109 M Block endurance for guaranteed valid blocks 00h 00h DS-GD5F1GM7xExxG-Rev1.3 28 December 2023 SPI-NAND GD5F1GM7 110 M Number of programs per page 04h 111 M Partial programming attributes 00h 5-7 Reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 Reserved 0 1 = partial page programming has constraints 112 M Number of bits ECC correctability 00h 113 M Number of interleaved address bits 00h 4-7 Reserved (0) 0-3 Number of interleaved address bits 114 O Interleaved operation attributes 00h 4-7 Reserved (0) 3 Address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 Overlapped / concurrent interleaving support 115-127 Reserved 00h … 00h Electrical parameters block 128 M I/O capacitance 08h 129-130 M IO clock support 00h 00h 131-132 O Reserved (0) 00h 00h 133-134 M tPROG Maximum page program time (us) 58h 02h 135-136 M tBERS Maximum block erase time (us) 10h 27h 137-138 M tR Maximum page read time (us) 78h 00h 139-140 M Reserved 00h 00h 141-163 Reserved 00h Vendor block 164-165 M 166-253 254-255 M Vendor specific Revision number 00h Vendor specific 00h Integrity CRC Set on test Redundant parameter pages 256-511 M Value of bytes 0-255 512-767 M Value of bytes 0-255 768+ O Additional redundant parameter pages DS-GD5F1GM7xExxG-Rev1.3 29 December 2023 SPI-NAND GD5F1GM7 Notes: 1. “O” Stands for Optional, “M” for Mandatory 2. The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit generator polynomial: G(X) = X16 + X15 +X2 + 1，This polynomial in hex may be represented as 8005h. 3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the final CRC value after it is calculated. There is no reversal of the data bytes or the CRC calculated value. Device Model ORGANIZATION VCC RANGE CRC value “GD5F1GM7UxxG” X4 2.7v ~ 3.6v 45h/05h “GD5F1GM7RxxG” X4 1.7v ~ 2.0v 9Dh/C8h DS-GD5F1GM7xExxG-Rev1.3 30 B254/B255 December 2023 SPI-NAND 9 GD5F1GM7 PROGRAM OPERATIONS 9.1 Page Program The PAGE PROGRAM operation sequence programs 1 byte to whole page bytes of data within a page. The page program sequence is as follows: • 02h (PROGRAM LOAD)/32h (PROGRAM LOAD x4) • 06h (WRITE ENABLE) • 10h (PROGRAM EXECUTE) • 0Fh (GET FEATURE command to read the status) Firstly, a PROGRAM LOAD (02h/32h) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4 dummy bits and a 12-bit column address, then the data bytes to be programmed. The Program address should be in sequential order in a block. The data bytes are loaded into a cache register that is whole page long. If more than one page data are loaded, then those additional bytes are ignored by the cache register. The command sequence ends when CS# goes from LOW to HIGH. Figure 9-1 shows the PROGRAM LOAD operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06h) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE must be executed in order to set the WEL bit. If this command is not issued, then the rest of the program sequence is ignored. Note: 1. The contents of Cache Register don’t reset when Program Random Load (84h/C4h/34h) command and RESET (FFh) command. 2. When Program Execute (10h) command was issued just after Program Load (02h/32h) command, the 0xFF is output to the address that data was not loaded by Program Load (02h/32h) command. 3. When Program Execute (10h) command was issued just after Program Load Random Data (84h/C4h/34h) command, the contents of Cache Register are output to the NAND. 4. The Program address should be in sequential order in a block. 5. Program Load x4 is only available with the QE enable. DS-GD5F1GM7xExxG-Rev1.3 31 December 2023 SPI-NAND GD5F1GM7 9.2 Program Load (PL) (02h) The command sequence is shown below. Figure 9-1. Program Load Sequence Diagram CS# 0 1 2 3 4 5 6 9 10 11 12 13 14 7 8 22 23 SCLK Dummy Command SI 02h 0 0 A11- A0 0 0 11 10 3 2 1 0 CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Data byte 0 SI 7 6 MSB 5 4 3 Data byte 1 2 1 0 7 6 5 4 3 2 1 Data byte N 0 7 6 5 4 3 2 1 0 Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112. DS-GD5F1GM7xExxG-Rev1.3 32 December 2023 SPI-NAND GD5F1GM7 9.3 Program Load x4 (PL x4) (32h) The Program Load x4 command (32h) is similar to the Program Load command (02h) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the program load x4 command. Figure 9-2. Program Load x4 Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCLK Command SI(SIO0) 0 0 0 Byte 0 Byte1 A11 - A0 Dummy 32h 0 11 1 0 4 0 4 0 4 0 4 0 SO(SIO1) 5 1 5 1 5 1 5 1 WP#(SIO2) 6 2 6 2 6 2 6 2 HOLD#(SIO3) 7 3 7 3 7 3 7 3 CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Byte10Byte11 Byte N Byte N+1 4 4 SI(SIO0) 4 SO(SIO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(SIO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 0 0 Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112. DS-GD5F1GM7xExxG-Rev1.3 33 December 2023 SPI-NAND GD5F1GM7 9.4 Program Execute (PE) (10h) After the data is loaded, a PROGRAM EXECUTE (10h) command must be issued to initiate the transfer of data from the cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and is busy for tPROG time. This operation shown in Figure 9-3. During this busy time, the status register can be polled to monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series of data can be loaded with the PROGRAM LOAD command. The command sequence is shown below. Note: After the Program Execute (10h) command is issued, the data in cache register are no longer valid. Figure 9-3. Program Execute Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 10h 23 22 21 3 2 1 0 High-Z SO CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK tCS 0Fh 7 6 5 4 3 2 1 0 MSB High-Z SO CS# Status register address get feature SI 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SCLK SI Status register data out SO 7 MSB DS-GD5F1GM7xExxG-Rev1.3 6 5 4 3 2 1 0 Status register data out 7 6 5 4 3 2 1 0 7 6 MSB 34 December 2023 SPI-NAND GD5F1GM7 9.5 Internal Data Move The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The INTERNAL DATA MOVE command sequence is as follows: • 13h (PAGE READ to cache) • Optional 84h/C4h/34h(PROGRAM LOAD RANDOM DATA) • 06h (WRITE ENABLE) • 10h (PROGRAM EXECUTE) • 0Fh (GET FEATURE command to read the status) Prior to performing an internal data move operation, the target page content must be read out into the cache register by issuing a PAGE READ (13h) command. The PROGRAM LOAD RANDOM DATA (84h/C4h) command can be issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random data is not sequential, another PROGRAM LOAD RANDOM DATA (84h/C4h) command must be issued with the new column address. After the data is loaded, the WRITE ENABLE command must be issued, and then PROGRAMEXECUTE (10h) command can be issued to start the programming operation. DS-GD5F1GM7xExxG-Rev1.3 35 December 2023 SPI-NAND GD5F1GM7 9.6 Program Load Random Data (84h) The Program Load Random Data command programs or replaces data in a page with existing data. This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD RANDOM DATA (84h) command must be issued with a new column address, see Figure 9-4 for details. Figure 9-4. Program Load Random Data Sequence Diagram CS# 0 1 2 3 4 5 6 7 9 10 11 12 13 14 8 22 23 SCLK Command SI A11 - A0 Dummy 84h 0 0 0 0 11 10 3 2 1 0 CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Data byte 0 SI 7 6 MSB 5 DS-GD5F1GM7xExxG-Rev1.3 4 3 Data byte 1 2 1 0 7 6 5 4 3 2 36 Data byte N 1 0 7 6 5 4 3 2 1 0 December 2023 SPI-NAND GD5F1GM7 9.7 Program Load Random Data x4 (C4h/34h) The Program Load Random Data x4 command (C4h/34h) is similar to the Program Load Random Data command (84h) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command. See Figure 9-5 for details. Figure 9-5. Program Load Random Data x4 Sequence Diagram CS# 0 1 2 3 4 5 6 7 9 10 11 12 8 22 23 24 25 26 27 28 29 30 31 SCLK Command SI(SIO0) Dummy C4h/34h 0 0 Byte 0 Byte 1 A11 - A0 0 0 11 1 0 4 0 4 0 4 0 4 0 SO(SIO1) 5 1 5 1 5 1 5 1 WP#(SIO2) 6 2 6 2 6 2 6 2 HOLD#(SIO3) 7 3 7 3 7 3 7 3 CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Byte10Byte11 Byte N SI(SIO0) 4 SO(SIO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(SIO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 0 DS-GD5F1GM7xExxG-Rev1.3 4 0 4 0 4 0 4 0 4 0 37 4 0 4 0 4 0 4 0 4 0 4 0 December 2023 SPI-NAND GD5F1GM7 10 ERASE OPERATIONS 10.1 Block Erase (D8h) The BLOCK ERASE (D8h) command is used to erase at the block level. The BLOCK ERASE command (D8h) operates on one block at a time. The command sequence for the BLOCK ERASE operation is as follows: • 06h (WRITE ENBALE command) • D8h (BLOCK ERASE command) • 0Fh (GET FEATURES command to read the status register) Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06h) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE command must be followed by a BLOCK ERASE (D8h) command. This command requires a 24-bit address. After the row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy for tBERS time during the BLOCK ERASE operation. The GET FEATURES (0Fh) command can be used to monitor the status of the operation. Figure 10-1. Block Erase Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address D8h 23 22 21 3 2 1 0 High-Z SO CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLK tCS 0Fh 7 6 5 4 3 2 1 0 MSB High-Z SO CS# Status register address get feature SI 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SCLK SI Status register data out SO 7 MSB DS-GD5F1GM7xExxG-Rev1.3 6 5 4 3 2 1 0 Status register data out 7 6 5 4 3 2 1 0 7 6 MSB 38 December 2023 SPI-NAND GD5F1GM7 11 RESET OPERATIONS 11.1 Soft Reset(FFh) The RESET (FFh) command stops all operations and the status. For example, in case of a program or erase or read operation, the reset command can make the device enter the idle state. Figure 11-1. Reset Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI FFh High-Z SO CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SLK SI 0Fh 7 6 5 4 3 2 1 0 MSB High-Z SO CS# Status register address get feature tCS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SCLK SI Status register data out SO 7 MSB 6 5 4 3 2 1 0 Status register data out 7 6 5 4 3 2 1 0 7 6 MSB Note: The Register bit value after soft reset refers to Table 12-2. Register bit Descriptions. DS-GD5F1GM7xExxG-Rev1.3 39 December 2023 SPI-NAND GD5F1GM7 11.2 Enable Power on Reset (66h) and Power on Reset (99h) If the Power on Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current feature settings. The “Enable Reset (66h)” and the “Reset (99h)” commands can be issued in SPI mode. The “Reset (99h)” command sequence as follow: CS# goes low -> Sending Enable Reset command ->CS# goes high ->CS# goes low.->Sending Reset command ->CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tVSL to reset. During this period, no command will be accepted. It is recommended to check the OIP bit in Status Register before issuing any other command sequence. The contents of the memory location being programmed or the block being erased are no longer valid. Figure 11-2. Reset Sequence Diagram CS# 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCLK Command SI SO DS-GD5F1GM7xExxG-Rev1.3 Command 66h 99h High-Z 40 High-Z December 2023 SPI-NAND GD5F1GM7 12 FEATURE OPERATIONS 12.1 Get Features (0Fh) and Set Features (1Fh) The GET FEATURES (0Fh) and SET FEATURES (1Fh) commands are used to monitor the device status and alter the device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified. Feature such as OTP can be enabled or disabled by setting specific feature bits (shown in the below table). The status register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06h) command. When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise specified in the following table, once the device is set, it remains set, even if a RESET (FFh) command is issued. Table 12-1. Features Settings Register Addr. Protection A0h 7 6 5 4 3 2 1 0 BRWD Reserved BP2 BP1 BP0 INV CMP Reserved Feature B0h OTP_PRT OTP_EN Reserved ECC_EN BPL Reserved Reserved QE Status C0h Reserved Reserved ECCS1 ECCS0 P_FAIL E_FAIL WEL OIP Feature D0H Reserved DS_S1 DS_S0 Reserved Reserved Reserved Reserved Reserved Status F0h Reserved Reserved ECCSE1 ECCSE0 BPS Reserved Reserved Reserved Note: 1. If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed. 2. If QE is enabled, the quad IO operations can be executed. 3. All the reserved bits must be held low when the feature is set. 4. These registers A0h/B0h/D0H are write/read type, and Registers C0h/F0h are read only. 5. The OTP_PRT is non-volatile, others bits are volatile. 6. The Register Bit default value after power-up refers to Table 12-2. Register Bit Descriptions. DS-GD5F1GM7xExxG-Rev1.3 41 December 2023 SPI-NAND GD5F1GM7 Table 12-2. Status Register Bit Descriptions Bit Bit Name After Power up After Reset or Power on command Reset(66h-99h) (FFh) Description Block BRWD register Which is used combined with WP#, If BRWD is high 0 No Change write disable BP2 enabled and WP# is LOW, then the Protection register cannot be changed 1 BP1 Block 1 BP0 Protection 1 INV bits 0 CMP No Change used combination, refer to chapter Block Protection No Change used combination, refer to chapter OTP Region 0 OTP_PRT OTP Region OTP_EN bits 0 0 Before OTP Set The device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with ECC_EN ECC Enable Latch internal ECC can be enabled or disabled by setting 1 No Change feature bit ECC_EN. ECC is enabled by default when device powered on, so the default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable. BPL is for Power Lock Down Protection. Once the BPL bit Block BPL Protection Lock sets as 1, the rest of the protection bits BP[0,2] , INV , 0 No Change default BPL is 0 after power-on-reset and this bit default register QE The Quad Enable bit CMP , BRWD can’t be changed until next power cycle. By is Power Lock Down Protection disable. This bit indicates that whether the quad IO operations can 0 No Change be executed. If QE is set to 1, the quad IO operations can be executed. ECCS provides ECC status as the following table. ECCS and ECCSE are set to 00b either following a ECCS1 0 ECCS0 0 ECCSE1 ECC Status ECCSE0 Page 0 Status RESET, or at the beginning of the READ. They are then updated after the device completes a valid READ operation. 0 ECCS and ECCSE are invalid if internal ECC is disabled 0 (via a SET FEATURES command to reset ECC_EN to 0). After power-on RESET, ECC status is set to reflect the contents of block 0, page 0. DS-GD5F1GM7xExxG-Rev1.3 42 December 2023 SPI-NAND GD5F1GM7 This bit indicates that a program failure has occurred (P_FAIL set to 1). It will also be set if the user attempts to P_FAIL Program Fail 0 0 program a protected region, including the OTP area. This bit is cleared during the PROGRAM EXECUTE command sequence or a RESET command (P_FAIL = 0). This bit indicates that an erase failure has occurred (E_FAIL set to 1). It will also be set if the user attempts to E_FAIL Erase Fail 0 0 erase a locked region. This bit is cleared (E_FAIL = 0) at the start of the BLOCK ERASE command sequence or the RESET command. This bit indicates the current status of the write enable latch (WEL) and must be set (WEL = 1), prior to issuing a WEL Write Enable Latch 0 PROGRAM EXECUTE or BLOCK ERASE command. It is 0 set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing the WRITE DISABLE command. This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, OIP Operation In Progress 0 PAGE READ, BLOCK ERASE, or RESET command is 0 executing, indicating the device is busy. When the bit is 0, the interface is in the ready state. DS_IO[1] DS_IO[0] Driven Strength register 0 0 No Change Block BPS Protection Block protection status 1 No Change Status DS-GD5F1GM7xExxG-Rev1.3 IO driver strength setting. Default is 00b. BPS is 1, selected block is protected BPS is 0, selected block is unprotected. 43 December 2023 SPI-NAND GD5F1GM7 Figure 12-1. Get Features Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 byte address Command SI 0Fh SO 7 6 5 4 3 2 1 0 Data byte MSB High-Z 7 6 5 4 3 2 1 0 MSB Figure 12-2. Set Features Sequence Diagram CS# SCLK 0 SI 1 2 3 DS-GD5F1GM7xExxG-Rev1.3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Command 1Fh SO 4 Data byte 1 byte address 7 6 MSB 5 4 3 High-Z 44 2 1 0 7 6 5 4 3 2 1 0 MSB December 2023 SPI-NAND GD5F1GM7 12.2 Status Register and Driver Register The NAND Flash device has an 8-bit status register that software can read during the device operation for operation state query. The status register can be read by issuing the GET FEATURES (0Fh) command, followed by the feature address C0h (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE (0Fh) and GET FEATURE command followed by the feature address D0h (see FEATURE OPERATION). Table 12-3. ECC Error Bits Descriptions Description ECCS1 ECCS0 ECCSE1 ECCSE0 0 0 x x No bit errors were detected during the previous read algorithm 0 1 0 0 Bit errors(≤4) were detected and corrected 0 1 0 1 Bit errors (=5) were detected and corrected. 0 1 1 0 Bit errors (=6) were detected and corrected. 0 1 1 1 Bit errors (=7) were detected and corrected. 1 1 x x Bit errors (=8) were detected and corrected. 1 0 x x Bit errors greater than ECC capability(8 bits) and not corrected Table 12-4. Driver Register Bits Descriptions by Design Trim DS_IO[1] DS_IO[0] Driver Strength 0 0 100%(Default) 0 1 75% 1 0 50% 1 1 25% DS-GD5F1GM7xExxG-Rev1.3 45 December 2023 SPI-NAND GD5F1GM7 12.3 OTP Region The serial device offers a protected, One-Time Programmable NAND Flash memory area. 10 full pages are available on the device. Customers can use the OTP area any way they want, like programming serial numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP_PRT is 0. To access the OTP feature, the user must set feature bits OTP_EN/OTP_PRT by SET FEATURES command. When the OTP is ready for access, pages 02h–0Bh can be programmed in sequential order by PROGRAM LOAD (02h) and PROGRAM EXECUTE (10h) commands (when not yet protected), and read out by PAGE READ (13h) command and output data by READ from CACHE (03h/0Bh/3Bh/6Bh/BBh/EBh). When ECC is enabled, data written in the OTP area is ECC protected. Table 12-5.OTP States OTP_PRT OTP_EN State x 0 Normal Operation 0 1 Access OTP region, read and program data 1 1 1. When the device power on state OTP_PRT is 0, user can set feature bit OTP_PRT and OTP_EN to 1, then issue PROGRAM EXECUTE (10h) to lock OTP, and after that OTP_PRT will permanently remain 1. 2. When the device power on state OTP_PRT is 1, user can only read the OTP region data Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this function carefully. Access to OTP data • Issue the SET FEATURES command (1Fh) • Set feature bit OTP_EN • Issue the PAGE PROGRAM (only when OTP_PRT is 0) or PAGE READ command Protect OTP region Only when the following steps are completed, the OTP_PRT will be set and users can get this feature out with 0Fh command. • Issue the SET FEATURES command (1Fh) • Set feature bit OTP_EN and OTP_PRT • 06h (WRITE ENABLE) • Issue the PROGRAM EXECUTE (10h) command. DS-GD5F1GM7xExxG-Rev1.3 46 December 2023 SPI-NAND GD5F1GM7 12.4 Assistant Bad Block Management As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number of valid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB during the endurance life of the product. Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide badblock management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array. NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with ONFI Factory Defect Mapping requirements. See the following table for the bad-block mark. System software should initially check the first spare area location for non-FFh data on the first page of each block prior to performing any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased. To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant Management options as below. Table 12-6. Bad Block Mark information (1Gb) Description Requirement Minimum number of valid blocks (NVB) 1004 Total available blocks per die 1024 First spare area location Byte 2048 Bad-block mark 00h(use non FFh to check) DS-GD5F1GM7xExxG-Rev1.3 47 December 2023 SPI-NAND GD5F1GM7 12.5 Block Protection The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and ERASE operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2 are set to 1, INV, CMP and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be issued to alter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection feature bits can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0. When an ERASE command is issued to a locked block, the erase failure, status bit E_FAIL set to 1. When a PROGRAM command is issued to a locked block, program failure, status bit P_FAIL set to 1. To enable the Write Protection (WP#), the Quad Enable bit (QE) of feature (B0[0]) must be set to 0. Table 12-7. Block Lock Register Block Protect Bits (1Gb) CMP INV BP2 BP1 BP0 Protect Row Address Protect Rows 1G x x 0 0 0 None None—all unlocked 0 0 0 0 1 FC00h～FFFFh Upper 1/64 locked 0 0 0 1 0 F800h～FFFFh Upper 1/32 locked 0 0 0 1 1 F000h～FFFFh Upper 1/16 locked 0 0 1 0 0 E000h～FFFFh Upper 1/8 locked 0 0 1 0 1 C000h～FFFFh Upper 1/4 locked 0 0 1 1 0 8000h～FFFFh Upper 1/2 locked x x 1 1 1 0000h～FFFFh All locked (default) 0 1 0 0 1 0000h～03FFh Lower 1/64 locked 0 1 0 1 0 0000h～07FFh Lower 1/32 locked 0 1 0 1 1 0000h～0FFFh Lower 1/16 locked 0 1 1 0 0 0000h～1FFFh Lower 1/8 locked 0 1 1 0 1 0000h～3FFFh Lower 1/4 locked 0 1 1 1 0 0000h～7FFFh Lower 1/2 locked 1 0 0 0 1 0000h～FBFFh Lower 63/64 locked 1 0 0 1 0 0000h～F7FFh Lower31/32 locked 1 0 0 1 1 0000h～EFFFh Lower 15/16 locked 1 0 1 0 0 0000h～DFFFh Lower7/8 locked 1 0 1 0 1 0000h～BFFFh Lower3/4 locked 1 0 1 1 0 0000h～003FH Block0 1 1 0 0 1 0400h～FFFFh Upper 63/64 locked 1 1 0 1 0 0800h～FFFFh Upper31/32 locked 1 1 0 1 1 1000h～FFFFh Upper 15/16 locked 1 1 1 0 0 2000h～FFFFh Upper7/8 locked 1 1 1 0 1 4000h～FFFFh Upper3/4 locked 1 1 1 1 0 0000h～003FH Block0 When WP# is not LOW, user can issue bellows commands to alter the protection states as want. • Issue SET FEATURES register write (1Fh) • Issue the feature bit address (A0h) and the feature bits combination as the table DS-GD5F1GM7xExxG-Rev1.3 48 December 2023 SPI-NAND GD5F1GM7 12.6 Power Lock Down Protection The Power lock down protection prevent the block protection state from software modifications. After it is enabled, this protection cannot be disabled by a software command. Also, BP[0,2] , INV , CMP and BRWD bits are protected from further software change. Only another power cycle can disable the Power Lock Down Protection. When the Hardware Protection is disabled during quad or x4 mode, Power Lock Down Protection can be used to prevent a block protection state change. To enable the Power Lock Down Protection, perform the following command sequence: • Issue the SET FEATURES command (with address B0h) to set the feature bit BPL to 1: DS-GD5F1GM7xExxG-Rev1.3 49 December 2023 SPI-NAND GD5F1GM7 12.7 Internal ECC The device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled by default when device powered on, so the default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable. To enable/disable ECC, perform the following command sequence: • Issue the SET FEATURES command (1Fh) to set the feature bit ECC_EN: 1. To enable ECC, Set ECC_EN to 1. 2. To disable ECC, Clear ECC_EN to 0. During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page is written to the NAND Flash array. During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cache register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was successful. The ECC Protection table below shows the ECC protection scheme used throughout a page. There are two ECC protection formats as follow: • all data in main area and spare areas data are protected. Any data wrote to the ECC parity data area are ignored when ECC enabled. Table 12-8. The Distribution of ECC Segment and Spare Area in a Page Main Area(2KB) Spare Area(128B) User data User meta data ECC Parity Data Main0 Main1 Main2 Main3 Spare0 Spare1 Spare2 Spare3 Spare0 Spare1 Spare2 Spare3 (512B) (512B) (512B) (512B) (16B) (16B) (16B) (16B) (16B) (16B) (16B) (16B) Table 12-9. ECC Protection and Spare Area Max Byte Address Min Byte Address ECC Protected Area Description 1FFh 000h Yes Main 0 User data 0 3FFh 200h Yes Main 1 User data 1 5FFh 400h Yes Main 2 User data 2 7FFh 600h Yes Main 3 User data 3 80Fh 800h Yes Spare 0 User meta data 0(1) 81Fh 810h Yes Spare 1 User meta data 1 82Fh 820h Yes Spare 2 User meta data 2 83Fh 830h Yes Spare 3 User meta data 3 87Fh 840h Yes Spare Area Internal ECC parity data Note 1. 800h is reserved for initial bad block mark. 2. When ECC is on, the ECC for main/spare area (840h-87Fh) is prohibited for user, but user can read the Address 840h~87Fh. 3. When ECC is off, the whole page area is open for user. DS-GD5F1GM7xExxG-Rev1.3 50 December 2023 SPI-NAND GD5F1GM7 12.8 Deep Power-Down (B9h) (1.8V Only) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down (ABh), Soft Reset(FFh) or Enable Reset (66h) and Reset (99h) commands. These commands can release the device from this mode. The Release from Deep Power-Down command releases the device from deep power down mode. The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-Up. The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS# goes high. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC1-DPD and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Read Operation is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12-3. Deep Power-Down Sequence Diagram CS# 0 1 2 3 4 5 6 7 tDP SCLK Command SI DS-GD5F1GM7xExxG-Rev1.3 Deep Power-down mode B9h 51 December 2023 SPI-NAND GD5F1GM7 12.9 Release from Deep Power-Down (ABh)(1.8V Only) To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABh” and driving CS# high. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used to release the device from the Power-Down state, the command is the same as previously described, after this time duration the device will resume normal operation and other command will be accepted. If the Release from PowerDown command is issued while an Erase, Program or Read Operation is in process (when OIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 12-4. Release Power-Down Sequence Diagram CS# 0 1 2 3 4 5 6 t RES1 7 SCLK Command SI ABh Deep Power-down mode Stand-by mode Note： (1) FFh/ABh can get off from the DPD. About tRES1, user can get feature to check OIP if it’s ready. (2) 66h+99h will terminate the DPD. About tVSL the device will return to its default power-on state and lose all the current feature settings. DS-GD5F1GM7xExxG-Rev1.3 52 December 2023 SPI-NAND GD5F1GM7 13 POWER ON TIMING Figure 13. Power on Timing Sequence Vcc(max) Chip Selection is not allowed Vcc(min) tVSL Device is fully accessible VWI Time Table 13. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V Symbol tVSL Parameter Min VCC(min) To CS# Low VWI DS-GD5F1GM7xExxG-Rev1.3 Write Inhibit Voltage Max 2 ms 1.8V 1.5 3.3V 2.5 53 Unit V December 2023 SPI-NAND GD5F1GM7 14 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Ambient Operating Temperature -40 to 85 / -40 to 105 ℃ Storage Temperature -65 to 150 ℃ Applied Input / Output Voltage -0.6 to VCC+0.4 V VCC(3.3V) -0.6 to 4.0 V VCC(1.8V) -0.6 to 2.5 V Figure 14. Overshoot Waveform Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns DS-GD5F1GM7xExxG-Rev1.3 54 20ns December 2023 SPI-NAND GD5F1GM7 15 CAPACITANCE MEASUREMENT CONDITIONS Symbol Parameter Min Typ Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 Input Rise And Fall time pF 5 ns Input Pulse Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure 15. Input Test Waveform and Measurement Level Input timing reference level 0.8VCC 0.7VCC 0.1VCC 0.2VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are