NSI1312
High Reliability Reinforced/Basic
Isolated Amplifier
Datasheet (EN) 1.3
Key Features
Up to 5000VRMS Insulation Voltage
±1.2V Linear Input Voltage Range
Offset Drift: ±20μV/°C (Max)
Gain Error: ±0.3% (Max)
Gain Error Drift: ±40ppm/°C (Max)
Nonlinearity: ±0.05% (Max)
Nonlinearity Drift: ±1ppm/°C (Typ)
SNR: 78dB (Typ)
SOP8 narrow body (SOP8 150mil)
UL recognition:
SOW8: 5000Vrms for 1 minute per UL1577
SOP8: 3000Vrms for 1 minute per UL1577
CQC certification per GB4943.1
CSA component notice 5A
DIN EN IEC 60747-17 (VDE 0884-17)
Applications
AC motor controls
Power and solar inverters
Uninterruptible Power Suppliers
Automotive onboard chargers
Device Information
Part Number
NSI1312x-DSWVR
Package
SOW8(300mil)
Body Size
5.85mm × 7.50mm
NSI1312x-DSPR
SOP8(150mil)
4.90mm × 3.90mm
Functional Block Diagrams
VDD1
Excellent DC Performance:
Offset Error: ±2.5mV (Max)
SOW8 wide body (SOP8 300mil)
Safety Regulatory Approvals
Fixed Gain : 1
VDD2
VDD1 detection
Reference
INP
Σ-Δ modulator
INN
RX
Retiming
and 4thOrder Active
Low-Pass
Filter
OUTP
OUTN
Reference
Oscillator
GND1
GND2
Figure 1. NSI1312D Block Diagram
VDD1
VDD2
VDD1 detection
Reference
INP
High CMTI: 150kV/μs (Typ)
System-Level Diagnostic Features:
TX
Isolation Barrier
NSI1312 is a cost-effective isolated amplifier with output
separated from input based on the NOVOSENSE capacitive
isolation technology Adaptive OOK®. The device has a
linear differential input signal range of ±1.2V (±1.5V fullscale). The high input impedance of NSI1312 makes it
highly suitable for connection to high-voltage resistive
dividers or other voltage signal sources with high output
resistance.
The device has a fixed gain of 1 and provides differential
analog output version (NSI1312D) and single-ended
analog output version (NSI1312S) option.
The low offset and gain drift ensure the accuracy over the
entire temperature range. The high common-mode
transient immunity ensures that the device is able to
provide accurate and reliable measurements even in the
presence of high-power switching such as in motor
control applications.
The fail-safe function (missing VDD1 detection) simplifies
system-level design and diagnostics.
RoHS-Compliant Packages:
Σ-Δ modulator
INN
TX
Isolation Barrier
Product Overview
RX
Oscillator
Retiming
and 4thOrder Active
Low-Pass
Filter
OUT
Reference
REFIN
VDD1 monitoring
Operation Temperature: -40°C~125°C
Copyright © 2023, NOVOSENSE
GND1
GND2
Figure 2. NSI1312S Block Diagram
Page 1
NSI1312
Datasheet (EN) 1.3
INDEX
1. PIN CONFIGURATION AND FUNCTIONS............................................................................................................................. 3
2. ABSOLUTE MAXIMUM RATINGS ......................................................................................................................................... 5
3. ESD RATINGS ..................................................................................................................................................................... 5
4. RECOMMENDED OPERATING CONDITIONS ....................................................................................................................... 5
5. THERMAL INFORMATION ................................................................................................................................................... 5
6. SPECIFICATIONS ................................................................................................................................................................ 6
6.1.
6.2.
6.3.
6.4.
ELECTRICAL CHARACTERISTICS....................................................................................................................................... 6
POWER RATING CHARACTERISTICS .................................................................................................................................. 7
TYPICAL PERFORMANCE CHARACTERISTICS ...................................................................................................................... 8
PARAMETER MEASUREMENT INFORMATION .................................................................................................................... 11
7. HIGH VOLTAGE FEATURE DESCRIPTION .......................................................................................................................... 11
7.1.
7.2.
7.3.
INSULATION AND SAFETY RELATED SPECIFICATIONS ......................................................................................................... 11
INSULATION CHARACTERISTICS..................................................................................................................................... 12
REGULATORY INFORMATION ......................................................................................................................................... 13
8. FUNCTION DESCRIPTION ................................................................................................................................................ 14
8.1.
8.2.
8.3.
OVERVIEW ................................................................................................................................................................ 14
ANALOG INPUT .......................................................................................................................................................... 15
ANALOG OUTPUT ....................................................................................................................................................... 15
9. APPLICATION NOTE ......................................................................................................................................................... 17
9.1.
9.2.
9.3.
TYPICAL APPLICATION CIRCUIT .................................................................................................................................... 17
SENSE RESISTOR SELECTION ....................................................................................................................................... 17
PCB LAYOUT ............................................................................................................................................................ 18
10. PACKAGE INFORMATION ............................................................................................................................................... 18
11. ORDERING INFORMATION ............................................................................................................................................. 21
12. DOCUMENTATION SUPPORT ......................................................................................................................................... 21
13. TAPE AND REEL INFORMATION ..................................................................................................................................... 22
14. REVISION HISTORY ........................................................................................................................................................ 24
Copyright © 2023, NOVOSENSE
Page 2
NSI1312
Datasheet (EN) 1.3
1. Pin Configuration and Functions
VDD1
1
INP
2
INN
3
GND1
4
NSI1312D
TOP VIEW
8
VDD2
7
OUTP
6
OUTN
5
GND2
Figure 1.1 NSI1312D Package (SOW8 and SOP8)
Table 1.1 NSI1312D Pin Configuration and Description
NSI1312D PIN
NO.
SYMBOL
FUNCTION
1
VDD1
Power supply for isolator input side (3.0V to 5.5V)
2
INP
Positive analog input
3
INN
Negative analog input
4
GND1
Ground 1, the ground reference for input side
5
GND2
Ground 2, the ground reference for output side
6
OUTN
Negative output
7
OUTP
Positive output
8
VDD2
Power supply for isolator output side (3.0V to 5.5V)
Copyright © 2023, NOVOSENSE
Page 3
NSI1312
Datasheet (EN) 1.3
VDD1
1
INP
2
INN
3
GND1
4
NSI1312S
TOP VIEW
8
VDD2
7
OUT
6
REFIN
5
GND2
Figure 1.2 NSI1312S Package (SOW8 and SOP8)
Table 1.2 NSI1312S Pin Configuration and Description
NSI1312S PIN
NO.
SYMBOL
FUNCTION
1
VDD1
Power supply for input side (3.0V to 5.5V)
2
INP
Positive analog input
3
INN
Negative analog input
4
GND1
Ground 1, the ground reference for input side
5
GND2
Ground 2, the ground reference for output side
6
REFIN
External Reference Input
7
OUT
Output
8
VDD2
Power supply for output side (3.0V to 5.5V)
Copyright © 2023, NOVOSENSE
Page 4
NSI1312
Datasheet (EN) 1.3
2. Absolute Maximum Ratings
Parameters
Symbol
Min
VDD1, VDD2
-0.3
6.5
V
INP, INN
GND1-6
VDD1+0.5
V
REFIN
GND2-0.5
VDD2+0.5
V
OUTP, OUTN,
OUT
GND2-0.5
VDD2+0.5
V
Output current per Output Pin
Io
-10
10
mA
Junction Temperature
TJ
-40
150
℃
Storage Temperature
TSTG
-55
150
℃
Power Supply Voltage
Input Voltage
Output Voltage
Typ
Max
Unit
3. ESD Ratings
Parameters
Electrostatic discharge
Test Condition
Value
Unit
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4.0
kV
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
±1.0
kV
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4. Recommended Operating Conditions
Parameters
Symbol
Min
Typ
Max
Unit
Input side Power Supply
VDD1
3.0
5.0
5.5
V
Output side Power Supply
VDD2
3.0
3.3
5.5
V
Differential input voltage before clipping
output
VClipping
Linear differential input full scale voltage
VFSR
-1.2
1.2
V
Operating common-mode input voltage
VCM
-0.8
0.8
V
Operating Ambient Temperature
TA
-40
125
℃
±1.5
V
5. Thermal Information
Parameters
Symbol
SOW8
SOP8
Unit
Junction–to-ambient thermal resistance
RθJA
86
137.7
°C/W
Junction-to-case (top) thermal resistance
RθJC(top)
28
54.9
°C/W
Junction-to-board thermal resistance
RθJB
42
71.7
°C/W
Junction–to-top characterization parameter
ΨJT
4
12
°C/W
Junction-to-board characterization parameter
ΨJB
42
46
°C/W
Copyright © 2023, NOVOSENSE
Page 5
NSI1312
Datasheet (EN) 1.3
6. Specifications
6.1. Electrical Characteristics
(AVDD = 3.0V ~ 5.5V, DVDD = 3.0V ~ 5.5V, INP = -1.2V to +1.2V, and INN = AGND = 0V, TA = -40°C to 125°C. Unless otherwise noted,
Typical values are at VDD1 = 5V, VDD2 = 3.3V, TA = 25°C.Output characteristics is based on OUTP-OUTN for NSI1312D, is based on
OUT-REFIN for NSI1312S.)
Parameters
Symbol
Min
Typ
Max
Unit
Input side supply voltage
VDD1
3.0
5.0
5.5
V
Output side supply voltage
VDD2
3.0
3.3
5.5
V
Input side supply current
IDD1
7.2
9
mA
Output side supply current
IDD2
4.7
6.2
mA
Comments
Power Supply
VDD1 undervoltage detection
threshold voltage
VDD1UV
1.8
2.3
2.7
V
VOS
-2.5
±1
2.5
mV
TCVOS
-20
0.5
20
μV/°C
VDD1 falling
Analog Input
Input offset voltage
Input offset drift
INP = INN = GND1, at TA =25°C
CMRRdc
-80
dB
INP = INN, fIN = 0 Hz, VCM min ≤ VIN ≤
VCM max
CMRRac
-82
dB
INP = INN, fIN = 10 kHz, VCM min ≤ VIN
≤ VCM max
Single-ended input resistance
RIN
1
MΩ
INN = GND1
Differential input resistance
RIND
1.6
MΩ
Input capacitance
CI
2
pF
Input bias current
IIB
Common-mode rejection ratio
Input bias current drift
-0.7
TCIIB
-0.6
-0.5
μA
-1
nA/°C
1
V/V
INP = INN = GND1, at TA =25°C, IIB =
(IIBP + IIBN) / 2
Analog Output
Nominal Gain
Gain error
Gain error thermal drift
EG
-0.3%
±0.1%
0.3%
TCEG
-40
-10
40
-0.05%
±0.01%
0.05%
Nonlinearity
Nonlinearity drift
Total harmonic distortion
THD
Output noise
Signal to noise ratio
Copyright © 2023, NOVOSENSE
SNR
at TA =25°C
ppm/°C
at TA =25°C
±1
ppm/°C
-75
dB
100
µVRMS
78
dB
VIN =±1.2V, fIN = 10kHz, BW = 50kHz
INP = INN = GND1, BW = 50kHz
VIN =±1.2V, fIN = 10kHz, BW = 50kHz
Page 6
NSI1312
Common-mode output voltage
Differential fail-safe output
voltage
Datasheet (EN) 1.3
VCMout
1.39
VFAILSAFE
Single-ended fail-safe output
voltage
VFAILSAFE
Single-ended reference input
REFIN
Single-ended reference input
impedance
REFININ
0.5
1.44
1.49
V
Only for NSI1312D
-1.8
-1.7
V
NSI1312D VDD1 missing
0
V
NSI1312S VDD1 missing,
REFIN1.8V
V
Only for NSI1312S. See
application description for more
details.
VDD2/2
VDD21.5
1
GΩ
100
kHz
PSRRdc
-95
dB
PSRR vs VDD1, at DC
PSRRac
-95
dB
PSRR vs VDD1, 100mV and 10kHz
ripple
PSRRdc
-90
dB
PSRR vs VDD2, at DC
PSRRac
-80
dB
PSRR vs VDD2 for NSI1312D,
100mV and 10kHz ripple
PSRRac
-72
dB
PSRR vs VDD2 for NSI1312S,
100mV and 1kHz ripple
Output resistance
ROUT
< 0.2
Ω
Output limit current
ILIM
±13
mA
150
kV/μs
Output bandwidth
Power supply rejection ratio
Common-mode transient
immunity
BW
CMTI
50
100
Only for NSI1312S
Common-mode transient
immunity
Timing
Rising time of OUTP, OUTN
tr
3.6
μs
Falling time of OUTP, OUTN
tf
3.6
μs
INP, INN to OUTP, OUTN signal
delay (50% - 50%)
tPD
3.5
Analog settling time
tAS
0.5
4
μs
ms
VDD1 step to 5.0 V with VDD2 ≥ 3.0
V, to OUTP, OUTN valid, 0.1%
settling
6.2. Power Rating Characteristics
Parameters
Symbol
Max
Unit
Comments
Total Power dissipation
PD
83.6
mW
VDD1=VDD2=5.5V
Power dissipation of high side
PD1
49.5
mW
VDD1=5.5V
Power dissipation of low side
PD2
34.1
mW
VDD2=5.5V
Copyright © 2023, NOVOSENSE
Page 7
NSI1312
Datasheet (EN) 1.3
6.3. Typical Performance Characteristics
Unless otherwise noted, test at NSI1312D VDD1 = 5V, VDD2 = 3.3V, INN=GND1=0V, INP = -1.2V to 1.2V, fIN = 1kHz, BW = 10kHz.
Characteristics of NSI1312S may be related to REFIN accuracy.
0.4
0.02
0.3
0.018
Sample1
0.016
Sample2
0.014
Sample3
Nonlinearity/%
0.2
Vos/mV
0.1
0
-0.1
Sample 1
-0.2
-40
-20
0
20
40
60
80
100
0.006
0.002
Sample 3
-0.4
0.01
0.008
0.004
Sample 2
-0.3
0.012
0
120
-40
140
-20
0
20
60
80
100
120
140
Figure 6.3 Nonlinearity vs Temperature
Figure 6.1 Input Offset Voltage vs Temperature
-0.55
0.2
0.15
Sample 1
0.1
Sample 2
0.05
Sample 3
Sample 1
-0.56
Sample 2
Sample 3
-0.57
IIB/uA
Gain Error/%
40
Templerature(℃)
Templerature(℃)
0
-0.05
-0.58
-0.59
-0.1
-0.6
-0.15
-0.61
-0.2
-40
-20
0
20
40
60
80
100
120
-40
140
-20
0
20
40
60
80
100
120
140
Templerature(℃)
Templerature(℃)
Figure 6.4 Input Bias Current vs Temperature
Figure 6.2 Gain Error vs Temperature
-60
1.6
-65
1.59
-75
RinD/MΩ
CMRR/dB
-70
-80
1.58
1.57
-85
1.56
-90
-95
-40
-20
0
20
40
60
80
100
120
140
Templerature(℃)
Figure 6.5 Common-Mode Rejection Ratio vs Temperature
Copyright © 2023, NOVOSENSE
1.55
-40
-20
0
20
40
60
80
100
120
140
Templerature(℃)
Figure 6.6 Differential Input Resistance vs Temperature
Page 8
Datasheet (EN) 1.3
-65
-65
-66
-66
-67
-67
-68
-68
-69
-69
THD/dB
THD/dB
NSI1312
-70
-71
-72
VDD1
VDD2
-70
-71
-72
-73
-73
-74
-74
-75
-40
-20
0
20
40
60
80
100
120
-75
140
3
Templerature(℃)
4.5
5
5.5
Figure 6.8 THD vs Supply Voltage
82
82
81
81
80
80
79
SNR/dB
SNR/dB
4
Supply Voltage(V)
Figure 6.7 THD vs Temperature
78
77
VDD1
VDD2
79
78
77
76
76
75
-40
-20
0
20
40
60
80
100
120
75
140
3
Templerature(℃)
3.5
4
4.5
5
5.5
Supply Voltage(V)
Figure 6.9 SNR vs Temperature
Figure 6.10 SNR vs Supply Voltage
0
2.5
vs VDD1
-20
2
vs VDD2
Output Voltage/V
-40
PSRR/dB
3.5
-60
-80
1.5
1
0.5
-100
-120
0.1
1
10
100
1000
Frequency(kHz)
Figure 6.11 Power-Supply Rejection Ratio vs Ripple Frequency
(NSI1312D)
Copyright © 2023, NOVOSENSE
OUTP-GND
OUTN-GND
0
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Input Voltage(V)
Figure 6.12 Output Voltage vs Input Voltage (NSI1312D)
Page 9
NSI1312
Datasheet (EN) 1.3
-1.75
1.5
Common Mode Voltage/V
Failsafe Voltage/V
-1.76
-1.77
-1.78
-1.79
-1.8
-1.81
1.48
1.46
1.44
1.42
-1.82
1.4
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
Templerature(℃)
Figure 6.13 Fail-Safe Output Voltage vs Temperature
(NSI1312D)
3.5
100
120
140
8
7.5
3.49
3.485
Supply Current/mA
Propagation Delay/us
80
Figure 6.14 Output Common-Mode Voltage vs Temperature
(NSI1312D)
3.495
3.48
3.475
3.47
3.465
7
6.5
3.46
3.455
4.5
-20
0
20
40
60
80
100
120
VDD2=3.3V
5.5
5
-40
VDD1=5V
6
3.45
4
140
-1.2
-0.7
-0.2
Templerature(℃)
0.3
0.8
Input Voltage(V)
Figure 6.15 Vin to Vout Delay vs Temperature
Figure 6.16 Supply Current vs Input Voltage
8
7.5
7.5
7
7
6.5
VDD1=5V
6
VDD2=3.3V
5.5
5
4.5
Supply Current/mA
Supply Current/mA
60
Templerature(℃)
6.5
6
VDD1
5.5
VDD2
5
4.5
4
-40
-20
0
20
40
60
80
100
120
Temperature(C)
Figure 6.17 Supply Current vs Temperature
Copyright © 2023, NOVOSENSE
140
4
3
3.5
4
4.5
5
5.5
Supply Voltage(V)
Figure 6.18 Supply Current vs Supply Voltage
Page 10
NSI1312
Datasheet (EN) 1.3
6.4. Parameter Measurement Information
3.3V
VDD2
VDD1
INP
OUTP
INN
OUTN
GND1
GND2
Battery
Differential
Probe
Oscilloscope
High Voltage
Probe
VCM
Figure 6.19 Common-Mode Transient Immunity Test Circuit
7. High Voltage Feature Description
7.1. Insulation and Safety Related Specifications
Parameters
Symbol
Value
SOP8
SOW8
Unit
Comments
Minimum External Clearance
CLR
4
8
mm
IEC 60664-1:2007
Minimum External Creepage
CPG
4
8
mm
IEC 60664-1:2007
Distance Through Insulation
DTI
28
μm
Distance through insulation
Tracking Resistance
(Comparative Tracking Index)
CTI
>600
V
Material Group
Description
Overvoltage Category per IEC60664-1
Climatic Classification
Pollution Degree per DIN VDE 0110
Copyright © 2023, NOVOSENSE
I
Test Condition
DIN EN 60112 (VDE 0303-11); IEC
60112
IEC 60664-1
Value
SOP8
SOW8
For Rated Mains Voltage ≤ 150Vrms
I to IV
I to IV
For Rated Mains Voltage ≤ 300Vrms
I to III
I to IV
For Rated Mains Voltage ≤ 600Vrms
I to II
I to IV
For Rated Mains Voltage ≤ 1000Vrms
I
I to III
40/125/21
2
Page 11
NSI1312
Datasheet (EN) 1.3
7.2. Insulation Characteristics
Description
Test Condition
Symbol
Value
Unit
SOP8
SOW8
990
2121
VPEAK
700
1500
VRMS
990
2121
VDC
DIN EN IEC 60747-17 (VDE 0884-17)
Maximum repetitive isolation voltage
Maximum working isolation voltage
VIORM
AC Voltage
DC Voltage
VIOWM
Method a, after Input/output safety
test subgroup 2/3,
pC
Vini=VIOTM, tini = 60 s , Vpd(m)=1.2*VIORM,
tm=10s.
Apparent Charge
Method a, after environmental tests
subgroup 1, Vini=VIOTM,
tini=60s ,Vpd(m)=1.6*VIORM, tm=10s
qpd
/
1012
Ω
VIO =500V, 100℃ ≤ Tamb ≤ 125°C
RIO
>1011
>1011
Ω
VIO =500V, Tamb=Ts
RIO
>109
>109
Ω
f = 1MHz
CIO
0.8
0.8
pF
VI = 5.5V, TJ = 150 °C, TA = 25 °C
Ps
907
1453
mW
Page 12
NSI1312
Datasheet (EN) 1.3
Description
Test Condition
Symbol
θJA = 137.7°C /W for SOP8, VI = 5.5V, TJ
= 150 °C, TA = 25°C
Safety input, output, or supply current
θJA = 86°C/W for SOW8, VI = 5.5V, TJ =
150 °C, TA = 25 °C
Maximum safety temperature
Value
Unit
SOP8
SOW8
165
/
mA
/
264
mA
Ts
150
150
℃
VISO
3000
5000
VRMS
Is
UL1577
VTEST = VISO, t = 60 s (qualification),
Insulation voltage per UL
VTEST = 1.2 × VISO, t = 1 s (100%
production test)
Safety Limiting Power(mW)
1600
SOP8
1400
SOW8
1200
1000
800
600
400
200
0
0
20
40
60
80
100
120
Ambient Temperature(℃)
140
160
Figure 7.1 NSI1312x Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE 0884-17
7.3. Regulatory Information
The NSI1312x-DSWVR are approved or pending approval by the organizations listed in table.
UL
UL 1577 Component
Recognition Program
Single Protection, 5000Vrms
Isolation voltage
Approved under CSA
Component Acceptance
Notice 5A
Single Protection, 5000Vrms
Isolation voltage
VDE
CQC
DIN EN IEC 60747-17 (VDE
0884-17)
Certified according to
GB4943.1
Reinforce Insulation
VIORM=2121Vpeak
VIOTM=8000Vpeak
Reinforced insulation
VIOSM=10000Vpeak
E500602
Copyright © 2023, NOVOSENSE
E500602
File (pending)
CQC20001264940
Page 13
NSI1312
Datasheet (EN) 1.3
The NSI1312x-DSPR are approved or pending approval by the organizations listed in table.
UL
Approved under CSA
Component Acceptance
Notice 5A
UL 1577 Component
Recognition Program
VDE
CQC
DIN EN IEC 60747-17 (VDE
0884-17)
Certified according to
GB4943.1
Basic Insulation
Single Protection, 3000Vrms
Isolation voltage
Single Protection, 3000Vrms
Isolation voltage
VIORM=990Vpeak
Basic insulation
VIOTM=4242Vpeak
VIOSM=6000Vpeak
E500602
E500602
File (pending)
CQC20001264940
8. Function Description
8.1. Overview
The NSI1312 is a cost-effective isolated amplifier with a high input impedance that accept wide range fully-differential input. The
fully-differential input is suited to AC or bus voltage monitoring in high voltage applications where isolation is required. The analog
input is continuously sampled by a second-order Σ-Δ modulator in the device. With the internal voltage reference and clock
generator, the modulator converts the analog input signal to a digital bitstream, as shown in the Figure 8.1. The output of the
modulator is transferred by the drivers (called TX in the Functional Block Diagram) across the isolation barrier that separates the
isolated input side and output side voltage. The received bitstream and clock are synchronized and processed, as shown in the
Functional Block Diagram, by a fourth-order analog filter on the output side and has a differential output. NSI1312 also has singleended output version, as shown in the Figure 8.2, the received bitstream are processed and presented as a single-ended output with
external voltage reference from REFIN pin.
VDD1
VDD2
VDD1 detection
INP
Σ-Δ modulator
INN
TX
Isolation Barrier
Reference
Retiming
and 4thOrder Active
Low-Pass
Filter
RX
OUTN
Reference
Oscillator
GND1
OUTP
GND2
Figure 8.1 Function Block Diagram of Differential Output Version
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
VDD1
VDD2
VDD1 detection
Isolation Barrier
Reference
INP
Σ-Δ modulator
TX
INN
Oscillator
GND1
RX
Retiming
and 4thOrder Active
Low-Pass
Filter
OUT
Reference
REFIN
GND2
Figure 8.2 Function Block Diagram of Single-ended Output Version
8.2. Analog Input
There are two restrictions on the analog input signals (VINP and VINN).
If the input voltage exceeds the range AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device
input electrostatic discharge (ESD) diodes turn on.
The linearity and noise performance of the device are ensured only when the analog input voltage remains within the specified
linear full-scale range (FSR) and within the specified common-mode input voltage range.
8.3. Analog Output
For linear input range, the analog output of NSI1312 has a fixed gain of 1. If a full-scale input signal is applied to the NSI1312 (VIN ≥
VClipping), the differential analog output (VOUTP -VOUTN for NSI1312D and VOUT -REFIN for NSI1312S) will be clipped (typically, 1.44V for
positive clipping and -1.44V for negative clipping). The negative clipping differential output waveform is shown in Figure 8.3.
Vout 1V/div
Vneg_clip=-1.44V
Figure 8.3 Typical negative clipping output
For differential output version (NSI1312D), the differential output pins have a common-mode voltage of 1.44V (typ). The
differential output Vout of the NSI1312D is expressed as:
𝑉𝑜𝑢𝑡 = 𝐺𝑎𝑖𝑛 ∗ (𝑉
−𝑉
)
For single-ended output version (NSI1312S), the REFIN pin with high input impedance needs external reference input. The output
voltage Vout of the NSI1312S is expressed as:
𝑉𝑜𝑢𝑡 = 𝐺𝑎𝑖𝑛 ∗ (𝑉
Copyright © 2023, NOVOSENSE
−𝑉
) + 𝑅𝐸𝐹𝐼𝑁
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NSI1312
Datasheet (EN) 1.3
In addition, NSI1312 integrates some diagnostic measures and offers a fail-safe output to simplify system-level design. The failsafe output is a negative differential output voltage that does not occur under normal device operation, and it will only be
activated when the undervoltage of VDD1 is detected (VDD1< VDD1UV). For NSI1312D, the typical failsafe output is -1.8V when VDD1
undervoltage, as is shown in Figure 8.4. For NSI1312S, the typical failsafe output is Vfailsafe= 0V if VREF1.8V when VDD1 undervoltage, as is shown in Figure 8.5.
VDD1 5V/div
Vout 1V/div
Vfailsafe=-1.8V
Figure 8.4 Typical Failsafe output when VDD1 undervoltage for NSI1312D
VDD1 2V/div
Vout 0.5V/div
Vfailsafe=0V
(a) VREF=1.6V (VREF1.8V)
Figure 8.5 Typical failsafe output when VDD1 undervoltage for NSI1312S
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
9. Application Note
9.1. Typical Application Circuit
NSI1312 has an input impedance of up to 1MΩ, and has a wide bidirectional input voltage range as well. These features make
NSI1312 ideally suitable for isolated AC and DC voltage sensing applications such as frequency inverters. The typical application
circuit is shown in Figure 9.1.
For high voltage side design, the voltage of the frequency inverter is divided by a resistance network, and the divided voltage is
applied to the input of NSI1312 through a RC filter to ensure best performance. The characteristics of this filter are dictated by the
input topology and sampling frequency of the ADC, customer can adjust the filter design by demand. To reduce extra offset
voltage caused by input bias current flowing through Rsense, suggest to add RFLTP as below. To reduce extra gain error caused by
input resistance of NSI1312, suggest customer to choose smaller resistance, such as Rsense≤10kΩ.
About controller side design, for differential output version (NSI1312D), the differential output of the isolated amplifier is
converted to a single-ended analog output with an operational-amplifier-based circuit. Suggest to add >1kΩ resistor on the OUTP
and OUTN pin to prevent output over-current protection.
For single-ended output version (NSI1312S), REFIN needs external reference input, such as accurate reference IC, LDO and resistor
divider network. The single-ended output swing range is GND2+0.3V~VDD2-0.3V. To avoid OUT clamp, REFIN is recommended to
be taken as VDD2/2 if need to support ±1.2V analog input range. If the reference is noisy, customer need to add RC filter and adjust
the value by demand. The output can be connected to an analog-to-digital converter without signal conditioning. An analog-todigital converter usually receives the analog output and converts to digital signal for controller processing.
VBU S+
R1
Rectifier
VAC+
Gate
Driver
Gate
Driver
R2
R3
VACRsense≤
10kΩ
Gate
Driver
M
Gate
Driver
Rsense
≤10kΩ
VBU S-
Gate
Driver
NSI1312D
3.0~5.5V
2.2uF
Gate
Driver
0.1uF
RFLTN=(R1+R2)//Rsense+RFLTP
100pF
VDD1
VDD2
GND1
GND2
INN
OUTP
INP
OUTN
RFLTP=10Ω
NSI1312S
3.0~5.5V
2.2uF
0.1uF
RFLTN=R3//Rsense+RFLTP
100pF
RFLTP=10Ω
VDD1
VDD2
GND1
GND2
INN
OUT
INP
0.1uF
3.0~5.5V
2.2uF
1kΩ
1kΩ
47pF
1kΩ
0.1uF
To ADC
1kΩ
3.0~5.5V
2.2uF
To ADC
RFLT=1kΩ
REFIN
External Reference
4.7uF
Figure 9.1 Typical application circuit in voltage sensing
9.2. Sense Resistor Selection
There are two other factors should be considered when selecting the sense resistor:
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
The voltage-drop on Rsense divided by nominal VBUS or VAC must not exceed the recommended linear input voltage range: VIN ≤
FSR.
The voltage-drop on Rsense divided by VBUS or VAC in maximum allowed overvoltage condition must not exceed the input
voltage that causes a clipping output: VIN ≤ VClipping.
9.3. PCB Layout
There are some key guidelines or considerations for optimizing performance in PCB layout:
NSI1312 requires a 0.1µF bypass capacitor between VDD1 and GND1, VDD2 and GND2. The capacitor should be placed as close
as possible to the VDD pin. If better filtering is required, an additional 1~10µF capacitor may be used.
Kelvin rules is recommended for the connection between shunt resistor to NSI1312. Because of the Kelvin connection, any
voltage drops across the trace and leads should have no impact on the measured voltage.
Place the shunt resistor close to the INP and INN inputs and keep the layout of both connections symmetrical and run very
close to each other to the input of the NSI1312. This minimizes the loop area of the connection and reduces the possibility of
stray magnetic fields from interfering with the measured signal.
10. Package Information
Figure 10.1 SOW8 Package Shape and Dimension in millimeters
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
Figure 10.2 SOW8 Package Board Layout Example
Figure 10.3 SOP8 package shape and dimension in millimeters
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
Figure 10.4 SOP8 Package Board Layout Example
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
11. Ordering Information
Part No.
NSI1312DDSPR
NSI1312SDSPR
NSI1312D DSWVR
NSI1312S DSWVR
Isolation
Rating(kV)
Linear
Input
Range(V)
Moisture
Sensitivity
Level
Temperature
Automotive
3
-1.2 ~ 1.2
Level-3
-40 to 125℃
NO
3
-1.2 ~ 1.2
Level-3
-40 to 125℃
NO
5
-1.2 ~ 1.2
Level-3
-40 to 125℃
NO
5
-1.2 ~ 1.2
Level-3
-40 to 125℃
NO
Package
Type
SOP8
(150mil)
SOP8
(150mil)
SOP8
(300mil)
SOP8
(300mil)
Package
Drawing
SPQ
SOP8
2500
SOP8
2500
SOW8
1000
SOW8
1000
12. Documentation Support
Part Number
Product Folder
Datasheet
Technical Documents
Isolator selection guide
NSI1312
Click here
Click here
Click here
Click here
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
13. Tape and Reel Information
Figure 13.1 Tape Information
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
Direction of Feed
Pin 1
1
3
2
4
Quadrant Designations
Figure 13.2 Reel Information of SOP8(300mil)
Direction of Feed
Pin 1
1
3
2
4
Quadrant Designations
Figure 13.3 Reel Information of SOP8(150mil)
Copyright © 2023, NOVOSENSE
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NSI1312
Datasheet (EN) 1.3
14. Revision History
Revision
1.0
1.1
1.2
1.3
Description
Initial Release
Update REFIN specification in 5.2 and UL certificate number in 6.3 and input
filter resistance in Fig 8.1
Update VCM range in part 3, VFAILSAFE and PSRRAC specifications in 5.1, the
comments of VOS, IIB, EG and Nonlinearity in 5.1, Figure 5.11~5.14 in 5.3, the
standard on which VIOSM test method is based in 6.2, CQC certificate number in
6.3, description for analog output of NSI1312S in 7.3 and input filter
resistance in Fig 8.1. Update typeface to Source Sans Pro.
Updated the description of isolation level in the header of first page
from ‘Reinforced’ to “Reinforced/Basic’;
Updated specifications in Key features;
Updated Offset Error from ±5mV to ±2.5mV in Section. 6.1;
Updated Offset Drift from ±25μV/℃ (Typ) to ±20μV/℃ (Max) in Section.
6.1;
Updated Gain Error from ±0.4% to ±0.3% in Section. 6.1;
Updated Gain Error Drift from ±50ppm/℃(Typ) to ±40ppm/℃(Max) in
Section. 6.1;
Updated THD from -70dB to -75dB in Section. 6.1;
Added a separate section of ESD ratings and changed its description;
Updated ESD the level of HBM from ±2.0kV to ±4.0kV;
Updated the lower limit of VDD1 power supply from 4.5V to 3.0V in Pin
Configuration and Functions;
Updated the description of Safety Regulation Approvals;
Updated the description of Safety certification in Section.7(Section.6 in
previous edition).
Copyright © 2023, NOVOSENSE
Date
2022/3/23
2022/6/27
2022/12/24
2023/7/20
Page 24
NSI1312
Datasheet (EN) 1.3
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as any warranty or authorization of, express or implied,
including but not limited to accuracy, completeness, merchantability, fitness for a particular purpose or infringement of any third
party’s intellectual property rights.
You are solely responsible for your use of Novosense’ products and applications, and for the safety thereof. You shall comply with
all laws, regulations and requirements related to Novosense’s products and applications, although information or support related
to any application may still be provided by Novosense.
The resources are intended only for skilled developers designing with Novosense’ products. Novosense reserves the rights to
make corrections, modifications, enhancements, improvements or other changes to the products and services provided.
Novosense authorizes you to use these resources exclusively for the development of relevant applications designed to integrate
Novosense’s products. Using these resources for any other purpose, or any unauthorized reproduction or display of these
resources is strictly prohibited. Novosense shall not be liable for any claims, damages, costs, losses or liabilities arising out of the
use of these resources.
For further information on applications, products and technologies, please contact Novosense (www.novosns.com ).
Suzhou Novosense Microelectronics Co., Ltd
Copyright © 2023, NOVOSENSE
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