GD32H757VMT6

GigaDevice Semiconductor Inc. GD32H757xx Arm® Cortex®-M7 32-bit MCU Datasheet GD32H757xx Datasheet Table of Contents Table of Contents ........................................................................................................... 1 List of Figures ................................................................................................................ 5 List of Tables .................................................................................................................. 6 1. General description ................................................................................................. 9 2. Device overview ..................................................................................................... 10 2.1. Device information ................................................................................................. 10 2.2. Block diagram ........................................................................................................ 12 2.3. Pinouts and pin assignment .................................................................................. 13 2.4. Memory map ........................................................................................................... 15 2.5. Clock tree................................................................................................................ 24 2.6. Pin definitions ........................................................................................................ 25 2.6.1. GD32H757Zx LQFP144 pin definitions ................................................................................ 25 2.6.2. GD32H757Vx LQFP100 pin definitions ................................................................................ 36 2.6.3. GD32H757Vx BGA100 pin definitions .................................................................................. 44 2.6.4. GD32H757xx pin alternate functions .................................................................................... 53 3. Functional description .......................................................................................... 61 3.1. Arm® Cortex®-M7 core ............................................................................................ 61 3.2. On-chip memory ..................................................................................................... 62 3.3. Clock, reset and supply management .................................................................. 62 3.4. Boot modes ............................................................................................................ 63 3.5. Power saving modes.............................................................................................. 64 3.6. Electronic fuse (EFUSE) ........................................................................................ 64 3.7. Trigger selection controller (TRIGSEL) ................................................................ 64 3.8. General-purpose and alternate-function I/Os (GPIO and AFIO) .......................... 65 3.9. CRC calculation unit (CRC) ................................................................................... 65 3.10. True random number generator (TRNG) ............................................................... 65 3.11. Cryptographic Acceleration Unit (CAU) ................................................................ 66 3.12. Hash Acceleration Unit (HAU) ............................................................................... 66 3.13. Trigonometric Math Unit (TMU) ............................................................................. 67 3.14. Direct memory access controller (DMA) ............................................................... 67 1 GD32H757xx Datasheet 3.15. Master direct memory access controller (MDMA) ................................................ 67 3.16. DMA request multiplexer (DMAMUX) .................................................................... 68 3.17. Analog to digital converter (ADC) ......................................................................... 68 3.18. Digital to analog converter (DAC) ......................................................................... 69 3.19. Real time clock (RTC) and backup registers ........................................................ 69 3.20. Timers and PWM generation ................................................................................. 70 3.21. Universal synchronous/asynchronous receiver transmitter (USART/UART) .... 71 3.22. Inter-integrated circuit (I2C) .................................................................................. 72 3.23. Serial peripheral interface (SPI) ............................................................................ 72 3.24. Inter-IC sound (I2S) ................................................................................................ 73 3.25. OSPI I/O manager(OSPIM) ..................................................................................... 73 3.26. Octal-SPI interface(OSPI)....................................................................................... 73 3.27. Clock phase delay module (CPDM) ....................................................................... 73 3.28. Digital camera interface (DCI)................................................................................ 74 3.29. TFT LCD interface (TLI) .......................................................................................... 74 3.30. Receiver of Sony/Philips Digtial Interface (RSPDIF) ............................................ 74 3.31. Serial Audio Interface (SAI) ................................................................................... 75 3.32. Image processing accelerator (IPA) ...................................................................... 75 3.33. Secure digital input and output card interface (SDIO) ......................................... 76 3.34. Management data input/output (MDIO) ................................................................. 76 3.35. External memory controller (EXMC) ..................................................................... 76 3.36. VREF ....................................................................................................................... 77 3.37. Low power digital temperature sensor (LPDTS) .................................................. 77 3.38. Encoder Divided-Output controller (EDOUT) ....................................................... 77 3.39. Controller area network (CAN) .............................................................................. 77 3.40. Ethernet (ENET) ...................................................................................................... 78 3.41. Comparator (CMP).................................................................................................. 78 3.42. High-Performance Digital Filter (HPDF) ................................................................ 79 3.43. Real-time decryption (RTDEC) .............................................................................. 79 3.44. Filter arithmetic accelerator (FAC) ........................................................................ 80 3.45. Hardware semaphore (HWSEM) ............................................................................ 81 3.46. Universal serial bus high-speed interface (USBHS) ............................................ 81 2 GD32H757xx Datasheet 3.47. Debug mode ........................................................................................................... 81 3.48. Package and operation temperature ..................................................................... 81 4. Electrical characteristics ....................................................................................... 83 4.1. Absolute maximum ratings ................................................................................... 83 4.2. Recommended DC characteristics ....................................................................... 84 4.3. Power consumption ............................................................................................... 86 4.4. EMC characteristics ............................................................................................... 89 4.5. Power supply supervisor characteristics ............................................................. 91 4.6. Embedded USB regulator characteristics ............................................................ 92 4.7. External clock characteristics ............................................................................... 92 4.8. Internal clock characteristics ................................................................................ 96 4.9. PLL characteristics ................................................................................................ 97 4.10. Memory characteristics ......................................................................................... 99 4.11. NRST pin characteristics ....................................................................................... 99 4.12. GPIO characteristics ............................................................................................ 100 4.13. 14-bit ADC characteristics ................................................................................... 103 4.14. 12-bit ADC characteristics ................................................................................... 106 4.15. High-precision temperature sensor characteristics ...........................................110 4.16. Temperature sensor characteristics .................................................................... 111 4.17. Low power digital temperature sensor characteristics ...................................... 111 4.18. Voltage reference buffer characteristics .............................................................112 4.19. CMP characteristics ..............................................................................................113 4.20. Temperature and VBAT monitoring .....................................................................114 4.21. DAC characteristics ..............................................................................................114 4.22. I2C characteristics ................................................................................................117 4.23. SPI characteristics ................................................................................................118 4.24. OSPI characteristics .............................................................................................119 4.25. CPDM characteristics .......................................................................................... 121 4.26. HPDF characteristics ........................................................................................... 121 4.27. SAI characteristics ............................................................................................... 122 4.28. I2S characteristics................................................................................................ 123 4.29. USART characteristics ......................................................................................... 124 3 GD32H757xx Datasheet 4.30. SDIO characteristics ............................................................................................ 125 4.31. CAN characteristics ............................................................................................. 125 4.32. USBHS characteristics ........................................................................................ 126 4.33. EXMC characteristics........................................................................................... 127 4.34. TIMER characteristics .......................................................................................... 131 4.35. DCI characteristics ............................................................................................... 132 4.36. WDGT characteristics .......................................................................................... 133 5. Package information............................................................................................ 134 5.1. LQFP144 package outline dimensions ............................................................... 134 5.2. BGA100 package outline dimensions ................................................................. 136 5.3. LQFP100 package outline dimensions ............................................................... 138 5.4. Thermal characteristics ....................................................................................... 140 6. Ordering information ........................................................................................... 142 7. Revision history ................................................................................................... 143 4 GD32H757xx Datasheet List of Figures Figure 2-1. GD32H757xx block diagram .................................................................................................. 12 Figure 2-2. GD32H757Vx BGA100 pinouts .............................................................................................. 13 Figure 2-3. GD32H757Zx LQFP144 pinouts ............................................................................................ 14 Figure 2-4. GD32H757Vx LQFP100 pinouts ............................................................................................ 15 Figure 2-5. GD32H757xx clock tree.......................................................................................................... 24 Figure 4-1. Recommended power supply decoupling capacitors (1)(2)(3) ............................................... 85 Figure 4-2. Recommended external OSCIN and OSCOUT pins circuit for crystal ............................. 95 Figure 4-3. Recommended external OSCIN and OSCOUT pins circuit for oscillator ......................... 95 Figure 4-4. Recommended external NRST pin circuit.......................................................................... 100 Figure 4-5. I2C bus timing diagram......................................................................................................... 118 Figure 4-6. SPI timing diagram - master mode ...................................................................................... 119 Figure 4-7. SPI timing diagram - slave mode ......................................................................................... 119 Figure 4-8. OSPI timing diagram - SDR mode ...................................................................................... 121 Figure 4-9. OSPI timing diagram - DTR mode ....................................................................................... 121 Figure 4-10. I2S timing diagram - master mode ................................................................................... 124 Figure 4-11. I2S timing diagram - slave mode ...................................................................................... 124 Figure 4-12. USBFS timings: definition of data signal rise and fall time ........................................... 127 Figure 5-1. LQFP144 package outline ................................................................................................... 134 Figure 5-2. LQFP144 recommended footprint ...................................................................................... 135 Figure 5-3. BGA100 package outline ..................................................................................................... 136 Figure 5-4. BGA100 recommended footprint ........................................................................................ 137 Figure 5-5. LQFP100 package outline ................................................................................................... 138 Figure 5-6. LQFP100 recommended footprint ...................................................................................... 139 5 GD32H757xx Datasheet List of Tables Table 2-1. GD32H757xx devices features and peripheral list ............................................................... 10 Table 2-2. GD32H757xx memory map ..................................................................................................... 15 Table 2-3. GD32H757Zx LQFP144 pin definitions .................................................................................. 25 Table 2-4. GD32H757Vx LQFP100 pin definitions .................................................................................. 36 Table 2-5. GD32H757Vx BGA100 pin definitions .................................................................................... 44 Table 2-6. Port A alternate functions summary ...................................................................................... 53 Table 2-7. Port B alternate functions summary ...................................................................................... 54 Table 2-8. Port C alternate functions summary ...................................................................................... 55 Table 2-9. Port D alternate functions summary ...................................................................................... 56 Table 2-10. Port E alternate functions summary .................................................................................... 57 Table 2-11. Port F alternate functions summary .................................................................................... 58 Table 2-12. Port G alternate functions summary .................................................................................... 59 Table 2-13. Port H alternate functions summary .................................................................................... 59 Table 4-1. Abbreviations ........................................................................................................................... 83 Table 4-2. Absolute maximum ratings(1)(4) ............................................................................................... 84 Table 4-3. DC operating conditions ......................................................................................................... 84 Table 4-4. Vcore operating conditions(1)(2)(3) ............................................................................................ 85 Table 4-5. Clock frequency (1)(2) ................................................................................................................ 85 Table 4-6. TCM interface frequency (1) ..................................................................................................... 86 Table 4-7. Operating conditions at Power up / Power down Table 4-8. Power consumption characteristics (1)(2)(3)(4) Table 4-9. System level ESD and EFT characteristics Table 4-10. EMI characteristics (1) (1) ............................................................. 86 .......................................................................... 86 (1) ....................................................................... 89 ............................................................................................................ 90 Table 4-11. Component level ESD characteristics (1) ............................................................................. 90 Table 4-12. Latch-up characteristics (1) ................................................................................................... 90 Table 4-13. Power supply supervisor characteristics............................................................................ 91 Table 4-14. USB regulator characteristics .............................................................................................. 92 Table 4-15. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics (4) ..................................................................................................................................................................... 92 Table 4-16. High speed external clock characteristics (HXTAL in bypass mode) .............................. 93 Table 4-17. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics (5) ..................................................................................................................................................................... 93 Table 4-18. Low speed external user clock characteristics (LXTAL in bypass mode) ....................... 94 Table 4-19. High speed internal clock (IRC48M) characteristics .......................................................... 96 Table 4-20. High speed internal clock (IRC64M) characteristics .......................................................... 96 Table 4-21. Low power internal clock (LPIRC4M) characteristics ........................................................ 97 Table 4-22. Low speed internal clock (IRC32K) characteristics ........................................................... 97 Table 4-23. PLL0/1/2 characteristics (wide VCO frequency range) ...................................................... 97 Table 4-24. PLL0/1/2 characteristics (narrow VCO frequency range) .................................................. 98 Table 4-25. PLLUSBHS0/1 characteristics(3) ........................................................................................... 98 6 GD32H757xx Datasheet Table 4-26. Flash memory characteristics .............................................................................................. 99 Table 4-27. NRST pin characteristics ...................................................................................................... 99 Table 4-28. I/O static characteristics ..................................................................................................... 100 Table 4-29. Output voltage characteristics for all I/Os except PC13, PC14, PC15 (1)(2) ...................... 100 Table 4-30. Output timing characteristics (IOSPDOP OFF) (3)(4) ........................................................... 101 Table 4-31. Output timing characteristics (IOSPDOP ON)(3)(4) ............................................................. 102 Table 4-32. 14-bit ADC characteristics .................................................................................................. 103 Table 4-33. ADC RAIN max for fADC = 72 MHz (14-bit ADC) Table 4-34. 14-bit ADC accuracy (1) (1)(2) ............................................................. 105 ........................................................................................................ 105 Table 4-35. 12-bit ADC characteristics .................................................................................................. 106 Table 4-36. ADC RAIN max for fADC = 80 MHz (12-bit ADC) (1)(2) ............................................................. 109 Table 4-37. 12-bit ADC accuracy(1) .......................................................................................................... 110 Table 4-38. High-precision temperature sensor characteristics ......................................................... 110 Table 4-39. High-precision temperature sensor calibration values .................................................... 111 Table 4-40. Temperature sensor characteristics(1) ................................................................................ 111 Table 4-41. Temperature sensor calibration values .............................................................................. 111 Table 4-42. Low power digital temperature sensor characteristics .................................................... 111 Table 4-43. Voltage reference buffer characteristics(1) ......................................................................... 112 Table 4-44. CMP characteristics(1) ........................................................................................................... 113 Table 4-45. VBAT monitoring characteristics(1) ..................................................................................... 114 Table 4-46. VBAT charging characteristics .............................................................................................. 114 Table 4-47. Temperature monitoring characteristics ............................................................................ 114 Table 4-48. DAC characteristics(1) ........................................................................................................... 114 Table 4-49. DAC accuracy(1) ..................................................................................................................... 116 Table 4-50. I2C characteristics(1)(2) .......................................................................................................... 117 Table 4-51. Standard SPI characteristics (1) Table 4-52. Standard OSPI characteristics ........................................................................................... 118 (1) ........................................................................................ 119 Table 4-53. CPDM characteristics .......................................................................................................... 121 Table 4-54. HPDF characteristics(1) (2) .................................................................................................... 121 Table 4-55. SAI characteristics(1) ............................................................................................................ 122 Table 4-56. I2S characteristics(1) (2) ......................................................................................................... 123 Table 4-57. USART characteristics in Synchronous mode (1) ............................................................. 124 Table 4-58. USART characteristics in Smartcard mode (1) ................................................................... 125 Table 4-59. SDIO characteristics(1) (2) ..................................................................................................... 125 Table 4-60. USBHS DC electrical characteristics ................................................................................. 126 Table 4-61. USBHS dynamic characteristics(1) ..................................................................................... 126 Table 4-62. USBHS Charger Detection characteristics(1) ..................................................................... 127 Table 4-63. USBHS clock timing parameters(1) ..................................................................................... 127 Table 4-64. USB-ULPI Dynamic characteristics(1) ................................................................................ 127 Table 4-65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) .......................... 127 Table 4-66. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) ......................... 128 Table 4-67. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) ............................................. 128 Table 4-68. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) ............................................ 129 Table 4-69. Synchronous multiplexed PSRAM/NOR read timings(1)(2) ............................................... 129 7 GD32H757xx Datasheet Table 4-70. Synchronous multiplexed PSRAM write timings(1)(2) ........................................................ 129 Table 4-71. Synchronous non-multiplexed PSRAM/NOR read timings(1)(2)........................................ 130 Table 4-72. Synchronous non-multiplexed PSRAM write timings (1)(2) ............................................... 130 Table 4-73. SDRAM read timings ........................................................................................................... 131 Table 4-74. TIMER characteristics(1) ...................................................................................................... 131 Table 4-75. DCI characteristics(1) ........................................................................................................... 132 Table 4-76. FWDGT min/max timeout period at 32 kHz (IRC32K) (1) ................................................... 133 Table 4-77. WWDGT min-max timeout value at 50 MHz (fPCLK1) (1) ....................................................... 133 Table 5-1. LQFP144 package dimensions ............................................................................................. 134 Table 5-2. BGA100 package dimensions .............................................................................................. 136 Table 5-3. LQFP100 package dimensions ............................................................................................. 138 Table 5-4. Package thermal characteristics(1) ....................................................................................... 140 Table 6-1. Part ordering code for GD32H757xx devices ...................................................................... 142 Table 7-1. Revision history ..................................................................................................................... 143 8 GD32H757xx Datasheet 1. General description The GD32H757xx device belongs to the high performance line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the Arm® Cortex®-M7 core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Arm® Cortex®-M7 processor is a highly efficient highperformance, embedded processor that features low interrupt latency, low-cost debug, and has backwards compatibility with existing Cortex-M profile processors. The processor has an in-order super-scalar pipeline that means many instructions can be dual-issued, including load/load and load/store instruction pairs because of multiple memory interfaces. The CortexM7 is a high-performance processor, which features a 6-stage superscalar pipeline with branch prediction and an optional FPU capable of single-precision and optionally doubleprecision operations. The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32H757xx device incorporates the Arm® Cortex®-M7 32-bit processor core operating at 600 MHz frequency with Flash security protection to prevent illegal code/data access. It provides up to 3840 KB on-chip Flash memory, 512KB AXI SRAM and 512KB RAM shared (ITCM/DTCM/AXI) memory. An extensive range of enhanced I/Os and peripherals connected to four APB buses. The devices offer up to two 14-bit 4 MSPS ADCs, a 12 bit 5.3 MSPS ADC, a 12-bit DAC, up to twelve general 16-bit timers, two 16-bit PWM advanced timers, four 32bit general timers, and four 16-bit basic timers, as well as standard and advanced communication interfaces: up to six SPIs, two OSPIs, four I2Cs, four USARTs and four UARTs, four I2Ss, three CANs, a USBHS, a ENET, two SDIOs and a MDIO. Additional peripherals as digital camera interface (DCI), EXMC interface with SDRAM extension support, TFT-LCD Interface (TLI), Image Processing Accelerator (IPA), Serial Audio Interface (SAI) and high performance digital filter module (HPDF) are included. The device operates from a 1.71V to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32H757xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, audio player, automotive navigation, drone, IoT and so on. 9 GD32H757xx Datasheet 2. Device overview 2.1. Device information Table 2-1. GD32H757xx devices features and peripheral list GD32H757 Part Number VGT6 VIT6 VMT6 VGJ6 VIJ6 VMJ6 ZGT6 ZIT6 ZMT6 FLASH (KB) 1024 2048 3840 1024 2048 3840 1024 2048 3840 SRAM (KB) 1024 1024 1024 1024 1024 1024 1024 1024 1024 10 10 10 10 10 10 General timer Timers (16-bit) 12 12 (2-3,14-16,30- (2-3,14-16,30- 31,40-44) 31,40-44) 31,40-44) (2-3,14-16,40-44) (2-3,14-16,40-44) (2-3,14-16,40-44) (2-3,14-16,40-44) (2-3,14-16,40-44) (2-3,14-16,40-44) General timer 4 4 4 4 4 4 4 4 4 (32-bit) (1,4,22-23) (1,4,22-23) (1,4,22-23) (1,4,22-23) (1,4,22-23) (1,4,22-23) (1,4,22-23) (1,4,22-23) (1,4,22-23) Advanced 2 2 2 2 2 2 2 2 2 timer(16-bit) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) Basic timer 2 2 2 2 2 2 2 2 2 (32-bit) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) Basic timer 2 2 2 2 2 2 2 2 2 (64-bit) (50,51) (50,51) (50,51) (50,51) (50,51) (50,51) (50,51) (50,51) (50,51) SysTick 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 USART 4 4 4 4 4 4 4 4 4 UART 4 4 4 4 4 4 4 4 4 I2C 4 4 4 4 4 4 4 4 4 5/4 5/4 5/4 5/4 5/4 5/4 6/4 6/4 6/4 (0-3,5)/(0-2,5) (0-3,5)/(0-2,5) (0-3,5)/(0-2,5) (0-3,5)/(0-2,5) (0-3,5)/(0-2,5) (0-3,5)/(0-2,5) (0-5)/(0-2,5) (0-5)/(0-2,5) (0-5)/(0-2,5) SDIO 2 2 2 2 2 2 2 2 2 SAI 2 2 2 2 2 2 3 3 3 CAN 3xFD 3xFD 3xFD 3xFD 3xFD 3xFD 3xFD 3xFD 3xFD USBHS 1 1 1 1 1 1 1 1 1 ENET 1 1 1 1 1 1 1 1 1 TLI 1 1 1 1 1 1 1 1 1 82 82 82 82 82 82 113 113 113 SPI/I2S Connectivity 12 (2-3,14-16,30- GPIO 10 GD32H757xx Datasheet GD32H757 Part Number EXMC/SDRAM Units 14bit ADC VGT6 VIT6 VMT6 VGJ6 VIJ6 VMJ6 ZGT6 ZIT6 ZMT6 1/0 1/0 1/0 1/0 1/0 1/0 1/1 1/1 1/1 2 2 2 2 2 2 2 2 2 14,12 14,12 14,12 14,12 14,12 16,14 16,14 16,14 Channels 14,12 12bit Units 1 1 1 1 1 1 1 1 1 ADC Channels 4 4 4 4 4 4 12 12 12 DAC 1 1 1 1 1 1 1 1 1 CMP 1 1 1 1 1 1 1 1 1 Package LQFP100 BGA100 LQFP144 11 GD32H757xx Datasheet 2.2. Block diagram Figure 2-1. GD32H757xx block diagram Powered By LDO (0.9V) TPIU SW/JTA G MPU I-Cache 32KB AHBP D-Cache 32KB DTCM RAM ITCM RAM ARM Cortex-M7 Processor Fmax: 600MHz RAM share d AXI SRAM AXIM AXI bus (64-bit) TLI MDMA IPA SDIO0 Flash Memory Powered By V DD FMC RTDEC0 OSP I0 RTDEC1 OSP I1 EXMC M DMA0 P M DMA1 P ENET0 USB PHY Powered By VDD33USB SDIO1 EFUSE USBHS0 AHB Interconnect Matrix (Fmax=300MHz) GPV PLLs IRC64M LPIRC4M SRAM0 SRAM1 HWSEM CRC GPIO RCU AHB4 Per ipheral s Powered By EFUSE 1.8V EFUSE WWDG T APB3 LVD TRNG DMAMUX CAU TMU AHB1 Per ipheral s (Fmax=150MHz) HAU FAC CPDM DCI AHB2 Per ipheral s AHB3 AHB Interconnect Matrix (Fmax=300MHz) TIMER51 CTC TIMER43 TIMER50 TIMER23 PMU TIMER42 TIMER31 TIMER22 FWDG T TIMER41 TIMER30 I2C2 TIMER40 MDIO CAN2 UART7 CAN1 UART6 CAN0 RSPDIF EDOUT I2C3 LPDTS LXTAL RTC IRC32K Backup RAM Powered By V B AT POR/PDR SAI0 SPI4 TIMER16 APB1 (Fmax=150MHz) SAI1 APB2 (Fmax=300MHz) SAI2 VREF CMP0 CMP1 SYS CFG EXTI RTC I2C1 TRIGS EL HPDF APB4 (Fmax=150MHz) TIMER44 I2C0 HXTAL FWDG T UART4 LDO PMU UART3 Powered By V DD USART2 USART1 DAC TIMER15 SPI2/I2S2 TIMER14 SPI1/I2S1 SPI5/I2S5 TIMER6 SPI3 TIMER5 SPI0/I2S0 TIMER4 USART5 TIMER3 USART0 TIMER2 TIMER7 TIMER1 TIMER0 ADC0~2 DAC VREF SAR ADC Powered By V DDA CMP0 CMP1 12 GD32H757xx Datasheet 2.3. Pinouts and pin assignment Figure 2-2. GD32H757Vx BGA100 pinouts 1 2 3 4 5 6 7 8 9 10 A PC14 PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15 VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 S0_DP C PH0 VSS PE4 PE1 PB5 PD6 PD3 PC12 PA9 USBH S0_DM D PH1 VDD PE5 PE0 BOOT PD7 PD4 PD0 PA8 PA10 NRST PC2_C PE6 VSS VSS VSS VCORE PD1 PC9 PC7 VDD33 USB PDR_ON VCORE PC8 PC6 E USBH F PC0 PC1 PC3_C VDD VDD G VSSA PA0 PA4 PC4 PB2 PE10 PE14 PD15 PD11 PB15 H VDDA PA1 PA5 PC5 PE7 PE11 J VSS PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDD PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 PE15 PD14 PD10 PB14 GigaDevice GD32H757Vx BGA100 13 GD32H757xx Datasheet Figure 2-3. GD32H757Zx LQFP144 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS VDD PD6 PD7 PG9 PG10 PG11 PG12 PG13 VSS PG14 VDD PG15 PB4 PB3 PB5 PB6 PB7 BOOT PB8 PB9 PE0 PE1 VDD PDR_ON 144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109 PE2 1 108 VDD PE3 PE4 2 107 VSS 3 106 VCORE PE5 PE6 4 105 PA13 5 104 USBHS0_DP VBAT 6 103 USBHS0_DM PC13 7 102 PA10 PC14-OSC32IN 8 101 PA9 PC15-OSC32OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 98 PC8 PF2 12 97 PF3 PF4 13 96 PC6 14 95 VDD33USB PF5 15 94 VSS VSS 16 93 PG8 92 PG7 91 PG6 VDD 17 PF6 18 PF7 19 PF8 20 PF9 21 GigaDevice GD32H757Zx LQFP144 90 PC7 PG5 89 PG4 88 PG3 PF10 22 87 PG2 PH0-OSCIN 23 86 PD15 PH1-OSCOUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2_C 28 81 PD12 PC3_C 29 80 PD11 VDD 30 79 PD10 VSSA VREFP 31 78 PD9 32 77 PD8 VDDA 33 76 PB15 PA0 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD VCORE PB11 PB10 PE15 PE13 PE14 PE12 PE11 VDD PE10 VSS PE8 PE9 PE7 PG1 PG0 PF15 PF14 VDD PF13 VSS PF12 PF11 PB1 PB2 PC5 PB0 PA7 PC4 PA6 PA5 VDD PA4 VSS PA3 14 GD32H757xx Datasheet Figure 2-4. GD32H757Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB4 PB3 PB5 PB6 PB7 BOOT PB8 PB9 PE0 PE1 VSS VDD PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS 3 73 VCORE PE5 PE6 4 72 PA13 5 71 USBHS0_DP VDD VBAT 6 7 70 69 USBHS0_DM PC13 PC14-OSC32IN 8 68 PA9 PC15-OSC32OUT 9 67 PA8 VSS 10 66 PC9 65 PC8 64 PC7 63 PC6 PA10 VDD 11 PH0-OSCIN 12 PH1-OSCOUT 13 NRST PC0 14 62 PD15 15 61 PD14 PC1 16 60 PD13 PC2_C 17 59 PD12 PC3_C 18 58 PD11 VSSA 19 57 PD10 VREFP VDDA 20 56 PD9 21 55 PD8 PA0 22 54 PB15 PA1 23 53 PB14 PA2 24 52 PB13 PA3 25 51 PB12 GigaDevice GD32H757Vx LQFP100 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD VSS VCORE PB11 PB10 PE15 PE14 PE12 PE13 PE10 PE11 PE9 PE8 PB2 PE7 PB0 PB1 PC5 PA7 PC4 PA6 PA4 PA5 VDD VSS 2.4. Memory map Table 2-2. GD32H757xx memory map Pre-defined Regions Bus Address Peripherals 0xD000 0000 - 0xDFFF FFFF EXMC - SDRAM device 1 0xC000 0000 - 0xCFFF FFFF External RAM Peripheral AHB4 EXMC - SDRAM device 0 (EXMC Bank 0 Region 0-3) 0xA000 1000 - 0xBFFF FFFF Reserved 0xA000 0000 - 0xA000 0FFF Reserved 0x9000 0000 - 0x9FFF FFFF OSPI0 0x8000 0000 - 0x8FFF FFFF EXMC - NAND 0x7000 0000 - 0x7FFF FFFF OSPI1 0x6000 0000 - 0x6FFF FFFF EXMC - NOR/PSRAM/SRAM 0x5802 7000 - 0x5FFF FFFF Reserved 0x5802 6400 - 0x5802 67FF HWSEM 0x5802 6000 - 0x5802 63FF Reserved 0x5802 5000 - 0x5802 5FFF Reserved 0x5802 4C00 - 0x5802 4FFF CRC 0x5802 4800 - 0x5802 4BFF Reserved 0x5802 4400 - 0x5802 47FF RCU 15 GD32H757xx Datasheet Pre-defined Regions Bus APB4 AHB3 Address Peripherals 0x5802 2C00 - 0x5802 43FF Reserved 0x5802 2800 - 0x5802 2BFF GPIOK 0x5802 2400 - 0x5802 27FF GPIOJ 0x5802 2000 - 0x5802 23FF Reserved 0x5802 1C00 - 0x5802 1FFF GPIOH 0x5802 1800 - 0x5802 1BFF GPIOG 0x5802 1400 - 0x5802 17FF GPIOF 0x5802 1000 - 0x5802 13FF GPIOE 0x5802 0C00 - 0x5802 0FFF GPIOD 0x5802 0800 - 0x5802 0BFF GPIOC 0x5802 0400 - 0x5802 07FF GPIOB 0x5802 0000 - 0x5802 03FF GPIOA 0x5801 0000 - 0x5801 FFFF Reserved 0x5800 7400 - 0x5800 FFFF Reserved 0x5800 7000 - 0x5800 73FF Reserved 0x5800 6C00 - 0x5800 6FFF Reserved 0x5800 6800 - 0x5800 6BFF LPDTS 0x5800 5800 - 0x5800 67FF PMU 0x5800 5400 - 0x5800 57FF Reserved 0x5800 4C00 - 0x5800 53FF Reserved 0x5800 4800 - 0x5800 4BFF FWDGT 0x5800 4000 - 0x5800 43FF RTC 0x5800 3C00 - 0x5800 3FFF VREF 0x5800 3800 - 0x5800 3BFF CMP0 - CMP1 0x5800 3400 - 0x5800 37FF Reserved 0x5800 3000 - 0x5800 33FF Reserved 0x5800 2C00 - 0x5800 2FFF Reserved 0x5800 2800 - 0x5800 2BFF Reserved 0x5800 2400 - 0x5800 27FF Reserved 0x5800 2000 - 0x5800 23FF Reserved 0x5800 1C00 - 0x5800 1FFF Reserved 0x5800 1400 - 0x5800 17FF Reserved 0x5800 0800 - 0x5800 13FF Reserved 0x5800 0400 - 0x5800 07FF SYSCFG 0x5800 0000 - 0x5800 03FF EXTI 0x5200 C000 - 0x57FF FFFF Reserved 0x5200 BC00 - 0x5200 BFFF RTDEC1 0x5200 B800 - 0x5200 BBFF RTDEC0 0x5200 B400 - 0x5200 B7FF OSPIM 0x5200 B000 - 0x5200 B3FF Reserved 16 GD32H757xx Datasheet Pre-defined Regions Bus APB3 AHB2 Address Peripherals 0x5200 A000 - 0x5200 AFFF OSPI1 0x5200 9400 - 0x5200 9FFF Reserved 0x5200 9000 - 0x5200 93FF RAMECCMU Region 0 0x5200 8000 - 0x5200 8FFF CPDM(SDIO0) 0x5200 7000 - 0x5200 7FFF SDIO0 0x5200 6000 - 0x5200 6FFF Reserved 0x5200 5000 - 0x5200 5FFF OSPI0 0x5200 4000 - 0x5200 4FFF EXMC 0x5200 3400 - 0x5200 3FFF Reserved 0x5200 3000 - 0x5200 33FF Reserved 0x5200 2000 - 0x5200 2FFF Flash memory interface 0x5200 1000 - 0x5200 1FFF IPA 0x5200 0000 - 0x5200 0FFF MDMA 0x5110 0000 - 0x51FF FFFF Reserved 0x5100 0000 - 0x510F FFFF AXI interconnect matrix 0x5006 1000 - 0x50FF FFFF Reserved 0x5006 0C00 - 0x5006 0FFF Reserved 0x5006 0800 - 0x5006 0BFF Reserved 0x5006 0400 - 0x5006 07FF Reserved 0x5006 0000 - 0x5006 03FF Reserved 0x5005 0400 - 0x5005 FFFF Reserved 0x5005 0000 - 0x5005 03FF Reserved 0x5004 0000 - 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF Reserved 0x5000 3000 - 0x5000 3FFF WWDGT 0x5000 2000 - 0x5000 2FFF Reserved 0x5000 1000 - 0x5000 1FFF TLI 0x5000 0000 - 0x5000 0FFF Reserved 0x4802 5000 - 0x4FFF FFFF Reserved(AHB2) 0x4802 4800 - 0x4802 4FFF FAC 0x4802 4400 - 0x4802 47FF TMU 0x4802 4000 - 0x4802 43FF Reserved 0x4802 3000 - 0x4802 3FFF RAMECCMU Region 1 0x4802 2C00 - 0x4802 2FFF Reserved(AHB2) 0x4802 2800 - 0x4802 2BFF CPDM(SDIO1) 0x4802 2400 - 0x4802 27FF SDIO1 0x4802 1C00 - 0x4802 23FF Reserved(AHB2) 0x4802 1800 - 0x4802 1BFF TRNG 0x4802 1400 - 0x4802 17FF HAU 0x4802 1000 - 0x4802 13FF CAU 17 GD32H757xx Datasheet Pre-defined Regions Bus AHB1 Address Peripherals 0x4802 0400 - 0x4802 0FFF Reserved(AHB2) 0x4802 0000 - 0x4802 03FF DCI 0x4800 1800 - 0x4801 FFFF Reserved(AHB2) 0x4800 1400 - 0x4800 17FF Reserved 0x4800 1000 - 0x4800 13FF Reserved 0x4800 0C00 - 0x4800 0FFF Reserved 0x4800 0800 - 0x4800 0BFF Reserved 0x4800 0400 - 0x4800 07FF Reserved 0x4800 0000 - 0x4800 03FF Reserved 0x400C 0000 - 0x47FF FFFF Reserved(AHB1) 0x4008 0000 - 0x400B FFFF Reserved 0x4004 0000 - 0x4007 FFFF USBHS0 0x4003 8C00 - 0x4003 FFFF Reserved 0x4003 8400 - 0x4003 8BFF Reserved 0x4003 8000 - 0x4003 83FF Reserved 0x4003 3000 - 0x4003 7FFF Reserved 0x4003 0000 - 0x4003 2FFF Reserved 0x4002 C000 - 0x4002 FFFF Reserved 0x4002 BC00 - 0x4002 BFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF ENET0 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF Reserved 0x4002 6000 - 0x4002 63FF Reserved 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Reserved 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF Reserved 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF EFUSE 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF Reserved 0x4002 1C00 - 0x4002 1FFF Reserved 0x4002 1800 - 0x4002 1BFF Reserved 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF Reserved 0x4002 0C00 - 0x4002 0FFF Reserved 18 GD32H757xx Datasheet Pre-defined Regions Bus APB2 Address Peripherals 0x4002 0800 - 0x4002 0BFF DMAMUX 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 F400 - 0x4001 FFFF Reserved 0x4001 F000 - 0x4001 F3FF TIMER44 0x4001 DC00 - 0x4001 DFFF TIMER43 0x4001 D800 - 0x4001 DBFF TIMER42 0x4001 D400 - 0x4001 D7FF TIMER41 0x4001 D000 - 0x4001 D3FF TIMER40 0x4001 C000 - 0x4001 CFFF CAN2(4KB) 0x4001 B000 - 0x4001 BFFF CAN1(4KB) 0x4001 A000 - 0x4001 AFFF CAN0(4KB) 0x4001 8C00 - 0x4001 9FFF Reserved 0x4001 8800 - 0x4001 8BFF EDOUT 0x4001 8400 - 0x4001 87FF TRIGSEL 0x4001 8000 - 0x4001 83FF Reserved(APB2) 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF HPDF 0x4001 6C00 - 0x4001 6FFF Reserved 0x4001 6800 - 0x4001 6BFF Reserved 0x4001 6400 - 0x4001 67FF Reserved 0x4001 6000 - 0x4001 63FF SAI2 0x4001 5C00 - 0x4001 5FFF SAI1 0x4001 5800 - 0x4001 5BFF SAI0 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF SPI4 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIMER16 0x4001 4400 - 0x4001 47FF TIMER15 0x4001 4000 - 0x4001 43FF TIMER14 0x4001 3C00 - 0x4001 3FFF Reserved 0x4001 3800 - 0x4001 3BFF SPI5/I2S5 0x4001 3400 - 0x4001 37FF SPI3 0x4001 3000 - 0x4001 33FF SPI0/I2S0 0x4001 2C00 - 0x4001 2FFF ADC2 0x4001 2800 - 0x4001 2BFF ADC1 0x4001 2400 - 0x4001 27FF ADC0 0x4001 2000 - 0x4001 23FF Reserved 19 GD32H757xx Datasheet Pre-defined Regions Bus APB1 Address Peripherals 0x4001 1C00 - 0x4001 1FFF Reserved 0x4001 1800 - 0x4001 1BFF Reserved 0x4001 1400 - 0x4001 17FF USART5 0x4001 1000 - 0x4001 13FF USART0 0x4001 0C00 - 0x4001 0FFF Reserved 0x4001 0800 - 0x4001 0BFF Reserved 0x4001 0400 - 0x4001 07FF TIMER7 0x4001 0000 - 0x4001 03FF TIMER0 0x4000 F800 - 0x4000 FFFF Reserved 0x4000 F400 - 0x4000 F7FF TIMER51 0x4000 F000 - 0x4000 F3FF TIMER50 0x4000 EC00 - 0x4000 EFFF TIMER31 0x4000 E800 - 0x4000 EBFF TIMER30 0x4000 E400 - 0x4000 E7FF TIMER23 0x4000 E000 - 0x4000 E3FF TIMER22 0x4000 DC00 - 0x4000 DFFF Reserved 0x4000 D800 - 0x4000 DBFF Reserved 0x4000 D400 - 0x4000 D7FF Reserved 0x4000 D000 - 0x4000 D3FF Reserved 0x4000 CC00 - 0x4000 CFFF Reserved 0x4000 C800 - 0x4000 CBFF Reserved 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF I2C2 0x4000 9800 - 0x4000 BFFF Reserved 0x4000 9400 - 0x4000 97FF MDIO 0x4000 8800 - 0x4000 93FF Reserved 0x4000 8400 - 0x4000 87FF CTC 0x4000 8000 - 0x4000 83FF Reserved 0x4000 7C00 - 0x4000 7FFF UART7 0x4000 7800 - 0x4000 7BFF UART6 0x4000 7400 - 0x4000 77FF DAC0/DAC1 0x4000 7000 - 0x4000 73FF Reserved 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF Reserved 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF UART4 20 GD32H757xx Datasheet Pre-defined Regions Bus Address Peripherals 0x4000 4C00 - 0x4000 4FFF UART3 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF RSPDIF 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF Reserved 0x4000 2C00 - 0x4000 2FFF Reserved 0x4000 2800 - 0x4000 2BFF Reserved 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF Reserved 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF Reserved 0x4000 1400 - 0x4000 17FF TIMER6 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x3880 1000 - 0x3FFF FFFF Reserved 0x3880 0000 - 0x3880 0FFF Backup SRAM 0x3000 8000 - 0x387F FFFF Reserved 0x3000 4000 - 0x3000 7FFF SRAM1(16KB) 0x3000 0000 - 0x3000 3FFF SRAM0(16KB) 0x2410 0000 - 0x2FFF FFFF Reserved 0x2408 0000 - 0x240F FFFF SRAM RAM(512KB) shared (ITCM/DTCM/AXI) 0x2400 0000 - 0x2407 FFFF AXI SRAM(512KB) 0x2008 0000 - 0x23FF FFFF Reserved 0x2007 0000 - 0x2007 FFFF 0x2006 0000 - 0x2006 FFFF 0x2003 0000 - 0x2005 FFFF 0x2002 0000 - 0x2002 FFFF 0x2001 C000 - 0x2001 FFFF 0x2001 8000 - 0x2001 BFFF DTCM RAM(from RAM shared) 0x2001 0000 - 0x2001 7FFF 0x2000 D000 - 0x2000 FFFF 0x2000 C000 - 0x2000 CFFF 0x2000 8000 - 0x2000 BFFF 21 GD32H757xx Datasheet Pre-defined Regions Bus Address Peripherals 0x2000 5000 - 0x2000 7FFF 0x2000 2000 - 0x2000 4FFF 0x2000 1000 - 0x2000 1FFF 0x2000 0000 - 0x2000 0FFF Code 0x1FFF FC10 - 0x1FFF FFFF Reserved 0x1FFF FC00 - 0x1FFF FC0F Reserved 0x1FFF F818 - 0x1FFF BFFF Reserved 0x1FFF F800 - 0x1FFF F817 Reserved 0x1FFF F000 - 0x1FFF F7FF Reserved 0x1FFF EC00 - 0x1FFF EFFF Reserved 0x1FFF C010 - 0x1FFF EBFF Reserved 0x1FFF C000 - 0x1FFF C00F Reserved 0x1FFF B000 - 0x1FFF BFFF Reserved 0x1FFF 8000 - 0x1FFF AFFF Reserved 0x1FFF 7A10 - 0x1FFF 7FFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 7400 - 0x1FFF 77FF Reserved 0x1FFF 7000 - 0x1FFF 73FF Reserved 0x1FFF 0000 - 0x1FFF 6FFF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Reserved 0x1FF6 0000 - 0x1FFE BFFF Reserved 0x1FF4 0000 - 0x1FF5 FFFF Reserved 0x1FFF 9000 - 0x1FF3 FFFF Reserved 0x1FF0 0000 - 0x1FFF 8FFF System Memory 0x1002 0000 - 0x1FEF FFFF Reserved 0x1001 0000 - 0x1001 FFFF Reserved 0x1000 0000 - 0x1000 FFFF Reserved 0x0A00 D000 - 0x0FFF FFFF Reserved 0x0A00 C000 - 0x0A00 CFFF Reserved 0x0A00 8000 - 0x0A00 BFFF Reserved 0x0A00 0000 - 0x0A00 7FFF Reserved 0x08C0 1000 - 0x09FF FFFF Reserved 0x08C0 0000 - 0x08C0 0FFF Reserved 0x0881 0000 - 0x08BF FFFF Reserved 0x0880 0000 - 0x0880 FFFF Reserved 0x0840 0000 - 0x087F FFFF Reserved 0x083C 0000 - 0x083F FFFF Reserved 0x0830 0000 - 0x083B FFFF 0x0810 0000 - 0x082F FFFF Flash memory 22 GD32H757xx Datasheet Pre-defined Regions Bus Address Peripherals 0x0808 0000 - 0x080F FFFF 0x0806 0000 - 0x0807 FFFF 0x0802 0000 - 0x0805 FFFF 0x0801 0000 - 0x0801 FFFF 0x0800 0000 - 0x0800 FFFF 0x0030 0000 - 0x07FF FFFF Reserved 0x0010 0000 - 0x002F FFFF Reserved 0x0008 0000 - 0x000F FFFF Reserved 0x0002 6000 - 0x0007 FFFF 0x0002 0000 - 0x0002 5FFF 0x0001 0000 - 0x0001 FFFF ITCM RAM(from RAM shared) 0x0000 0000 - 0x0000 FFFF 23 GD32H757xx Datasheet 2.5. Clock tree Figure 2-5. GD32H757xx clock tree RTCDIV[5:0] CK_HXTAL FCLK /2 to /63 (free running clock) 11 32.768 KHz LXTAL OSC CK_CST ÷2 CK_RTC 01 (to Cortex-M7 SysTick) (to RTC) 10 RTCSRC[1:0] 32 KHz IRC32K CK_FWDGT CK_DAC (to FWDGT) (to DAC) 300 MHz max ACLK AXI enable CK_OUT1 CK_SYS CK_PLL1R CK_HXTAL CK_PLL0P CK_LPIRC4M CK_IRC32K CK_PLL2R 000 001 010 011 100 101 110 CKOUT1DIV ÷1,2,3...15 to AXI peripherals 300 MHz max HCLK AHB enable to AHB bus, Cortex-M7, SRAM, DMA, peripherals CK_OSPI to OSPI Peripheral enable CKOUT1SEL[2:0] CK_OUT0 CK_IRC64MDIV CK_LXTAL CK_HXTAL CK_PLL0P CK_IRC48M CK_PER USBHS0 60M USBHS1 60M 000 001 010 011 100 101 110 111 CKOUT0DIV ÷1,2,3...15 CK_IRC64MDIV IRC64MDIV ÷1,2,4,8 CK_HXTAL CK_LPIRC4M CK_PLL0P TIMER0,7,14,15,1 6,40,41,42,43,44 (CK_APB2×1 ×2 or ×4) 01 AHB/AXI Prescaler ÷1,2...512 CK_SYS 600 MHz max 10 APB1 Prescaler ÷1,2,4,8,16 CK_AHB/AXI 300 MHz max APB2 Prescaler ÷1,2,4,8,16 11 PLLSEL[1:0] 01 CK_APB1 PCLK1 150 MHz max to APB1 peripherals Peripheral enable CK_APB2 to APB2 peripherals CK_APB3 PCLK3 150 MHz max to APB3 peripherals CK_APB4 PCLK4 150 MHz max to APB4 peripherals CK_LXTAL PLL0FRAN CK_PLL0P /P PCLK2 300 MHz max Peripheral enable 10 0 CK_LPDTS 1 to LPDTS REFSEL(1) CK_PLL0Q /Q xN CK_TIMERx to TIMER0,7,14,15,1 6,40,41,42,43,44 Peripheral enable APB4 Prescaler ÷1,2,4,8,16 00 /PLL0PSC VCO 300 MHz max Peripheral enable APB3 Prescaler ÷1,2,4,8,16 4 MHz LPIRC4M CK_TIMERx to TIMER1,2,3,4,5,6, 22,23,30,31,50,51 TIMERx enable 00 Clock Monitor 4-50 MHz HXTAL 300 MHz max TIMERx enable SCS[1:0] CKOUT0SEL[2:0] 64 MHz IRC64M TIMER1,2,3,4,5,6,2 2,23,30,31,50,51 (CK_APB1×1 ×2 or ×4) CK_PLL0R /R PLL0 /PLL1PSC PLL1FRAN VCO CK_PLL1P /P CTC CK_PLL1Q /Q xN CK_PLL1R /R PLL1 I2S_CKIN /PLL2PSC PLL2FRAN VCO xN /Q CK_PLL2Q /R CK_PLL2R CK_CTC 48 MHz IRC48M PLL48MSEL CK_IRC48M 1 CK_PLL2P /P 0 CK_48M 0 Peripheral enable 1 PLL2RDIV ÷2,4,8,16 PLL2 to TLI 0 CK_PER(2) 01 CK_HXTAL 10 CK_ENETxTX 1 /2 or /20 Peripheral enable PERSEL[1:0] to ENETx TX ENETx_PHY_SEL 1 ENETx_RX_CLK 00 CK_LPIRC4M CK_TLI Peripheral enable ENETx_TX_CLK CK_IRC64MDIV to TRNG CK48MSEL CK_ENETxRX 0 Peripheral enable to ENETx RX EMBPHY_HS CK_IRC64MDIV 00 USB HS PHY clock 24Mhz to 60Mhz CK_USBHS_ULPI Peripheral enable PLLUSBHSxPRESEL PLLUSBHSxPREDV 0 Prescaler CK_IRC48M ÷1,2...15 1 CK_HXTAL x16,17... 127 USBHSxDV Prescaler ÷2,4...16 480 MHz max Prescaler ÷1,2...8 USBHSxPSC CK_USBHS 1 CK_PLL0R PLLUSBHSxMF CK_PLL1Q CK_HXTAL 0 to USBHS ULPI CK_PLLUSBHSx Peripheral enable to USBHSx CK_HXTAL 01 10 00 CK_PLL0R USBHSxSEL 11 01 0 10 CK_IRC48M USBHSx 60M(6) SCS[1:0] 1 11 USBHSx48MSEL[1:0] CK_APBx(x=1,2) 00 00 CK_APB1 CK_APB2 01 CK_APB2 / 2 10 CK_IRC64MDIV CK_TPIU (3) CK_LPIRC4M Peripheral enable CK_CAN to CANx CK_AHB CK_USART CANxSEL[1:0] Peripheral enable 10 CK_IRC64MDIV 11 00 01 CK_LXTAL CK_PLL2R 01 CK_I2C to USARTx CK_IRC64MDIV 11 CK_LPIRC4M 10 Peripheral enable to I2Cx 11 USARTxSEL[1:0] I2CxSEL[1:0] CK_PLL0Q CK_PLL0Q 000 CK_PLL1P 001 CK_PLL2P CK_SAI2B0 or CK_SAI2B1 010 I2S_CKIN 011 CK_PER Peripheral enable to SAI2_B0 or SAI2_B1 CK_SAI0 or CK_SAI1 001 CK_PLL2P 010 CK_PLL0Q 00 CK_PLL1R 01 to SAI0 or SAI1 I2S_CKIN CK_PER 100 CK_RSPDIF_SYMB 000 CK_PLL1P 011 Peripheral enable 100 CK_SAI0 CK_RSPDIF CK_PLL2R CK_HPDFAUDIO 10 CK_IRC64MDIV (4) 101 SAI0SEL[2:0] or SAI1SEL[2:0] CK_APB2 CK_AHB 00 CK_PLL0Q Peripheral enable RSPDIFSEL[1:0] ADCxSEL[1:0] 0 CK_PLL1P 00 CK_PLL2R 01 CK_PER 10 to HPDF CK_EXMC 10 Peripheral enable to EXMC CK_IRC64MDIV 0000 HCLK/2 CK_EFUSE Peripheral enable CK_PER to EFUSE SDIOxSEL CK_PLL0Q CK_PLL1R HCLK/4 1000 1001 HCLK/6 1010 HCLK/8 1011 HCLK/10 1100 HCLK/12 1101 11 EXMCSEL[1:0] ADCSCK(5)[3:0] CK_HPDF 1 Peripheral enable HPDFSEL 01 CK_PLL1R to RSPDIF to HPDFAUDIO SAI2B0SEL[2:0] or SAI2B1SEL[2:0] CK_AHB Peripheral enable 11 0 HCLK/14 CK_SDIO to SDIOx 1 HCLK/16 CK_ADCx to ADCx Peripheral enable 1110 1111 Peripheral enable CK_APB2 000 CK_APB2 CK_PLL0Q 000 CK_PLL1Q CK_PLL1P 001 CK_PLL2Q CK_PLL2P I2S_CKIN 010 Peripheral enable CK_SPIx to SPIx CK_IRC64MDIV CK_PLL1Q 001 CK_PLL2Q 010 CK_SPIx 011 011 CK_LPIRC4M CK_PER 000 Peripheral enable 100 100 CK_HXTAL 101 to SPIx 001 010 CK_IRC64MDIV CK_LPIRC4M CK_HXTAL I2S_CKIN CK_SPI5 011 Peripheral enable to SPI5 100 101 110 SPIxSEL[2:0](x=0,1,2) SPIxSEL[2:0](x=3,4) SPI5SEL[2:0] Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator 24 GD32H757xx Datasheet IRC16M: Internal 16M RC oscillators IRC32K: Internal 32K RC oscillator IRC48M: Internal 48M RC oscillators 2.6. Pin definitions 2.6.1. GD32H757Zx LQFP144 pin definitions Table 2-3. GD32H757Zx LQFP144 pin definitions Pin Name Pins Pin Type (1) I/O Functions description Level(2) Default: PE2 PE2 1 Alternate: TRACECK, SAI0_CLK0, SPI3_SCK, I/O SAI0_MCLK0, SAI2_MCLK0, OSPIM_P0_IO2, SAI2_CLK0, EXMC_A23, EVENTOUT Default: PE3 PE3 2 Alternate: TRACED0, TIMER14_BRKIN0, SAI0_SD1, I/O SAI2_SD1, EXMC_A19, DCI_PIXCLK, EVENTOUT Default: PE4 Alternate: TRACED1 , TIMER0_BRKIN1, SAI0_DAT1, PE4 3 HPDF_DATAIN3, TIMER14_MCH0, SPI3_NSS, SAI0_FS0, I/O SAI2_FS0, SAI2_DAT1, EXMC_A20, DCI_D4, TLI_B0, EVENTOUT Default: PE5 PE5 4 Alternate: TRACED2 , SAI0_CLK1, HPDF_CKIN3, I/O TIMER14_CH0 , SPI3_MISO, SAI0_SCK0, SAI2_SCK0, SAI2_CLK1, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT Default: PE6 Alternate: TRACED3 , TIMER0_BRKIN2, SAI0_DAT0, PE6 5 TIMER14_CH1 , SPI3_MOSI, SAI0_SD0 , SAI2_SD0, I/O SAI2_DAT0, SAI1_MCLK1, CMP_MUX_OUT3 , EXMC_A22, DCI_D7, TLI_G1, EVENTOUT VBAT 6 P - Default: VBAT Default: PC13 PC13 7 I/O Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_TS, WKUP3, RTC_OUT PC14OSC32IN Default: PC14 8 I/O Additional: OSC32IN PC15OSC32OU Alternate: EVENTOUT Default: PC15 9 I/O Alternate: EVENTOUT Additional: OSC32OUT T Default: PF0 PF0 10 I/O Alternate: I2C1_SDA, USBHS0_ULPI_D4, OSPIM_P1_IO0, EXMC_A0, TIMER22_CH0, EVENTOUT PF1 11 I/O Default: PF1 25 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: I2C1_SCL, USBHS0_ULPI_D5, OSPIM_P1_IO1, EXMC_A1, TIMER22_CH1, EVENTOUT Default: PF2 PF2 12 Alternate: I2C1_SMBA, USBHS0_ULPI_D6, OSPIM_P1_IO2, I/O EXMC_A2, TIMER22_CH2, EVENTOUT Default: PF3 PF3 13 Alternate: OSPIM_P1_IO3, EXMC_A3, TIMER22_CH3, I/O EVENTOUT Additional: ADC2_IN5 Default: PF4 Alternate: TIMER0_MCH1, TIMER7_MCH1, USART0_TX, PF4 14 HPDF_DATAIN2, USART2_RTS, USART2_DE, I/O UART3_RTS, UART3_DE, OSPIM_P1_SCK, SDIO1_D0, EXMC_A4, TRIGSEL_OUT1, TLI_PIXCLK, EVENTOUT Additional: ADC2_IN9 Default: PF5 Alternate: TIMER0_MCH2, TIMER7_MCH2, USART0_RX, PF5 15 HPDF_CKIN2, UART3_CTS, SDIO1_D1, EXMC_A5, I/O TRIGSEL_OUT5, TLI_G7, EVENTOUT Additional: ADC2_IN4 VSS 16 P - Default: VSS VDD 17 P - Default: VDD Default: PF6 Alternate: TIMER15_CH0, CAN2_RX, SPI4_NSS, PF6 18 I/O SAI0_SD1, UART6_RX, SAI2_SD1, OSPIM_P0_IO3, EXMC_D24, TIMER22_CH0, EVENTOUT Additional: ADC2_IN8 Default: PF7 Alternate: TIMER16_CH0, CAN2_TX, SPI4_SCK, PF7 19 I/O SAI0_MCLK1, UART6_TX, SAI2_MCLK1, OSPIM_P0_IO2, EXMC_D25, TIMER22_CH1, EVENTOUT Additional: ADC2_IN3 Default: PF8 Alternate: TIMER15_MCH0, SPI4_MISO, SAI0_SCK1, PF8 20 I/O UART6_RTS, UART6_DE, SAI2_SCK1, OSPIM_P0_IO0, EXMC_D26, TIMER22_CH2, EVENTOUT Additional: ADC2_IN7 Default: PF9 Alternate: TIMER16_MCH0, SPI4_MOSI, SAI0_FS1, PF9 21 I/O UART6_CTS, SAI2_FS1, OSPIM_P0_IO1, EXMC_D27, TIMER22_CH3, EVENTOUT Additional: ADC2_IN2 Default: PF10 PF10 22 I/O Alternate: TIMER15_BRKIN0, SAI0_DAT2, OSPIM_P0_SCK, SAI2_DAT2, DCI_D11, TLI_DE , EVENTOUT Additional: ADC2_IN6 26 GD32H757xx Datasheet Pin Name PH0OSCIN PH1OSCOUT NRST Pins Pin I/O Functions description Type(1) Level(2) Default: PH0 23 Alternate: EVENTOUT I/O Additional: OSCIN Default: PH1 24 Alternate: EVENTOUT I/O Additional: OSCOUT 25 - - Default: NRST Default: PC0 Alternate: EXMC_D12, HPDF_CKIN0, HPDF_DATAIN4, PC0 26 TIMER40_CH0, SAI1_FS1, EXMC_A25, I/O USBHS0_ULPI_STP , TLI_G2, EXMC_SDNWE, TRIGSEL_IN8, TLI_R5, EVENTOUT Additional: ADC012_IN10 Default: PC1 Alternate: TRACED0 , SAI2_DAT0, SAI0_DAT0, HPDF_DATAIN0, HPDF_CKIN4, SPI1_MOSI, I2S1_SD, PC1 27 SAI0_SD0, TIMER40_MCH0, SAI2_SD0, SDIO1_CK, I/O OSPIM_P0_IO4, ETH0_MDC, MDC, TRIGSEL_IN9, TLI_G5, EVENTOUT Additional: ADC012_IN11, RTC_TAMP2, WKUP5 Default: PC2_C PC2_C 28 I/O PC3_C 29 I/O VDD 30 P - Default: VDD VSSA 31 P - Default: VSSA VREFP 32 P - Default: VREFP VDDA 33 P - Default: VDDA Additional: ADC2_IN0 Default: PC3_C Additional: ADC2_IN1 Default: PA0 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, PA0 34 I/O TIMER7_ETI, TIMER14_BRKIN0, SPI5_NSS, I2S5_WS, OSPIM_P0_IO6, USART1_CTS, UART3_TX, SDIO1_CMD, SAI1_SD1, EXMC_A19, TRIGSEL_IN0 , EVENTOUT Additional: ADC0_IN16, WKUP0 Default: PA1 Alternate: TIMER1_CH1, TIMER4_CH1, TIMER14_MCH0, PA1 35 I/O USART1_RTS, USART1_DE, UART3_RX, OSPIM_P0_IO3, SAI1_MCLK1, ETH0_RMII_REF_CLK, TRIGSEL_IN1, TLI_R2, EVENTOUT Additional: ADC0_IN17 Default: PA2 Alternate: TIMER1_CH2, TIMER4_CH2, TIMER14_CH0, PA2 36 I/O OSPIM_P0_IO0, USART1_TX, SAI1_SCK1, ETH0_MDIO, MDIO, TRIGSEL_IN7, TLI_R1, EVENTOUT Additional: ADC01_IN14, WKUP1 27 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PA3 Alternate: TIMER1_CH3, TIMER4_CH3, TIMER14_CH1, PA3 37 I2S5_MCK, OSPIM_P0_IO2, USART1_RX, TLI_B2, I/O USBHS0_ULPI_D0, OSPIM_P0_SCK, TRIGSEL_IN4, TLI_B5, EVENTOUT Additional: ADC01_IN15 VSS 38 P - Default: VSS VDD 39 P - Default: VDD Default: PA4 Alternate: TIMER4_ETI, SPI0_NSS, I2S0_WS, SPI2_NSS, PA4 40 I/O I2S2_WS, USART1_CK, SPI5_NSS, I2S5_WS, EXMC_D8, DCI_HSYNC, TLI_VSYNC, EVENTOUT Additional: ADC01_IN18, DAC0_OUT0 Default: PA5 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER7_MCH0, PA5 41 I/O SPI0_SCK, I2S0_CK, SPI5_SCK, I2S5_CK, USBHS0_ULPI_CK, MDIO_A0, EXMC_D9, TLI_R4, EVENTOUT Additional: ADC01_IN19, DAC0_OUT1 Default: PA6 Alternate: TIMER0_BRKIN0, TIMER2_CH0, PA6 42 I/O TIMER7_BRKIN0, SPI0_MISO, OSPIM_P0_IO3, SPI5_MISO, CMP_MUX_OUT0, MDIO_MDC, DCI_PIXCLK, TLI_G2, EVENTOUT Additional: ADC01_IN3 Default: PA7 Alternate: TIMER0_MCH0, TIMER2_CH1, TIMER7_MCH0, PA7 43 I/O SPI0_MOSI, I2S0_SD, SPI5_MOSI, I2S5_SD, OSPIM_P0_IO2, ETH0_RMII_CRS_DV, EXMC_SDNWE, TRIGSEL_IN5, TLI_VSYNC, EVENTOUT Additional: ADC01_IN7 Default: PC4 Alternate: PMU_DEEPSLEEP, EXMC_A22, HPDF_CKIN2, PC4 44 I/O I2S0_MCK, TIMER41_CH0, RSPDIF_CH2, SDIO1_CKIN, ETH0_RMII_RXD0, EXMC_SDNE0, TLI_R7, EVENTOUT Additional: ADC01_IN4, CMP0_IM7 Default: PC5 Alternate: PMU_SLEEP, SAI2_DAT2, SAI0_DAT2, PC5 45 I/O HPDF_DATAIN2, TIMER41_MCH0, RSPDIF_CH3, ETH0_RMII_RXD1, EXMC_SDCKE0, CMP0_OUT, TLI_DE, EVENTOUT Additional: ADC01_IN8 Default: PB0 PB0 46 I/O Alternate: TIMER0_MCH1, TIMER2_CH2, TIMER7_MCH1, OSPIM_P0_IO1, HPDF_CKOUT, UART3_CTS, TLI_R3, USBHS0_ULPI_D1, MDIO_A1, TRIGSEL_OUT3, TLI_G1, 28 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) EVENTOUT Additional: ADC01_IN9, CMP0_IP0 Default: PB1 Alternate: TIMER0_MCH2, TIMER2_CH3, TIMER7_MCH2, PB1 47 OSPIM_P0_IO0, HPDF_DATAIN1, TLI_R6, I/O USBHS0_ULPI_D2, MDIO_A2, TRIGSEL_OUT4, TLI_G0, EVENTOUT Additional: ADC01_IN5, CMP0_IM6 Default: PB2 Alternate: RTC_OUT, SAI2_DAT0, SAI0_DAT0, EXMC_D10, PB2 48 HPDF_CKIN1, SAI0_SD0, SPI2_MOSI, I2S2_SD, I/O SAI2_SD0, OSPIM_P0_SCK, EXMC_NCE, MDIO_A3, TIMER22_ETI, EVENTOUT Additional: CMP0_IP1 Default: PF11 PF11 49 Alternate: SPI4_MOSI, SAI1_SD1, EXMC_NRAS, DCI_D12, I/O TIMER23_CH0, EVENTOUT Additional: ADC0_IN2 Default: PF12 PF12 50 Alternate: EXMC_A6, TIMER23_CH1, EVENTOUT I/O Additional: ADC0_IN6 VSS 51 P - Default: VSS VDD 52 P - Default: VDD Default: PF13 PF13 53 I/O Alternate: HPDF_DATAIN6, I2C3_SMBA, EXMC_A7, TIMER23_CH2, EVENTOUT Additional: ADC1_IN2 Default: PF14 PF14 54 I/O Alternate: HPDF_CKIN6, I2C3_SCL, SPI4_IO2, EXMC_A8, TIMER23_CH3, EVENTOUT Additional: ADC1_IN6 PF15 55 I/O PG0 56 I/O Default: PF15 Alternate: I2C3_SDA, SPI4_IO3, EXMC_A9, EVENTOUT Default: PG0 Alternate: TIMER31_CH0, OSPIM_P1_IO4, EXMC_A10, EVENTOUT Default: PG1 PG1 57 I/O Alternate: TIMER31_CH1, OSPIM_P1_IO5, EXMC_A11, EVENTOUT Default: PE7 PE7 58 I/O Alternate: TIMER0_ETI, HPDF_DATAIN2, UART6_RX, OSPIM_P0_IO4, EXMC_D4, EVENTOUT Additional: CMP1_IM7 Default: PE8 PE8 59 I/O Alternate: TIMER0_MCH0, HPDF_CKIN2, UART6_TX, OSPIM_P0_IO5, EXMC_D5, CMP1_OUT, EVENTOUT 29 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PE9 Alternate: TIMER0_CH0, HPDF_CKOUT, SPI3_IO2, PE9 60 UART6_RTS, UART6_DE, OSPIM_P0_IO6, EXMC_D6, I/O EVENTOUT Additional: CMP1_IP0 VSS 61 P - Default: VSS VDD 62 P - Default: VDD Default: PE10 PE10 63 Alternate: TIMER0_MCH1, HPDF_DATAIN4, SPI3_IO3, I/O UART6_CTS, OSPIM_P0_IO7, EXMC_D7, EVENTOUT Additional: CMP1_IM6 Default: PE11 Alternate: TIMER0_CH1, HPDF_CKIN4, SPI3_NSS, PE11 64 SAI1_SD1, OSPIM_P0_CSN, EXMC_D8, TLI_G3, I/O EVENTOUT Additional: CMP1_IP1 Default: PE12 PE12 65 Alternate: TIMER0_MCH2, HPDF_DATAIN5, SPI3_SCK, I/O SAI1_SCK1, EXMC_D9, CMP0_OUT, TLI_B4, EVENTOUT Default: PE13 PE13 66 Alternate: TIMER0_CH2, HPDF_CKIN5, SPI3_MISO, I/O SAI1_FS1, EXMC_D10, CMP1_OUT, TLI_DE, EVENTOUT Default: PE14 PE14 67 Alternate: TIMER0_CH3, SPI3_MOSI, SAI1_MCLK1, I/O EXMC_D11, TLI_PIXCLK, EVENTOUT Default: PE15 PE15 68 Alternate: TIMER0_BRKIN0, TLI_HSYNC, EXMC_D12, I/O CMP_MUX_OUT4, TLI_R7, EVENTOUT Default: PB10 PB10 69 Alternate: TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I/O HPDF_DATAIN7, USART2_TX, OSPIM_P0_NCS, USBHS0_ULPI_D3, TRIGSEL_OUT2, TLI_G4, EVENTOUT Default: PB11 PB11 70 Alternate: TIMER1_CH3, I2C1_SDA, HPDF_CKIN7, I/O USART2_RX, USBHS0_ULPI_D4, ETH0_RMII_TX_EN, TLI_G5, EVENTOUT VCORE 71 P - Default: VCORE VDD 72 P - Default: VDD Default: PB12 Alternate: TIMER0_BRKIN0, I2C1_SMBA, SPI1_NSS, PB12 73 I/O 5VT I2S1_WS, HPDF_DATAIN1, USART2_CK, CAN1_RX, USBHS0_ULPI_D5, ETH0_RMII_TXD0, OSPIM_P0_IO0, CMP_MUX_OUT2, UART4_RX, EVENTOUT Default: PB13 PB13 74 I/O 5VT Alternate: RTC_REFIN, TIMER0_MCH0, OSPIM_P0_IO2, SPI1_SCK, I2S1_CK, HPDF_CKIN1, USART2_CTS, 30 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) CAN1_TX, USBHS0_ULPI_D6, ETH0_RMII_TXD1, SDIO0_D0, DCI_D2, UART4_TX, EVENTOUT Default: PB14 Alternate: TIMER0_MCH1, TIMER7_MCH1, USART0_TX, PB14 75 SPI1_MISO, HPDF_DATAIN2, USART2_RTS, USART2_DE, I/O UART3_RTS, UART3_DE, SDIO1_D0, EXMC_D10, TRIGSEL_OUT1, TLI_PIXCLK, EVENTOUT Default: PB15 Alternate: RTC_REFIN, TIMER0_MCH2, TIMER7_MCH2, PB15 76 USART0_RX, SPI1_MOSI, I2S1_SD, HPDF_CKIN2, I/O UART3_CTS, SDIO1_D1, EXMC_D11, TRIGSEL_OUT5, TLI_G7, EVENTOUT Default: PD8 PD8 77 Alternate: HPDF_CKIN3, USART2_TX, SAI1_CLK0, I/O RSPDIF_CH1, EXMC_D13, EVENTOUT Default: PD9 PD9 78 Alternate: HPDF_DATAIN3, USART2_RX, SAI1_CLK1, I/O EXMC_D14, EVENTOUT Default: PD10 PD10 79 Alternate: HPDF_CKOUT, USART2_CK, SAI1_DAT1, I/O EXMC_D15, TLI_B3, EVENTOUT Default: PD11 PD11 80 Alternate: TIMER40_CH1, TIMER7_MCH3, I2C3_SMBA, I/O USART2_CTS, SAI1_DAT2, OSPIM_P0_IO0, SAI1_SD0, EXMC_A16, EXMC_CLE, EVENTOUT Default: PD12 Alternate: TIMER41_CH1, TIMER3_CH0, I2C3_SCL, PD12 81 CAN2_RX, EDOUT_A, USART2_RTS, USART2_DE, I/O OSPIM_P0_IO1, SAI1_FS0, EXMC_A17, EXMC_ALE, DCI_D12, EVENTOUT Default: PD13 PD13 82 Alternate: TIMER42_CH1, TIMER3_CH1, I2C3_SDA, I/O CAN2_TX, EDOUT_B, OSPIM_P0_IO3, SAI1_SCK0, EXMC_A18, DCI_D13, EVENTOUT VSS 83 P - Default: VSS VDD 84 P - Default: VDD Default: PD14 PD14 85 I/O Alternate: TIMER43_CH1, TIMER3_CH2, SPI3_IO2, EDOUT_Z, UART7_CTS, EXMC_D0, EVENTOUT Default: PD15 PD15 86 I/O Alternate: TIMER44_CH1, TIMER3_CH3, SPI3_IO3, UART7_RTS, UART7_DE, EXMC_D1, EVENTOUT Default: PG2 PG2 87 I/O Alternate: TIMER0_BRKIN1, TIMER7_BRKIN0, TIMER31_CH2, SPI1_MISO, CMP_MUX_OUT5, EXMC_A12, TIMER23_ETI, EVENTOUT 31 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PG3 PG3 88 Alternate: TIMER7_BRKIN2, TIMER31_CH3, SPI1_MOSI, I/O I2S1_SD, CMP_MUX_OUT6, EXMC_A13, TIMER22_ETI, EVENTOUT Default: PG4 PG4 89 Alternate: TIMER0_BRKIN2, TIMER7_BRKIN1, I/O TIMER31_ETI, CMP_MUX_OUT7, EXMC_A14, EVENTOUT Default: PG5 PG5 90 Alternate: TIMER0_ETI, TIMER30_CH0, EXMC_A15, I/O EVENTOUT Default: PG6 PG6 91 Alternate: TIMER16_BRKIN0, TIMER30_CH1, I/O OSPIM_P0_CSN, EXMC_NE2, DCI_D12, TLI_R7, EVENTOUT Default: PG7 PG7 92 Alternate: EXMC_D28, TIMER30_CH2, SAI0_MCLK0, I/O USART5_CK, EXMC_INT, DCI_D13, TLI_PIXCLK, EVENTOUT Default: PG8 Alternate: TIMER7_ETI, TIMER30_CH3, SPI5_NSS, PG8 93 I/O VSS 94 P - Default: VSS 95 P - Default: VDD33USB I2S5_WS, USART5_RTS, USART5_DE, RSPDIF_CH2, ETH0_PPS_OUT, EXMC_SDCLK, TLI_G7, EVENTOUT VDD33US B Default: PC6 Alternate: TIMER0_BRKIN1, TIMER2_CH0, TIMER7_CH0, PC6 96 I/O HPDF_CKIN3, I2S1_MCK, USART5_TX, SDIO0_DAT0DIR, EXMC_NWAIT, SDIO1_D6, SDIO0_D6, DCI_D0, TLI_HSYNC, EVENTOUT Default: PC7 Alternate: TIMER0_CH3, TIMER2_CH1, TIMER7_CH1, PC7 97 I/O HPDF_DATAIN3, I2S2_MCK, USART5_RX, SDIO0_DAT123DIR, EXMC_NE0, SDIO1_D7, SDIO0_D7, DCI_D1, TLI_G6, EVENTOUT Default: PC8 PC8 98 I/O Alternate: TRACED1, TIMER2_CH2, TIMER7_CH2, USART5_CK, UART4_RTS, UART4_DE, EXMC_NE1, EXMC_INT, SDIO0_D0, DCI_D2, EVENTOUT Default: PC9 Alternate: CK_OUT1, TIMER0_MCH3, TIMER2_CH3, PC9 99 I/O TIMER7_CH3, I2C2_SDA, I2S_CKIN, UART4_CTS, OSPIM_P0_IO0, TLI_G3, SDIO0_D1, DCI_D3, TLI_B2, EVENTOUT PA8 100 I/O Default: PA8 Alternate: CK_OUT0, TIMER0_CH0, TIMER7_BRKIN2, 32 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) I2C2_SCL, USART0_CK, USBHS0_SOF, UART6_RX, CMP_MUX_OUT1, TLI_B3, TLI_R6, EVENTOUT Default: PA9 PA9 101 I/O 5VT Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, TRIGSEL_IN13, DCI_D0, TLI_R5, EVENTOUT Additional: USBHS0_VBUS Default: PA10 PA10 102 I/O 5VT Alternate: TIMER0_CH2, USART0_RX, TRIGSEL_IN12, USBHS0_ID, MDIO, TLI_B4, DCI_D1, TLI_B1, EVENTOUT USBHS0_ DM USBHS0_ DP 103 I/O Default: USBHS0_DM 104 I/O Default: USBHS0_DP Default: JTMS, SWDIO, PA13 Alternate: TIMER0_BRKIN1, TIMER7_BRKIN1, SPI1_NSS, PA13 105 I2S1_WS, UART3_RX, USART0_CTS, CAN0_RX, I/O MDIO_A3, EXMC_INT, TRIGSEL_IN10, TLI_R4, EVENTOUT VCORE 106 P - Default: VCORE VSS 107 P - Default: VSS VDD 108 P - Default: VDD Default: JTCK, SWCLK, PA14 Alternate: TLI_G7, SPI1_SCK, I2S1_CK, UART3_TX, PA14 109 I/O USART0_RTS, USART0_DE, SAI1_FS1, CAN0_TX, MDIO_A4, TIMER0_BRKIN2, TRIGSEL_IN11, TLI_R5, EVENTOUT Default: JTDI, PA15 Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, PA15 110 I/O I2S0_WS, SPI2_NSS, I2S2_WS, SPI5_NSS, I2S5_WS, UART3_RTS, UART3_DE, TLI_R3, UART6_TX, MDIO_A0, TRIGSEL_OUT0, TLI_B6, EVENTOUT Default: PC10 Alternate: TIMER0_CH3, HPDF_CKIN5, SPI2_SCK, PC10 111 I/O I2S2_CK, USART2_TX, UART3_TX, OSPIM_P0_IO1, TLI_B1, MDIO_A1, SDIO0_D2, DCI_D8, TLI_R2, EVENTOUT Default: PC11 PC11 112 I/O Alternate: TIMER0_ETI, HPDF_DATAIN5, SPI2_MISO, USART2_RX, UART3_RX, OSPIM_P0_CSN, EXMC_NBL2, MDIO_A2, SDIO0_D3, DCI_D4, TLI_B4, EVENTOUT Default: PC12 PC12 113 I/O Alternate: TRACED3, EXMC_D6, TIMER14_CH0, SPI5_SCK, I2S5_CK, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO0_CK, DCI_D9, TLI_R6, EVENTOUT PD0 114 I/O Default: PD0 33 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER7_CH2, HPDF_CKIN6, UART3_RX, CAN0_RX, EXMC_D2, TRIGSEL_IN3, TLI_B1, EVENTOUT Default: PD1 PD1 115 Alternate: HPDF_DATAIN6, UART3_TX, CAN0_TX, I/O EXMC_D3, TRIGSEL_IN6, EVENTOUT Default: PD2 PD2 116 Alternate: TRACED2, EXMC_D7, TIMER2_ETI, I/O TIMER14_BRKIN0, UART4_RX, TLI_B7, SDIO0_CMD, DCI_D11, TLI_B2, EVENTOUT Default: PD3 PD3 117 Alternate: HPDF_CKOUT, SPI1_SCK, I2S1_CK, I/O USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT Default: PD4 PD4 118 Alternate: TIMER7_MCH3, USART1_RTS, USART1_DE, I/O OSPIM_P0_IO4, EXMC_NOE, EVENTOUT Default: PD5 Alternate: TIMER7_CH3, USART1_TX, OSPIM_P0_IO5, PD5 119 I/O VSS 120 P - Default: VSS VDD 121 P - Default: VDD EXMC_NWE, EVENTOUT Default: PD6 Alternate: SAI1_DAT0, SAI0_DAT0, HPDF_CKIN4, PD6 122 I/O HPDF_DATAIN1, SPI2_MOSI, I2S2_SD, SAI0_SD0, USART1_RX, SAI2_SD0, OSPIM_P0_IO6, SDIO1_CK, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT Default: PD7 Alternate: HPDF_DATAIN4, SPI0_MOSI, I2S0_SD, PD7 123 I/O HPDF_CKIN1, USART1_CK, RSPDIF_CH0, OSPIM_P0_IO7, SDIO1_CMD, EXMC_NE0, EXMC_NCE, EVENTOUT Default: PG9 Alternate: EXMC_D30, CAN2_TX, TIMER7_BRKIN1, PG9 124 I/O TIMER30_ETI, SPI0_MISO, USART5_RX, RSPDIF_CH3, OSPIM_P0_IO6, SAI1_FS1, SDIO1_D0, EXMC_NE1, DCI_VSYNC, EVENTOUT Default: PG10 PG10 125 I/O Alternate: EXMC_D31, CAN2_RX, OSPIM_P1_IO6, SPI0_NSS, I2S0_WS, TLI_G3, SAI1_SD1, SDIO1_D1, EXMC_NE2, DCI_D2, TLI_B2, EVENTOUT Default: PG11 PG11 126 I/O Alternate: EXMC_D29, SPI0_SCK, I2S0_CK, RSPDIF_CH0, OSPIM_P1_IO7, SDIO1_D2, ETH0_RMII_TX_EN, DCI_D3, TLI_B3, EVENTOUT Default: PG12 PG12 127 I/O Alternate: OSPIM_P1_CSN, SPI5_MISO, USART5_RTS, USART5_DE, RSPDIF_CH1, TLI_B4, SDIO1_D3, 34 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) ETH0_RMII_TXD1, EXMC_NE3, TIMER22_CH0, TLI_B1, EVENTOUT Default: PG13 PG13 128 Alternate: TRACED0, SPI5_SCK, I2S5_CK, USART5_CTS, I/O TIMER44_CH0, SDIO1_D6, ETH0_RMII_TXD0, EXMC_A24, TIMER22_CH1, TLI_R0, EVENTOUT Default: PG14 Alternate: TRACED1, SPI5_MOSI, I2S5_SD, USART5_TX, PG14 129 TIMER44_MCH0, OSPIM_P0_IO7, SDIO1_D7, I/O ETH0_RMII_TXD1, EXMC_A25, TIMER22_CH2, TLI_B0, EVENTOUT VSS 130 P - Default: VSS VDD 131 P - Default: VDD Default: PG15 PG15 132 I/O Alternate: USART5_CTS, TIMER44_BRKIN0, EXMC_SDNCAS, DCI_D13, EVENTOUT Default: JTDO, PB3 Alternate: TRACESWO, TIMER1_CH1, TLI_PIXCLK, PB3 133 I/O SPI0_SCK, I2S0_CK, SPI2_SCK, I2S2_CK, SPI5_SCK, I2S5_CK, SDIO1_D2, CTC_SYNC, UART6_RX, MDIO_A4, TRIGSEL_OUT7, TIMER23_ETI, EVENTOUT Default: NJTRST, PB4 PB4 134 I/O Alternate: TIMER15_BRKIN0, TIMER2_CH0, SPI0_MISO, SPI2_MISO, SPI1_NSS, I2S1_WS, SPI5_MISO, SDIO1_D3, UART6_TX, TRIGSEL_OUT6, EVENTOUT Default: PB5 Alternate: TIMER16_BRKIN0, TIMER2_CH1, TLI_B5, PB5 135 I/O I2C0_SMBA, SPI0_MOSI, I2S0_SD, I2C3_SMBA, SPI2_MOSI, I2S2_SD, SPI5_MOSI, I2S5_SD, CAN1_RX, USBHS0_ULPI_D7, ETH0_PPS_OUT, EXMC_SDCKE1, DCI_D10, UART4_RX, EVENTOUT Default: PB6 Alternate: TIMER15_MCH0, TIMER3_CH0, EXMC_D11, PB6 136 I/O I2C0_SCL, I2C3_SCL, USART0_TX, CAN1_TX, OSPIM_P0_CSN, HPDF_DATAIN5, EXMC_SDNE1, DCI_D5, UART4_TX, EVENTOUT Default: PB7 Alternate: TIMER16_MCH0, TIMER3_CH1, I2C0_SDA, PB7 137 I/O I2C3_SDA, USART0_RX, HPDF_CKIN5, EXMC_NL, EXMC_NADV, DCI_VSYNC, EVENTOUT Additional: PVD_IN BOOT 138 I/O Default: BOOT Default: PB8 PB8 139 I/O Alternate: TIMER15_CH0, TIMER3_CH2, HPDF_CKIN7, I2C0_SCL, I2C3_SCL, SDIO0_CKIN, UART3_RX, CAN0_RX, SDIO1_D4, SDIO0_D4, DCI_D6, TLI_B6, 35 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) EVENTOUT Default: PB9 Alternate: TIMER16_CH0, TIMER3_CH3, HPDF_DATAIN7, PB9 140 I2C0_SDA, SPI1_NSS, I2S1_WS, I2C3_SDA, I/O SDIO0_CMDDIR, UART3_TX, CAN0_TX, SDIO1_D5, I2C3_SMBA, SDIO0_D5, DCI_D7, TLI_B7, EVENTOUT Default: PE0 PE0 141 Alternate: TIMER3_ETI, UART7_RX, SAI1_MCLK0, I/O EXMC_NBL0, DCI_D2, TLI_R0, EVENTOUT Default: PE1 PE1 142 Alternate: UART7_TX, EXMC_NBL1, DCI_D3, TLI_R6, I/O EVENTOUT PDR_ON 143 P - Default: PDR_ON VDD 144 P - Default: VDD Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 2.6.2. GD32H757Vx LQFP100 pin definitions Table 2-4. GD32H757Vx LQFP100 pin definitions Pin Name Pins PE2 1 Pin I/O Type(1) Level(2) Functions description Default: PE2 Alternate: TRACECK, SAI0_CLK0, SPI3_SCK, I/O SAI0_MCLK0, OSPIM_P0_IO2, EXMC_A23, EVENTOUT Default: PE3 PE3 2 Alternate: TRACED0, TIMER14_BRKIN0, SAI0_SD1, I/O EXMC_A19, DCI_PIXCLK, EVENTOUT Default: PE4 PE4 3 Alternate: TRACED1 , TIMER0_BRKIN1, SAI0_DAT1, I/O HPDF_DATAIN3, TIMER14_MCH0, SPI3_NSS, SAI0_FS0, EXMC_A20, DCI_D4, TLI_B0, EVENTOUT Default: PE5 PE5 4 Alternate: TRACED2 , SAI0_CLK1, HPDF_CKIN3, I/O TIMER14_CH0 , SPI3_MISO, SAI0_SCK0, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT Default: PE6 Alternate: TRACED3 , TIMER0_BRKIN2, SAI0_DAT0, PE6 5 TIMER14_CH1 , SPI3_MOSI, SAI0_SD0 , SAI1_MCLK1, I/O CMP_MUX_OUT3, EXMC_A22, DCI_D7, TLI_G1, EVENTOUT VBAT 6 P PC13 7 I/O - Default: VBAT Default: PC13 36 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_TS, WKUP3, RTC_OUT PC14OSC32IN Default: PC14 8 Alternate: EVENTOUT I/O Additional: OSC32IN PC15OSC32OU Default: PC15 9 Alternate: EVENTOUT I/O Additional: OSC32OUT T VSS 10 P - Default: VSS VDD 11 P - Default: VDD PH0OSCIN PH1OSCOUT NRST Default: PH0 12 Alternate: EVENTOUT I/O Additional: OSCIN Default: PH1 13 Alternate: EVENTOUT I/O Additional: OSCOUT 14 - - Default: NRST Default: PC0 Alternate: EXMC_D12, HPDF_CKIN0, HPDF_DATAIN4, PC0 15 TIMER40_CH0, SAI1_FS1, EXMC_A25, I/O USBHS0_ULPI_STP , TLI_G2, EXMC_SDNWE, TRIGSEL_IN8, TLI_R5, EVENTOUT Additional: ADC012_IN10 Default: PC1 Alternate: TRACED0 , SAI0_DAT0, HPDF_DATAIN0, PC1 16 HPDF_CKIN4, SPI1_MOSI, I2S1_SD, SAI0_SD0, I/O TIMER40_MCH0, SDIO1_CK, OSPIM_P0_IO4, ETH0_MDC, MDC, TRIGSEL_IN9, TLI_G5, EVENTOUT Additional: ADC012_IN11, RTC_TAMP2, WKUP5 Default: PC2_C PC2_C 17 I/O PC3_C 18 I/O VSSA 19 P - Default: VSSA VREFP 20 P - Default: VREFP VDDA 21 P - Default: VDDA Additional: ADC2_IN0 Default: PC3_C Additional: ADC2_IN1 Default: PA0 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, PA0 22 I/O TIMER7_ETI, TIMER14_BRKIN0, SPI5_NSS, I2S5_WS, OSPIM_P0_IO6, USART1_CTS, UART3_TX, SDIO1_CMD, SAI1_SD1, EXMC_A19, TRIGSEL_IN0 , EVENTOUT Additional: ADC0_IN16, WKUP0 Default: PA1 PA1 23 I/O Alternate: TIMER1_CH1, TIMER4_CH1, TIMER14_MCH0, USART1_RTS, USART1_DE, UART3_RX, OSPIM_P0_IO3, 37 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) SAI1_MCLK1, ETH0_RMII_REF_CLK, TRIGSEL_IN1, TLI_R2, EVENTOUT Additional: ADC0_IN17 Default: PA2 Alternate: TIMER1_CH2, TIMER4_CH2, TIMER14_CH0, PA2 24 OSPIM_P0_IO0, USART1_TX, SAI1_SCK1, ETH0_MDIO, I/O MDIO, TRIGSEL_IN7 , TLI_R1, EVENTOUT Additional: ADC01_IN14, WKUP1 Default: PA3 Alternate: TIMER1_CH3, TIMER4_CH3, TIMER14_CH1, PA3 25 I2S5_MCK, OSPIM_P0_IO2, USART1_RX, TLI_B2, I/O USBHS0_ULPI_D0, OSPIM_P0_SCK, TRIGSEL_IN4, TLI_B5, EVENTOUT Additional: ADC01_IN15 VSS 26 P - Default: VSS VDD 27 P - Default: VDD Default: PA4 Alternate: TIMER4_ETI, SPI0_NSS, I2S0_WS, SPI2_NSS, PA4 28 I/O I2S2_WS, USART1_CK, SPI5_NSS, I2S5_WS, EXMC_D8, DCI_HSYNC, TLI_VSYNC, EVENTOUT Additional: ADC01_IN18, DAC0_OUT0 Default: PA5 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER7_MCH0, PA5 29 I/O SPI0_SCK, I2S0_CK, SPI5_SCK, I2S5_CK, USBHS0_ULPI_CK, MDIO_A0, EXMC_D9, TLI_R4, EVENTOUT Additional: ADC01_IN19, DAC0_OUT1 Default: PA6 Alternate: TIMER0_BRKIN0, TIMER2_CH0, PA6 30 I/O TIMER7_BRKIN0, SPI0_MISO, OSPIM_P0_IO3, SPI5_MISO, CMP_MUX_OUT0, MDIO_MDC, DCI_PIXCLK, TLI_G2, EVENTOUT Additional: ADC01_IN3 Default: PA7 Alternate: TIMER0_MCH0, TIMER2_CH1, TIMER7_MCH0, PA7 31 I/O SPI0_MOSI, I2S0_SD, SPI5_MOSI, I2S5_SD, OSPIM_P0_IO2, ETH0_RMII_CRS_DV, EXMC_SDNWE, TRIGSEL_IN5, TLI_VSYNC, EVENTOUT Additional: ADC01_IN7 Default: PC4 Alternate: PMU_DEEPSLEEP, EXMC_A22, HPDF_CKIN2, PC4 32 I/O I2S0_MCK, TIMER41_CH0, RSPDIF_CH2, SDIO1_CKIN, ETH0_RMII_RXD0, EXMC_SDNE0, TLI_R7, EVENTOUT Additional: ADC01_IN4, CMP0_IM7 PC5 33 I/O Default: PC5 Alternate: PMU_SLEEP, SAI0_DAT2, HPDF_DATAIN2, 38 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) TIMER41_MCH0, RSPDIF_CH3, ETH0_RMII_RXD1, EXMC_SDCKE0, CMP0_OUT, TLI_DE, EVENTOUT Additional: ADC01_IN8 Default: PB0 Alternate: TIMER0_MCH1, TIMER2_CH2, TIMER7_MCH1, PB0 34 I/O OSPIM_P0_IO1, HPDF_CKOUT, UART3_CTS, TLI_R3, USBHS0_ULPI_D1, MDIO_A1, TRIGSEL_OUT3, TLI_G1, EVENTOUT Additional: ADC01_IN9, CMP0_IP0 Default: PB1 Alternate: TIMER0_MCH2, TIMER2_CH3, TIMER7_MCH2, PB1 35 I/O OSPIM_P0_IO0, HPDF_DATAIN1, TLI_R6, USBHS0_ULPI_D2, MDIO_A2, TRIGSEL_OUT4, TLI_G0, EVENTOUT Additional: ADC01_IN5, CMP0_IM6 Default: PB2 Alternate: RTC_OUT, SAI0_DAT0, EXMC_D10, PB2 36 I/O HPDF_CKIN1, SAI0_SD0, SPI2_MOSI, I2S2_SD, OSPIM_P0_SCK, EXMC_NCE, MDIO_A3, TIMER22_ETI, EVENTOUT Additional: CMP0_IP1 Default: PE7 PE7 37 I/O Alternate: TIMER0_ETI, HPDF_DATAIN2, UART6_RX, OSPIM_P0_IO4, EXMC_D4, EVENTOUT Additional: CMP1_IM7 Default: PE8 PE8 38 I/O Alternate: TIMER0_MCH0, HPDF_CKIN2, UART6_TX, OSPIM_P0_IO5, EXMC_D5, CMP1_OUT, EVENTOUT Default: PE9 Alternate: TIMER0_CH0, HPDF_CKOUT, SPI3_IO2, PE9 39 I/O UART6_RTS, UART6_DE, OSPIM_P0_IO6, EXMC_D6, EVENTOUT Additional: CMP1_IP0 Default: PE10 PE10 40 I/O Alternate: TIMER0_MCH1, HPDF_DATAIN4, SPI3_IO3, UART6_CTS, OSPIM_P0_IO7, EXMC_D7, EVENTOUT Additional: CMP1_IM6 Default: PE11 Alternate: TIMER0_CH1, HPDF_CKIN4, SPI3_NSS, PE11 41 I/O SAI1_SD1, OSPIM_P0_CSN, EXMC_D8, TLI_G3, EVENTOUT Additional: CMP1_IP1 Default: PE12 PE12 42 I/O PE13 43 I/O Alternate: TIMER0_MCH2, HPDF_DATAIN5, SPI3_SCK, SAI1_SCK1, EXMC_D9, CMP0_OUT, TLI_B4, EVENTOUT Default: PE13 39 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER0_CH2, HPDF_CKIN5, SPI3_MISO, SAI1_FS1, EXMC_D10, CMP1_OUT, TLI_DE, EVENTOUT Default: PE14 PE14 44 Alternate: TIMER0_CH3, SPI3_MOSI, SAI1_MCLK1, I/O EXMC_D11, TLI_PIXCLK, EVENTOUT Default: PE15 PE15 45 Alternate: TIMER0_BRKIN0, TLI_HSYNC, EXMC_D12, I/O CMP_MUX_OUT4, TLI_R7, EVENTOUT Default: PB10 PB10 46 Alternate: TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I/O HPDF_DATAIN7, USART2_TX, OSPIM_P0_NCS, USBHS0_ULPI_D3, TRIGSEL_OUT2, TLI_G4, EVENTOUT Default: PB11 PB11 47 Alternate: TIMER1_CH3, I2C1_SDA, HPDF_CKIN7, I/O USART2_RX, USBHS0_ULPI_D4, ETH0_RMII_TX_EN, TLI_G5, EVENTOUT VCORE 48 P - Default: VCORE VSS 49 P - Default: VSS VDD 50 P - Default: VDD Default: PB12 Alternate: TIMER0_BRKIN0, I2C1_SMBA, SPI1_NSS, PB12 51 I/O 5VT I2S1_WS, HPDF_DATAIN1, USART2_CK, CAN1_RX, USBHS0_ULPI_D5, ETH0_RMII_TXD0, OSPIM_P0_IO0, CMP_MUX_OUT2, UART4_RX, EVENTOUT Default: PB13 Alternate: RTC_REFIN, TIMER0_MCH0, OSPIM_P0_IO2, PB13 52 I/O 5VT SPI1_SCK, I2S1_CK, HPDF_CKIN1, USART2_CTS, CAN1_TX, USBHS0_ULPI_D6, ETH0_RMII_TXD1, SDIO0_D0, DCI_D2, UART4_TX, EVENTOUT Default: PB14 Alternate: TIMER0_MCH1, TIMER7_MCH1, USART0_TX, PB14 53 I/O SPI1_MISO, HPDF_DATAIN2, USART2_RTS, USART2_DE, UART3_RTS, UART3_DE, SDIO1_D0, EXMC_D10, TRIGSEL_OUT1, TLI_PIXCLK, EVENTOUT Default: PB15 Alternate: RTC_REFIN, TIMER0_MCH2, TIMER7_MCH2, PB15 54 I/O USART0_RX, SPI1_MOSI, I2S1_SD, HPDF_CKIN2, UART3_CTS, SDIO1_D1, EXMC_D11, TRIGSEL_OUT5, TLI_G7, EVENTOUT Default: PD8 PD8 55 I/O Alternate: HPDF_CKIN3, USART2_TX, SAI1_CLK0, RSPDIF_CH1, EXMC_D13, EVENTOUT Default: PD9 PD9 56 I/O Alternate: HPDF_DATAIN3, USART2_RX, SAI1_CLK1, EXMC_D14, EVENTOUT PD10 57 I/O Default: PD10 40 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: HPDF_CKOUT, USART2_CK, SAI1_DAT1, EXMC_D15, TLI_B3, EVENTOUT Default: PD11 PD11 58 Alternate: TIMER40_CH1, TIMER7_MCH3, I2C3_SMBA, I/O USART2_CTS, SAI1_DAT2, OSPIM_P0_IO0, SAI1_SD0, EXMC_A16, EXMC_CLE, EVENTOUT Default: PD12 Alternate: TIMER41_CH1, TIMER3_CH0, I2C3_SCL, PD12 59 CAN2_RX, EDOUT_A, USART2_RTS, USART2_DE, I/O OSPIM_P0_IO1, SAI1_FS0, EXMC_A17, EXMC_ALE, DCI_D12, EVENTOUT Default: PD13 PD13 60 Alternate: TIMER42_CH1, TIMER3_CH1, I2C3_SDA, I/O CAN2_TX, EDOUT_B, OSPIM_P0_IO3, SAI1_SCK0, EXMC_A18, DCI_D13, EVENTOUT Default: PD14 PD14 61 Alternate: TIMER43_CH1, TIMER3_CH2, SPI3_IO2, I/O EDOUT_Z, UART7_CTS, EXMC_D0, EVENTOUT Default: PD15 PD15 62 Alternate: TIMER44_CH1, TIMER3_CH3, SPI3_IO3, I/O UART7_RTS, UART7_DE, EXMC_D1, EVENTOUT Default: PC6 Alternate: TIMER0_BRKIN1, TIMER2_CH0, TIMER7_CH0, PC6 63 HPDF_CKIN3, I2S1_MCK, USART5_TX, SDIO0_DAT0DIR, I/O EXMC_NWAIT, SDIO1_D6, SDIO0_D6, DCI_D0, TLI_HSYNC, EVENTOUT Default: PC7 Alternate: TIMER0_CH3, TIMER2_CH1, TIMER7_CH1, PC7 64 HPDF_DATAIN3, I2S2_MCK, USART5_RX, I/O SDIO0_DAT123DIR, EXMC_NE0, SDIO1_D7, SDIO0_D7, DCI_D1, TLI_G6, EVENTOUT Default: PC8 PC8 65 Alternate: TRACED1, TIMER2_CH2, TIMER7_CH2, I/O USART5_CK, UART4_RTS, UART4_DE, EXMC_NE1, EXMC_INT, SDIO0_D0, DCI_D2, EVENTOUT Default: PC9 Alternate: CK_OUT1, TIMER0_MCH3, TIMER2_CH3, PC9 66 TIMER7_CH3, I2C2_SDA, I2S_CKIN, UART4_CTS, I/O OSPIM_P0_IO0, TLI_G3, SDIO0_D1, DCI_D3, TLI_B2, EVENTOUT Default: PA8 PA8 67 Alternate: CK_OUT0, TIMER0_CH0, TIMER7_BRKIN2, I/O I2C2_SCL, USART0_CK, USBHS0_SOF, UART6_RX, CMP_MUX_OUT1, TLI_B3, TLI_R6, EVENTOUT PA9 68 I/O 5VT Default: PA9 Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, 41 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) USART0_TX, TRIGSEL_IN13, DCI_D0, TLI_R5, EVENTOUT Additional: USBHS0_VBUS Default: PA10 PA10 69 I/O 5VT Alternate: TIMER0_CH2, USART0_RX, TRIGSEL_IN12, USBHS0_ID, MDIO, TLI_B4, DCI_D1, TLI_B1, EVENTOUT USBHS0_ DM USBHS0_ DP 70 I/O Default: USBHS0_DM 71 I/O Default: USBHS0_DP Default: JTMS, SWDIO, PA13 Alternate: TIMER0_BRKIN1, TIMER7_BRKIN1, SPI1_NSS, PA13 72 I2S1_WS, UART3_RX, USART0_CTS, CAN0_RX, I/O MDIO_A3, EXMC_INT, TRIGSEL_IN10, TLI_R4, EVENTOUT VCORE 73 P - Default: VCORE VSS 74 P - Default: VSS VDD 75 P - Default: VDD Default: JTCK, SWCLK, PA14 Alternate: TLI_G7, SPI1_SCK, I2S1_CK, UART3_TX, PA14 76 I/O USART0_RTS, USART0_DE, SAI1_FS1, CAN0_TX, MDIO_A4, TIMER0_BRKIN2, TRIGSEL_IN11, TLI_R5, EVENTOUT Default: JTDI, PA15 Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, PA15 77 I/O I2S0_WS, SPI2_NSS, I2S2_WS, SPI5_NSS, I2S5_WS, UART3_RTS, UART3_DE, TLI_R3, UART6_TX, MDIO_A0, TRIGSEL_OUT0, TLI_B6, EVENTOUT Default: PC10 Alternate: TIMER0_CH3, HPDF_CKIN5, SPI2_SCK, PC10 78 I/O I2S2_CK, USART2_TX, UART3_TX, OSPIM_P0_IO1, TLI_B1, MDIO_A1, SDIO0_D2, DCI_D8, TLI_R2, EVENTOUT Default: PC11 PC11 79 I/O Alternate: TIMER0_ETI, HPDF_DATAIN5, SPI2_MISO, USART2_RX, UART3_RX, OSPIM_P0_CSN, EXMC_NBL2, MDIO_A2, SDIO0_D3, DCI_D4, TLI_B4, EVENTOUT Default: PC12 PC12 80 I/O Alternate: TRACED3, EXMC_D6, TIMER14_CH0, SPI5_SCK, I2S5_CK, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO0_CK, DCI_D9, TLI_R6, EVENTOUT Default: PD0 PD0 81 I/O Alternate: TIMER7_CH2, HPDF_CKIN6, UART3_RX, CAN0_RX, EXMC_D2, TRIGSEL_IN3, TLI_B1, EVENTOUT PD1 82 I/O Default: PD1 Alternate: HPDF_DATAIN6, UART3_TX, CAN0_TX, 42 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) EXMC_D3, TRIGSEL_IN6, EVENTOUT Default: PD2 PD2 83 I/O Alternate: TRACED2, EXMC_D7, TIMER2_ETI, TIMER14_BRKIN0, UART4_RX, TLI_B7, SDIO0_CMD, DCI_D11, TLI_B2, EVENTOUT Default: PD3 PD3 84 I/O Alternate: HPDF_CKOUT, SPI1_SCK, I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT Default: PD4 PD4 85 I/O Alternate: TIMER7_MCH3, USART1_RTS, USART1_DE, OSPIM_P0_IO4, EXMC_NOE, EVENTOUT Default: PD5 PD5 86 I/O Alternate: TIMER7_CH3, USART1_TX, OSPIM_P0_IO5, EXMC_NWE, EVENTOUT Default: PD6 Alternate: SAI1_DAT0, SAI0_DAT0, HPDF_CKIN4, PD6 87 I/O HPDF_DATAIN1, SPI2_MOSI, I2S2_SD, SAI0_SD0, USART1_RX, OSPIM_P0_IO6, SDIO1_CK, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT Default: PD7 Alternate: HPDF_DATAIN4, SPI0_MOSI, I2S0_SD, PD7 88 I/O HPDF_CKIN1, USART1_CK, RSPDIF_CH0, OSPIM_P0_IO7, SDIO1_CMD, EXMC_NE0, EXMC_NCE, EVENTOUT Default: JTDO, PB3 Alternate: TRACESWO, TIMER1_CH1, TLI_PIXCLK, PB3 89 I/O SPI0_SCK, I2S0_CK, SPI2_SCK, I2S2_CK, SPI5_SCK, I2S5_CK, SDIO1_D2, CTC_SYNC, UART6_RX, MDIO_A4, TRIGSEL_OUT7, TIMER23_ETI, EVENTOUT Default: NJTRST, PB4 PB4 90 I/O Alternate: TIMER15_BRKIN0, TIMER2_CH0, SPI0_MISO, SPI2_MISO, SPI1_NSS, I2S1_WS, SPI5_MISO, SDIO1_D3, UART6_TX, TRIGSEL_OUT6, EVENTOUT Default: PB5 Alternate: TIMER16_BRKIN0, TIMER2_CH1, TLI_B5, PB5 91 I/O I2C0_SMBA, SPI0_MOSI, I2S0_SD, I2C3_SMBA, SPI2_MOSI, I2S2_SD, SPI5_MOSI, I2S5_SD, CAN1_RX, USBHS0_ULPI_D7, ETH0_PPS_OUT, EXMC_SDCKE1, DCI_D10, UART4_RX, EVENTOUT Default: PB6 Alternate: TIMER15_MCH0, TIMER3_CH0, EXMC_D11, PB6 92 I/O I2C0_SCL, I2C3_SCL, USART0_TX, CAN1_TX, OSPIM_P0_CSN, HPDF_DATAIN5, EXMC_SDNE1, DCI_D5, UART4_TX, EVENTOUT PB7 93 I/O Default: PB7 Alternate: TIMER16_MCH0, TIMER3_CH1, I2C0_SDA, 43 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) I2C3_SDA, USART0_RX, HPDF_CKIN5, EXMC_NL, EXMC_NADV, DCI_VSYNC, EVENTOUT Additional: PVD_IN BOOT 94 Default: BOOT I/O Default: PB8 Alternate: TIMER15_CH0, TIMER3_CH2, HPDF_CKIN7, PB8 95 I2C0_SCL, I2C3_SCL, SDIO0_CKIN, UART3_RX, I/O CAN0_RX, SDIO1_D4, SDIO0_D4, DCI_D6, TLI_B6, EVENTOUT Default: PB9 Alternate: TIMER16_CH0, TIMER3_CH3, HPDF_DATAIN7, PB9 96 I2C0_SDA, SPI1_NSS, I2S1_WS, I2C3_SDA, I/O SDIO0_CMDDIR, UART3_TX, CAN0_TX, SDIO1_D5, I2C3_SMBA, SDIO0_D5, DCI_D7, TLI_B7, EVENTOUT Default: PE0 PE0 97 Alternate: TIMER3_ETI, UART7_RX, SAI1_MCLK0, I/O EXMC_NBL0, DCI_D2, TLI_R0, EVENTOUT Default: PE1 PE1 98 Alternate: UART7_TX, EXMC_NBL1, DCI_D3, TLI_R6, I/O EVENTOUT VSS 99 P - Default: VSS VDD 100 P - Default: VDD (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 2.6.3. GD32H757Vx BGA100 pin definitions Table 2-5. GD32H757Vx BGA100 pin definitions Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PE2 PE2 A3 I/O Alternate: TRACECK, SAI0_CLK0, SPI3_SCK, SAI0_MCLK0, OSPIM_P0_IO2, EXMC_A23, EVENTOUT Default: PE3 PE3 B3 I/O Alternate: TRACED0, TIMER14_BRKIN0, SAI0_SD1, EXMC_A19, DCI_PIXCLK, EVENTOUT Default: PE4 PE4 C3 I/O Alternate: TRACED1 , TIMER0_BRKIN1, SAI0_DAT1, HPDF_DATAIN3, TIMER14_MCH0, SPI3_NSS, SAI0_FS0, EXMC_A20, DCI_D4, TLI_B0, EVENTOUT Default: PE5 PE5 D3 I/O Alternate: TRACED2 , SAI0_CLK1, HPDF_CKIN3, TIMER14_CH0 , SPI3_MISO, SAI0_SCK0, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT 44 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PE6 Alternate: TRACED3 , TIMER0_BRKIN2, SAI0_DAT0, PE6 E3 TIMER14_CH1 , SPI3_MOSI, SAI0_SD0 , SAI1_MCLK1, I/O CMP_MUX_OUT3, EXMC_A22, DCI_D7, TLI_G1, EVENTOUT VSS C2 P - Default: VSS VDD D2 P - Default: VDD VBAT B2 P - Default: VBAT PC13 A2 I/O Default: PC13 Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_TS, WKUP3, RTC_OUT PC14OSC32IN Default: PC14 A1 Alternate: EVENTOUT I/O Additional: OSC32IN PC15OSC32OU Default: PC15 B1 Alternate: EVENTOUT I/O Additional: OSC32OUT T PH0OSCIN PH1OSCOUT NRST Default: PH0 C1 Alternate: EVENTOUT I/O Additional: OSCIN Default: PH1 D1 Alternate: EVENTOUT I/O Additional: OSCOUT E1 - - Default: NRST Default: PC0 Alternate: EXMC_D12, HPDF_CKIN0, HPDF_DATAIN4, PC0 F1 TIMER40_CH0, SAI1_FS1, EXMC_A25, I/O USBHS0_ULPI_STP, TLI_G2, EXMC_SDNWE, TRIGSEL_IN8, TLI_R5, EVENTOUT Additional: ADC012_IN10 Default: PC1 Alternate: TRACED0, SAI0_DAT0, HPDF_DATAIN0, PC1 F2 HPDF_CKIN4, SPI1_MOSI, I2S1_SD, SAI0_SD0, I/O TIMER40_MCH0, SDIO1_CK, OSPIM_P0_IO4, ETH0_MDC, MDC, TRIGSEL_IN9, TLI_G5, EVENTOUT Additional: ADC012_IN11, RTC_TAMP2, WKUP5 Default: PC2_C PC2_C E2 I/O PC3_C F3 I/O VDD K1 P - Default: VDD VSS J1 P - Default: VSS VSSA G1 P - Default: VSSA VDDA H1 P - Default: VDDA PA0 G2 I/O Additional: ADC2_IN0 Default: PC3_C Additional: ADC2_IN1 Default: PA0 45 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, TIMER14_BRKIN0, SPI5_NSS, I2S5_WS, OSPIM_P0_IO6, USART1_CTS, UART3_TX, SDIO1_CMD, SAI1_SD1, EXMC_A19, TRIGSEL_IN0, EVENTOUT Additional: ADC0_IN16, WKUP0 Default: PA1 Alternate: TIMER1_CH1, TIMER4_CH1, TIMER14_MCH0, PA1 H2 USART1_RTS, USART1_DE, UART3_RX, OSPIM_P0_IO3, I/O SAI1_MCLK1, ETH0_RMII_REF_CLK, TRIGSEL_IN1, TLI_R2, EVENTOUT Additional: ADC0_IN17 Default: PA2 Alternate: TIMER1_CH2, TIMER4_CH2, TIMER14_CH0, PA2 J2 OSPIM_P0_IO0, USART1_TX, SAI1_SCK1, ETH0_MDIO, I/O MDIO, TRIGSEL_IN7 , TLI_R1, EVENTOUT Additional: ADC01_IN14, WKUP1 Default: PA3 Alternate: TIMER1_CH3, TIMER4_CH3, TIMER14_CH1, PA3 K2 I2S5_MCK, OSPIM_P0_IO2, USART1_RX, TLI_B2, I/O USBHS0_ULPI_D0, OSPIM_P0_SCK, TRIGSEL_IN4, TLI_B5, EVENTOUT Additional: ADC01_IN15 VDD F4 P - Default: VDD Default: PA4 Alternate: TIMER4_ETI, SPI0_NSS, I2S0_WS, SPI2_NSS, PA4 G3 I/O I2S2_WS, USART1_CK, SPI5_NSS, I2S5_WS, EXMC_D8, DCI_HSYNC, TLI_VSYNC, EVENTOUT Additional: ADC01_IN18, DAC0_OUT0 Default: PA5 Alternate: TIMER1_CH0, TIMER1_ETI, TIMER7_MCH0, PA5 H3 I/O SPI0_SCK, I2S0_CK, SPI5_SCK, I2S5_CK, USBHS0_ULPI_CK, MDIO_A0, EXMC_D9, TLI_R4, EVENTOUT Additional: ADC01_IN19, DAC0_OUT1 Default: PA6 Alternate: TIMER0_BRKIN0, TIMER2_CH0, PA6 J3 I/O TIMER7_BRKIN0, SPI0_MISO, OSPIM_P0_IO3, SPI5_MISO, CMP_MUX_OUT0, MDIO_MDC, DCI_PIXCLK, TLI_G2, EVENTOUT Additional: ADC01_IN3 Default: PA7 Alternate: TIMER0_MCH0, TIMER2_CH1, TIMER7_MCH0, PA7 K3 I/O SPI0_MOSI, I2S0_SD, SPI5_MOSI, I2S5_SD, OSPIM_P0_IO2, ETH0_RMII_CRS_DV, EXMC_SDNWE, TRIGSEL_IN5, TLI_VSYNC, EVENTOUT Additional: ADC01_IN7 46 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PC4 Alternate: PMU_DEEPSLEEP, EXMC_A22, HPDF_CKIN2, PC4 G4 I2S0_MCK, TIMER41_CH0, RSPDIF_CH2, SDIO1_CKIN, I/O ETH0_RMII_RXD0, EXMC_SDNE0, TLI_R7, EVENTOUT Additional: ADC01_IN4, CMP0_IM7 Default: PC5 Alternate: PMU_SLEEP, SAI0_DAT2, HPDF_DATAIN2, PC5 H4 TIMER41_MCH0, RSPDIF_CH3, ETH0_RMII_RXD1, I/O EXMC_SDCKE0, CMP0_OUT, TLI_DE, EVENTOUT Additional: ADC01_IN8 Default: PB0 Alternate: TIMER0_MCH1, TIMER2_CH2, TIMER7_MCH1, PB0 J4 OSPIM_P0_IO1, HPDF_CKOUT, UART3_CTS, TLI_R3, I/O USBHS0_ULPI_D1, MDIO_A1, TRIGSEL_OUT3, TLI_G1, EVENTOUT Additional: ADC01_IN9, CMP0_IP0 Default: PB1 Alternate: TIMER0_MCH2, TIMER2_CH3, TIMER7_MCH2, PB1 K4 OSPIM_P0_IO0, HPDF_DATAIN1, TLI_R6, I/O USBHS0_ULPI_D2, MDIO_A2, TRIGSEL_OUT4, TLI_G0, EVENTOUT Additional: ADC01_IN5, CMP0_IM6 Default: PB2 Alternate: RTC_OUT, SAI0_DAT0, EXMC_D10, PB2 G5 HPDF_CKIN1, SAI0_SD0, SPI2_MOSI, I2S2_SD, I/O OSPIM_P0_SCK, EXMC_NCE, MDIO_A3, TIMER22_ETI, EVENTOUT Additional: CMP0_IP1 VDD F5 P - Default: VDD Default: PE7 PE7 H5 I/O Alternate: TIMER0_ETI, HPDF_DATAIN2, UART6_RX, OSPIM_P0_IO4, EXMC_D4, EVENTOUT Additional: CMP1_IM7 Default: PE8 PE8 J5 I/O Alternate: TIMER0_MCH0, HPDF_CKIN2, UART6_TX, OSPIM_P0_IO5, EXMC_D5, CMP1_OUT, EVENTOUT Default: PE9 Alternate: TIMER0_CH0, HPDF_CKOUT, SPI3_IO2, PE9 K5 I/O UART6_RTS, UART6_DE, OSPIM_P0_IO6, EXMC_D6, EVENTOUT Additional: CMP1_IP0 Default: PE10 PE10 G6 I/O Alternate: TIMER0_MCH1, HPDF_DATAIN4, SPI3_IO3, UART6_CTS, OSPIM_P0_IO7, EXMC_D7, EVENTOUT Additional: CMP1_IM6 PE11 H6 I/O Default: PE11 47 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TIMER0_CH1, HPDF_CKIN4, SPI3_NSS, SAI1_SD1, OSPIM_P0_CSN, EXMC_D8, TLI_G3, EVENTOUT Additional: CMP1_IP1 Default: PE12 PE12 J6 Alternate: TIMER0_MCH2, HPDF_DATAIN5, SPI3_SCK, I/O SAI1_SCK1, EXMC_D9, CMP0_OUT, TLI_B4, EVENTOUT Default: PE13 PE13 K6 Alternate: TIMER0_CH2, HPDF_CKIN5, SPI3_MISO, I/O SAI1_FS1, EXMC_D10, CMP1_OUT, TLI_DE, EVENTOUT Default: PE14 PE14 G7 Alternate: TIMER0_CH3, SPI3_MOSI, SAI1_MCLK1, I/O EXMC_D11, TLI_PIXCLK, EVENTOUT Default: PE15 PE15 H7 Alternate: TIMER0_BRKIN0, TLI_HSYNC, EXMC_D12, I/O CMP_MUX_OUT4, TLI_R7, EVENTOUT Default: PB10 PB10 J7 Alternate: TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I/O HPDF_DATAIN7, USART2_TX, OSPIM_P0_NCS, USBHS0_ULPI_D3, TRIGSEL_OUT2, TLI_G4, EVENTOUT Default: PB11 PB11 K7 Alternate: TIMER1_CH3, I2C1_SDA, HPDF_CKIN7, I/O USART2_RX, USBHS0_ULPI_D4, ETH0_RMII_TX_EN, TLI_G5, EVENTOUT VCORE F8 P - Default: VCORE Default: PB12 Alternate: TIMER0_BRKIN0, I2C1_SMBA, SPI1_NSS, PB12 K8 I/O 5VT I2S1_WS, HPDF_DATAIN1, USART2_CK, CAN1_RX, USBHS0_ULPI_D5, ETH0_RMII_TXD0, OSPIM_P0_IO0, CMP_MUX_OUT2, UART4_RX, EVENTOUT Default: PB13 Alternate: RTC_REFIN, TIMER0_MCH0, OSPIM_P0_IO2, PB13 J8 I/O 5VT SPI1_SCK, I2S1_CK, HPDF_CKIN1, USART2_CTS, CAN1_TX, USBHS0_ULPI_D6, ETH0_RMII_TXD1, SDIO0_D0, DCI_D2, UART4_TX, EVENTOUT Default: PB14 Alternate: TIMER0_MCH1, TIMER7_MCH1, USART0_TX, PB14 H10 I/O SPI1_MISO, HPDF_DATAIN2, USART2_RTS, USART2_DE, UART3_RTS, UART3_DE, SDIO1_D0, EXMC_D10, TRIGSEL_OUT1, TLI_PIXCLK, EVENTOUT Default: PB15 Alternate: RTC_REFIN, TIMER0_MCH2, TIMER7_MCH2, PB15 G10 I/O USART0_RX, SPI1_MOSI, I2S1_SD, HPDF_CKIN2, UART3_CTS, SDIO1_D1, EXMC_D11, TRIGSEL_OUT5, TLI_G7, EVENTOUT PD8 K9 I/O Default: PD8 48 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: HPDF_CKIN3, USART2_TX, SAI1_CLK0, RSPDIF_CH1, EXMC_D13, EVENTOUT Default: PD9 PD9 J9 Alternate: HPDF_DATAIN3, USART2_RX, SAI1_CLK1, I/O EXMC_D14, EVENTOUT Default: PD10 PD10 H9 Alternate: HPDF_CKOUT, USART2_CK, SAI1_DAT1, I/O EXMC_D15, TLI_B3, EVENTOUT Default: PD11 PD11 G9 Alternate: TIMER40_CH1, TIMER7_MCH3, I2C3_SMBA, I/O USART2_CTS, SAI1_DAT2, OSPIM_P0_IO0, SAI1_SD0, EXMC_A16, EXMC_CLE, EVENTOUT Default: PD12 Alternate: TIMER41_CH1, TIMER3_CH0, I2C3_SCL, PD12 K10 CAN2_RX, EDOUT_A, USART2_RTS, USART2_DE, I/O OSPIM_P0_IO1, SAI1_FS0, EXMC_A17, EXMC_ALE, DCI_D12, EVENTOUT Default: PD13 PD13 J10 Alternate: TIMER42_CH1, TIMER3_CH1, I2C3_SDA, I/O CAN2_TX, EDOUT_B, OSPIM_P0_IO3, SAI1_SCK0, EXMC_A18, DCI_D13, EVENTOUT Default: PD14 PD14 H8 Alternate: TIMER43_CH1, TIMER3_CH2, SPI3_IO2, I/O EDOUT_Z, UART7_CTS, EXMC_D0, EVENTOUT Default: PD15 PD15 G8 Alternate: TIMER44_CH1, TIMER3_CH3, SPI3_IO3, I/O UART7_RTS, UART7_DE, EXMC_D1, EVENTOUT VDD33US B F6 P - Default: VDD33USB Default: PC6 Alternate: TIMER0_BRKIN1, TIMER2_CH0, TIMER7_CH0, PC6 F10 I/O HPDF_CKIN3, I2S1_MCK, USART5_TX, SDIO0_DAT0DIR, EXMC_NWAIT, SDIO1_D6, SDIO0_D6, DCI_D0, TLI_HSYNC, EVENTOUT Default: PC7 Alternate: TIMER0_CH3, TIMER2_CH1, TIMER7_CH1, PC7 E10 I/O HPDF_DATAIN3, I2S2_MCK, USART5_RX, SDIO0_DAT123DIR, EXMC_NE0, SDIO1_D7, SDIO0_D7, DCI_D1, TLI_G6, EVENTOUT Default: PC8 PC8 F9 I/O Alternate: TRACED1, TIMER2_CH2, TIMER7_CH2, USART5_CK, UART4_RTS, UART4_DE, EXMC_NE1, EXMC_INT, SDIO0_D0, DCI_D2, EVENTOUT Default: PC9 PC9 E9 I/O Alternate: CK_OUT1, TIMER0_MCH3, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, UART4_CTS, 49 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) OSPIM_P0_IO0, TLI_G3, SDIO0_D1, DCI_D3, TLI_B2, EVENTOUT Default: PA8 PA8 D9 Alternate: CK_OUT0, TIMER0_CH0, TIMER7_BRKIN2, I/O I2C2_SCL, USART0_CK, USBHS0_SOF, UART6_RX, CMP_MUX_OUT1, TLI_B3, TLI_R6, EVENTOUT Default: PA9 PA9 C9 I/O 5VT Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, TRIGSEL_IN13, DCI_D0, TLI_R5, EVENTOUT Additional: USBHS0_VBUS Default: PA10 PA10 D10 I/O 5VT Alternate: TIMER0_CH2, USART0_RX, TRIGSEL_IN12, USBHS0_ID, MDIO, TLI_B4, DCI_D1, TLI_B1, EVENTOUT USBHS0_ DM USBHS0_ DP C10 I/O Default: USBHS0_DM B10 I/O Default: USBHS0_DP Default: JTMS, SWDIO, PA13 Alternate: TIMER0_BRKIN1, TIMER7_BRKIN1, SPI1_NSS, PA13 A10 I2S1_WS, UART3_RX, USART0_CTS, CAN0_RX, I/O MDIO_A3, EXMC_INT, TRIGSEL_IN10, TLI_R4, EVENTOUT VCORE E7 P - Default: VCORE VSS E5 P - Default: VSS Default: JTCK, SWCLK, PA14 Alternate: TLI_G7, SPI1_SCK, I2S1_CK, UART3_TX, PA14 A9 I/O USART0_RTS, USART0_DE, SAI1_FS1, CAN0_TX, MDIO_A4, TIMER0_BRKIN2, TRIGSEL_IN11, TLI_R5, EVENTOUT Default: JTDI, PA15 Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, PA15 A8 I/O I2S0_WS, SPI2_NSS, I2S2_WS, SPI5_NSS, I2S5_WS, UART3_RTS, UART3_DE, TLI_R3, UART6_TX, MDIO_A0, TRIGSEL_OUT0, TLI_B6, EVENTOUT Default: PC10 Alternate: TIMER0_CH3, HPDF_CKIN5, SPI2_SCK, PC10 B9 I/O I2S2_CK, USART2_TX, UART3_TX, OSPIM_P0_IO1, TLI_B1, MDIO_A1, SDIO0_D2, DCI_D8, TLI_R2, EVENTOUT Default: PC11 PC11 B8 I/O Alternate: TIMER0_ETI, HPDF_DATAIN5, SPI2_MISO, USART2_RX, UART3_RX, OSPIM_P0_CSN, EXMC_NBL2, MDIO_A2, SDIO0_D3, DCI_D4, TLI_B4, EVENTOUT PC12 C8 I/O Default: PC12 50 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: TRACED3, EXMC_D6, TIMER14_CH0, SPI5_SCK, I2S5_CK, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO0_CK, DCI_D9, TLI_R6, EVENTOUT Default: PD0 PD0 D8 Alternate: TIMER7_CH2, HPDF_CKIN6, UART3_RX, I/O CAN0_RX, EXMC_D2, TRIGSEL_IN3, TLI_B1, EVENTOUT Default: PD1 PD1 E8 Alternate: HPDF_DATAIN6, UART3_TX, CAN0_TX, I/O EXMC_D3, TRIGSEL_IN6, EVENTOUT Default: PD2 PD2 B7 Alternate: TRACED2, EXMC_D7, TIMER2_ETI, I/O TIMER14_BRKIN0, UART4_RX, TLI_B7, SDIO0_CMD, DCI_D11, TLI_B2, EVENTOUT Default: PD3 PD3 C7 Alternate: HPDF_CKOUT, SPI1_SCK, I2S1_CK, I/O USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT Default: PD4 PD4 D7 Alternate: TIMER7_MCH3, USART1_RTS, USART1_DE, I/O OSPIM_P0_IO4, EXMC_NOE, EVENTOUT Default: PD5 PD5 B6 Alternate: TIMER7_CH3, USART1_TX, OSPIM_P0_IO5, I/O EXMC_NWE, EVENTOUT Default: PD6 Alternate: SAI1_DAT0, SAI0_DAT0, HPDF_CKIN4, PD6 C6 HPDF_DATAIN1, SPI2_MOSI, I2S2_SD, SAI0_SD0, I/O USART1_RX, OSPIM_P0_IO6, SDIO1_CK, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT Default: PD7 Alternate: HPDF_DATAIN4, SPI0_MOSI, I2S0_SD, PD7 D6 HPDF_CKIN1, USART1_CK, RSPDIF_CH0, I/O OSPIM_P0_IO7, SDIO1_CMD, EXMC_NE0, EXMC_NCE, EVENTOUT VSS E6 P - Default: VSS Default: JTDO, PB3 Alternate: TRACESWO, TIMER1_CH1, TLI_PIXCLK, PB3 A7 I/O SPI0_SCK, I2S0_CK, SPI2_SCK, I2S2_CK, SPI5_SCK, I2S5_CK, SDIO1_D2, CTC_SYNC, UART6_RX, MDIO_A4, TRIGSEL_OUT7, TIMER23_ETI, EVENTOUT Default: NJTRST, PB4 PB4 A6 I/O Alternate: TIMER15_BRKIN0, TIMER2_CH0, SPI0_MISO, SPI2_MISO, SPI1_NSS, I2S1_WS, SPI5_MISO, SDIO1_D3, UART6_TX, TRIGSEL_OUT6, EVENTOUT Default: PB5 PB5 C5 I/O Alternate: TIMER16_BRKIN0, TIMER2_CH1, TLI_B5, I2C0_SMBA, SPI0_MOSI, I2S0_SD, I2C3_SMBA, 51 GD32H757xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) SPI2_MOSI, I2S2_SD, SPI5_MOSI, I2S5_SD, CAN1_RX, USBHS0_ULPI_D7, ETH0_PPS_OUT, EXMC_SDCKE1, DCI_D10, UART4_RX, EVENTOUT Default: PB6 Alternate: TIMER15_MCH0, TIMER3_CH0, EXMC_D11, PB6 B5 I2C0_SCL, I2C3_SCL, USART0_TX, CAN1_TX, I/O OSPIM_P0_CSN, HPDF_DATAIN5, EXMC_SDNE1, DCI_D5, UART4_TX, EVENTOUT Default: PB7 Alternate: TIMER16_MCH0, TIMER3_CH1, I2C0_SDA, PB7 A5 I2C3_SDA, USART0_RX, HPDF_CKIN5, EXMC_NL, I/O EXMC_NADV, DCI_VSYNC, EVENTOUT Additional: PVD_IN BOOT D5 Default: BOOT I/O Default: PB8 Alternate: TIMER15_CH0, TIMER3_CH2, HPDF_CKIN7, PB8 B4 I2C0_SCL, I2C3_SCL, SDIO0_CKIN, UART3_RX, I/O CAN0_RX, SDIO1_D4, SDIO0_D4, DCI_D6, TLI_B6, EVENTOUT Default: PB9 Alternate: TIMER16_CH0, TIMER3_CH3, HPDF_DATAIN7, PB9 A4 I2C0_SDA, SPI1_NSS, I2S1_WS, I2C3_SDA, I/O SDIO0_CMDDIR, UART3_TX, CAN0_TX, SDIO1_D5, I2C3_SMBA, SDIO0_D5, DCI_D7, TLI_B7, EVENTOUT Default: PE0 PE0 D4 Alternate: TIMER3_ETI, UART7_RX, SAI1_MCLK0, I/O EXMC_NBL0, DCI_D2, TLI_R0, EVENTOUT Default: PE1 PE1 C4 Alternate: UART7_TX, EXMC_NBL1, DCI_D3, TLI_R6, I/O EVENTOUT VSS E4 P - Default: VSS PDR_ON F7 P - Default: PDR_ON Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 52 GD32H757xx Datasheet 2.6.4. GD32H757xx pin alternate functions Table 2-6. Port A alternate functions summary Pin Name AF0 AF1 AF2 PA0 TIMER1_CH0 TIMER4_ /TIMER1_ETI CH0 PA1 TIMER1_CH1 PA2 TIMER1_CH2 TIMER4_ CH1 TIMER4_ CH2 TIMER4_ TIMER1_CH3 CH3 PA3 TIMER4_ ETI PA4 TIMER1_CH0 /TIMER1_ETI PA5 PA6 TIMER0_BR TIMER2_ KIN0 CH0 PA7 TIMER0_MC TIMER2_ H0 CH1 PA8 CK_OUT TIMER0_CH0 0 PA9 TIMER0_CH1 PA10 TIMER0_CH2 PA13 JTMS/S WDIO PA14 JTCK/S WCLK TIMER0_BR KIN1 AF3 AF4 AF5 AF6 AF7 SPI5_N TIMER7_E TIMER14_ OSPIM_P0_I USART1_ SS/I2S5 TI BRKIN0 O6 CTS _WS USART1_ TIMER14_ RTS/USA MCH0 RT1_DE TIMER14_ OSPIM_P0_I USART1_ CH0 O0 TX TIMER14_ I2S5_M OSPIM_P0_I USART1_ CH1 CK O2 RX SPI0_N SPI2_NSS/I2 USART1_ SS/I2S0 S2_WS CK _WS SPI0_S TIMER7_ CK/I2S0 MCH0 _CK TIMER7_B SPI0_MI OSPIM_P0_I RKIN0 SO O3 SPI0_M TIMER7_ OSI/I2S MCH0 0_SD TIMER7_B I2C2_SCL RKIN2 AF8 AF9 USART0_ TX TLI_G7 SPI1_N SS/I2S1 UART3_RX _WS SPI1_S CK/I2S1 UART3_TX _CK USART0_ CTS AF12 SAI1_SCK 1 ETH0_MDIO TLI_B2 AF13 AF14 EXMC_A TRIGSEL_ 19 IN0 UART3_R OSPIM_P SAI1_MCL ETH0_RMII X 0_IO3 K1 _REF_CLK USBHS0_ ULPI_D0 SPI5_NSS /I2S5_WS AF15 EVENTOUT TRIGSEL_ TLI_R2 IN1 TRIGSEL_ TLI_R1 IN7 OSPIM_ TRIGSEL_ TLI_B5 P0_SCK IN4 MDIO EVENTOUT EVENTOUT EVENTOUT EXMC_D DCI_HSY TLI_VS EVENTOUT 8 NC YNC SPI5_SCK /I2S5_CK USBHS0_ ULPI_CK SPI5_MIS O SPI5_MO SI/I2S5_S D CMP_MU MDIO_MDC X_OUT0 MDIO_A0 EXMC_D 9 TLI_R4 EVENTOUT DCI_PIXC TLI_G2 EVENTOUT LK OSPIM_P ETH0_RMII EXMC_S TRIGSEL_ TLI_VS EVENTOUT 0_IO2 _CRS_DV DNWE IN5 YNC CMP_M USBHS0_ UART6_RX UX_OUT SOF 1 TRIGSEL_ IN13 USART0_ RX TIMER7_B RKIN1 AF11 UART3_T SDIO1_C SAI1_SD1 X MD USART0_ CK SPI1_S I2C2_SMB CK/I2S1 A _CK AF10 USBHS0_I D MDIO TLI_B4 TLI_B3 TLI_R6 EVENTOUT DCI_D0 TLI_R5 EVENTOUT DCI_D1 TLI_B1 EVENTOUT CAN0_RX MDIO_A3 EXMC_I TRIGSEL_ TLI_R4 NT IN10 EVENTOUT USART0_ RTS/USA SAI1_FS1 CAN0_TX RT0_DE MDIO_A4 TIMER0_ TRIGSEL_ TLI_R5 BRKIN2 IN11 EVENTOUT 53 GD32H757xx Datasheet Pin Name PA15 AF0 JTDI AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 SPI0_N UART3_R SPI2_NSS/I2 SPI5_NSS SS/I2S0 TS/UART3 S2_WS /I2S5_WS _WS _DE TIMER1_CH0 /TIMER1_ETI AF9 AF10 TLI_R3 AF11 UART6_TX AF12 AF13 AF14 MDIO_A TRIGSEL_ TLI_B6 0 OUT0 AF15 EVENTOUT Table 2-7. Port B alternate functions summary Pin Name PB0 PB1 PB2 PB3 PB4 AF0 AF1 AF2 AF3 AF4 TIMER0_ TIMER2_C TIMER7_ OSPIM_P MCH1 H2 MCH1 0_IO1 TIMER0_ TIMER2_C TIMER7_ OSPIM_P MCH2 H3 MCH2 0_IO0 SAI2_DAT SAI0_DAT EXMC_D1 HPDF_CKI RTC_OUT 0(1) 0 0 N1 AF5 AF6 SAI0_SD0 JTDO/TRA TIMER1_C TLI_PIXCL CESWO H1 K SPI0_SCK SPI2_SCK /I2S0_CK /I2S2_CK TIMER15_ TIMER2_C BRKIN0 H0 SPI0_MIS SPI2_MIS O O SPI0_MO I2C0_SMB I2C3_SMB SI/ A A I2S0_SD NJTRST PB5 TIMER16_ TIMER2_C BRKIN0 H1 PB6 TIMER15_ TIMER3_C EXMC_D1 I2C0_SCL MCH0 H0 1 I2C3_SCL PB7 TIMER16_ TIMER3_C MCH0 H1 I2C3_SDA PB8 PB9 PB10 PB11 PB12 PB13 PB14 TLI_B5 I2C0_SDA AF7 HPDF_CK OUT HPDF_DA TAIN1 AF8 UART3_ CTS AF9 TLI_R3 TLI_R6 SPI2_MOSI SAI2_SD /I2S2_SD 0(1) SPI5_SC K/I2S5_C K SPI1_NSS/I SPI5_MI 2S1_WS SO SPI5_MO SPI2_MOSI SI/I2S5_ /I2S2_SD SD USART0_T X OSPIM_P 0_SCK SDIO1_D2 SDIO1_D3 CAN1_RX CAN1_TX USART0_R X TIMER15_ TIMER3_C HPDF_CKI SDIO0_CKI I2C0_SCL I2C3_SCL CH0 H2 N7 N TIMER16_ TIMER3_C HPDF_DA SPI1_NSS SDIO0_CM I2C0_SDA I2C3_SDA CH0 H3 TAIN7 /I2S1_WS DDIR TIMER1_C SPI1_SCK HPDF_DA USART2_T I2C1_SCL H2 /I2S1_CK TAIN7 X TIMER1_C HPDF_CKI USART2_R I2C1_SDA H3 N7 X TIMER0_B I2C1_SMB SPI1_NSS HPDF_DA USART2_C RKIN0 A /I2S1_WS TAIN1 K RTC_REFI TIMER0_ OSPIM_P SPI1_SCK HPDF_CKI USART2_C N MCH0 0_IO2 /I2S1_CK N1 TS USART2_R TIMER0_ TIMER7_ USART0_ SPI1_MIS HPDF_DA TS/USART MCH1 MCH1 TX O TAIN2 2_DE UART3_ CAN0_RX RX UART3_T CAN0_TX X OSPIM_P 0_NCS CAN1_RX CAN1_TX UART3_ RTS/UAR SDIO1_D0 T3_DE AF10 USBHS0_ ULPI_D1 USBHS0_ ULPI_D2 AF11 AF12 AF13 AF14 AF15 MDIO_A TRIGSEL_ TLI_G1 EVENTOUT 1 OUT3 MDIO_A TRIGSEL_ TLI_G0 EVENTOUT 2 OUT4 MDIO_A TIMER22_ EXMC_NCE EVENTOUT 3 ETI CTC_SYN MDIO_A TRIGSEL_ TIMER2 UART6_RX EVENTOUT C 4 OUT7 3_ETI TRIGSEL_ OUT6 UART6_TX EVENTOUT USBHS0_ ETH0_PPS_ EXMC_S UART4_ DCI_D10 EVENTOUT ULPI_D7 OUT DCKE1 RX OSPIM_P HPDF_DAT EXMC_S 0_CSN AIN5 DNE1 EXMC_N HPDF_CKIN L/EXMC 5 _NADV, SDIO0_ SDIO1_D4 D4 SDIO0_ SDIO1_D5 I2C3_SMBA D5 USBHS0_ ULPI_D3 USBHS0_ ETH0_RMII ULPI_D4 _TX_EN USBHS0_ ETH0_RMII OSPIM_ ULPI_D5 _TXD0 P0_IO0 USBHS0_ ETH0_RMII SDIO0_ ULPI_D6 _TXD1 D0 DCI_D5 UART4_ EVENTOUT TX DCI_VSY NC EVENTOUT DCI_D6 TLI_B6 EVENTOUT DCI_D7 TLI_B7 EVENTOUT TRIGSEL_ TLI_G4 EVENTOUT OUT2 TLI_G5 EVENTOUT CMP_MU UART4_ EVENTOUT X_OUT2 RX UART4_ DCI_D2 EVENTOUT TX EXMC_D TRIGSEL_ TLI_CL EVENTOUT 10 OUT1 K 54 GD32H757xx Datasheet Pin Name PB15 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SPI1_MO TIMER7_ USART0_ HPDF_CKI SI/I2S1_S MCH2 RX N2 D RTC_REFI TIMER0_ N MCH2 AF8 AF9 AF10 AF11 UART3_ SDIO1_D1 CTS AF12 AF13 AF14 AF15 EXMC_D TRIGSEL_ TLI_G7 EVENTOUT 11 OUT5 Table 2-8. Port C alternate functions summary Pin Name PC0 PC1 PC4 PC5 PC6 AF0 PC9 PC10 PC11 PC12 AF2 AF3 AF4 TRACED 1 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 HPDF_CKI HPDF_DA TIMER40_C SAI1_FS USBHS0_U EXMC_SD TRIGSE EXMC_A25 TLI_G2 TLI_R5 EVENTOUT N0 TAIN4 H0 1 LPI_STP NWE L_IN8 HPDF_DAT HPDF_CKI SPI1_MOSI TIMER40_ SAI2_SD OSPIM_P0 ETH0_MD TRIGSE SAI0_SD0 SDIO1_CK MDC TLI_G5 EVENTOUT AIN0 N4 /I2S1_SD MCH0 0(1) _IO4 C L_IN9 HPDF_CKI N2 I2S0_MCK HPDF_DAT AIN2 TIMER7_C HPDF_CKI I2S1_MCK H0 N3 TIMER0_ TIMER2_C TIMER7_C HPDF_DAT CH3 H1 H1 AIN3 PC7 PC8 AF1 EXMC_D 12 TRACED SAI2_DA SAI0_DAT0 0 T0(1) PMU_DE EXMC_A EPSLEE 22 P PMU_SL SAI2_DA SAI0_DAT2 EEP T2(1) TIMER0_ TIMER2_C BRKIN1 H0 I2S2_MCK TIMER2_C TIMER7_C H2 H2 CK_OUT TIMER0_ TIMER2_C TIMER7_C I2C2_SDA I2S_CKIN 1 MCH3 H3 H3 TIMER0_ HPDF_CKI SPI2_SCK/ CH3 N5 I2S2_CK TIMER0_ HPDF_DAT SPI2_MIS ETI AIN5 O TRACED EXMC_D TIMER14_ SPI5_SCK/ SPI2_MOS 3 6 CH0 I2S5_CK I/I2S2_SD TIMER41_C H0 RSPDIF_C SDIO1_CKI ETH0_RMII EXMC_SD H2 N _RXD0 NE0 TIMER41_ MCH0 USART5_T SDIO0_D X AT0DIR SDIO0_D USART5_R AT123DI X R UART4_ USART5_C RTS/UA K RT4_DE UART4_ CTS USART2_T UART3_ X TX USART2_R UART3_ X RX USART2_C UART4_ K TX RSPDIF_C ETH0_RMII EXMC_SD CMP0_ TLI_DE EVENTOUT H3 _RXD1 CKE0 OUT EXMC_NW TLI_HS SDIO1_D6 SDIO0_D6 DCI_D0 EVENTOUT AIT YNC TLI_R7 EVENTOUT EXMC_NE SDIO1_D7 0 SDIO0_D7 DCI_D1 TLI_G6 EVENTOUT EXMC_NE EXMC_INT 1 SDIO0_D0 DCI_D2 EVENTOUT SDIO0_D1 DCI_D3 TLI_B2 EVENTOUT MDIO_A1 SDIO0_D2 DCI_D8 TLI_R2 EVENTOUT MDIO_A2 SDIO0_D3 DCI_D4 TLI_B4 EVENTOUT SDIO0_CK DCI_D9 TLI_R6 EVENTOUT OSPIM_P0 TLI_G3 _IO0 OSPIM_P0 TLI_B1 _IO1 OSPIM_P0 EXMC_NB _CSN L2 PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT 55 GD32H757xx Datasheet Table 2-9. Port D alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 PD0 TIMER7_C HPDF_CKI H2 N6 UART3_R CAN0_R X X PD1 HPDF_DA TAIN6 UART3_T CAN0_T X X PD2 TRACED2 EXMC_D TIMER2_E 7 TI TIMER14 _BRKIN0 UART4_R X SPI1_SCK/ I2S1_CK AF10 TLI_B7 USART1_ CTS AF11 AF12 AF13 AF14 AF15 EXMC_D2 TRIGSEL_ TLI_B1 IN3 EVENTOUT EXMC_D3 TRIGSEL_ IN6 EVENTOUT SDIO0_CMD DCI_D11 TLI_B2 EVENTOUT EXMC_CLK TLI_G7 EVENTOUT PD3 HPDF_CK OUT PD4 TIMER7_ MCH3 USART1_ RTS/USA RT1_DE OSPIM_P0 _IO4 EXMC_NOE EVENTOUT PD5 TIMER7_C H3 USART1_ TX OSPIM_P0 _IO5 EXMC_NWE EVENTOUT SAI1_DA HPDF_CKI HPDF_D SPI2_MOSI USART1_ SAI2_SD0 SAI0_DAT0 SAI0_SD0 (1) T0 N4 ATAIN1 /I2S2_SD RX PD6 SPI0_MOSI HPDF_CKI USART1_ /I2S0_SD N1 CK DCI_D5 OSPIM_P0 SDIO1_C EXMC_NWAI DCI_D10 _IO6 K T TLI_B2 RSPDIF_ OSPIM_P0 SDIO1_C EXMC_NE0/ CH0 _IO7 MD EXMC_NCE EVENTOUT PD7 HPDF_DA TAIN4 PD8 HPDF_CKI N3 USART2_ SAI1_CLK RSPDIF_ TX 0 CH1 EXMC_D13 EVENTOUT PD9 HPDF_DA TAIN3 USART2_ SAI1_CLK RX 1 EXMC_D14 EVENTOUT PD10 HPDF_CK OUT USART2_ SAI1_DAT CK 1 EXMC_D15 TIMER7_ I2C3_SM MCH3 BA USART2_ SAI1_DAT OSPIM_ SAI1_SD0 CTS 2 P0_IO0 EXMC_A16/ EXMC_CLE EVENTOUT TLI_B3 EVENTOUT PD11 TIMER40_ CH1 PD12 TIMER41_ CH1 TIMER3_C H0 USART2_ I2C3_SC CAN2_RX EDOUT_A RTS/USA L RT2_DE OSPIM_ P0_IO1 SAI1_FS0 EXMC_A17/ EXMC_ALE DCI_D12 EVENTOUT PD13 TIMER42_ CH1 TIMER3_C H1 I2C3_SD A OSPIM_ SAI1_SCK P0_IO3 0 EXMC_A18 DCI_D13 EVENTOUT PD14 TIMER43_ CH1 TIMER3_C H2 SPI3_IO2 PD15 TIMER44_ CH1 TIMER3_C H3 SPI3_IO3 CAN2_TX EDOUT_B EDOUT_Z EVENTOUT UART7_C TS EXMC_D0 EVENTOUT UART7_R TS/UART7 _DE EXMC_D1 EVENTOUT 56 GD32H757xx Datasheet Table 2-10. Port E alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 TIMER3_E TI PE0 PE1 PE2 TRACECK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 PE6 TRACED3 AF8 AF14 AF15 EXMC_NB DCI_D2 L0 TLI_R0 EVENTOUT UART7_T X EXMC_NB DCI_D3 L1 TLI_R6 EVENTOUT SAI2_MCL OSPIM_ SAI2_CLK0 (1) K0(1) P0_IO2 EXMC_A23 UART7_R X SPI3_SC SAI0_MCL K K0 SAI0_CLK0 TIMER14_ BRKIN0 AF9 AF10 SAI1_MCL K0 SAI2_SD1 SAI0_SD1 AF11 AF12 EXMC_A19 (1) TIMER0_ HPDF_DAT TIMER14_ SPI3_NS SAI0_DAT1 SAI0_FS0 BRKIN1 AIN3 MCH0 S SAI2_FS0 SAI2_DAT1 (1) (1) SAI0_CLK1 HPDF_CKI TIMER14_ SPI3_MI SAI0_SCK N3 CH0 SO 0 SAI2_SCK 0(1) SAI2_CLK1 TIMER0_ SAI0_DAT0 BRKIN2 TIMER14_ SPI3_MO SAI0_SD0 CH1 SI AF13 EVENTOUT DCI_PIX CLK EVENTOUT EXMC_A20 DCI_D4 TLI_B0 EVENTOUT EXMC_A21 DCI_D6 TLI_G0 EVENTOUT SAI2_SD0 SAI2_DA SAI1_MCL CMP_MUX EXMC_A22 DCI_D7 (1) T0 K1 _OUT3 TLI_G1 EVENTOUT (1) PE7 TIMER0_ ETI HPDF_DAT AIN2 UART6_R X OSPIM_P0 _IO4 EXMC_D4 PE8 TIMER0_ MCH0 HPDF_CKI N2 UART6_T X OSPIM_P0 _IO5 EXMC_D5 PE9 TIMER0_ CH0 HPDF_CK OUT SPI3_IO2 UART6_R TS/UART 6_DE OSPIM_P0 _IO6 EXMC_D6 EVENTOUT PE10 TIMER0_ MCH1 HPDF_DAT AIN4 SPI3_IO3 UART6_C TS OSPIM_P0 _IO7 EXMC_D7 EVENTOUT PE11 TIMER0_ CH1 HPDF_CKI N4 SPI3_NS S SAI1_SD1 OSPIM_P0 EXMC_D8 _CSN PE12 TIMER0_ MCH2 HPDF_DAT AIN5 SPI3_SC K SAI1_SCK 1 EXMC_D9 CMP0_O UT PE13 TIMER0_ CH2 HPDF_CKI N5 SPI3_MI SO SAI1_FS1 EXMC_D10 PE14 TIMER0_ CH3 SPI3_MO SI SAI1_MCL K1 EXMC_D11 PE15 TIMER0_ BRKIN0 TLI_HSYN C EXMC_D12 EVENTOUT CMP1_O UT EVENTOUT TLI_G3 EVENTOUT TLI_B4 EVENTOUT CMP1_O TLI_DE UT EVENTOUT TLI_PIXC EVENTOUT LK CMP_MU TLI_R7 X_OUT4 EVENTOUT 57 GD32H757xx Datasheet Table 2-11. Port F alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 PF0 USBHS0_ I2C1_SDA ULPI_D4 OSPIM_P 1_IO0 TIMER22_ EXMC_A0 CH0 EVENTOUT PF1 I2C1_SCL USBHS0_ ULPI_D5 OSPIM_P 1_IO1 EXMC_A1 TIMER22_ CH1 EVENTOUT PF2 I2C1_SMB USBHS0_ A ULPI_D6 OSPIM_P 1_IO2 EXMC_A2 TIMER22_ CH2 EVENTOUT OSPIM_P 1_IO3 EXMC_A3 TIMER22_ CH3 EVENTOUT PF3 PF4 TIMER0_ MCH1 TIMER7_ USART0_ MCH1 TX USART2_ UART3_R HPDF_DA OSPIM_P SDIO1_D RTS/USA TS/UART3 TAIN2 1_SCK 0 RT2_DE _DE EXMC_A4 TRIGSEL_ TLI_PIX EVENTOUT OUT1 CLK PF5 TIMER0_ MCH2, TIMER7_ USART0_ MCH2 RX HPDF_CKI N2 UART3_C TS SDIO1_D 1 EXMC_A5 TRIGSEL_ TLI_G7 EVENTOUT OUT5 PF6 TIMER15_ CAN2_RX CH0 SPI4_NSS SAI0_SD1 UART6_R SAI2_SD1 X OSPIM_P 0_IO3 EXMC_D2 TIMER22_ 4 CH0 EVENTOUT PF7 TIMER16_ CAN2_TX CH0 SPI4_SCK SAI0_MCL UART6_T SAI2_MCL K1 X K1 OSPIM_P 0_IO2 EXMC_D2 TIMER22_ 5 CH1 EVENTOUT PF8 TIMER15_ MCH0 UART6_R SPI4_MIS SAI0_SCK SAI2_SCK TS/UART6 O 1 1 _DE OSPIM_P 0_IO0 EXMC_D2 TIMER22_ 6 CH2 EVENTOUT PF9 TIMER16_ MCH0 SPI4_MO UART6_C SAI0_FS1 SAI2_FS1 SI TS OSPIM_P 0_IO1 EXMC_D2 TIMER22_ 7 CH3 EVENTOUT PF10 TIMER15_ SAI0_DAT BRKIN0 2 OSPIM_P SAI2_DA 0_SCK T2 SPI4_MO SI PF11 PF12 SAI1_SD 1 DCI_D11 TLI_DE EVENTOUT EXMC_SD TIMER2 DCI_D12 EVENTOUT NRAS 3_CH0 EXMC_A6 TIMER2 EVENTOUT 3_CH1 PF13 HPDF_DA I2C3_SMB TAIN6 A EXMC_A7 TIMER2 EVENTOUT 3_CH2 PF14 HPDF_CKI I2C3_SCL SPI4_IO2 N6 EXMC_A8 TIMER2 EVENTOUT 3_CH3 PF15 I2C3_SDA SPI4_IO3 EXMC_A9 EVENTOUT 58 GD32H757xx Datasheet Table 2-12. Port G alternate functions summary Pin Name PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 TIMER31_ CH0 TIMER31_ CH1 TIMER0_B TIMER7_B TIMER31_ SPI1_MISO RKIN1 RKIN0 CH2 TIMER7_B TIMER31_ SPI1_MOSI RKIN2 CH3 /I2S1_SD TIMER0_B TIMER7_B TIMER31_ RKIN2 RKIN1 ETI TIMER0_E TIMER30_ TI CH0 TIMER16_ TIMER30_ BRKIN0 CH1 EXMC_D2 TIMER30_ SAI0_MCL USART5_ 8 CH2 K0 CK USART5_ TIMER7_E TIMER30_ SPI5_NSS/ RTS/USA TI CH3 I2S5_WS RT5_DE EXMC_D3 CAN2_T TIMER7_B TIMER30_ USART5_ SPI0_MISO 0 X RKIN1 ETI RX EXMC_D3 CAN2_R OSPIM_P1 SPI0_NSS/ 1 X _IO6 I2S0_WS EXMC_ SPI0_SCK/ D29 I2S0_CK USART5_ OSPIM_P1 SPI5_MISO RTS/USA _CSN RT5_DE SPI5_SCK/ USART5_ TRACED0 I2S5_CK CTS SPI5_MOSI USART5_ TRACED1 /I2S5_SD TX USART5_ CTS AF8 AF9 AF10 AF11 OSPIM_P 1_IO4 OSPIM_P 1_IO5 CMP_MU X_OUT5 CMP_MU X_OUT6 CMP_MU X_OUT7 OSPIM_P 0_CSN AF12 AF13 ETH0_PP EXMC_SD S_OUT CLK RSPDIF_C H2 AF14 AF15 EXMC_A1 EVENTOUT 0 EXMC_A1 EVENTOUT 1 EXMC_A1 TIMER23 EVENTOUT 2 _ETI EXMC_A1 TIMER22 EVENTOUT 3 _ETI EXMC_A1 EVENTOUT 4 EXMC_A1 EVENTOUT 5 EXMC_NE DCI_D12 TLI_R7 EVENTOUT 2 TLI_PIXC EXMC_INT DCI_D13 EVENTOUT LK TLI_G7 EVENTOUT RSPDIF_C OSPIM_P SDIO1_D EXMC_NE DCI_VSY SAI1_FS1 H3 0_IO6 0 1 NC SDIO1_D EXMC_NE TLI_G3 SAI1_SD1 DCI_D2 1 2 RSPDIF_C OSPIM_P ETH0_RM SDIO1_D2 DCI_D3 H0 1_IO7 II_TX_EN TLI_B2 EVENTOUT TLI_B3 EVENTOUT RSPDIF_C H1 TLI_B1 EVENTOUT TLI_R0 EVENTOUT TLI_B0 EVENTOUT TLI_B4 SDIO1_D3 ETH0_RM EXMC_NE TIMER22 II_TXD1 3 _CH0 TIMER44_ /ETH0_R EXMC_A2 TIMER22 SDIO1_D6 CH0 MII_TXD0 4 _CH1 TIMER44_ OSPIM_P ETH0_RM EXMC_A2 TIMER22 SDIO1_D7 MCH0 0_IO7 II_TXD1 5 _CH2 TIMER44_ EXMC_SD DCI_D13 BRKIN0 NCAS EVENTOUT EVENTOUT Table 2-13. Port H alternate functions summary Pin Name PH0 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 EVENTOUT 59 GD32H757xx Datasheet Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PH1 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 EVENTOUT Notes: (1) Functions are available on GD32H757Zx devices only. 60 GD32H757xx Datasheet 3. Functional description 3.1. Arm® Cortex®-M7 core The Arm® Cortex®-M7 processor is a highly efficient high-performance, embedded processor that features low interrupt latency, low-cost debug, and has backwards compatibility with existing Cortex-M profile processors. The processor has an in-order super-scalar pipeline that means many instructions can be dual-issued, including load/load and load/store instruction pairs because of multiple memory interfaces. The Cortex-M7 is a high-performance processor, which features a 6-stage superscalar pipeline with branch prediction and an optional FPU capable of single-precision and optionally double-precision operations. The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. The interfaces that the processor supports include:  64-bit AXI4 interface  32-bit AHB master interface  32-bit AHB slave interface  64-bit instruction TCM interface  2x32-bit data TCM interfaces The processor contains the following external interfaces:  AHBP interface  AHBS interface  AHBD interface  External Private Peripheral Bus  ATB interfaces  TCM interface  Cross Trigger interface  MBIST interface  AXIM interface 32-bit Arm® Cortex®-M7 processor core  Up to 600 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated DSP instructions  24-bit SysTick timer The Cortex®-M7 processor is based on the ARMv7-M architecture and supports a powerful and scalable instruction set including general data processing I/O control tasks, advanced data processing bit field manipulations, DSP and floating point instructions. Some system peripherals listed below are also provided by Cortex®-M7:  Nested Vectored Interrupt Controller (NVIC) 61 GD32H757xx Datasheet 3.2.  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrumentation Trace Macrocell (ITM)  Embedded Trace Macrocell (ETM)  JTAG or SWD Debug Port  Trace Port Interface Unit (TPIU)  Memory Protection Unit (MPU)  Floating Point Unit (FPU), double-precision  Load Store Unit (LSU)  Data Processing Unit (DPU)  Prefetch Unit (PFU) On-chip memory  Up to 3840KB of on-chip flash memory for instruction and data  Up to 512 KB of configurable SRAM for ITCM/DTCM/AXI SRAM  Up to 512 KB of on-chip SRAM (AXI SRAM)  4KB of backup SRAM  RAM ECC monitor for each Region The GD32H757xx has up to 3840KB of on-chip flash memory for instruction and data. The flash memory consists of 3840KB main flash organized into 960 sectors with 4KB and 64KB information block. Each sector can be erased individually. The GD32H757xx series contain up to 512KB of on-chip SRAM (AXI SRAM), 4KB of backup SRAM and up to 512KB RAM shared by ITCM/DTCM/AXI SRAM. All of AHB SRAM support byte, half-word (16 bits), and word (32 bits) accesses. The on-chip SRAM (AXI SRAM) support byte, half-word (16 bits), word (32 bits) and double words (64 bits) accesses. SRAM0 and SRAM1 can be accessed by almost all AHB masters. The backup SRAM (BKPSRAM) is implemented in the backup domain, which can keep its content even when the V DD power supply is down. Table 2-2. GD32H757xx memory map shows the memory map of the GD32H757xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions. 3.3. Clock, reset and supply management  Internal 64 MHz factory-trimmed RC and external 4 to 50 MHz crystal oscillator  Internal 48 MHz RC oscillator  Low power internal 4 MHz RC oscillator  Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  1.71 to 3.6V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage 62 GD32H757xx Datasheet detector (LVD) The Clock Control Unit (CCTL) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AXI, three AHB and four APB domains. The maximum frequency of the system clock can be up to 600 MHz. The maximum frequency of the three AHB domains are 300 MHz. The maximum frequency of the four APB domains including APB1 = APB3 = PAB4 is 150 MHz and APB2 is 300 MHz. See Figure 2-5. GD32H757xx clock tree for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components except for the SW-DP controller and the Backup domain. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 1.53V and down to 1.48V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 1.71V to 3.6V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins  VSSA, VDDA range: 1.71V to 3.6V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively  VBAT range: 1.71V to 3.6V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present 3.4. Boot modes GD32H757xx supports four BOOT modes, including:  USER BOOT  SECURITY BOOT  SYSTEM BOOT  SRAM BOOT At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDR0/1 in Boot address, allowing to program any boot memory address from 0x0000 0000 to to 0x9000 0000. The boot loader is located in non-user System memory. It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PA2 and PA3), USART2 (PB10 and PB11), USBHS0 (USBHS0_DP and USBHS0_DM) and SDIO0 (PC12, PD2, PB13, PC9, PC10 and PC11) in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. 63 GD32H757xx Datasheet 3.5. Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt / event can wake up the system.  Deep-sleep mode In deep-sleep mode, all clocks in the 0.9V domain are off, and all of LPIRC4M, IRC64M, HXTAL and PLLs are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deepsleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp event, LXTAL clock stuck, the LVD \ LVD \ OVD, CMP output, LPDTS wakeup, ENET wakeup, RTC wakeup, CAN wakeup, I2C wakeup, USART0 wakeup and USBHS wakeup. When exiting the deep-sleep mode, the IRC64M is selected as the system clock.  Standby mode In standby mode, the whole 0.9V domain is power off, the LDO is shut down, and all of LPIRC4M, IRC64M, HXTAL and PLLs are disabled. The contents of SRAM and registers in 0.9V power domain are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC, the FWDGT reset, WKUP pins and LCKMD. 3.6. Electronic fuse (EFUSE)  One-time programmable nonvolatile efuse storage cells organized as 32*32 bits  Double-bit redundant backup mechanism  All bits in the efuse cannot be rollback from 1 to 0  Each bit in efuse macro can only be programmed once, and software must avoid reprogramming  Voltage range for program: 1.71~1.98 V  Voltage range for read: 0.72~1.05 V The Efuse controller has efuse macro that store system parameters. As a non-volatile unit of storage, the bit of efuse macro cannot be restored to 0 once it is programmed to 1. 3.7. Trigger selection controller (TRIGSEL)  Supports different optional trigger inputs  Trigger input source could be external input signal or output of peripheral  Trigger selection output could be for external output or peripheral 64 GD32H757xx Datasheet The trigger selection controller (TRIGSEL) allows software to select the trigger input signal for various peripherals. TRIGSEL provides a flexible mechanism for a peripheral to select different trigger inputs. It’s up to 4 trigger selection outputs could be selected for each peripheral. And every output could select from different trigger input signal. 3.8. General-purpose and alternate-function I/Os (GPIO and AFIO)  Up to 135 fast GPIOs, all mappable on 16 external interrupt lines, each pin weak pullup/pull-down function  Output push-pull/open drain enable control  Analog input/output configuration  Alternate function input/output configuration GD32H757xx is up to 113 general purpose I/O pins (GPIO), named PA0~PA10, PA13~PA15, PB0~PB15, PC0~PC15, PD0~PD15, PE0~PE15, PF0~PF15, PG0~PG15, PH0~PH1 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/Event Controller Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), input, peripheral alternate function or analog mode. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog mode. 3.9. CRC calculation unit (CRC)  Supports 7/8/16/32 bit data input  For 7(8)/16/32 bit input data length, the calculation cycles are 1/2/4 AHB clock cycles  User configurable polynomial value and size  Free 8-bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. The CRC calculation unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial. 3.10. True random number generator (TRNG)  LFSR mode and NIST mode to generate random number (National Institute of Standards and Technology) mode to generate random number  About 40 periods of TRNG_CLK are needed between two consecutive random numbers 65 GD32H757xx Datasheet in LFSR mode  32-bit random numbers are generated each time in LFSR mode  TRNG NIST mode follows the NIST SP800-90B  Support health tests recommended by the NIST SP800-90B  32-bit*4 or 32-bit*8 random numbers are generated each time in NIST mode  TRNG has the functions of startup and in-service self-check, associated with specific error flags  128-bit random value seed is generated from analog noise The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise and it has been pre-certified NIST SP800-90B. 3.11. Cryptographic Acceleration Unit (CAU)  Supports DES, TDES or AES (128, 192, or 256) algorithms  DES/TDES supports Electronic codebook (ECB) or Cipher block chaining (CBC) mode  AES supports 128bits-key, 192bits-key or 256 bits-key  Multiple modes are supported respectively in DES, TDES and AES, including Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois / counter mode (GCM), Galois message authentication code mode (GMAC), Counter with CBCMAC (CCM), Cipher Feedback mode (CFB) and Output Feedback mode(OFB)  DMA transfer for incoming and outgoing data is supported The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. DES / TDES / AES algorithms with different key sizes are supported to perform data encryption and decryption in the CAU in multiple modes. The CAU is a 32-bit peripheral, DMA transfer is supported and data can be accessed in the input and output FIFO. 3.12. Hash Acceleration Unit (HAU)  Federal Information Processing Standards Publication 180-4(FIPS PUB 180-4)  Secure Hash Standard specifications (SHA-1, SHA-224, SHA-256)  Internet Engineering Task Force Request for Comments number 1321 (IETF RFC 1321) specifications (MD5)  High performance of computation of hash algorithms  Automatic data padding to fill the 512-bit message block for digest computation.  DMA transfer is supported  Hash / HMAC process suspended mode The hash acceleration unit (HAU) is used for information security. The secure hash algorithm (SHA-1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash message authentication code (HMAC) algorithm are supported for various applications. The digest will be computed and the length is 160 / 224 / 256 / 128 bits for a message up to (264 66 GD32H757xx Datasheet - 1) bits computed by SHA-1, SHA-224, SHA-256 and MD5 algorithms respectively. In HMAC algorithm, SHA-1, SHA-224, SHA-256 or MD5 will be called twice as hash functions and authenticating messages can be produced. 3.13. Trigonometric Math Unit (TMU)  10 kinds of functions  The fixed point format is configurable  Programmable precision  CORDIC-algorithm core: circular system and hyperbolic system, rotation pattern and vectoring pattern The Trigonometric Math Unit (TMU) is a fully configurable block that execute common trigonometric and arithmetic operations. It can be used to calculate total 10 kinds of functions. The input/output data meet q1.31 or q1.15 fixed point format. 3.14. Direct memory access controller (DMA)  Two AHB master interface for transferring data, and one AHB slave interface for programming DMA  16 channels (8 for DMA0 and 8 for DMA1) and each channel are configurable  Support independent single, 4, 8, 16-beat incrementing burst memory and peripheral transfer  Support independent 8, 16, 32-bit memory and peripheral transfer  Peripherals supported: Timers, ADC, HPDF, SPI, I2C, USART, UART, DAC, I2S, RSPDIF, SAI, CAU, HAU, FAC, TMU, CAN and DCI The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory. Two AHB master interfaces and eight four-word depth 32-bit width FIFOs are presented in each DMA controller, which achieves a high DMA transmission performance. There are 16 independent channels in the DMA controller (8 for DMA0 and 8 for DMA1). Each channel is assigned a specific or multiple target peripheral devices for memory access request management. Two arbiters respectively for memory and peripheral are implemented inside to handle the priority among DMA requests. 3.15. Master direct memory access controller (MDMA)  16 channels, each channel supports software triggering and requests can be selected among any request source 67 GD32H757xx Datasheet  Support independent single, 2, 4, 8, 16, 32, 64, 128-beat incrementing burst source and destination transfer   Support three transfer modes: – Read from memory and write to memory (software triggered) – Read from peripheral and write to memory (or memory mapped peripherals) – Read from memory (or memory mapped peripherals) and write to peripheral Automatic pack / unpack of data to optimize bandwidth when the data width of the source and destination are different  34 hardware trigger sources, all channels can be connected to any hardware trigger source  Two FIFOs of 16 double word depth to maximize data bandwidth and bus utilization The master direct memory access (MDMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data. MDMA can be used in combination with a DMA controller (DMA0 or DMA1) to provide up to 16 channels. Each channel request can be selected among any request source. The built-in arbiter is used to handle priority among MDMA requests. 3.16. DMA request multiplexer (DMAMUX)  16 channels for DMAMUX request multiplexer  8 channels for DMAMUX request generator  Support 36 trigger inputs and 29 synchronization inputs DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer is used for routing a DMA request line between the peripherals / generated DMA request (from the DMAMUX request generator) and the DMA controller. Each DMAMUX request multiplexer channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. The DMA request is pending until it is served by the DMA controller which generates a DMA acknowledge signal (the DMA request signal is de-asserted). 3.17. Analog to digital converter (ADC)  14-bit ADC0 and ADC1 conversion rate is up to 4 MSPS  12-bit ADC2 conversion rate is up to 5.3 MSPS  14-bit,12-bit, 10-bit, 8-bit configurable resolution for ADC0 and ADC1  12-bit, 10-bit, 8-bit or 6-bit configurable resolution for ADC2  In ADC0 and ADC1, Oversampling ratio arbitrarily adjustable from 2x to 1024X  ADC2, Oversampling ratio arbitrarily adjustable from 2x to 256X  ADC0 and ADC1 supply requirements: 1.8V to 3.6V, and typical power supply voltage is 68 GD32H757xx Datasheet 3.3V, ADC2 supply requirements: 1.71V to 3.6V, typical power supply voltage is 3.3V  ADC input voltage range: VREFN ≤VIN ≤VREFP  Temperature sensor  Start-of-conversion can be initiated by software or TRIGSEL A 12 / 14-bit successive approximation analog-to-digital converter module (ADC) is integrated on the MCU chip. ADC0 has 20 external channels, 1 internal channel (DAC_OUT0 channel), ADC1 has 18 external channels, 3 internal channels (the battery voltage, VREFINT inputs channel and DAC_OUT1 channel), ADC2 has 17 external channels, 4 internal channels (the battery voltage, VREFINT inputs channel, tempeture sensor and high-precision tempeture sensor). After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit (LSB) alignment or the most significant (MSB) bit alignment (ADC0 / 1 are 32-bit data register, ADC2 is 16-bit data register). An on-chip hardware oversample scheme improves performances and reduces the computational burden of MCU. 3.18. Digital to analog converter (DAC)  8-bit or 12-bit resolution. Left or right data alignment  Conversion update synchronously  Conversion trigged by external triggers  Input voltage reference, VREFP  Output buffer calibration  Using sample and keep mode to reduce the power consumption  Noise wave generation (LFSR noise mode and Triangle noise mode)  Two DAC channels in concurrent mode The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be set to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability, and DAC output buffer can be calibrated to improve output accuracy. The sample and keep mode can reduce the power consumption of DAC. 3.19. Real time clock (RTC) and backup registers  Support calendar function, which can support year, month, date, day, hours, minutes, seconds and subseconds (date is the day of week and day is the day of month)  Daylight saving compensation supported, which is realized through software  External high-accurate low frequency (50Hz or 60Hz) clock used to achieve higher calendar accuracy performed by reference clock detection option function  Atomic clock adjust (max adjust accuracy is 0.95PPM) for calendar calibration performed by digital calibration function 69 GD32H757xx Datasheet  Sub-second adjustment by shift function The RTC provides a time which includes hour/minute/second/sub-second and a calendar includes year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time. The RTC is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator. 3.20. Timers and PWM generation  Two 16-bit Advanced timer (TIMER0 & TIMER7), four16-bit General-L0 timers (TIMER2, TIMER3, TIMER30, TIMER31), four 32-bit General-L0 timers (TIMER1, TIMER4, TIMER22, TIMER23), six 16-bit General-L3 timers (TIMER14, TIMER40, TIMER41, TIMER42, TIMER43, TIMER44), two16-bit General-L4 timers (TIMER15, TIMER16), two 32-bit Basic timer (TIMER5 & TIMER6) and two 64-bit Basic timer (TIMER50 & TIMER51)  Up to 70 independent channels of PWM, output compare or input capture for each general timer and external trigger input  16-bit, motor control PWM advanced timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder and nonquadrature decoder mode  24-bit SysTick timer down counter  2 watchdog timers (free watchdog timer and window watchdog timer) The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 8 independent channels can be used for input capture, output compare, PWM generation (edge-aligned or center-aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features. The general level 0 timer, can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1/4/22/23 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2/3/30/31 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. The general level 0 timer also supports an encoder interface with two inputs using quadrature decoder mode and non-quadrature decoder mode. The general level3 timer module (TIMER14/40/41/42/43/44) is a three-channel timer that supports both input capture and output compare. They can generate PWM signals to control 70 GD32H757xx Datasheet motor or be used for power management applications. The general level3 timer has a 16-bit counter that can be used as an unsigned counter. The general level4 timer module (TIMER15/16) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level4 timer has a 16-bit counter that can be used as an unsigned counter. The basic timer module(TIMER5/6/50/51) has a 32-bit or 64-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate a DMA request and a TRGO0 to connect to DAC. The GD32H757xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 32 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog timer is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 3.21.  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Universal synchronous/asynchronous receiver transmitter (USART/UART)  Programmable baud-rate generator allowing speed up to 37.5 MBits/s when the clock frequency is 300 MHz and oversampling is by 8  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4, UART6, UART7) are used to transfer data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly 71 GD32H757xx Datasheet used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. 3.22. Inter-integrated circuit (I2C)  Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode  SMBus 3.0 and PMBus 1.3 compatible  Wakeup from sleep mode and Deep-sleep mode on I2C address match The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode (up to 100KHz), fast mode (up to 400KHz) and fast mode plus (up to 1MHz) as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus). 3.23. Serial peripheral interface (SPI)  Master or slave operation with full-duplex, half-duplex or simplex mode  Separate transmit and receive 32-bit FIFO  Data frame size can be 4 to 32 bits  Hardware CRC calculation, transmission and checking  SPI TI mode supported  Multi-master or multi-slave mode function  Protect configurations and settings  Adjustable main device receiver sampling time  Configurable FIFO thresholds (data packing)  Quad-SPI configuration available in master mode (in SPI3 / 4) The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI3 and SPI4. 72 GD32H757xx Datasheet 3.24. Inter-IC sound (I2S)  Master or slave operation for transmission/reception  Four I2S standards supported: Phillips, MSB justified, LSB justified and PCM standard  Data length can be 16 bits, 24 bits or 32 bits  Channel length can be 16 bits or 32 bits  Transmission and reception use a 32 bits wide buffer  Audio sample frequency can be 8 kHz to 192 kHz using I2S clock divider  Programmable idle state clock polarity  Separate transmit and receive 32-bit FIFO The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 4-wire serial lines. GD32H757xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported. 3.25. OSPI I/O manager(OSPIM)  Supports two OSPI (single-line, two-lines, four-lines, eight-lines) interfaces  Support two ports for pin assignment  Fully programmable IO matrix, can assign pins according to function OSPIM supports OSPI pin assignment with full matrix. 3.26. Octal-SPI interface(OSPI)  Three functional modes: indirect mode, status polling mode, memory-mapped mode  Support read and write in memory-mapped mode  Support single, dual, quad and octal communication  Fully programmable command format for both indirect and memory-mapped mode  Support SDR (signal data rate) and DTR (double transfer rate, only for GD25LX512ME)  Integrated FIFO for transmission/reception  8, 16 and 32-bits data access The OSPI is a specialized interface that communicate with external memories. The interface support single, dual, quad and octal SPI flash (PSRAMS, NAND, NOR Flash, etc). 3.27. Clock phase delay module (CPDM)  Supports the input clock frequency ranges: 25 MHz ~ 208MHz  Supports up to 12 oversampling phases The Clock Phase Delay Module (CPDM) is used to delay the phase of the input clock and 73 GD32H757xx Datasheet then output the clock. When used, the application needs to first program the phase of the output clock, and then use the output clock in other peripherals to receive data. Phase delay is related to voltage and temperature and may require reconfiguration of the application and redetermination of the phase relationship between the output clock and the received data as parameters change. 3.28. Digital camera interface (DCI)  Digital video/picture capture  8/10/12/14 data width supported  High transfer efficiency with DMA interface  Video/picture crop supported  Various pixel digital encoding formats supported including YCbCr422 / RGB565 / YUV420 / Bayer  Hard/embedded synchronous signals supported  Support for CCIR656 video interface as well as traditional sensor interface DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation. DCI supports various color space such as YUV/RGB, as well as compression format such as JPEG. Support CCIR656 video decoder formats and perform additional processing of the image. 3.29. TFT LCD interface (TLI)  Supports up to 24 bits data output per pixel  Supports up to 2048 x 2048 resolution  Support various pixel formats: ARGB8888, RGB888, RGB565, etc  Support CLUT (Color Look-Up-Table) and Color-Keying format The TFT LCD interface provides a parallel digital RGB (Red, Green and Blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display. Two separate layers are supported in TLI, as well as layer window and blending function. 3.30. Receiver of Sony/Philips Digtial Interface (RSPDIF)  Supports audio IEC-60958 and IEC-61937  Up to 4 inputs available  Supports maximum symbol rate: 12.288 MHz 74 GD32H757xx Datasheet  Supports stereo stream from 8 to 192 kHz  Supports automatic symbol rate detection  Genrate symbol clock  Check the parity bit of the received data  Support multiple data processing methods, which can process audio data and user channel information separately or together  Supports using DMA communication to receive audio data and user channel information respectively The receiver of Sony/Philips Digital Interface (RSPDIF) module provides the function of receiving and decoding RSPDIF audio data streams. 3.31. Serial Audio Interface (SAI) ■ Two independent audio sub-blocks ■ Each audio sub-block can be configured as any of the master/slave and transmitter/receiver combination with 8-word FIFO ■ Local clock divider logic to satisfy the various audio sampling rates ■ Flexible audio protocol configuration such as I2S, PCM/DSP, AC’97, LSB or MSBjustified and TDM ■ PDM interface, supporting up to 3 microphone pairs ■ Mono/Stereo audio capability with mute option ■ Frame Synchronization configuration (active level, active length and offset) ■ Each audio frame contains up to 16 configurable slots ■ Slot length is flexible, and can be configured as active or inactive ■ Each slot can hold a data of size 8-, 10-, 16-, 20-, 24-, and 32-bits with configurable first bit offset, and configurable LSB or MSB data transfer ■ Two independent DMA interface for each audio sub-block. Support slave mode with a frequency up to 4MHz The Serial Audio Interface (SAI) is designed to target a wide range of commonly used audio protocols, both in mono and stereo modes, such as I2S, PCM/DSP, AC’97, LSB or MSBjustified and TDM. SPDIF output is offered when the audio block is configured as a transmitter. The SAI can be configured to any of the master/slave and transmitter/receiver combination, full/half-duplex operating mode depends on synchronous/asynchronous configuration of the audio sub-blocks. 3.32. Image processing accelerator (IPA)  Copy one source image to the destination image  Convert one source image to the destination image with specific pixel format  Convert and blend two source images to the destination image with specific pixel format  Fill up the destination image with a specific color 75 GD32H757xx Datasheet The IPA provides a configurable and flexible image format conversion from one or two source image to the destination image. Sixteen pixel formats for foreground from 4-bit up to 32-bit per pixel, eleven pixel formats for background from 4-bit up to 32-bit per pixel, and five pixel formats from 16-bit up to 32-bit per pixel for the destination image are supported. Two 256*32 bits LUTs (Look-Up Table) separately for the two source images are implemented for the indirect pixel formats. 3.33. Secure digital input and output card interface (SDIO)  e•MMC: Support for embedded Multimedia Card System Specification Version 4.51 (and previous versions) Card and five different data bus modes: 1-bit (default), 4-bit (SDR/DDR) and 8-bit(SDR/DDR)  SD Card: Full support for SD Memory Card Specifications Version 3.0  SD I/O: Full support for SD I/O Card Specification Version 3.0 card and three different data bus modes: 1-bit (default) and 4-bit (SDR/DDR)  104MHz data transfer frequency and 8-bit data transfer mode  Support DDR and max clock frequency is 50Mhz The secure digital input/output interface (SDIO) defines the SD, SD I/O and embedded MultiMediaCard (e•MMC) host interface, which provides command/data transfer between the AHB system bus and SD memory cards, SD I/O cards and e•MMC. 3.34. Management data input/output (MDIO)  Support slave mode with a frequency up to 4MHz  Support CFP/CFP2 MSA Management Interface Specification The MDIO interface can receive complete MDIO frames. As long as the data is written to the register before receiving the turnaround bits (TA) of the read or post read increment address frame, the MDIO interface can transmit complete MDIO frames. Interrupts are generated at the end of every complete frame, which can be used or provided at correct time. Interrupts can also be generated after every valid PHYADR and DEVADD, which allows more complex controls within frames. 3.35. External memory controller (EXMC)  Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and, 8-bit or 16-bit NAND Flash and Synchronous DRAM(SDRAM)  Embedded ECC hardware for NAND Flash access  Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits Column Address, 2-bits internal banks address  SDRAM Memory size: 4x16Mx32bit (256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB) 76 GD32H757xx Datasheet The external memory controller EXMC, is used as a translator for CPU to access a variety of external memory, it automatically converts AXI memory access protocol into a specific memory access protocol defined in the configuration register, such as SRAM, ROM, NOR Flash, PSRAM, NAND Flash and SDRAM. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity. 3.36. VREF  Stable voltage, and product calibrated  Connects to VREFP pin to source off-chip circuits  1.5V, 1.8V, 2.048V or 2.5V configurable reference voltage output A precision internal reference circuit is inside. The internal voltage reference unit is used to provide voltage reference for ADC / DAC, or used by off-chip circuit connecting to VREFP pin. 3.37. Low power digital temperature sensor (LPDTS)  The trigger source of measurement can be set to software or hardware  Programmable sampling time  Temperature window watchdog  The interrupt can be generated when the temperature is below a low threshold or above a high threshold and at the end of measurement  The generation of asynchronous wakeup signal in LXTAL mode indicates that the measurement result is higher or lower than the specified threshold Low power digital tempearature sensor(LPDTS) is used to transmit square wave, which is converted by temperature and the frequency is proportional to the absolute temperature. The frequency measurement is based on the PCLK or the LXTAL clock. 3.38. Encoder Divided-Output controller (EDOUT)  Support for changing the activation polarity of B  Support configuration of Z-phase output location and pulse width  Number of edges per rotation: 16 to 65536 (must be the multiple of four)  Support for the input of update period event signals from the TRIGSEL The encoder divided-output controller (EDOUT) is used to output location information obtained from the encoder in the form of A-phase, B-phase, and Z-phase pulses. 3.39. Controller area network (CAN)  Supports CAN protocol version 2.0A/B 77 GD32H757xx Datasheet  Compliant with the ISO 11898-1:2015 standard  Supports CAN FD frame with up to 64 data bytes, baudrate up to 8 Mbit/s  Supports CAN classical frame with up to 8 data bytes, baudrate up to 1 Mbit/s  Supports time stamp based on 16-bit free running counter  Supports transmitter delay compensation for CAN FD frames at faster data rates  Maskable interrupts  Supports four communication mode: normal mode, Inactive mode, Loopback and silent mode, and Monitor mode  Supports two power saving modes: CAN_Deepsleep mode, and CAN_sleep mode  Support two wakeup methods for waking up from Pretended Networking mode: wakeup matching event, and wakup timeout event  Global network time, synchronized by a specific message CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. The CAN interface supports the CAN 2.0A/B protocol, ISO 11898-1:2015 and BOSCH CAN FD specification. The CAN module is a CAN Protocol controller with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system consists of a set of mailboxes that store configuration and control data, timestamp, message ID, and data. The space of up to 32 mailboxes can also be configured as Rx FIFO with ID filtering against up to 104 extended IDs or 208 standard IDs or 416 partial 8-bit IDs, and configure receive FIFO/mailbox private filter register for up to 32 ID filter table elements. 3.40. Ethernet (ENET)  IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN  10/100 Mbit/s rates with dedicated DMA controller and SRAM  Support hardware precision time protocol (PTP) with conformity to IEEE 1588 The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via a reduced media independent interface (RMII). The number of RMII signals provided up to 7 with 50 MHz output. The function of 32-bit CRC checking is also available. 3.41. Comparator (CMP)  Rail-to-rail comparators  Configurable hysteresis  Configurable speed and consumption  Each comparator has configurable analog input source:  Outputs with blanking source  Outputs to I/O 78 GD32H757xx Datasheet  Outputs to timers for capture  Outputs to EXTI and NVIC The general purpose comparators, CMP0 and CMP1, can work either standalone (all terminal are available on I/Os) or together with the timers. It could be used to wake up the MCU from low-power mode by an analog signal, provide a trigger source when an analog signal is in a certain condition, achieves some current control by working together with a PWM output of a timer and the DAC. It blanking function can be used for false overcurrent detection in motor control applications. 3.42. High-Performance Digital Filter (HPDF)  8 multiplex digital serial input channels -     configurable SPI and Manchester interfaces 8 internal digital parallel input channels - input with up to 16-bit resolution - internal source: ADC data or memory (CPU/DMA write) data stream Configurable Sinc filter and integrator - the order and oversampling rate (decimation rate) of Sinc filter can be configured - sampling rate of configurable integrator Threshold monitor function - independent Sinc filter, configurable order and oversampling rate (decimation rate) - configurable data input source: serial channel input data or HPDF output data Malfunction monitor function - A counter with 8 bits is used to monitor the continuous 0 or 1 in the serial channel input data stream  Extreme monitor function - store minimum and maximum values of output data values of HPDF;  Up to 24-bit output data resolution  Clock signal can be provided to external sigma delta modulator -  provide configurable clock signal by the CKOUT pin HPDF output data is in signed format A high performance digital filter module (HPDF) for external sigma delta (Σ-Δ) modulator is integrated in GD32H757xx. HPDF supports SPI interface and Manchester-coded single-wire interface. The external sigma delta modulator can be connected with MCU by the serial interface, and the serial data stream output by sigma delta modulator can be filtered. In addition, HPDF also supports the parallel data stream input, which can be selected from internal ADC peripherals or from MCU memory. 3.43. Real-time decryption (RTDEC)  Software configurable encrypted areas up to 4 79 GD32H757xx Datasheet  Granularity is 4096 bytes in RTDEC programmed areas  Every area can be configured the independent 128-bits key, 16-bits area firmware version, and 64-bits application-defined nonce  Confidentiality and completeness protection for encryption keys – 128-bits key registers are write-only, with software locking mechanism – 8-bits CRC is calculated automatically by hardware, and it’s used as the public key information   The real-time decryption when OSPI memory-mapped read operations. – Use of AES-128 in CTR mode – Support key stream FIFO with depth 4 – Support various read size – Decryption / encryption with physical address of the reads Support for GD32 OSPI pre-fetching mechanism The real-time decryption (RTDEC) allows to decrypt in real-time according to information of the read request address. RTDEC can configure four independent and different encrypted areas. And each area has the option of execute-only or execute-never enforcement to choose. For real-time performance, RTDEC uses the counter (CTR) mode of AES-128. Since RTDEC using AES in counter mode, the whole area has to be re-encrypted with an updated cryptographic context (key or initialization vector) when the data or code of one encrypted area is changed. This feature makes RTDEC only suitable for decrypting read-only content, like that stored in external flash. 3.44. Filter arithmetic accelerator (FAC)  Fixed or float multiplier and accumulator  256 x 32-bit local memory  16-bit fixed-point or 32-bit float point input and output  Up to three buffers, two input buffers and one output buffer  Buffer can be circular  FIR and IIR can be realized  Vector functions support convolution, Dot product, correlation functions  Data can be read and written through DMA The filter arithmetic accelerator unit consist of multiplier, accumulator and address generation logic, so as to index vector elements stored in local memory. Circular buffering is valid for both input and output, which allows to realize finite impulse response (FIR) filters and infinite impulse response (IIR) filters. The unit support CPU to be free from frequent or lengthy filtering operations, compared with software implementation, it can accelerate calculations and the processing speed of time critical tasks. 80 GD32H757xx Datasheet 3.45. Hardware semaphore (HWSEM)  32 semaphores  An interrupt is generated when a semaphore is unlocked  Semaphore is unlocked only when MID[3:0] and PID[7:0] are matched Hardware semaphore (HWSEM) provides a non-blocking mechanism to ensure the synchronous of processes. HWSEM realizes 32 semaphores in an atomic way, supporting semaphore write lock and read lock, and semaphore can only be unlocked when bus master and process are matched. 3.46. Universal serial bus high-speed interface (USBHS)  Supports USB 2.0 Host mode at High-Speed(480Mb/s), Full-Speed(12Mb/s) or LowSpeed(1.5Mb/s)  Supports USB 2.0 device mode at High-Speed(480Mb/s) or Full-Speed(12Mb/s)  Supports OTG protocol with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol) USB High-Speed (USBHS) controller provides a USB-connection solution for portable devices. USBHS supports both host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol). USBHS contains an embedded USB PHY internal which can be configured as High-Speed or Full-Speed. USBHS supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. There is also a DMA engine operating as an AHB bus master in USBHS to speed up the data transfer between USBHS and system. For Full-Speed operation, battery charging detection (BCD), attach detection protocol (ADP), and link power management (LPM) are also supported. 3.47. Debug mode  JTAG and SWD Debug Port The GD32H757xx series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm ® CoreSight™ module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM® Cortex®-M7. The debug system supports serial wire debug (SWD) and trace functions in addition to standard JTAG debug. 3.48. Package and operation temperature  LQFP144 (GD32H757Zx), BGA100\LQFP100 (GD32H757Vx) 81 GD32H757xx Datasheet  Operation temperature range: -40°C to +85°C (industrial level) 82 GD32H757xx Datasheet 4. Electrical characteristics To better understand this chapter, read the following before moving on to the rest of this chapter.  A + or no sign before the current value indicates that the current is output from the MCU.  A - before the current value indicates that the current is input to the MCU.  TA (Ambient temperature) tested condition.  TJ (Junction temperature) tested condition.  Value guaranteed by design, not 100% tested in production indicates that the value is derived from simulation of IC designers.  Value guaranteed by characterization, not 100% tested in production indicates that the value is derived from random test.  Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TJ = 25 °C.  The devices will be damaged or work abnormally if the electrical parameters beyond the range of maximum and minimum values. See the following table for some abbreviation terms and their descriptions in this chapter. Table 4-1. Abbreviations 4.1. Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus CAN Controller Area Network DAC Digital-to-Analog Converter DMA Direct Memory Access GPIO General Purpose Input/Output JTAG Joint Test Action Group PLL Phase-Locked Loop PWM Pulse Width Modulator USB Universal Serial Bus SPI Serial Peripheral Interface RMII Reduced Media Independent Interface Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. 83 GD32H757xx Datasheet Table 4-2. Absolute maximum ratings(1)(4) Symbol Parameter Min Max Unit VDD External voltage range(2) VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage(3) VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V VDD50USB VDD50USB supply voltage VSS - 0.3 VSS + 5.6 V VIN Input voltage on I/O VSS - 0.3 VSS +3.6 V |ΔVDDX| Variations between different VDD power pins — 50 mV |VSSX −VSS| Variations between different ground pins — 50 mV IIO Maximum current for GPIO pins — 25 ∑IIO Maximum current sunk/sourced by all GPIO pin — 120 IDD Maximum current into each VDD pin — 120 ISS Maximum current into each VSS pin — 120 ∑IDD Total current into all VDD pins — TBD ∑ISS Total current into all VSS pins — TBD TA Operating temperature range -40 +85 Power dissipation at TA = 85°C of LQFP144 — 847 Power dissipation at TA = 85°C of LQFP100 — 836 Power dissipation at TA = 85°C of BGA100 — TBD TSTG Storage temperature range -65 +150 °C TJ Maximum junction temperature — 125 °C PD (1) (2) (3) (4) 4.2. mA °C mW Value guaranteed by design, not 100% tested in production. All main power and ground pins should be connected to an external power source within the allowable range. It is recommended that VDD and VDDA are powered by the same source. The maximum difference between VDD and VDDA does not exceed 300 mV during power-up and operation. The device junction temperature must be kept below maximum TJ. Recommended DC characteristics Table 4-3. DC operating conditions Min(1) Typ Max(1) Unit Symbol Parameter Conditions VDD Supply voltage — 1.71 3.3 3.6 V VDDLDO ≤ VDD 1.71 — 3.6 V USB regulator ON 4.0 5.0 5.5 V USB regulator OFF — — V VDDLDO VDD50USB Supply voltage for the internal regular — VDD33 USB Standard operating voltage, USB USB used 3.0 — 3.6 V domain USB not used 0 — 3.6 V VDDA Analog supply voltage Same as VDD 1.71 3.3 3.6 V VBAT Battery supply voltage — 1.71 — 3.6 V VDD33USB (1) Value guaranteed by characterization, not 100% tested in production. 84 GD32H757xx Datasheet Figure 4-1. Recommended power supply decoupling capacitors(1)(2)(3) VBAT 100 nF VSS N * VDD 4.7 μF + N * 100 nF VSS VDDA 1 μF VSSA 10 nF VREFP 1 μF VREFN 10 nF VCORE VSS 2x2.2μF or 2x100nF (1) (2) (3) The VREFP and VREFN pins are only available on no less than 100-pin packages, or else the VREFP and VREFN pins are not available and internally connected to VDDA and VSSA pins. All decoupling capacitors need to be as close as possible to the pins on the PCB board. When voltage regulator is enabled the two 2.2 μF Vcore capacitors are required , if bypassing the voltage regulator ,two 100 nF decoupling capacitors are required. Table 4-4. Vcore operating conditions(1)(2)(3) (1) (2) (3) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2uF ESR ESR of external capacitor