SQ33068WAQ

Application Note: SQ33068 6V to 75V Synchronous Buck Controller With Wide Duty Cycle Range Advanced Design Specification General Description Features The SQ33068 is 75V synchronous buck controller with type Ⅲ voltage mode control and feedforward. Minimum tens of nanosecond on-time facilitates large step-down ratios. The SQ33068 continues to operate when input voltage decreases to as low as 6V.    Ordering Information SQ33068□(□□□)  Package Code Optional Spec Code Ordering Number SQ33068WAQ Package type QFN3.5x4.5-20 ar t m VIN pin voltage determines whether SQ33068 enters DEM to prevent reverse charging. Cycle-by-cycle over current protection is accomplished by measuring the voltage across the low-side MOSFET or current sense resistor. Forced-PWM (FPWM) eliminates frequency variation and a selectable diode emulation lowers power consumption at light-load conditions. The switching frequency as high as 1 MHz can be set or synchronized to an external clock. iS         6V to 75V Input Voltage Range 0.8V to 60V Output Voltage Range Switching Frequency: 100kHz~1MHz – SYNC In/Out Capability Soft-Start or Voltage Tracking 0.8V±1% Reference Voltage Minimum On-Time: 60ns typical Minimum Off-Time: 240ns typical Type Ⅲ Voltage-Mode Control with Feedforward High Gain-Bandwidth Error Amplifier Open-Drain Power Good Indicator Protection Features – Cycle-by-cycle Over current Protection – Prevent Reverse Charging Protection – Input UVLO with Hysteresis – VCC and BST UVLO Protection – Thermal Shutdown Protection with Hysteresis Compact Package: QFN3.5x4.5-20 Applications Note  Telecom Power Application  RF Power Application  Commercial Drone Application Typical Application CVIN VOUT REN2 R1 RFB1 RT C3 REN1 EN/UVLO RRT C1 SS/TRK VIN RVIN CIN VIN CBST BST HO Q1 CSS R2 C2 COMP LX FB NC AGND EP SYNCOUT RBST LF D1 VCC RILIM RFB2 SYNCIN RSYNCIN NC PGOOD COUT LO PGND ILIM VOUT Q2 CVCC CILIM VCC RPGOOD Figure 1. Typical Application AN_SQ33068 Rev. 0.0 © 2023 Silergy Corp. Silergy Corp. Confidential- Prepared for Customer Use Only 1 All Rights Reserved. AN_SQ33068 20 RT 2 19 LX SS/TRK 3 18 HO COMP 4 17 BST 16 NC 15 EP SYNCOUT 7 14 VCC SYNCIN 8 13 LO NC 9 12 PGND FB 5 Exposed Pad (EP) AGND 6 10 11 PGOOD ILIM ar VIN 1 iS m EN/UVLO t Pinout (Top View) Top mark: GQYxyz (Device code: GQY, x=year code, y=week code, z= lot number code) Pin Name EN/UVLO Pin Number 1 RT 2 SS/TRK 3 COMP FB AGND 4 5 6 SYNCOUT 7 SYNCIN NC PGOOD ILIM PGND LO VCC EP NC BST HO 8 9 10 11 12 13 14 15 16 17 18 LX 19 VIN 20 EP - AN_SQ33068 Rev. 0.0 © 2023 Silergy Corp. Pin Description Enable and UVLO pin Switching frequency set pin. A resistor is connected to RT pin and set the operation frequency. Soft-start and voltage tracking pin. A capacitor is connected to set soft-start time. Output of the internal error amplifier. Output Feedback Pin. Analog ground. Synchronization output. Logic output that provides a clock signal that is 180°out-of phase with the high-side FET gate drive. Synchronization input pin. No electrical connection. Power Good indicator. Current limit set and protection pin. Power ground. Low side MOSFET gate driver pin. Power supply pin. Exposed pad of the package. No electrical connection. Bootstrap supply for the high-side gate driver. High side MOSFET gate driver pin. Inductor pin. Connect this pin to the switching node of inductor. Voltage supply for VCC LDO regulator and prevent reverse charging protection pin. Exposed pad of the package. Connect to the system ground to reduce thermal resistance. Silergy Corp. Confidential- Prepared for Customer Use Only 2 All Rights Reserved. AN_SQ33068 Absolute Maximum Ratings iS m ar t Absolute Maximum Voltage (Note 1) VIN, EN/UVLO, PGOOD------------------------------------------------------------------------------------------------- -0.3V to 95V LX------------------------------------------------------------------------------------------------------------------------------- -1V to 95V ILIM-------------------------------------------------------------------------------------------------------------------------- -0.3V to 95V VCC, SYNCIN------------------------------------------------------------------------------------------------------------- -0.3V to 14V BST to LX------------------------------------------------------------------------------------------------------------------ -0.3V to 14V FB, COMP, SS/TRK, RT--------------------------------------------------------------------------------------------------- -0.3V to 6V BST ------------------------------------------------------------------------------------------------------------------------- -0.3V to 105V Package Thermal Resistance (Note 2) Power Dissipation max, @ TA=25°C QFN3.5x4.5-20 ------------------------------------------------------------------------- 3.3W ƟJA --------------------------------------------------------------------------------------- ------------------------------------------ 42°C/W ƟJC(top) ----------------------------------------------------------------------------------------------------------------------------- 14°C/W Junction Temperature Range ----------------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------------------ 260°C Storage Temperature Range ------------------------------------------------------------------------------------------- -65°C to 150°C Recommended Operating Conditions (Note 3) VIN ----------------------------------------------------------------------------------------------------------------------------- 6V to 75V External VCC------------------------------------------------------------------------------------------------------------------ 8V to 13V Junction Temperature Range ------------------------------------------------------------------------------------------ -40°C to 125°C Block Diagram LDO V IN 7.5V VCC VCC UVLO 10uA 1.2V S tandby BST UVLO EN B ST S hutdow n PG O O D PGOOD Comparator FB 0.4V HO PWM Control&Logic &Protection 10uA OTP LX V R EF S S /T R K VCC COMP LO V IN /kF F RT Oscillation Generator RAMP Generator Synchronization Function CLK S Y N C IN FPWM&Diode Emulation Mode Selection OCP ILIM S YN C O U T PG N D AG N D Fig 2. Simplified Block Diagram AN_SQ33068 Rev. 0.0 © 2023 Silergy Corp. Silergy Corp. Confidential- Prepared for Customer Use Only 3 All Rights Reserved. AN_SQ33068 Electrical Characteristics (VIN=48V, VEN/UVLO=1.5V, RRT=25kΩ, Tj=25˚C, Minimum and maximum limits apply over the –40°C to 125°C junction temperature range, unless otherwise specified) Unit 75 V 1.05 1.3 mA 88 5 425 9.3 93 510 12.8 V V μA μA 7.5 7.7 V 285 650 mV 50 5.25 65 5.5 mA V 6 83 7.3 VVCC-EXT IVCC VSS/TRK = 0V, VVCC = 13V VSDN VEN/UVLO rising VSDN-HYS EN/UVLO rising – falling threshold VEN VEN/UVLO rising 1.164 1.2 1.236 V IEN-HYS VEN/UVLO = 1.5V 9 10 11 μA VREF IFB-BIAS FB connected to COMP VFB = 0.8V VFB = 0V, COMP sourcing 1mA FB=1V, COMP sinking 1mA 792 -0.1 800 808 0.1 mV μA VVCC-LDO VCC Short-circuit Current VCC UVLO Threshold ISC-LDO VUVLO_H VCC UVLO Hysteresis VUVLO_HYS COMP Output High Voltage VCOMP-OH COMP Output Low Voltage VCOMP-OL DC Gain AVOL Unity Gain Bandwidth GBW Soft Start and Voltage Tracking SS/TRK Capacitor Charging ISS Current SS/TRK Discharge FET RSS Resistance SS/TRK to FB Offset VSS-FB SS/TRK Clamp Voltage VSS-CLAMP POWER GOOD INDICATOR FB Upper Threshold for PGUTH PGOOD High to Low AN_SQ33068 Rev. 0.0 © 2023 Silergy Corp. Max Typ VIN = 6 V, VSS/TRK = 0 V, IVCC = 20 mA VSS/TRK = 0V, VCC = 6V VCC rising Rising threshold – falling threshold Voltage required to disable VCC regulator VIN to VCC Dropout Voltage Minimum External Bias Supply Voltage External VCC Input Current, not Switching Enable And Input UVLO Shutdown to Standby Threshold Shutdown Threshold Hysteresis Standby to Operating Threshold Standby to Operating Hysteresis Current Error Amplifier FB Reference Voltage FB Input Bias Current Min t Conditions ar Symbol iS m Parameter Vin Input Supply& Prevent Reverse Charging Protection (VIN DEM) VIN Voltage Range VIN Operating Input Current, not VEN/UVLO = 1.5V, VSS/TRK = IQ-RUN 0V Switching VIN DEM Threshold VIN_DEM VIN DEM HYS VIN_DEMHYS VEN/UVLO = 0.8V Standby Input Current IQ-STBY VEN/UVLO = 0V, VVCC< 1V Shutdown Input Current IQ-SDN VCC Regulator VEN/UVLO = 1.5V VCC Regulation Voltage VVCC VSS/TRK = 0V 40 5 270 8 V 1.3 8.5 VEN/UVLO = 0.8V, VSS/TRK = 0.1V V 33 mV 4.2 V 0.44 V 100 6.6 dB MHz 10 -15 11.5 15 108% uA Ω 120 105% mA 0.41 26 VSS/TRK–VFB, VFB = 0.8V % of VREF, VFB rising mV mV mV 111% Silergy Corp. Confidential- Prepared for Customer Use Only 4 All Rights Reserved. AN_SQ33068 Minimum off-time TOFF(MIN) DC100kHz Maximum Duty Cycle DC400kHz Ramp Valley Voltage (COMP at 0%duty cycle) PWM Feedforward Gain (VIN / VRAMP) AN_SQ33068 Rev. 0.0 © 2023 Silergy Corp. % of VREF, VFB falling 92% % of VREF 3% % of VREF 3% FB to PGOOD rising edge FB to PGOOD falling edge 33 33 95% μs μs 300 VFB = 0.8V, VPGOOD = 13V 100 nA 420 kHz kHz kHz ar RRT = 100kΩ RRT = 25kΩ RRT = 12.5kΩ 380 % of nominal frequency set by RRT 80% 104 400 770 150% 2 V 1 VSYNCIN =0.3V Minimum high state or low state duration ISYNCOUT = –1 mA (sourcing) V kΩ 23 50 ns 2.8 V ISYNCOUT = 1 mA (sinking) VSYNCIN Floating, TS = 1/FSW,FSW set by RRT mV t VFB = 0.9 V, IPGOOD = 2 mA 0.9 TS/2 – 240 V ns 50% to 50% 260 ns VSS/TRK = 0V, VLX = 48V,VBST = 54V 48 uA VBST – VLX falling 3.5 V VBST – VLX rising 0.34 V VBST – VLX = 7 V, HO 50% to 50% VBST – VLX = 7 V, HO 50% to 50% FSW = 100 kHz, 6 V ≤ VVIN≤ 60 V FSW = 400 kHz, 6 V ≤ VVIN≤ 60 V VRAMP(min) kFF 89% iS m FB Lower Threshold for PGLTH PGOOD High to Low PGOOD Upper Threshold PGHYS_U Hysteresis PGOOD Lower Threshold PGHYS_L Hysteresis PGOOD Rising Filter TPG-RISE PGOOD Falling Filter TPG-FALL PGOOD Low State Output VPG-OL Voltage PGOOD High State Leakage IPG-OH Current Switching Frequency Oscillator Frequency – 1 FSW1 Oscillator Frequency – 2 FSW2 Oscillator Frequency – 3 FSW3 Synchronization Input and Output SYNCIN External Clock FSYNC Frequency Range Minimum SYNCIN Input VSYNC-IH Logic High Maximum SYNCIN Input VSYNC-IL Logic Low SYNCIN Input Resistance RSYNCIN SYNCIN Input Minimum TSYNCI-PW Pulse Width SYNCOUT High State Output VSYNCO-OH Voltage SYNCOUT Low State Output VSYNCO-OL Voltage Delay from HO Rising to TSYNCOUT SYNCOUT Leading Edge Delay from SYNCIN Leading TSYNCIN Edge to HO Rising Bootstrap Under Voltage Threshold BST to LX Quiescent Current, IQ-BST not Switching BST to LX under Voltage VBST-UV Detection BST to LX under Voltage VBST-HYS Hysteresis PWM CONTROL Minimum Controllable onTON(MIN) time 6 V ≤ VVIN≤ 75 V 60 90 ns 240 340 ns 97% 90% 300 mV 15 V/V Silergy Corp. Confidential- Prepared for Customer Use Only 5 All Rights Reserved. AN_SQ33068 VZCD-DIS ZCD threshold measured at LX pin 1000 clock cycles after first HO pulse Diode Emulation Zero-cross Threshold VDEM-TH Measured at LX with VLX rising Gate Driver HO High-state Resistance, HO to BST HO Low-state Resistance, HO to LX LO High-state Resistance, LO to VCC LO Low-state Resistance, LO to PGND RHO-UP RHO-DOWN RLO-UP RLO-DOWN HO, LO Source Current IHOH, ILOH HO, LO Sink Current IHOL, ILOL THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Switching Characteristics TSD TSD-HYS HO, LO Rise Times THO-TR _TLO-TR HO, LO Fall Times THO-TF _TLO-TF HO Turn on Dead Time THO-DT LO Turn on Dead Time TLO-DT VBST – VLX = 7 V, IHO = –100 mA VBST – VLX = 7 V, IHO = 100 mA VBST – VLX = 7 V, ILO = –100 mA VBST – VLX = 7 V, ILO = 100 mA VBST – VLX = 7 V, HO = LX, LO = AGND VBST – VLX = 7 V, HO = BST, LO = VCC TJ rising VBST – VLX = 7 V, CLOAD = 1 nF, 20% to 80% VBST – VLX = 7 V, CLOAD = 1 nF, 80% to 20% VBST – VLX = 7 V, LO off to HO on, 50% to 50% VBST – VLX = 7 V, HO off to LO on, 50% to 50% 100 110 uA 180 200 220 uA 2700 0 0 6.5 mV t -6.5 ppm/°C ppm/°C ar Zero-cross Detect Disable Threshold 90 iS m OVERCURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING ILIM Source Current, Low voltage detected at IRS ILIM RSENSE Mode ILIM Source Current, LX voltage detected at IRDSON ILIM, TJ = 25°C RDS(on) Mode RDS-ON mode ILIM Current Tempco IRSTC RSENSE mode ILIM Current Tempco IRDSONTC ILIM Comparator Threshold VILIM-TH at ILIM DIODE EMULATION 200 -6.5 0 6.5 mV mV 1.7 Ω 0.73 Ω 1.7 Ω 0.73 Ω 2.3 A 3.5 A 160 18 ˚C ˚C 5 ns 4 ns 25 ns 10 ns Note 1: Stresses beyond the listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may remain possibility to affect device reliability. Note 2: θJA is measured in the natural convection at TA=25ºC on a high effective four-layer PCB with thermal via according with JESD 51-2, -5, -7, -8, -14 measurement standard. Note 3: The device is not guaranteed to function outside its operating conditions. AN_SQ33068 Rev. 0.0 © 2023 Silergy Corp. Silergy Corp. Confidential- Prepared for Customer Use Only 6 All Rights Reserved. AN_SQ33068 DEM, the device will enter diode emulation mode to stop energy flowing back to input capacitor. 6V~75V SQ33068 VIN RVI N Vin CVI N PGND Fig 3. Vin Pin Connection Power Supply VCC In SQ33068, a LDO is connected to Vin to generate VCC voltage, providing internal logic power and gate driver power. If Vin>7.5V, output of LDO (VCC) is 7.5V. If Vin